Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 07:46:40 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx | Design : ngFEC_top | Device : xcku115-flva2104-1-c | Speed File : -1 | Design State : Synthesized ------------------------------------------------------------------------------------------------------------------ Report DRC Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Ruledeck: default Max violations: Violations found: 4511 +-------------+----------+---------------------------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-------------+----------+---------------------------------------------------------------------+------------+ | CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | | DPIP-2 | Warning | Input pipelining | 1523 | | DPOP-3 | Warning | PREG Output pipelining | 249 | | DPREG-7 | Warning | DSP48E2_PregDynOpmodeZmuxP: | 478 | | IOBUSSLRC-1 | Warning | IO Bus SLR Crossings | 6 | | AVAL-155 | Advisory | enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND | 382 | | AVAL-156 | Advisory | enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND | 382 | | REQP-1669 | Advisory | enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND | 2 | | REQP-1671 | Advisory | enum_AREG_1_connects_CEA1_GND | 139 | | REQP-1673 | Advisory | enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND | 2 | | REQP-1675 | Advisory | enum_BREG_1_connects_CEB1_GND | 139 | | REQP-1678 | Advisory | enum_CREG_0_connects_CEC_GND | 386 | | REQP-1680 | Advisory | enum_PREG_0_connects_CEP_GND | 130 | | REQP-1681 | Advisory | with_OPMODE_USE_MULT_NONE | 11 | | REQP-1934 | Advisory | RAMB18E2_nochange_collision_advisory | 681 | +-------------+----------+---------------------------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. Related violations: DPIP-2#1 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#2 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#3 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#4 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#5 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#6 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#7 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#8 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#9 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#10 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#11 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#12 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#13 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#14 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#15 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#16 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#17 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#18 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#19 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#20 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#21 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#22 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#23 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#24 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#25 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#26 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#27 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#28 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#29 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#30 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#31 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#32 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#33 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#34 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#35 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#36 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#37 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#38 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#39 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#40 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#41 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#42 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#43 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#44 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#45 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#46 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#47 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#48 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#49 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#50 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#51 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#52 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#53 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#54 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#55 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#56 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#57 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#58 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#59 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#60 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#61 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#62 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#63 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#64 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#65 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#66 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#67 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#68 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#69 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#70 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#71 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#72 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#73 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#74 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#75 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#76 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#77 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#78 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#79 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#80 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#81 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#82 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#83 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#84 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#85 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#86 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#87 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#88 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#89 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#90 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#91 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#92 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#93 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#94 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#95 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#96 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#97 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#98 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#99 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#100 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#101 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#102 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#103 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#104 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#105 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#106 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#107 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#108 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#109 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#110 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#111 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#112 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#113 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#114 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#115 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#116 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#117 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#118 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#119 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#120 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#121 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#122 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#123 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#124 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#125 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#126 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#127 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#128 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#129 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#130 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#131 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#132 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#133 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#134 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#135 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#136 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#137 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#138 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#139 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#140 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#141 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#142 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#143 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#144 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#145 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#146 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#147 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#148 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#149 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#150 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#151 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#152 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#153 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#154 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#155 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#156 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#157 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#158 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#159 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#160 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#161 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#162 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#163 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#164 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#165 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#166 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#167 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#168 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#169 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#170 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#171 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#172 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#173 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#174 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#175 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#176 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#177 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#178 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#179 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#180 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#181 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#182 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#183 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#184 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#185 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#186 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#187 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#188 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#189 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#190 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#191 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#192 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#193 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#194 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#195 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#196 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#197 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#198 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#199 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#200 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#201 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#202 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#203 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#204 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#205 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#206 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#207 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#208 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#209 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#210 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#211 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#212 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#213 Warning Input pipelining DSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#214 Warning Input pipelining DSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#215 Warning Input pipelining DSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#216 Warning Input pipelining DSP ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#217 Warning Input pipelining DSP g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#218 Warning Input pipelining DSP g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#219 Warning Input pipelining DSP g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#220 Warning Input pipelining DSP g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#221 Warning Input pipelining DSP g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#222 Warning Input pipelining DSP g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#223 Warning Input pipelining DSP g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#224 Warning Input pipelining DSP g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#225 Warning Input pipelining DSP g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#226 Warning Input pipelining DSP g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#227 Warning Input pipelining DSP g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#228 Warning Input pipelining DSP g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#229 Warning Input pipelining DSP g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#230 Warning Input pipelining DSP g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#231 Warning Input pipelining DSP g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#232 Warning Input pipelining DSP g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#233 Warning Input pipelining DSP g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#234 Warning Input pipelining DSP g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#235 Warning Input pipelining DSP g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#236 Warning Input pipelining DSP g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#237 Warning Input pipelining DSP g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#238 Warning Input pipelining DSP g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#239 Warning Input pipelining DSP g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#240 Warning Input pipelining DSP g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#241 Warning Input pipelining DSP g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#242 Warning Input pipelining DSP g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#243 Warning Input pipelining DSP g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#244 Warning Input pipelining DSP g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#245 Warning Input pipelining DSP g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#246 Warning Input pipelining DSP g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#247 Warning Input pipelining DSP g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#248 Warning Input pipelining DSP g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#249 Warning Input pipelining DSP g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#250 Warning Input pipelining DSP g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#251 Warning Input pipelining DSP g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#252 Warning Input pipelining DSP g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#253 Warning Input pipelining DSP g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#254 Warning Input pipelining DSP g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#255 Warning Input pipelining DSP g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#256 Warning Input pipelining DSP g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#257 Warning Input pipelining DSP g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#258 Warning Input pipelining DSP g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#259 Warning Input pipelining DSP g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#260 Warning Input pipelining DSP g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#261 Warning Input pipelining DSP g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#262 Warning Input pipelining DSP g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#263 Warning Input pipelining DSP g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#264 Warning Input pipelining DSP g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#265 Warning Input pipelining DSP g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#266 Warning Input pipelining DSP g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#267 Warning Input pipelining DSP g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#268 Warning Input pipelining DSP g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#269 Warning Input pipelining DSP g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#270 Warning Input pipelining DSP g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#271 Warning Input pipelining DSP g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#272 Warning Input pipelining DSP g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#273 Warning Input pipelining DSP g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#274 Warning Input pipelining DSP g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#275 Warning Input pipelining DSP g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#276 Warning Input pipelining DSP g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#277 Warning Input pipelining DSP g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#278 Warning Input pipelining DSP g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#279 Warning Input pipelining DSP g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#280 Warning Input pipelining DSP g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#281 Warning Input pipelining DSP g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#282 Warning Input pipelining DSP g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#283 Warning Input pipelining DSP g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#284 Warning Input pipelining DSP g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#285 Warning Input pipelining DSP g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#286 Warning Input pipelining DSP g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#287 Warning Input pipelining DSP g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#288 Warning Input pipelining DSP g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#289 Warning Input pipelining DSP g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#290 Warning Input pipelining DSP g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#291 Warning Input pipelining DSP g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#292 Warning Input pipelining DSP g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#293 Warning Input pipelining DSP g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#294 Warning Input pipelining DSP g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#295 Warning Input pipelining DSP g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#296 Warning Input pipelining DSP g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#297 Warning Input pipelining DSP g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#298 Warning Input pipelining DSP g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#299 Warning Input pipelining DSP g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#300 Warning Input pipelining DSP g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#301 Warning Input pipelining DSP g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#302 Warning Input pipelining DSP g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#303 Warning Input pipelining DSP g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#304 Warning Input pipelining DSP g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#305 Warning Input pipelining DSP g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#306 Warning Input pipelining DSP g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#307 Warning Input pipelining DSP g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#308 Warning Input pipelining DSP g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#309 Warning Input pipelining DSP g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#310 Warning Input pipelining DSP g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#311 Warning Input pipelining DSP g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#312 Warning Input pipelining DSP g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#313 Warning Input pipelining DSP g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#314 Warning Input pipelining DSP g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#315 Warning Input pipelining DSP g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#316 Warning Input pipelining DSP g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#317 Warning Input pipelining DSP g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#318 Warning Input pipelining DSP g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#319 Warning Input pipelining DSP g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#320 Warning Input pipelining DSP g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#321 Warning Input pipelining DSP g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#322 Warning Input pipelining DSP g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#323 Warning Input pipelining DSP g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#324 Warning Input pipelining DSP g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#325 Warning Input pipelining DSP g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#326 Warning Input pipelining DSP g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#327 Warning Input pipelining DSP g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#328 Warning Input pipelining DSP g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#329 Warning Input pipelining DSP g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#330 Warning Input pipelining DSP g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#331 Warning Input pipelining DSP g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#332 Warning Input pipelining DSP g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#333 Warning Input pipelining DSP g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#334 Warning Input pipelining DSP g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#335 Warning Input pipelining DSP g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#336 Warning Input pipelining DSP g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#337 Warning Input pipelining DSP g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#338 Warning Input pipelining DSP g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#339 Warning Input pipelining DSP g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#340 Warning Input pipelining DSP g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#341 Warning Input pipelining DSP g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#342 Warning Input pipelining DSP g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#343 Warning Input pipelining DSP g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#344 Warning Input pipelining DSP g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#345 Warning Input pipelining DSP g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#346 Warning Input pipelining DSP g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#347 Warning Input pipelining DSP g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#348 Warning Input pipelining DSP g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#349 Warning Input pipelining DSP g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#350 Warning Input pipelining DSP g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#351 Warning Input pipelining DSP g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#352 Warning Input pipelining DSP g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#353 Warning Input pipelining DSP g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#354 Warning Input pipelining DSP g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#355 Warning Input pipelining DSP g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#356 Warning Input pipelining DSP g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#357 Warning Input pipelining DSP g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#358 Warning Input pipelining DSP g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#359 Warning Input pipelining DSP g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#360 Warning Input pipelining DSP g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#361 Warning Input pipelining DSP g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#362 Warning Input pipelining DSP g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#363 Warning Input pipelining DSP g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#364 Warning Input pipelining DSP g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#365 Warning Input pipelining DSP g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#366 Warning Input pipelining DSP g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#367 Warning Input pipelining DSP g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#368 Warning Input pipelining DSP g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#369 Warning Input pipelining DSP g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#370 Warning Input pipelining DSP g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#371 Warning Input pipelining DSP g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#372 Warning Input pipelining DSP g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#373 Warning Input pipelining DSP g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#374 Warning Input pipelining DSP g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#375 Warning Input pipelining DSP g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#376 Warning Input pipelining DSP g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#377 Warning Input pipelining DSP g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#378 Warning Input pipelining DSP g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#379 Warning Input pipelining DSP g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#380 Warning Input pipelining DSP g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#381 Warning Input pipelining DSP g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#382 Warning Input pipelining DSP g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#383 Warning Input pipelining DSP g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#384 Warning Input pipelining DSP g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#385 Warning Input pipelining DSP g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#386 Warning Input pipelining DSP g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#387 Warning Input pipelining DSP g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#388 Warning Input pipelining DSP g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#389 Warning Input pipelining DSP g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#390 Warning Input pipelining DSP g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#391 Warning Input pipelining DSP g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#392 Warning Input pipelining DSP g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#393 Warning Input pipelining DSP g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#394 Warning Input pipelining DSP g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#395 Warning Input pipelining DSP g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#396 Warning Input pipelining DSP g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#397 Warning Input pipelining DSP g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#398 Warning Input pipelining DSP g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#399 Warning Input pipelining DSP g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#400 Warning Input pipelining DSP g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#401 Warning Input pipelining DSP g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#402 Warning Input pipelining DSP g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#403 Warning Input pipelining DSP g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#404 Warning Input pipelining DSP g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#405 Warning Input pipelining DSP g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#406 Warning Input pipelining DSP g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#407 Warning Input pipelining DSP g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst input g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#408 Warning Input pipelining DSP g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst input g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#409 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#410 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#411 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#412 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#413 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#414 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#415 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#416 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#417 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#418 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#419 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#420 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#421 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#422 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#423 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#424 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#425 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#426 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#427 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#428 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#429 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#430 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#431 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#432 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#433 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#434 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#435 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#436 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#437 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#438 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#439 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#440 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#441 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#442 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#443 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#444 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#445 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#446 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#447 Warning Input pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#448 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#449 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#450 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#451 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#452 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#453 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#454 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#455 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#456 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#457 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#458 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#459 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#460 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#461 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#462 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#463 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#464 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#465 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#466 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#467 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#468 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#469 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#470 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#471 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#472 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#473 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#474 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#475 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#476 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#477 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#478 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#479 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#480 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#481 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#482 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#483 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#484 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#485 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#486 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#487 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#488 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#489 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#490 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#491 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#492 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#493 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#494 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#495 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#496 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#497 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#498 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#499 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#500 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#501 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#502 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#503 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#504 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#505 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#506 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#507 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#508 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#509 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#510 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#511 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#512 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#513 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#514 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#515 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#516 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#517 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#518 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#519 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#520 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#521 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#522 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#523 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#524 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#525 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#526 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#527 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#528 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#529 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#530 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#531 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#532 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#533 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#534 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#535 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#536 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#537 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#538 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#539 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#540 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#541 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#542 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#543 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#544 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#545 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#546 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#547 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#548 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#549 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#550 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#551 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#552 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#553 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#554 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#555 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#556 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#557 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#558 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#559 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#560 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#561 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#562 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#563 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#564 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#565 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#566 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#567 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#568 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#569 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#570 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#571 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#572 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#573 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#574 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#575 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#576 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#577 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#578 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#579 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#580 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#581 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#582 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#583 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#584 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#585 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#586 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#587 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#588 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#589 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#590 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#591 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#592 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#593 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#594 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#595 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#596 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#597 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#598 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#599 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#600 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#601 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#602 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#603 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#604 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#605 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#606 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#607 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#608 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#609 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#610 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#611 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#612 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#613 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#614 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#615 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#616 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#617 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#618 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#619 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#620 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#621 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#622 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#623 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#624 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#625 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#626 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#627 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#628 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#629 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#630 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#631 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#632 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#633 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#634 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#635 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#636 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#637 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#638 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#639 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#640 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#641 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#642 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#643 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#644 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#645 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#646 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#647 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#648 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#649 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#650 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#651 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#652 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#653 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#654 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#655 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#656 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#657 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#658 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#659 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#660 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#661 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#662 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#663 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#664 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#665 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#666 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#667 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#668 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#669 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#670 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#671 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#672 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#673 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#674 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#675 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#676 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#677 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#678 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#679 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#680 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#681 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#682 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#683 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#684 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#685 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#686 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#687 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#688 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#689 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#690 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#691 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#692 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#693 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#694 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#695 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#696 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#697 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#698 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#699 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#700 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#701 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#702 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#703 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#704 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#705 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#706 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#707 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#708 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#709 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#710 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#711 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#712 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#713 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#714 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#715 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#716 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#717 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#718 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#719 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#720 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#721 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#722 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#723 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#724 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#725 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#726 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#727 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#728 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#729 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#730 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#731 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#732 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#733 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#734 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#735 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#736 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#737 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#738 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#739 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#740 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#741 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#742 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#743 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#744 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#745 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#746 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#747 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#748 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#749 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#750 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#751 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#752 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#753 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#754 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#755 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#756 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#757 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#758 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#759 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#760 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#761 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#762 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#763 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#764 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#765 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#766 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#767 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#768 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#769 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#770 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#771 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#772 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#773 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#774 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#775 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#776 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#777 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#778 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#779 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#780 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#781 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#782 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#783 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#784 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#785 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#786 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#787 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#788 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#789 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#790 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#791 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#792 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#793 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#794 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#795 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#796 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#797 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#798 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#799 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#800 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#801 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#802 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#803 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#804 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#805 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#806 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#807 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#808 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#809 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#810 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#811 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#812 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#813 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#814 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#815 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#816 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#817 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#818 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#819 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#820 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#821 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#822 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#823 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#824 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#825 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#826 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#827 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#828 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#829 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#830 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#831 Warning Input pipelining DSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#832 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#833 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#834 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#835 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#836 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#837 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#838 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#839 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#840 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#841 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#842 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#843 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#844 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#845 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#846 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#847 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#848 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#849 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#850 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#851 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#852 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#853 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#854 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#855 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#856 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#857 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#858 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#859 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#860 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#861 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#862 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#863 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#864 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#865 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#866 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#867 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#868 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#869 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#870 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#871 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#872 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#873 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#874 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#875 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#876 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#877 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#878 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#879 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#880 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#881 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#882 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#883 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#884 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#885 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#886 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#887 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#888 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#889 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#890 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#891 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#892 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#893 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#894 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#895 Warning Input pipelining DSP stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst input stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#896 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#897 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#898 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#899 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#900 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#901 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#902 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#903 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#904 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#905 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#906 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#907 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#908 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#909 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#910 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#911 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#912 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#913 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#914 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#915 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#916 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#917 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#918 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#919 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#920 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#921 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#922 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#923 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#924 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#925 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#926 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#927 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#928 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#929 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#930 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#931 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#932 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#933 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#934 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#935 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#936 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#937 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#938 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#939 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#940 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#941 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#942 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#943 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#944 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#945 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#946 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#947 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#948 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#949 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#950 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#951 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#952 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#953 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#954 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#955 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#956 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#957 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#958 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#959 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#960 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#961 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#962 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#963 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#964 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#965 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#966 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#967 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#968 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#969 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#970 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#971 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#972 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#973 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#974 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#975 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#976 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#977 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#978 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#979 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#980 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#981 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#982 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#983 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#984 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#985 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#986 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#987 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#988 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#989 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#990 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#991 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#992 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#993 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#994 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#995 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#996 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#997 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#998 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#999 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1000 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1001 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1002 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1003 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1004 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1005 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1006 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1007 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1008 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1009 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1010 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1011 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1012 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1013 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1014 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1015 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1016 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1017 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1018 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1019 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1020 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1021 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1022 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1023 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1024 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1025 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1026 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1027 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1028 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1029 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1030 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1031 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1032 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1033 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1034 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1035 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1036 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1037 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1038 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1039 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1040 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1041 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1042 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1043 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1044 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1045 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1046 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1047 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1048 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1049 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1050 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1051 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1052 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1053 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1054 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1055 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1056 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1057 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1058 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1059 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1060 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1061 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1062 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1063 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1064 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1065 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1066 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1067 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1068 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1069 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1070 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1071 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1072 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1073 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1074 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1075 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1076 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1077 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1078 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1079 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1080 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1081 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1082 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1083 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1084 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1085 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1086 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1087 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1088 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1089 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1090 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1091 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1092 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1093 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1094 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1095 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1096 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1097 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1098 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1099 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1100 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1101 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1102 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1103 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1104 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1105 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1106 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1107 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1108 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1109 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1110 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1111 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1112 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1113 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1114 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1115 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1116 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1117 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1118 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1119 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1120 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1121 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1122 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1123 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1124 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1125 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1126 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1127 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1128 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1129 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1130 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1131 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1132 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1133 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1134 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1135 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1136 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1137 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1138 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1139 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1140 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1141 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1142 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1143 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1144 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1145 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1146 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1147 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1148 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1149 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1150 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1151 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1152 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1153 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1154 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1155 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1156 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1157 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1158 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1159 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1160 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1161 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1162 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1163 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1164 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1165 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1166 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1167 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1168 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1169 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1170 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1171 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1172 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1173 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1174 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1175 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1176 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1177 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1178 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1179 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1180 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1181 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1182 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1183 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1184 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1185 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1186 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1187 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1188 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1189 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1190 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1191 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1192 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1193 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1194 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1195 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1196 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1197 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1198 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1199 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1200 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1201 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1202 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1203 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1204 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1205 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1206 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1207 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1208 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1209 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1210 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1211 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1212 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1213 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1214 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1215 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1216 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1217 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1218 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1219 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1220 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1221 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1222 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1223 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1224 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1225 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1226 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1227 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1228 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1229 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1230 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1231 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1232 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1233 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1234 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1235 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1236 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1237 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1238 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1239 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1240 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1241 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1242 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1243 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1244 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1245 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1246 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1247 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1248 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1249 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1250 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1251 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1252 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1253 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1254 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1255 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1256 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1257 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1258 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1259 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1260 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1261 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1262 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1263 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1264 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1265 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1266 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1267 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1268 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1269 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1270 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1271 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1272 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1273 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1274 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1275 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1276 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1277 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1278 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1279 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1280 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1281 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1282 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1283 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1284 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1285 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1286 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1287 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1288 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1289 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1290 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1291 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1292 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1293 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1294 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1295 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1296 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1297 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1298 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1299 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1300 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1301 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1302 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1303 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1304 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1305 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1306 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1307 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1308 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1309 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1310 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1311 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1312 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1313 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1314 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1315 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1316 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1317 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1318 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1319 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1320 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1321 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1322 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1323 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1324 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1325 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1326 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1327 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1328 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1329 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1330 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1331 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1332 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1333 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1334 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1335 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1336 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1337 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1338 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1339 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1340 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1341 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1342 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1343 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1344 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1345 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1346 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1347 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1348 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1349 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1350 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1351 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1352 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1353 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1354 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1355 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1356 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1357 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1358 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1359 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1360 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1361 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1362 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1363 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1364 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1365 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1366 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1367 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1368 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1369 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1370 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1371 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1372 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1373 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1374 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1375 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1376 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1377 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1378 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1379 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1380 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1381 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1382 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1383 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1384 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1385 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1386 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1387 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1388 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1389 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1390 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1391 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1392 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1393 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1394 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1395 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1396 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1397 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1398 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1399 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1400 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1401 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1402 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1403 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1404 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1405 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1406 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1407 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1408 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1409 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1410 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1411 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1412 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1413 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1414 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1415 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1416 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1417 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1418 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1419 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1420 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1421 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1422 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1423 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1424 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1425 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1426 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1427 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1428 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1429 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1430 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1431 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1432 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1433 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1434 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1435 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1436 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1437 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1438 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1439 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1440 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1441 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1442 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1443 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1444 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1445 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1446 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1447 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1448 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1449 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1450 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1451 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1452 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1453 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1454 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1455 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1456 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1457 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1458 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1459 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1460 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1461 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1462 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1463 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1464 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1465 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1466 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1467 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1468 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1469 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1470 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1471 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1472 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1473 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1474 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1475 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1476 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1477 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1478 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1479 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1480 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1481 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1482 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1483 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1484 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1485 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1486 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1487 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1488 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1489 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1490 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1491 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1492 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1493 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1494 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1495 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1496 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1497 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1498 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1499 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1500 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1501 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1502 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1503 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1504 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1505 Warning Input pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1506 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1507 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1508 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1509 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1510 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1511 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1512 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1513 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1514 Warning Input pipelining DSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst input stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1515 Warning Input pipelining DSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1516 Warning Input pipelining DSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1517 Warning Input pipelining DSP stat_regs_inst/i_DSP_cntr input stat_regs_inst/i_DSP_cntr/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1518 Warning Input pipelining DSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1519 Warning Input pipelining DSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1520 Warning Input pipelining DSP stat_regs_inst/i_DSP_rate input stat_regs_inst/i_DSP_rate/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1521 Warning Input pipelining DSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1522 Warning Input pipelining DSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-2#1523 Warning Input pipelining DSP stat_regs_inst/i_stat_MUX_b/DSP48E2_inst input stat_regs_inst/i_stat_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPOP-3#1 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#2 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#3 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#4 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#5 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#6 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#7 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#8 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#9 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#10 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#11 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#12 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#13 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#14 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#15 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#16 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#17 Warning PREG Output pipelining DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#18 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#19 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#20 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#21 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#22 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#23 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#24 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#25 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#26 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#27 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#28 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#29 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#30 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#31 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#32 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#33 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#34 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#35 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#36 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#37 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#38 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#39 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#40 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#41 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#42 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#43 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#44 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#45 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#46 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#47 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#48 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#49 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#50 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#51 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#52 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#53 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#54 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#55 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#56 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#57 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#58 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#59 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#60 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#61 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#62 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#63 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#64 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#65 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#66 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#67 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#68 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#69 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#70 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#71 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#72 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#73 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#74 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#75 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#76 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#77 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#78 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#79 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#80 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#81 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#82 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#83 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#84 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#85 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#86 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#87 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#88 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#89 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#90 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#91 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#92 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#93 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#94 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#95 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#96 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#97 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#98 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#99 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#100 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#101 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#102 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#103 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#104 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#105 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#106 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#107 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#108 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#109 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#110 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#111 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#112 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#113 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#114 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#115 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#116 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#117 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#118 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#119 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#120 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#121 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#122 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#123 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#124 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#125 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#126 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#127 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#128 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#129 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#130 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#131 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#132 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#133 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#134 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#135 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#136 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#137 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#138 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#139 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#140 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#141 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#142 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#143 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#144 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#145 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#146 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#147 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#148 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#149 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#150 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#151 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#152 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#153 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#154 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#155 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#156 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#157 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#158 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#159 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#160 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#161 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#162 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#163 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#164 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#165 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#166 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#167 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#168 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#169 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#170 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#171 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#172 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#173 Warning PREG Output pipelining DSP stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#174 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#175 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#176 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#177 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#178 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#179 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#180 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#181 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#182 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#183 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#184 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#185 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#186 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#187 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#188 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#189 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#190 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#191 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#192 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#193 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#194 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#195 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#196 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#197 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#198 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#199 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#200 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#201 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#202 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#203 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#204 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#205 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#206 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#207 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#208 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#209 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#210 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#211 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#212 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#213 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#214 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#215 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#216 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#217 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#218 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#219 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#220 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#221 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#222 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#223 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#224 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#225 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#226 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#227 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#228 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#229 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#230 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#231 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#232 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#233 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#234 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#235 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#236 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#237 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#238 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#239 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#240 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#241 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#242 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#243 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#244 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#245 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#246 Warning PREG Output pipelining DSP stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#247 Warning PREG Output pipelining DSP stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst output stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#248 Warning PREG Output pipelining DSP stat_regs_inst/i_DSP_cntr output stat_regs_inst/i_DSP_cntr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-3#249 Warning PREG Output pipelining DSP stat_regs_inst/i_DSP_rate output stat_regs_inst/i_DSP_rate/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPREG-7#1 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#2 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#3 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#4 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#5 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#6 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#7 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#8 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#9 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#10 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#11 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#12 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#13 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#14 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#15 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#16 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#17 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#18 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#19 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#20 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#21 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#22 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#23 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#24 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#25 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#26 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#27 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#28 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#29 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#30 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#31 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#32 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#33 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#34 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#35 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#36 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#37 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#38 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#39 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#40 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#41 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#42 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#43 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#44 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#45 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#46 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#47 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#48 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#49 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#50 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#51 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#52 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#53 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#54 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#55 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#56 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#57 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#58 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#59 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#60 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#61 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#62 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#63 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#64 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#65 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#66 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#67 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#68 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#69 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#70 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#71 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#72 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#73 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#74 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#75 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#76 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#77 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#78 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#79 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#80 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#81 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#82 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#83 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#84 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#85 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#86 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#87 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#88 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#89 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#90 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#91 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#92 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#93 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#94 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#95 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#96 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#97 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#98 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#99 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#100 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#101 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#102 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#103 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#104 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#105 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#106 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#107 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#108 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#109 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#110 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#111 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#112 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#113 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#114 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#115 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#116 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#117 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#118 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#119 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#120 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#121 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#122 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#123 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#124 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#125 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#126 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#127 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#128 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#129 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#130 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#131 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#132 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#133 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#134 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#135 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#136 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#137 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#138 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#139 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#140 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#141 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#142 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#143 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#144 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#145 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#146 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#147 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#148 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#149 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#150 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#151 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#152 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#153 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#154 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#155 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#156 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#157 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#158 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#159 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#160 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#161 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#162 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#163 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#164 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#165 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#166 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#167 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#168 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#169 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#170 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#171 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#172 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#173 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#174 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#175 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#176 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#177 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#178 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#179 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#180 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#181 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#182 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#183 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#184 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#185 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#186 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#187 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#188 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#189 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#190 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#191 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#192 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#193 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#194 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#195 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#196 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#197 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#198 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#199 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#200 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#201 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#202 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#203 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#204 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#205 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#206 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#207 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#208 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#209 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#210 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#211 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#212 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#213 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#214 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#215 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#216 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#217 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#218 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#219 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#220 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#221 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#222 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#223 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#224 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#225 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#226 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#227 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#228 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#229 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#230 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#231 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#232 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#233 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#234 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#235 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#236 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#237 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#238 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#239 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#240 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#241 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#242 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#243 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#244 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#245 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#246 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#247 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#248 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#249 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#250 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#251 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#252 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#253 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#254 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#255 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#256 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#257 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#258 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#259 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#260 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#261 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#262 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#263 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#264 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#265 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#266 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#267 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#268 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#269 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#270 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#271 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#272 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#273 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#274 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#275 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#276 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#277 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#278 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#279 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#280 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#281 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#282 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#283 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#284 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#285 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#286 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#287 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#288 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#289 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#290 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#291 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#292 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#293 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#294 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#295 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#296 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#297 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#298 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#299 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#300 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#301 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#302 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#303 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#304 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#305 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#306 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#307 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#308 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#309 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#310 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#311 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#312 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#313 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#314 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#315 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#316 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#317 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#318 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#319 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#320 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#321 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#322 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#323 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#324 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#325 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#326 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#327 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#328 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#329 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#330 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#331 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#332 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#333 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#334 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#335 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#336 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#337 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#338 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#339 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#340 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#341 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#342 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#343 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#344 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#345 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#346 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#347 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#348 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#349 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#350 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#351 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#352 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#353 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#354 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#355 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#356 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#357 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#358 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#359 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#360 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#361 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#362 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#363 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#364 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#365 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#366 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#367 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#368 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#369 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#370 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#371 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#372 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#373 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#374 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#375 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#376 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#377 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#378 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#379 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#380 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#381 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#382 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#383 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#384 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#385 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#386 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#387 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#388 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#389 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#390 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#391 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#392 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#393 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#394 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#395 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#396 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#397 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#398 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#399 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#400 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#401 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#402 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#403 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#404 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#405 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#406 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#407 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#408 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#409 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#410 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#411 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#412 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#413 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#414 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#415 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#416 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#417 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#418 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#419 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#420 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#421 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#422 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#423 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#424 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#425 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#426 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#427 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#428 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#429 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#430 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#431 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#432 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#433 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#434 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#435 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#436 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#437 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#438 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#439 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#440 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#441 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#442 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#443 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#444 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#445 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#446 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#447 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#448 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#449 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#450 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#451 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#452 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#453 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#454 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#455 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#456 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#457 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#458 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#459 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#460 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#461 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#462 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#463 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#464 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#465 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#466 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#467 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#468 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#469 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#470 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#471 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#472 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#473 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#474 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#475 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#476 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#477 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: DPREG-7#478 Warning DSP48E2_PregDynOpmodeZmuxP: The DSP48E2 cell stat_regs_inst/i_stat_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 Related violations: IOBUSSLRC-1#1 Warning IO Bus SLR Crossings Bus port GBT_refclk1_n spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. Related violations: IOBUSSLRC-1#2 Warning IO Bus SLR Crossings Bus port GBT_refclk1_p spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. Related violations: IOBUSSLRC-1#3 Warning IO Bus SLR Crossings Bus port GBT_rxn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Related violations: IOBUSSLRC-1#4 Warning IO Bus SLR Crossings Bus port GBT_rxp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Related violations: IOBUSSLRC-1#5 Warning IO Bus SLR Crossings Bus port GBT_txn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Related violations: IOBUSSLRC-1#6 Warning IO Bus SLR Crossings Bus port GBT_txp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. Related violations: AVAL-155#1 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#2 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#3 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#4 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#5 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#6 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#7 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#8 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#9 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#10 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#11 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#12 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#13 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#14 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#15 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#16 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#17 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#18 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#19 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#20 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#21 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#22 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#23 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#24 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#25 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#26 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#27 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#28 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#29 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#30 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#31 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#32 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#33 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#34 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#35 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#36 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#37 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#38 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#39 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#40 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#41 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#42 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#43 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#44 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#45 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#46 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#47 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#48 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#49 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#50 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#51 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#52 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#53 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#54 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#55 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#56 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#57 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#58 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#59 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#60 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#61 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#62 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#63 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#64 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#65 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#66 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#67 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#68 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#69 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#70 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#71 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#72 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#73 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#74 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#75 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#76 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#77 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#78 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#79 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#80 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#81 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#82 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#83 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#84 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#85 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#86 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#87 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#88 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#89 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#90 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#91 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#92 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#93 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#94 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#95 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#96 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#97 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#98 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#99 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#100 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#101 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#102 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#103 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#104 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#105 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#106 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#107 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#108 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#109 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#110 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#111 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#112 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#113 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#114 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#115 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#116 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#117 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#118 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#119 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#120 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#121 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#122 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#123 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#124 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#125 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#126 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#127 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#128 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#129 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#130 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#131 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#132 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#133 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#134 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#135 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#136 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#137 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#138 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#139 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#140 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#141 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#142 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#143 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#144 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#145 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#146 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#147 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#148 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#149 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#150 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#151 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#152 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#153 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#154 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#155 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#156 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#157 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#158 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#159 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#160 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#161 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#162 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#163 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#164 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#165 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#166 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#167 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#168 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#169 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#170 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#171 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#172 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#173 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#174 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#175 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#176 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#177 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#178 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#179 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#180 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#181 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#182 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#183 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#184 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#185 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#186 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#187 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#188 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#189 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#190 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#191 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#192 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#193 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#194 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#195 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#196 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#197 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#198 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#199 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#200 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#201 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#202 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#203 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#204 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#205 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#206 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#207 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#208 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#209 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#210 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#211 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#212 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#213 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#214 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#215 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#216 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#217 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#218 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#219 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#220 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#221 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#222 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#223 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#224 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#225 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#226 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#227 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#228 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#229 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#230 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#231 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#232 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#233 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#234 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#235 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#236 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#237 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#238 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#239 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#240 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#241 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#242 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#243 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#244 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#245 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#246 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#247 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#248 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#249 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#250 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#251 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#252 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#253 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#254 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#255 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#256 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#257 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#258 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#259 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#260 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#261 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#262 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#263 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#264 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#265 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#266 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#267 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#268 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#269 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#270 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#271 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#272 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#273 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#274 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#275 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#276 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#277 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#278 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#279 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#280 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#281 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#282 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#283 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#284 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#285 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#286 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#287 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#288 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#289 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#290 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#291 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#292 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#293 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#294 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#295 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#296 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#297 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#298 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#299 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#300 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#301 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#302 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#303 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#304 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#305 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#306 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#307 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#308 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#309 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#310 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#311 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#312 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#313 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#314 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#315 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#316 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#317 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#318 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#319 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#320 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#321 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#322 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#323 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#324 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#325 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#326 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#327 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#328 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#329 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#330 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#331 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#332 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#333 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#334 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#335 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#336 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#337 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#338 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#339 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#340 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#341 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#342 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#343 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#344 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#345 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#346 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#347 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#348 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#349 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#350 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#351 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#352 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#353 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#354 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#355 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#356 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#357 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#358 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#359 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#360 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#361 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#362 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#363 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#364 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#365 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#366 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#367 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#368 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#369 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#370 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#371 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#372 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#373 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#374 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#375 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#376 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#377 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#378 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#379 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#380 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#381 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-155#382 Advisory enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#1 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#2 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#3 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#4 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#5 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#6 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#7 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#8 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#9 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#10 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#11 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#12 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#13 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#14 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#15 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#16 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#17 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#18 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#19 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#20 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#21 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#22 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#23 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#24 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#25 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#26 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#27 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#28 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#29 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#30 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#31 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#32 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#33 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#34 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#35 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#36 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#37 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#38 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#39 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#40 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#41 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#42 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#43 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#44 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#45 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#46 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#47 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#48 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#49 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#50 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#51 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#52 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#53 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#54 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#55 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#56 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#57 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#58 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#59 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#60 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#61 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#62 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#63 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#64 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#65 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#66 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#67 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#68 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#69 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#70 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#71 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#72 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#73 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#74 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#75 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#76 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#77 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#78 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#79 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#80 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#81 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#82 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#83 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#84 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#85 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#86 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#87 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#88 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#89 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#90 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#91 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#92 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#93 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#94 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#95 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#96 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#97 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#98 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#99 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#100 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#101 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#102 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#103 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#104 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#105 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#106 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#107 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#108 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#109 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#110 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#111 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#112 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#113 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#114 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#115 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#116 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#117 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#118 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#119 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#120 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#121 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#122 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#123 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#124 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#125 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#126 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#127 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#128 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#129 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#130 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#131 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#132 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#133 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#134 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#135 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#136 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#137 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#138 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#139 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#140 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#141 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#142 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#143 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#144 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#145 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#146 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#147 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#148 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#149 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#150 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#151 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#152 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#153 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#154 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#155 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#156 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#157 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#158 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#159 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#160 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#161 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#162 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#163 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#164 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#165 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#166 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#167 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#168 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#169 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#170 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#171 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#172 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#173 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#174 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#175 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#176 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#177 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#178 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#179 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#180 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#181 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#182 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#183 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#184 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#185 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[1].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#186 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#187 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#188 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#189 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#190 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#191 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#192 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#193 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#194 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#195 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#196 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#197 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#198 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#199 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#200 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#201 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#202 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#203 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#204 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#205 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#206 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#207 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#208 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#209 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#210 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#211 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#212 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#213 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#214 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#215 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#216 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#217 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[2].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#218 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#219 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#220 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#221 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#222 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#223 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#224 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#225 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#226 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#227 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#228 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#229 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#230 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#231 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#232 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#233 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#234 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#235 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#236 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#237 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#238 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#239 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#240 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#241 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#242 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#243 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#244 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#245 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#246 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#247 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#248 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#249 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[3].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#250 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#251 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#252 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#253 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#254 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#255 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#256 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#257 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#258 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#259 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#260 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#261 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#262 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#263 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#264 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#265 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#266 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#267 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#268 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#269 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#270 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#271 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#272 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#273 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#274 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#275 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#276 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#277 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#278 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#279 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#280 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#281 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[4].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#282 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#283 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#284 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#285 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#286 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#287 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#288 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#289 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#290 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#291 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#292 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#293 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#294 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#295 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#296 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#297 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#298 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#299 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#300 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#301 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#302 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#303 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#304 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#305 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#306 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#307 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#308 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#309 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#310 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#311 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#312 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#313 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[5].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#314 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#315 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#316 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#317 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#318 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#319 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#320 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#321 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#322 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#323 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#324 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#325 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#326 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#327 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#328 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#329 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#330 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#331 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#332 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#333 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#334 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#335 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#336 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#337 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#338 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#339 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#340 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#341 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#342 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#343 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#344 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#345 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[6].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#346 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#347 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#348 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#349 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#350 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#351 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#352 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#353 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#354 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#355 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#356 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#357 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#358 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#359 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#360 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#361 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#362 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#363 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#364 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#365 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#366 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#367 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#368 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#369 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#370 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#371 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#372 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#373 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#374 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#375 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#376 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#377 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/g_stat_MUX_k[7].g_stat_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#378 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#379 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#380 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#381 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: AVAL-156#382 Advisory enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND stat_regs_inst/i_stat_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Related violations: REQP-1669#1 Advisory enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. Related violations: REQP-1669#2 Advisory enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND stat_regs_inst/i_DSP_rate: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. Related violations: REQP-1671#1 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#2 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#3 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#4 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#5 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#6 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#7 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#8 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#9 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#10 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#11 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#12 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#13 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#14 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#15 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#16 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#17 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#18 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#19 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#20 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#21 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#22 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#23 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#24 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#25 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#26 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#27 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#28 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#29 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#30 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#31 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#32 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#33 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#34 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#35 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#36 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#37 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#38 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#39 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#40 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#41 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#42 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#43 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#44 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#45 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#46 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#47 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#48 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#49 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#50 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#51 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#52 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#53 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#54 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#55 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#56 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#57 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#58 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#59 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#60 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#61 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#62 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#63 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#64 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#65 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#66 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#67 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#68 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#69 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#70 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#71 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#72 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#73 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#74 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#75 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#76 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#77 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#78 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#79 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#80 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#81 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#82 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#83 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#84 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#85 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#86 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#87 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#88 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#89 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#90 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#91 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#92 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#93 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#94 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#95 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#96 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#97 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#98 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#99 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#100 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#101 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#102 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#103 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#104 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#105 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#106 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#107 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#108 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#109 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#110 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#111 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#112 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#113 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#114 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#115 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#116 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#117 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#118 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#119 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#120 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#121 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#122 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#123 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#124 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#125 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#126 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#127 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#128 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#129 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#130 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#131 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#132 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#133 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#134 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#135 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#136 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#137 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#138 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1671#139 Advisory enum_AREG_1_connects_CEA1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1673#1 Advisory enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. Related violations: REQP-1673#2 Advisory enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND stat_regs_inst/i_DSP_rate: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. Related violations: REQP-1675#1 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#2 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#3 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#4 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#5 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#6 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#7 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#8 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#9 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#10 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#11 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#12 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#13 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#14 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#15 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#16 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#17 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#18 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#19 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#20 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#21 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#22 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#23 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#24 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#25 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#26 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#27 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#28 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#29 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#30 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#31 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#32 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#33 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#34 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#35 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#36 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#37 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#38 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#39 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#40 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#41 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#42 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#43 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#44 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#45 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#46 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#47 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#48 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#49 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#50 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#51 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#52 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#53 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#54 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#55 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#56 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#57 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#58 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#59 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#60 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#61 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#62 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#63 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#64 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#65 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#66 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#67 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#68 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#69 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#70 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#71 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#72 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#73 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#74 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#75 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#76 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#77 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#78 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#79 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#80 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#81 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#82 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#83 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#84 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#85 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#86 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#87 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#88 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#89 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#90 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#91 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#92 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#93 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#94 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#95 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#96 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#97 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#98 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#99 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#100 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#101 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#102 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#103 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#104 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#105 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#106 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#107 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#108 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#109 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#110 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#111 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#112 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#113 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#114 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#115 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#116 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#117 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#118 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#119 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#120 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#121 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#122 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#123 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#124 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#125 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#126 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#127 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#128 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#129 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#130 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#131 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#132 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#133 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#134 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#135 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#136 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#137 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#138 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1675#139 Advisory enum_BREG_1_connects_CEB1_GND stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. Related violations: REQP-1678#1 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#2 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#3 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#4 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#5 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#6 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#7 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#8 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#9 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#10 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#11 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#12 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#13 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#14 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#15 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#16 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#17 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#18 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#19 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#20 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#21 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#22 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#23 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#24 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#25 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#26 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#27 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#28 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#29 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#30 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#31 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#32 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#33 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#34 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#35 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#36 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#37 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#38 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#39 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#40 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#41 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#42 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#43 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#44 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#45 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#46 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#47 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#48 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#49 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#50 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#51 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#52 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#53 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#54 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#55 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#56 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#57 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#58 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#59 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#60 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#61 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#62 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#63 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#64 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#65 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#66 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#67 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#68 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#69 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#70 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#71 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#72 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#73 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#74 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#75 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#76 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#77 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#78 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#79 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#80 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#81 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#82 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#83 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#84 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#85 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#86 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#87 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#88 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#89 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#90 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#91 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#92 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#93 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#94 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#95 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#96 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#97 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#98 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#99 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#100 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#101 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#102 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#103 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#104 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#105 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#106 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#107 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#108 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#109 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#110 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#111 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#112 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#113 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#114 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#115 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#116 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#117 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#118 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#119 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#120 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#121 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#122 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#123 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#124 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#125 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#126 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#127 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#128 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#129 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#130 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#131 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#132 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#133 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#134 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#135 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#136 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#137 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#138 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#139 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#140 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#141 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#142 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#143 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#144 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#145 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#146 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#147 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#148 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#149 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#150 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#151 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#152 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#153 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#154 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#155 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#156 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#157 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#158 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#159 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#160 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#161 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#162 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#163 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#164 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#165 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#166 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#167 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#168 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#169 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#170 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#171 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#172 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#173 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#174 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#175 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#176 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#177 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#178 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#179 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#180 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#181 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#182 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#183 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#184 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#185 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#186 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#187 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#188 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#189 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#190 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#191 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#192 Advisory enum_CREG_0_connects_CEC_GND g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#193 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#194 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#195 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#196 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#197 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#198 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#199 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#200 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#201 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#202 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#203 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#204 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#205 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#206 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#207 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#208 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#209 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#210 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#211 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#212 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#213 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#214 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#215 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#216 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#217 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#218 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#219 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#220 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#221 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#222 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#223 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#224 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#225 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#226 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#227 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#228 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#229 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#230 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#231 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#232 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#233 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#234 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#235 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#236 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#237 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#238 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#239 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#240 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#241 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#242 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#243 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#244 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#245 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#246 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#247 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#248 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#249 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#250 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#251 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#252 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#253 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#254 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#255 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#256 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#257 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#258 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#259 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#260 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#261 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#262 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#263 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#264 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#265 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#266 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#267 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#268 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#269 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#270 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#271 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#272 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#273 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#274 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#275 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#276 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#277 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#278 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#279 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#280 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#281 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#282 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#283 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#284 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#285 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#286 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#287 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#288 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#289 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#290 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#291 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#292 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#293 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#294 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#295 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#296 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#297 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#298 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#299 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#300 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#301 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#302 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#303 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#304 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#305 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#306 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#307 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#308 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#309 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#310 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#311 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#312 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#313 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#314 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#315 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#316 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#317 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#318 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#319 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#320 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#321 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#322 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#323 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#324 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#325 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#326 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#327 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#328 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#329 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#330 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#331 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#332 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#333 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#334 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#335 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#336 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#337 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#338 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#339 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#340 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#341 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#342 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#343 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#344 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#345 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#346 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#347 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#348 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#349 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#350 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#351 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#352 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#353 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#354 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#355 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#356 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#357 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#358 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#359 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#360 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#361 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#362 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#363 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#364 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#365 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#366 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#367 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#368 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#369 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#370 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#371 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#372 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#373 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#374 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#375 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#376 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#377 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#378 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#379 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#380 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#381 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#382 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#383 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#384 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#385 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/i_DSP_cntr: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1678#386 Advisory enum_CREG_0_connects_CEC_GND stat_regs_inst/i_DSP_rate: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. Related violations: REQP-1680#1 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#2 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#3 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#4 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#5 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#6 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#7 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#8 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#9 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#10 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#11 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#12 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#13 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#14 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#15 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#16 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#17 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#18 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#19 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#20 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#21 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#22 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#23 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#24 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#25 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#26 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#27 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#28 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#29 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#30 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#31 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#32 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#33 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#34 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#35 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#36 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#37 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#38 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#39 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#40 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#41 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#42 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#43 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#44 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#45 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#46 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#47 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#48 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#49 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#50 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#51 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#52 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#53 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#54 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#55 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#56 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#57 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#58 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#59 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#60 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#61 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#62 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#63 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#64 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#65 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#66 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#67 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#68 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#69 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#70 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#71 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#72 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#73 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#74 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#75 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#76 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#77 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#78 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#79 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#80 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#81 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#82 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#83 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#84 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#85 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#86 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#87 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#88 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#89 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#90 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#91 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#92 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#93 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#94 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#95 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#96 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#97 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#98 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#99 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#100 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#101 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#102 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#103 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#104 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#105 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#106 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#107 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#108 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#109 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#110 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#111 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#112 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#113 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#114 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#115 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#116 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#117 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#118 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#119 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#120 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#121 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#122 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#123 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#124 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#125 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#126 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#127 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#128 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#129 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/i_DSP_cntr: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1680#130 Advisory enum_PREG_0_connects_CEP_GND stat_regs_inst/i_DSP_rate: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. Related violations: REQP-1681#1 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#2 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#3 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#4 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#5 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#6 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#7 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#8 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#9 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#10 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1681#11 Advisory with_OPMODE_USE_MULT_NONE stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. Related violations: REQP-1934#1 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#2 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#3 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#4 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#5 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#6 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#7 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#8 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#9 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#10 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#11 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#12 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#13 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#14 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#15 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#16 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#17 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#18 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#19 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#20 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#21 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#22 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#23 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#24 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#25 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#26 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#27 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#28 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#29 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#30 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#31 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#32 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#33 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#34 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#35 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#36 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#37 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#38 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#39 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#40 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#41 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#42 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#43 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#44 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#45 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#46 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#47 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#48 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#49 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#50 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#51 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#52 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#53 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#54 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#55 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#56 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#57 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#58 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#59 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#60 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#61 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#62 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#63 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#64 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#65 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#66 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#67 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#68 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#69 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#70 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#71 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#72 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#73 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#74 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#75 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#76 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#77 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#78 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#79 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#80 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#81 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#82 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#83 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#84 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#85 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#86 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#87 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#88 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#89 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#90 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#91 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#92 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#93 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#94 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#95 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#96 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#97 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#98 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#99 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#100 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#101 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#102 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#103 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#104 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#105 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#106 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#107 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#108 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#109 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#110 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#111 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#112 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#113 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#114 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#115 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#116 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#117 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#118 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#119 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#120 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#121 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#122 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#123 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#124 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#125 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#126 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[17].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#127 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#128 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#129 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#130 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#131 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#132 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#133 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#134 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#135 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#136 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#137 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#138 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#139 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#140 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[18].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#141 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#142 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#143 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#144 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#145 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#146 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#147 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#148 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#149 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#150 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#151 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#152 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#153 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#154 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[19].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#155 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#156 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#157 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#158 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#159 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#160 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#161 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#162 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#163 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#164 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#165 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#166 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#167 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#168 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[1].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#169 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#170 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#171 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#172 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#173 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#174 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#175 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#176 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#177 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#178 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#179 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#180 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#181 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#182 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[20].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#183 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#184 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#185 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#186 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#187 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#188 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#189 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#190 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#191 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#192 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#193 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#194 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#195 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#196 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#197 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#198 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#199 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#200 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#201 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#202 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#203 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#204 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#205 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#206 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#207 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#208 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#209 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#210 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[22].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#211 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#212 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#213 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#214 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#215 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#216 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#217 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#218 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#219 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#220 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#221 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#222 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#223 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#224 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[23].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#225 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#226 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#227 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#228 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#229 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#230 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#231 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#232 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#233 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#234 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#235 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#236 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#237 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#238 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[24].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#239 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#240 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#241 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#242 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#243 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#244 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#245 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#246 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#247 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#248 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#249 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#250 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#251 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#252 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[25].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#253 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#254 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#255 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#256 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#257 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#258 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#259 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#260 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#261 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#262 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#263 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#264 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#265 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#266 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[26].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#267 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#268 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#269 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#270 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#271 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#272 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#273 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#274 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#275 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#276 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#277 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#278 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#279 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#280 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[27].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#281 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#282 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#283 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#284 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#285 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#286 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#287 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#288 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#289 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#290 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#291 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#292 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#293 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#294 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[28].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#295 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#296 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#297 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#298 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#299 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#300 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#301 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#302 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#303 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#304 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#305 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#306 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#307 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#308 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[29].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#309 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#310 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#311 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#312 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#313 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#314 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#315 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#316 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#317 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#318 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#319 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#320 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#321 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#322 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[2].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#323 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#324 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#325 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#326 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#327 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#328 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#329 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#330 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#331 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#332 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#333 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#334 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#335 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#336 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[30].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#337 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#338 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#339 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#340 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#341 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#342 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#343 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#344 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#345 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#346 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#347 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#348 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#349 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#350 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[31].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#351 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#352 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#353 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#354 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#355 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#356 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#357 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#358 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#359 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#360 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#361 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#362 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#363 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#364 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[32].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#365 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#366 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#367 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#368 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#369 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#370 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#371 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#372 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#373 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#374 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#375 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#376 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#377 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#378 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[33].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#379 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#380 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#381 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#382 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#383 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#384 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#385 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#386 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#387 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#388 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#389 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#390 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#391 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#392 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[34].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#393 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#394 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#395 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#396 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#397 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#398 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#399 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#400 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#401 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#402 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#403 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#404 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#405 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#406 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[35].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#407 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#408 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#409 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#410 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#411 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#412 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#413 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#414 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#415 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#416 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#417 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#418 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#419 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#420 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[36].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#421 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#422 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#423 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#424 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#425 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#426 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#427 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#428 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#429 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#430 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#431 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#432 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#433 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#434 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[37].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#435 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#436 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#437 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#438 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#439 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#440 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#441 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#442 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#443 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#444 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#445 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#446 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#447 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#448 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[38].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#449 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#450 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#451 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#452 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#453 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#454 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#455 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#456 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#457 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#458 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#459 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#460 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#461 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#462 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[39].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#463 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#464 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#465 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#466 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#467 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#468 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#469 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#470 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#471 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#472 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#473 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#474 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#475 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#476 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[3].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#477 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#478 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#479 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#480 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#481 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#482 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#483 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#484 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#485 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#486 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#487 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#488 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#489 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#490 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[40].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#491 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#492 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#493 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#494 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#495 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#496 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#497 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#498 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#499 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#500 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#501 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#502 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#503 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#504 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[41].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#505 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#506 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#507 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#508 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#509 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#510 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#511 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#512 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#513 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#514 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#515 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#516 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#517 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#518 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#519 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#520 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#521 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#522 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#523 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#524 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#525 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#526 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#527 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#528 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#529 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#530 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#531 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#532 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[43].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#533 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#534 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#535 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#536 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#537 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#538 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#539 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#540 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#541 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#542 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#543 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#544 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#545 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#546 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[44].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#547 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#548 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#549 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#550 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#551 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#552 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#553 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#554 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#555 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#556 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#557 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#558 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#559 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#560 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[45].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#561 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#562 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#563 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#564 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#565 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#566 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#567 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#568 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#569 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#570 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#571 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#572 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#573 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#574 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[46].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#575 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#576 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#577 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#578 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#579 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#580 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#581 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#582 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#583 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#584 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#585 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#586 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#587 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#588 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[47].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#589 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#590 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#591 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#592 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#593 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#594 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#595 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#596 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#597 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#598 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#599 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#600 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#601 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#602 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[4].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#603 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#604 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#605 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#606 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#607 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#608 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#609 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#610 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#611 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#612 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#613 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#614 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#615 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#616 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[5].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#617 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#618 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#619 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#620 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#621 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#622 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#623 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#624 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#625 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#626 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#627 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#628 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#629 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#630 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[6].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#631 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#632 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#633 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#634 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#635 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#636 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#637 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#638 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#639 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#640 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#641 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#642 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#643 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#644 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[7].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#645 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#646 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#647 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#648 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#649 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#650 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#651 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#652 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#653 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#654 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#655 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#656 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#657 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#658 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[8].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#659 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#660 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#661 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#662 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#663 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#664 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#665 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#666 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#667 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#668 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#669 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#670 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#671 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#672 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (SFP_GEN[9].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#673 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#674 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#675 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#676 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#677 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#678 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#679 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#680 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: REQP-1934#681 Advisory RAMB18E2_nochange_collision_advisory Synchronous clocking is detected for BRAM (i_I2C_if/I2C_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. Related violations: