
z
Command: %s
53*	vivadotcl2I
5link_design -top ngFEC_top -part xcku115-flva2104-1-c2default:defaultZ4-113h px 
g
#Design is defaulting to srcset: %s
437*	planAhead2
	sources_12default:defaultZ12-437h px 
j
&Design is defaulting to constrset: %s
434*	planAhead2
	constrs_12default:defaultZ12-434h px 
[
Loading part %s157*device2(
xcku115-flva2104-1-c2default:defaultZ21-403h px 
¦
-Reading design checkpoint '%s' for cell '%s'
275*project2l
Xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/mgt_ip.dcp2default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip2default:defaultZ1-454h px 
ù
-Reading design checkpoint '%s' for cell '%s'
275*project2~
jd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.dcp2default:default2(
i_axi_slave/i_aurora2default:defaultZ1-454h px 
‹
-Reading design checkpoint '%s' for cell '%s'
275*project2ˆ
td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.dcp2default:default2/
i_axi_slave/i_axi_chip2chip2default:defaultZ1-454h px 
ó
-Reading design checkpoint '%s' for cell '%s'
275*project2n
Zd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/ttc_mgt.dcp2default:default22
i_tcds2_if/i_mgt_wrapper/i_mgt2default:defaultZ1-454h px 
’
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:232default:default2
00:00:232default:default2
3330.2892default:default2
126.4492default:defaultZ17-268h px 
i
-Analyzing %s Unisim elements for replacement
17*netlist2
109142default:defaultZ29-17h px 
k
2Unisim Transformation completed in %s CPU seconds
28*netlist2
152default:defaultZ29-28h px 
x
Netlist was created with %s %s291*project2
Vivado2default:default2
2020.22default:defaultZ1-479h px 
K
)Preparing netlist for logic optimization
349*projectZ1-570h px 
’
$Parsing XDC File [%s] for cell '%s'
848*designutils2Š
td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc2default:default26
 i_axi_slave/i_axi_chip2chip/inst	2default:default8Z20-848h px 
›
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2Š
td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc2default:default26
 i_axi_slave/i_axi_chip2chip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
´
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
½
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2o
Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
³
$Parsing XDC File [%s] for cell '%s'
848*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-848h px 
¼
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2t
^d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc2default:default2n
Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst	2default:default8Z20-847h px 
€
$Parsing XDC File [%s] for cell '%s'
848*designutils2v
`d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc2default:default29
#i_tcds2_if/i_mgt_wrapper/i_mgt/inst	2default:default8Z20-848h px 
‰
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2v
`d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc2default:default29
#i_tcds2_if/i_mgt_wrapper/i_mgt/inst	2default:default8Z20-847h px 
í
$Parsing XDC File [%s] for cell '%s'
848*designutils2•
d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master.xdc2default:default2…
oi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0	2default:default8Z20-848h px 
ö
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2•
d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master.xdc2default:default2…
oi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0	2default:default8Z20-847h px 
ö
$Parsing XDC File [%s] for cell '%s'
848*designutils2Ž
xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_0/synth/aurora_64b66b_0_gt.xdc2default:default2•
i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst	2default:default8Z20-848h px 
ÿ
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2Ž
xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_0/synth/aurora_64b66b_0_gt.xdc2default:default2•
i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst	2default:default8Z20-847h px 

$Parsing XDC File [%s] for cell '%s'
848*designutils2€
jd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.xdc2default:default2/
i_axi_slave/i_aurora/inst	2default:default8Z20-848h px 
Š
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2€
jd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0.xdc2default:default2/
i_axi_slave/i_aurora/inst	2default:default8Z20-847h px 
©
Parsing XDC File [%s]
179*designutils2h
RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc2default:default8Z20-179h px 
Î
%Done setting XDC timing constraints.
35*timing2h
RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc2default:default2
1262default:default8@Z38-35h px 
”
ËThe instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2ö
îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST	îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2"
QPLL1REFCLKSEL2default:default2h
RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc2default:default2
1262default:default8@Z38-277h px 
Á
Deriving generated clocks
2*timing2h
RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc2default:default2
1262default:default8@Z38-2h px 
…
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2 
get_clocks: 2default:default2
00:02:572default:default2
00:01:422default:default2
6324.6522default:default2
1849.2502default:defaultZ17-268h px 
²
Finished Parsing XDC File [%s]
178*designutils2h
RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/constrs_1/ngFEC_pcie.xdc2default:default8Z20-178h px 
™
$Parsing XDC File [%s] for cell '%s'
848*designutils2‘
{d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc2default:default26
 i_axi_slave/i_axi_chip2chip/inst	2default:default8Z20-848h px 
‚
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2 
get_clocks: 2default:default2
00:00:112default:default2
00:00:072default:default2
6333.5592default:default2
0.0002default:defaultZ17-268h px 
¢
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2‘
{d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc2default:default26
 i_axi_slave/i_axi_chip2chip/inst	2default:default8Z20-847h px 
õ
$Parsing XDC File [%s] for cell '%s'
848*designutils2
†d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master_clocks.xdc2default:default2…
oi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0	2default:default8Z20-848h px 
þ
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2
†d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/ip_1/aurora_64b66b_0_fifo_gen_master_clocks.xdc2default:default2…
oi_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0	2default:default8Z20-847h px 
ˆ
$Parsing XDC File [%s] for cell '%s'
848*designutils2‡
qd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0_clocks.xdc2default:default2/
i_axi_slave/i_aurora/inst	2default:default8Z20-848h px 
‘
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2‡
qd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0_clocks.xdc2default:default2/
i_axi_slave/i_aurora/inst	2default:default8Z20-847h px 
l
2%s XPM XDC files have been applied to the design.
665*project2
62default:defaultZ1-1715h px 
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138h px 
‘
'Inserted BUFG_GT_SYNC %s for BUFG_GT %s303*opt2á
Ìi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC2default:default2e
Qi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst2default:defaultZ31-441h px 
“
'Inserted BUFG_GT_SYNC %s for BUFG_GT %s303*opt2ã
Îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_12default:default2e
Qi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst2default:defaultZ31-441h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:012default:default2 
00:00:00.4152default:default2
6333.5592default:default2
0.0002default:defaultZ17-268h px 
à
!Unisim Transformation Summary:
%s111*project2š
…  A total of 1045 instances were transformed.
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances
  IBUF => IBUF (IBUFCTRL, INBUF): 16 instances
  IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances
  RAM64M8 => RAM64M8 (RAMD64E(x8)): 4 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 4 instances
2default:defaultZ1-111h px 
Æ
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
162default:default2
12default:default2
02default:default2
02default:defaultZ4-41h px 
]
%s completed successfully
29*	vivadotcl2
link_design2default:defaultZ4-42h px 
†
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2!
link_design: 2default:default2
00:08:192default:default2
00:06:502default:default2
6333.5592default:default2
5305.7582default:defaultZ17-268h px 


End Record