Command: %s 53* vivadotcl2j Vsynth_design -top axi_chip2chip_64B66B -part xcku115-flva2104-1-c -mode out_of_context2default:defaultZ4-113hpx : Starting synth_design 149* vivadotclZ4-321hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2 Synthesis2default:default2 xcku1152default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2 Synthesis2default:default2 xcku1152default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2021.012default:defaultZ17-1540hpx [ Loading part %s157*device2( xcku115-flva2104-1-c2default:defaultZ21-403hpx  HMultithreading enabled for synth_design using a maximum of %s processes.4828*oasys2 22default:defaultZ8-7079hpx a ?Launching helper process for spawning children vivado processes4827*oasysZ8-7078hpx ` #Helper process launched with PID %s4824*oasys2 159962default:defaultZ8-7075hpx  %s *synth2 yStarting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1453.801 ; gain = 254.152 2default:defaulthp x   synthesizing module '%s'%s4497*oasys2( axi_chip2chip_64B66B2default:default2 2default:default2 xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/synth/axi_chip2chip_64B66B.v2default:default2 582default:default8@Z8-6157hpx  synthesizing module '%s'%s4497*oasys2" xpm_fifo_async2default:default2 2default:default2R Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter USE_MEM_INIT bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter MEMORY_OPTIMIZATION bound to: true - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter WAKEUP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter MESSAGE_CONTROL bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter CASCADE_HEIGHT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter WRITE_PROTECT bound to: 1 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter WRITE_DATA_WIDTH_A bound to: 50 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter READ_DATA_WIDTH_A bound to: 50 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter BYTE_WRITE_WIDTH_A bound to: 50 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_A bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_A bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_A bound to: SYNC - type: string 2default:defaulthp x  h %s *synth2P < Parameter WRITE_DATA_WIDTH_B bound to: 50 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter READ_DATA_WIDTH_B bound to: 50 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter BYTE_WRITE_WIDTH_B bound to: 50 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_B bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_B bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_B bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_B bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_B bound to: SYNC - type: string 2default:defaulthp x  j %s *synth2R > Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 2default:defaulthp x  h %s *synth2P < Parameter P_MIN_WIDTH_DATA_A bound to: 50 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_MIN_WIDTH_DATA_B bound to: 50 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_MIN_WIDTH_DATA bound to: 50 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_MIN_WIDTH_DATA_ECC bound to: 50 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter P_ECC_MODE bound to: no_ecc - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter P_MEMORY_OPT bound to: yes - type: string 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_COL_WRITE_A bound to: 50 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_COL_WRITE_B bound to: 50 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter P_SDP_WRITE_MODE bound to: no - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter rsta_loop_iter bound to: 52 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter rstb_loop_iter bound to: 52 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter NUM_CHAR_LOC bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter MAX_NUM_CHAR bound to: 0 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter P_MIN_WIDTH_DATA_SHFT bound to: 50 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys2# xpm_memory_base2default:default2 2default:default2 82default:default2 12default:default2V @D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2 572default:default8@Z8-6155hpx  synthesizing module '%s'%s4497*oasys2 xpm_cdc_gray2default:default2 2default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6157hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 3 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 1 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter REG_OUTPUT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  Z %s *synth2B . Parameter WIDTH bound to: 8 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys2 xpm_cdc_gray2default:default2 2default:default2 92default:default2 12default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6155hpx  synthesizing module '%s'%s4497*oasys2$ xpm_fifo_reg_vec2default:default2 2default:default2R Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  Z %s *synth2B . Parameter WIDTH bound to: 9 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys20 xpm_cdc_gray__parameterized02default:default2 2default:default2 102default:default2 12default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6155hpx  synthesizing module '%s'%s4497*oasys24 xpm_fifo_reg_vec__parameterized02default:default2 2default:default2R Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  Z %s *synth2B . Parameter WIDTH bound to: 9 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys20 xpm_cdc_gray__parameterized12default:default2 2default:default2 102default:default2 12default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6155hpx  default block is never used226*oasys2R Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter USE_MEM_INIT bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter MEMORY_OPTIMIZATION bound to: true - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter WAKEUP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter MESSAGE_CONTROL bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter CASCADE_HEIGHT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter WRITE_PROTECT bound to: 1 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter WRITE_DATA_WIDTH_A bound to: 41 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter READ_DATA_WIDTH_A bound to: 41 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter BYTE_WRITE_WIDTH_A bound to: 41 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_A bound to: 9 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_A bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_A bound to: SYNC - type: string 2default:defaulthp x  h %s *synth2P < Parameter WRITE_DATA_WIDTH_B bound to: 41 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter READ_DATA_WIDTH_B bound to: 41 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter BYTE_WRITE_WIDTH_B bound to: 41 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_B bound to: 9 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_B bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_B bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_B bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_B bound to: SYNC - type: string 2default:defaulthp x  j %s *synth2R > Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 2default:defaulthp x  h %s *synth2P < Parameter P_MIN_WIDTH_DATA_A bound to: 41 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_MIN_WIDTH_DATA_B bound to: 41 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_MIN_WIDTH_DATA bound to: 41 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_MIN_WIDTH_DATA_ECC bound to: 41 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter P_ECC_MODE bound to: no_ecc - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter P_MEMORY_OPT bound to: yes - type: string 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_COL_WRITE_A bound to: 41 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_COL_WRITE_B bound to: 41 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter P_SDP_WRITE_MODE bound to: no - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter rsta_loop_iter bound to: 44 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter rstb_loop_iter bound to: 44 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter NUM_CHAR_LOC bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter MAX_NUM_CHAR bound to: 0 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter P_MIN_WIDTH_DATA_SHFT bound to: 41 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys23 xpm_memory_base__parameterized02default:default2 2default:default2 182default:default2 12default:default2V @D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2 572default:default8@Z8-6155hpx  synthesizing module '%s'%s4497*oasys20 xpm_cdc_gray__parameterized22default:default2 2default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6157hpx a %s *synth2I 5 Parameter DEST_SYNC_FF bound to: 5 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter INIT_SYNC_FF bound to: 1 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter REG_OUTPUT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  [ %s *synth2C / Parameter WIDTH bound to: 10 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys20 xpm_cdc_gray__parameterized22default:default2 2default:default2 182default:default2 12default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6155hpx  synthesizing module '%s'%s4497*oasys24 xpm_fifo_reg_vec__parameterized12default:default2 2default:default2R Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  [ %s *synth2C / Parameter WIDTH bound to: 10 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys20 xpm_cdc_gray__parameterized32default:default2 2default:default2 182default:default2 12default:default2P :D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2 2842default:default8@Z8-6155hpx  default block is never used226*oasys2R Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter USE_MEM_INIT bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter MEMORY_OPTIMIZATION bound to: true - type: string 2default:defaulthp x  ` %s *synth2H 4 Parameter WAKEUP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 2default:defaulthp x  d %s *synth2L 8 Parameter MESSAGE_CONTROL bound to: 0 - type: integer 2default:defaulthp x  \ %s *synth2D 0 Parameter VERSION bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter CASCADE_HEIGHT bound to: 0 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter WRITE_PROTECT bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter WRITE_DATA_WIDTH_A bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_DATA_WIDTH_A bound to: 8 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter BYTE_WRITE_WIDTH_A bound to: 8 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_A bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_A bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_A bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_A bound to: SYNC - type: string 2default:defaulthp x  g %s *synth2O ; Parameter WRITE_DATA_WIDTH_B bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_DATA_WIDTH_B bound to: 8 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter BYTE_WRITE_WIDTH_B bound to: 8 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter ADDR_WIDTH_B bound to: 8 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter READ_RESET_VALUE_B bound to: 0 - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter READ_LATENCY_B bound to: 2 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter WRITE_MODE_B bound to: 1 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter RST_MODE_B bound to: SYNC - type: string 2default:defaulthp x  p %s *synth2X D Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 2default:defaulthp x  g %s *synth2O ; Parameter P_MIN_WIDTH_DATA_A bound to: 8 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_MIN_WIDTH_DATA_B bound to: 8 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter P_MIN_WIDTH_DATA bound to: 8 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_MIN_WIDTH_DATA_ECC bound to: 8 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter P_ECC_MODE bound to: no_ecc - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter P_MEMORY_OPT bound to: yes - type: string 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_COL_WRITE_A bound to: 8 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_COL_WRITE_B bound to: 8 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 2default:defaulthp x  l %s *synth2T @ Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter P_SDP_WRITE_MODE bound to: yes - type: string 2default:defaulthp x  c %s *synth2K 7 Parameter rsta_loop_iter bound to: 8 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter rstb_loop_iter bound to: 8 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter NUM_CHAR_LOC bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter MAX_NUM_CHAR bound to: 0 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter P_MIN_WIDTH_DATA_SHFT bound to: 8 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 2default:defaulthp x   'done synthesizing module '%s'%s (%s#%s)4495*oasys23 xpm_memory_base__parameterized12default:default2 2default:default2 182default:default2 12default:default2V @D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2 572default:default8@Z8-6155hpx  default block is never used226*oasys2R  Processing XDC Constraints 244*projectZ1-262hpx = Initializing timing engine 348*projectZ1-569hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_ooc.xdc2default:default2 inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 xd:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_ooc.xdc2default:default2 inst 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc2default:default2 inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc2default:default2 inst 2default:default8Z20-847hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 td:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc2default:default2: &.Xil/axi_chip2chip_64B66B_propImpl.xdc2default:defaultZ1-236hpx  Parsing XDC File [%s] 179* designutils2{ eD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/dont_touch.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2{ eD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/dont_touch.xdc2default:default8Z20-178hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 {d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc2default:default2 inst 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 {d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc2default:default2 inst 2default:default8Z20-847hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2 {d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc2default:default2: &.Xil/axi_chip2chip_64B66B_propImpl.xdc2default:defaultZ1-236hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2T @D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl2default:default2: &.Xil/axi_chip2chip_64B66B_propImpl.xdc2default:defaultZ1-236hpx  Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s]. 233*project2U AD:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl2default:default2: &.Xil/axi_chip2chip_64B66B_propImpl.xdc2default:defaultZ1-236hpx l 2%s XPM XDC files have been applied to the design. 665*project2 32default:defaultZ1-1715hpx H &Completed Processing XDC Constraints 245*projectZ1-263hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0022default:default2 1675.5942default:default2 0.0002default:defaultZ17-268hp x  ~ !Unisim Transformation Summary: %s111*project29 %No Unisim elements were transformed. 2default:defaultZ1-111hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common24 Constraint Validation Runtime : 2default:default2 00:00:002default:default2 00:00:00.0882default:default2 1675.5942default:default2 0.0002default:defaultZ17-268hp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1675.594 ; gain = 475.945 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  V %s *synth2> *Start Loading Part and Timing Information 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Loading part: xcku115-flva2104-1-c 2default:defaulthp x  B Reading net delay rules and data4578*oasysZ8-6742hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1675.594 ; gain = 475.945 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Z %s *synth2B .Start Applying 'set_property' XDC Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1675.594 ; gain = 475.945 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2E 1axi_chip2chip_v5_0_9_asitv10_axisc_register_slice2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default2U Aaxi_chip2chip_v5_0_9_asitv10_axisc_register_slice__parameterized02default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys20 gen_fwft.curr_fwft_state_reg2default:default2, xpm_fifo_base__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys20 gen_fwft.curr_fwft_state_reg2default:default2! xpm_fifo_base2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys20 gen_fwft.curr_fwft_state_reg2default:default2< (xpm_fifo_base__parameterized0__xdcDup__12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys20 gen_fwft.curr_fwft_state_reg2default:default21 xpm_fifo_base__parameterized02default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 xpm_fifo_rst2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 xpm_fifo_rst2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys20 gen_fwft.curr_fwft_state_reg2default:default21 xpm_fifo_base__parameterized12default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 state_reg2default:default21 axi_chip2chip_v5_0_9_phy_init2default:defaultZ8-802hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ ZERO | 1000 | 10 2default:defaulthp x   %s *synth2s _ ONE | 0010 | 11 2default:defaulthp x   %s *synth2s _ TWO | 0001 | 01 2default:defaulthp x   %s *synth2s _ iSTATE | 0100 | 00 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2E 1axi_chip2chip_v5_0_9_asitv10_axisc_register_slice2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ ZERO | 1000 | 10 2default:defaulthp x   %s *synth2s _ ONE | 0010 | 11 2default:defaulthp x   %s *synth2s _ TWO | 0001 | 01 2default:defaulthp x   %s *synth2s _ iSTATE | 0100 | 00 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 state_reg2default:default2 one-hot2default:default2U Aaxi_chip2chip_v5_0_9_asitv10_axisc_register_slice__parameterized02default:defaultZ8-3354hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ WRST_IDLE | 00001 | 000 2default:defaulthp x   %s *synth2s _ WRST_IN | 00010 | 010 2default:defaulthp x   %s *synth2s _ WRST_OUT | 00100 | 111 2default:defaulthp x   %s *synth2s _ WRST_EXIT | 01000 | 110 2default:defaulthp x   %s *synth2s _ WRST_GO2IDLE | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 one-hot2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 01 | 10 2default:defaulthp x   %s *synth2s _ iSTATE1 | 10 | 11 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 sequential2default:default2+ xpm_fifo_rst__xdcDup__12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ invalid | 00 | 00 2default:defaulthp x   %s *synth2s _ stage1_valid | 01 | 10 2default:defaulthp x   %s *synth2s _ both_stages_valid | 10 | 11 2default:defaulthp x   %s *synth2s _ stage2_valid | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys20 gen_fwft.curr_fwft_state_reg2default:default2 sequential2default:default2, xpm_fifo_base__xdcDup__12default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ WRST_IDLE | 00001 | 000 2default:defaulthp x   %s *synth2s _ WRST_IN | 00010 | 010 2default:defaulthp x   %s *synth2s _ WRST_OUT | 00100 | 111 2default:defaulthp x   %s *synth2s _ WRST_EXIT | 01000 | 110 2default:defaulthp x   %s *synth2s _ WRST_GO2IDLE | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 one-hot2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 01 | 10 2default:defaulthp x   %s *synth2s _ iSTATE1 | 10 | 11 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 sequential2default:default2+ xpm_fifo_rst__xdcDup__22default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ invalid | 00 | 00 2default:defaulthp x   %s *synth2s _ stage1_valid | 01 | 10 2default:defaulthp x   %s *synth2s _ both_stages_valid | 10 | 11 2default:defaulthp x   %s *synth2s _ stage2_valid | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys20 gen_fwft.curr_fwft_state_reg2default:default2 sequential2default:default2! xpm_fifo_base2default:defaultZ8-3354hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ WRST_IDLE | 00001 | 000 2default:defaulthp x   %s *synth2s _ WRST_IN | 00010 | 010 2default:defaulthp x   %s *synth2s _ WRST_OUT | 00100 | 111 2default:defaulthp x   %s *synth2s _ WRST_EXIT | 01000 | 110 2default:defaulthp x   %s *synth2s _ WRST_GO2IDLE | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 one-hot2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 01 | 10 2default:defaulthp x   %s *synth2s _ iSTATE1 | 10 | 11 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 sequential2default:default2+ xpm_fifo_rst__xdcDup__32default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ invalid | 00 | 00 2default:defaulthp x   %s *synth2s _ stage1_valid | 01 | 10 2default:defaulthp x   %s *synth2s _ both_stages_valid | 10 | 11 2default:defaulthp x   %s *synth2s _ stage2_valid | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys20 gen_fwft.curr_fwft_state_reg2default:default2 sequential2default:default2< (xpm_fifo_base__parameterized0__xdcDup__12default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_wrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ WRST_IDLE | 00001 | 000 2default:defaulthp x   %s *synth2s _ WRST_IN | 00010 | 010 2default:defaulthp x   %s *synth2s _ WRST_OUT | 00100 | 111 2default:defaulthp x   %s *synth2s _ WRST_EXIT | 01000 | 110 2default:defaulthp x   %s *synth2s _ WRST_GO2IDLE | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 one-hot2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_rrst_state_reg2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 01 | 10 2default:defaulthp x   %s *synth2s _ iSTATE1 | 10 | 11 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 sequential2default:default2+ xpm_fifo_rst__xdcDup__42default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ invalid | 00 | 00 2default:defaulthp x   %s *synth2s _ stage1_valid | 01 | 10 2default:defaulthp x   %s *synth2s _ both_stages_valid | 10 | 11 2default:defaulthp x   %s *synth2s _ stage2_valid | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys20 gen_fwft.curr_fwft_state_reg2default:default2 sequential2default:default21 xpm_fifo_base__parameterized02default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_wrst_state_reg2default:default2 xpm_fifo_rst2default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ WRST_IDLE | 00001 | 000 2default:defaulthp x   %s *synth2s _ WRST_IN | 00010 | 010 2default:defaulthp x   %s *synth2s _ WRST_OUT | 00100 | 111 2default:defaulthp x   %s *synth2s _ WRST_EXIT | 01000 | 110 2default:defaulthp x   %s *synth2s _ WRST_GO2IDLE | 10000 | 100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_wrst_state_reg2default:default2 one-hot2default:default2 xpm_fifo_rst2default:defaultZ8-3354hpx  BImplemented safe state '%s' for state register '%s' in module '%s'4006*oasys2! default_state2default:default22 gen_rst_ic.curr_rrst_state_reg2default:default2 xpm_fifo_rst2default:defaultZ8-5552hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE | 00 | 00 2default:defaulthp x   %s *synth2s _ iSTATE0 | 01 | 10 2default:defaulthp x   %s *synth2s _ iSTATE1 | 10 | 11 2default:defaulthp x   %s *synth2s _ iSTATE2 | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys22 gen_rst_ic.curr_rrst_state_reg2default:default2 sequential2default:default2 xpm_fifo_rst2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ invalid | 00 | 00 2default:defaulthp x   %s *synth2s _ stage1_valid | 01 | 10 2default:defaulthp x   %s *synth2s _ both_stages_valid | 10 | 11 2default:defaulthp x   %s *synth2s _ stage2_valid | 11 | 01 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys20 gen_fwft.curr_fwft_state_reg2default:default2 sequential2default:default21 xpm_fifo_base__parameterized12default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2s _ IDLE | 00000001 | 00000001 2default:defaulthp x   %s *synth2s _ PAT0 | 00000100 | 00000100 2default:defaulthp x   %s *synth2s _ PAT1 | 00001000 | 00001000 2default:defaulthp x   %s *synth2s _ RX_READY | 00010000 | 00010000 2default:defaulthp x   %s *synth2s _ PHY_ERROR | 00100000 | 00100000 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   6No Re-encoding of one hot register '%s' in module '%s'3445*oasys2 state_reg2default:default21 axi_chip2chip_v5_0_9_phy_init2default:defaultZ8-3898hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1675.594 ; gain = 475.945 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  X %s *synth2@ , 2 Input 24 Bit Adders := 1 2default:defaulthp x  X %s *synth2@ , 4 Input 10 Bit Adders := 6 2default:defaulthp x  X %s *synth2@ , 2 Input 10 Bit Adders := 2 2default:defaulthp x  X %s *synth2@ , 3 Input 10 Bit Adders := 4 2default:defaulthp x  X %s *synth2@ , 4 Input 9 Bit Adders := 15 2default:defaulthp x  X %s *synth2@ , 2 Input 9 Bit Adders := 3 2default:defaulthp x  X %s *synth2@ , 3 Input 9 Bit Adders := 8 2default:defaulthp x  X %s *synth2@ , 4 Input 8 Bit Adders := 9 2default:defaulthp x  X %s *synth2@ , 3 Input 8 Bit Adders := 3 2default:defaulthp x  X %s *synth2@ , 2 Input 7 Bit Adders := 1 2default:defaulthp x  X %s *synth2@ , 2 Input 4 Bit Adders := 2 2default:defaulthp x  X %s *synth2@ , 4 Input 2 Bit Adders := 5 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 56 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 10 Bit XORs := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 9 Bit XORs := 10 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit XORs := 7 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 166 2default:defaulthp x  Z %s *synth2B . 8 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 7 Input 1 Bit XORs := 3 2default:defaulthp x  Z %s *synth2B . 13 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 14 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 31 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 28 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 26 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 67 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 16 Input 1 Bit XORs := 2 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit XORs := 5 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 24 Input 1 Bit XORs := 1 2default:defaulthp x  Z %s *synth2B . 62 Input 1 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 64 Bit Registers := 3 2default:defaulthp x  Z %s *synth2B . 56 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 51 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 50 Bit Registers := 5 2default:defaulthp x  Z %s *synth2B . 41 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 24 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 23 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 15 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 13 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 12 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 10 Bit Registers := 34 2default:defaulthp x  Z %s *synth2B . 9 Bit Registers := 79 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 45 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 21 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 11 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 23 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 138 2default:defaulthp x  8 %s *synth2 +---RAMs : 2default:defaulthp x  j %s *synth2R > 20K Bit (512 X 41 bit) RAMs := 2 2default:defaulthp x  j %s *synth2R > 12K Bit (256 X 50 bit) RAMs := 2 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  X %s *synth2@ , 2 Input 64 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 2 Input 56 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ , 2 Input 50 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ , 6 Input 8 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 3 Input 6 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ , 6 Input 5 Bit Muxes := 5 2default:defaulthp x  X %s *synth2@ , 2 Input 5 Bit Muxes := 41 2default:defaulthp x  X %s *synth2@ , 3 Input 4 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ , 2 Input 4 Bit Muxes := 8 2default:defaulthp x  X %s *synth2@ , 4 Input 4 Bit Muxes := 3 2default:defaulthp x  X %s *synth2@ , 6 Input 4 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 6 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 2 Input 3 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 2 Input 2 Bit Muxes := 170 2default:defaulthp x  X %s *synth2@ , 8 Input 2 Bit Muxes := 1 2default:defaulthp x  X %s *synth2@ , 4 Input 2 Bit Muxes := 41 2default:defaulthp x  X %s *synth2@ , 5 Input 2 Bit Muxes := 2 2default:defaulthp x  X %s *synth2@ , 2 Input 1 Bit Muxes := 38 2default:defaulthp x  X %s *synth2@ , 4 Input 1 Bit Muxes := 21 2default:defaulthp x  X %s *synth2@ , 6 Input 1 Bit Muxes := 15 2default:defaulthp x  X %s *synth2@ , 5 Input 1 Bit Muxes := 10 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Finished RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2p \Part Resources: DSPs: 5520 (col length:120) BRAMs: 4320 (col length: RAMB18 240 RAMB36 120) 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  W %s *synth2? +Start Cross Boundary and Area Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1675.594 ; gain = 475.945 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  d %s *synth2L 8 Block RAM: Preliminary Mapping Report (see note below) 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x   %s *synth2 |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x   %s *synth2 Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 2default:defaulthp x  j %s *synth2R > Distributed RAM: Preliminary Mapping Report (see note below) 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 |inst/\slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | User Attribute | 256 x 8 | RAM64X1D x 4 RAM64M8 x 4 | 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  R %s *synth2: &Start Applying XDC Timing Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1783.563 ; gain = 583.914 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  F %s *synth2. Start Timing Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx  `Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 4174*oasys24 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 }Finished Timing Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1808.730 ; gain = 609.082 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 ! Block RAM: Final Mapping Report 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x   %s *synth2 |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | 2default:defaulthp x   %s *synth2 +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ 2default:defaulthp x  S %s *synth2; ' Distributed RAM: Final Mapping Report 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 |inst/\slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | User Attribute | 256 x 8 | RAM64X1D x 4 RAM64M8 x 4 | 2default:defaulthp x   %s *synth2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2- Start Technology Mapping 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 |Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1819.531 ; gain = 619.883 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ? %s *synth2' Start IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Q %s *synth29 %Start Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  T %s *synth2< (Finished Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 vFinished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Start Renaming Generated Instances 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start Rebuilding User Hierarchy 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Renaming Generated Ports 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 !Start Handling Custom Attributes 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  J %s *synth22 Start Renaming Generated Nets 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23  Static Shift Register Report: 2default:defaulthp x   %s *synth2 +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 2default:defaulthp x   %s *synth2 +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |axi_chip2chip_v5_0_9 | slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[127] | 125 | 1 | NO | NO | YES | 0 | 4 | 2default:defaulthp x   %s *synth2 +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Writing Synthesis Report 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  A %s *synth2)  Report BlackBoxes: 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  J %s *synth22 | |BlackBox name |Instances | 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  A %s *synth2)  Report Cell Usage: 2default:defaulthp x  F %s *synth2. +------+---------+------+ 2default:defaulthp x  F %s *synth2. | |Cell |Count | 2default:defaulthp x  F %s *synth2. +------+---------+------+ 2default:defaulthp x  F %s *synth2. |1 |CARRY8 | 37| 2default:defaulthp x  F %s *synth2. |2 |LUT1 | 51| 2default:defaulthp x  F %s *synth2. |3 |LUT2 | 428| 2default:defaulthp x  F %s *synth2. |4 |LUT3 | 259| 2default:defaulthp x  F %s *synth2. |5 |LUT4 | 273| 2default:defaulthp x  F %s *synth2. |6 |LUT5 | 222| 2default:defaulthp x  F %s *synth2. |7 |LUT6 | 374| 2default:defaulthp x  F %s *synth2. |8 |RAM64M8 | 4| 2default:defaulthp x  F %s *synth2. |9 |RAM64X1D | 4| 2default:defaulthp x  F %s *synth2. |10 |RAMB36E2 | 4| 2default:defaulthp x  F %s *synth2. |11 |SRLC32E | 4| 2default:defaulthp x  F %s *synth2. |12 |FDCE | 8| 2default:defaulthp x  F %s *synth2. |13 |FDPE | 14| 2default:defaulthp x  F %s *synth2. |14 |FDRE | 2195| 2default:defaulthp x  F %s *synth2. |15 |FDSE | 45| 2default:defaulthp x  F %s *synth2. +------+---------+------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  r %s *synth2Z FSynthesis finished with 0 errors, 0 critical warnings and 0 warnings. 2default:defaulthp x   %s *synth2 Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1823.426 ; gain = 508.422 2default:defaulthp x   %s *synth2 Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 2default:defaulthp x  B Translating synthesized netlist 350*projectZ1-571hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0862default:default2 1837.4772default:default2 0.0002default:defaultZ17-268hp x  f -Analyzing %s Unisim elements for replacement 17*netlist2 452default:defaultZ29-17hpx j 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28hpx K )Preparing netlist for logic optimization 349*projectZ1-570hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0022default:default2 1875.9142default:default2 0.0002default:defaultZ17-268hp x   !Unisim Transformation Summary: %s111*project2  A total of 8 instances were transformed. RAM64M8 => RAM64M8 (RAMD64E(x8)): 4 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 4 instances 2default:defaultZ1-111hpx U Releasing license: %s 83*common2 Synthesis2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 1602default:default2 02default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 synth_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" synth_design: 2default:default2 00:00:562default:default2 00:00:582default:default2 1875.9142default:default2 846.6292default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2 oD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/axi_chip2chip_64B66B.dcp2default:defaultZ17-1381hpx  '%s' is deprecated. %s 384*common2# use_project_ipc2default:default2A -This option is deprecated and no longer used.2default:defaultZ17-576hpx