Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Fri Mar 12 21:30:37 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_utilization -file axi_chip2chip_64B66B_utilization_synth.rpt -pb axi_chip2chip_64B66B_utilization_synth.pb | Design : axi_chip2chip_64B66B | Device : xcku115flva2104-1 | Design State : Synthesized ----------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. CLB Logic 1.1 Summary of Registers by Type 2. BLOCKRAM 3. ARITHMETIC 4. I/O 5. CLOCK 6. ADVANCED 7. CONFIGURATION 8. Primitives 9. Black Boxes 10. Instantiated Netlists 11. SLR Connectivity 12. SLR Connectivity Matrix 13. SLR CLB Logic and Dedicated Block Utilization 14. SLR IO Utilization 1. CLB Logic ------------ +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ | CLB LUTs* | 1312 | 0 | 663360 | 0.20 | | LUT as Logic | 1268 | 0 | 663360 | 0.19 | | LUT as Memory | 44 | 0 | 293760 | 0.01 | | LUT as Distributed RAM | 40 | 0 | | | | LUT as Shift Register | 4 | 0 | | | | CLB Registers | 2262 | 0 | 1326720 | 0.17 | | Register as Flip Flop | 2262 | 0 | 1326720 | 0.17 | | Register as Latch | 0 | 0 | 1326720 | 0.00 | | CARRY8 | 37 | 0 | 82920 | 0.04 | | F7 Muxes | 0 | 0 | 331680 | 0.00 | | F8 Muxes | 0 | 0 | 165840 | 0.00 | | F9 Muxes | 0 | 0 | 82920 | 0.00 | +----------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 14 | Yes | - | Set | | 8 | Yes | - | Reset | | 45 | Yes | Set | - | | 2195 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. BLOCKRAM ----------- +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ | Block RAM Tile | 4 | 0 | 2160 | 0.19 | | RAMB36/FIFO* | 4 | 0 | 2160 | 0.19 | | RAMB36E2 only | 4 | | | | | RAMB18 | 0 | 0 | 4320 | 0.00 | +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2 3. ARITHMETIC ------------- +-----------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------+------+-------+-----------+-------+ | DSPs | 0 | 0 | 5520 | 0.00 | +-----------+------+-------+-----------+-------+ 4. I/O ------ +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ | Bonded IOB | 0 | 0 | 832 | 0.00 | +------------+------+-------+-----------+-------+ 5. CLOCK -------- +----------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------+------+-------+-----------+-------+ | GLOBAL CLOCK BUFFERs | 0 | 0 | 1248 | 0.00 | | BUFGCE | 0 | 0 | 576 | 0.00 | | BUFGCE_DIV | 0 | 0 | 96 | 0.00 | | BUFG_GT | 0 | 0 | 384 | 0.00 | | BUFGCTRL* | 0 | 0 | 192 | 0.00 | | PLLE3_ADV | 0 | 0 | 48 | 0.00 | | MMCME3_ADV | 0 | 0 | 24 | 0.00 | +----------------------+------+-------+-----------+-------+ * Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability. 6. ADVANCED ----------- +-----------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------+------+-------+-----------+-------+ | GTHE3_CHANNEL | 0 | 0 | 52 | 0.00 | | GTHE3_COMMON | 0 | 0 | 13 | 0.00 | | IBUFDS_GTE3 | 0 | 0 | 26 | 0.00 | | OBUFDS_GTE3 | 0 | 0 | 26 | 0.00 | | OBUFDS_GTE3_ADV | 0 | 0 | 26 | 0.00 | | PCIE_3_1 | 0 | 0 | 6 | 0.00 | | SYSMONE1 | 0 | 0 | 2 | 0.00 | +-----------------+------+-------+-----------+-------+ 7. CONFIGURATION ---------------- +-------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------+------+-------+-----------+-------+ | BSCANE2 | 0 | 0 | 8 | 0.00 | | DNA_PORTE2 | 0 | 0 | 2 | 0.00 | | EFUSE_USR | 0 | 0 | 2 | 0.00 | | FRAME_ECCE3 | 0 | 0 | 2 | 0.00 | | ICAPE3 | 0 | 0 | 4 | 0.00 | | MASTER_JTAG | 0 | 0 | 2 | 0.00 | | STARTUPE3 | 0 | 0 | 2 | 0.00 | +-------------+------+-------+-----------+-------+ 8. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ | FDRE | 2195 | Register | | LUT2 | 428 | CLB | | LUT6 | 374 | CLB | | LUT4 | 273 | CLB | | LUT3 | 259 | CLB | | LUT5 | 222 | CLB | | LUT1 | 51 | CLB | | FDSE | 45 | Register | | RAMD64E | 40 | CLB | | CARRY8 | 37 | CLB | | FDPE | 14 | Register | | FDCE | 8 | Register | | SRLC32E | 4 | CLB | | RAMB36E2 | 4 | BLOCKRAM | +----------+------+---------------------+ 9. Black Boxes -------------- +----------+------+ | Ref Name | Used | +----------+------+ 10. Instantiated Netlists ------------------------- +----------+------+ | Ref Name | Used | +----------+------+ 11. SLR Connectivity -------------------- +----------------------------------+------+-------+-----------+-------+ | | Used | Fixed | Available | Util% | +----------------------------------+------+-------+-----------+-------+ | SLR1 <-> SLR0 | 0 | | 17280 | 0.00 | | SLR0 -> SLR1 | 0 | | | 0.00 | | Using TX_REG only | 0 | 0 | | | | Using RX_REG only | 0 | 0 | | | | Using Both TX_REG and RX_REG | 0 | 0 | | | | SLR1 -> SLR0 | 0 | | | 0.00 | | Using TX_REG only | 0 | 0 | | | | Using RX_REG only | 0 | 0 | | | | Using Both TX_REG and RX_REG | 0 | 0 | | | +----------------------------------+------+-------+-----------+-------+ | Total SLLs Used | 0 | | | | +----------------------------------+------+-------+-----------+-------+ 12. SLR Connectivity Matrix --------------------------- +-----------+------+------+ | FROM \ TO | SLR1 | SLR0 | +-----------+------+------+ | SLR1 | 0 | 0 | | SLR0 | 0 | 0 | +-----------+------+------+ 13. SLR CLB Logic and Dedicated Block Utilization ------------------------------------------------- +----------------------------+------+------+--------+--------+ | Site Type | SLR0 | SLR1 | SLR0 % | SLR1 % | +----------------------------+------+------+--------+--------+ | CLB | 0 | 0 | 0.00 | 0.00 | | CLBL | 0 | 0 | 0.00 | 0.00 | | CLBM | 0 | 0 | 0.00 | 0.00 | | CLB LUTs | 0 | 0 | 0.00 | 0.00 | | LUT as Logic | 0 | 0 | 0.00 | 0.00 | | LUT as Memory | 0 | 0 | 0.00 | 0.00 | | LUT as Distributed RAM | 0 | 0 | 0.00 | 0.00 | | LUT as Shift Register | 0 | 0 | 0.00 | 0.00 | | CLB Registers | 0 | 0 | 0.00 | 0.00 | | CARRY8 | 0 | 0 | 0.00 | 0.00 | | F7 Muxes | 0 | 0 | 0.00 | 0.00 | | F8 Muxes | 0 | 0 | 0.00 | 0.00 | | F9 Muxes | 0 | 0 | 0.00 | 0.00 | | Block RAM Tile | 0 | 0 | 0.00 | 0.00 | | RAMB36/FIFO | 0 | 0 | 0.00 | 0.00 | | RAMB18 | 0 | 0 | 0.00 | 0.00 | | URAM | 0 | 0 | 0.00 | 0.00 | | DSPs | 0 | 0 | 0.00 | 0.00 | | PLL | 0 | 0 | 0.00 | 0.00 | | MMCM | 0 | 0 | 0.00 | 0.00 | | Unique Control Sets | 0 | 0 | 0.00 | 0.00 | +----------------------------+------+------+--------+--------+ * Note: Available Control Sets based on CLB Registers / 8 14. SLR IO Utilization ---------------------- +-----------+-----------+---------+------------+----------+------------+----------+-----+ | SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs | +-----------+-----------+---------+------------+----------+------------+----------+-----+ | SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 | | SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 | +-----------+-----------+---------+------------+----------+------------+----------+-----+ | Total | 0 | | 0 | | 0 | | 0 | +-----------+-----------+---------+------------+----------+------------+----------+-----+