#----------------------------------------------------------- # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 # Start of session at: Fri Mar 12 21:29:30 2021 # Process ID: 13264 # Current directory: D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1 # Command line: vivado.exe -log axi_chip2chip_64B66B.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_chip2chip_64B66B.tcl # Log file: D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/axi_chip2chip_64B66B.vds # Journal file: D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1\vivado.jou #----------------------------------------------------------- source axi_chip2chip_64B66B.tcl -notrace Command: synth_design -top axi_chip2chip_64B66B -part xcku115-flva2104-1-c -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xcku115-flva2104-1-c INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 15996 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1453.801 ; gain = 254.152 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'axi_chip2chip_64B66B' [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/synth/axi_chip2chip_64B66B.v:58] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 50 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 128 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 50 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 12800 - type: integer Parameter WR_WIDTH_LOG bound to: 6 - type: integer Parameter WR_DEPTH_LOG bound to: 8 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter READ_MODE_LL bound to: 1 - type: integer Parameter PF_THRESH_ADJ bound to: 126 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 8 - type: integer Parameter PF_THRESH_MAX bound to: 251 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 251 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 12800 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 50 - type: integer Parameter READ_DATA_WIDTH_A bound to: 50 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 50 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 50 - type: integer Parameter READ_DATA_WIDTH_B bound to: 50 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 50 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 50 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 50 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 50 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 50 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 50 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 50 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter rsta_loop_iter bound to: 52 - type: integer Parameter rstb_loop_iter bound to: 52 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 50 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (8#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (9#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] Parameter REG_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (10#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 5 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (10#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] Parameter REG_WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (10#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (10#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1204] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1271] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1293] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1902] Parameter RST_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (11#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1902] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 2 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (12#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1618] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (13#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (14#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1618] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (14#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (14#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (14#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (15#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (16#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 512 - type: integer Parameter WRITE_DATA_WIDTH bound to: 41 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 384 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 41 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 512 - type: integer Parameter FIFO_SIZE bound to: 20992 - type: integer Parameter WR_WIDTH_LOG bound to: 6 - type: integer Parameter WR_DEPTH_LOG bound to: 9 - type: integer Parameter WR_PNTR_WIDTH bound to: 9 - type: integer Parameter RD_PNTR_WIDTH bound to: 9 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter READ_MODE_LL bound to: 1 - type: integer Parameter PF_THRESH_ADJ bound to: 382 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 8 - type: integer Parameter PF_THRESH_MAX bound to: 507 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 507 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 10 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 20992 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 41 - type: integer Parameter READ_DATA_WIDTH_A bound to: 41 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 41 - type: integer Parameter ADDR_WIDTH_A bound to: 9 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 41 - type: integer Parameter READ_DATA_WIDTH_B bound to: 41 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 41 - type: integer Parameter ADDR_WIDTH_B bound to: 9 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 41 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 41 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 41 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 41 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 41 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 41 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter rsta_loop_iter bound to: 44 - type: integer Parameter rstb_loop_iter bound to: 44 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 41 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized2' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 5 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 10 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized2' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] Parameter REG_WIDTH bound to: 10 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1880] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized3' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 10 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized3' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1204] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1271] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1293] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 10 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1854] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized0' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 128 - type: integer Parameter USE_ADV_FEATURES bound to: 0707 - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 1 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 2048 - type: integer Parameter WR_WIDTH_LOG bound to: 3 - type: integer Parameter WR_DEPTH_LOG bound to: 8 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter READ_MODE_LL bound to: 1 - type: integer Parameter PF_THRESH_ADJ bound to: 126 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 8 - type: integer Parameter PF_THRESH_MAX bound to: 251 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 251 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0000011100000111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b0 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b0 Parameter EN_DVLD bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 1 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 8 - type: integer Parameter READ_DATA_WIDTH_A bound to: 8 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 8 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 8 - type: integer Parameter READ_DATA_WIDTH_B bound to: 8 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 8 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 1 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 8 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 8 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 8 - type: integer Parameter rstb_loop_iter bound to: 8 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1204] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1271] INFO: [Synth 8-226] default block is never used [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1293] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized1' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (18#1) [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2142] INFO: [Synth 8-6155] done synthesizing module 'axi_chip2chip_64B66B' (28#1) [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/synth/axi_chip2chip_64B66B.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1542.320 ; gain = 342.672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1560.238 ; gain = 360.590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1560.238 ; gain = 360.590 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.115 . Memory (MB): peak = 1560.238 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_ooc.xdc] for cell 'inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_ooc.xdc] for cell 'inst' Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc] for cell 'inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axi_chip2chip_64B66B_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axi_chip2chip_64B66B_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/dont_touch.xdc] Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc] for cell 'inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axi_chip2chip_64B66B_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axi_chip2chip_64B66B_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axi_chip2chip_64B66B_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axi_chip2chip_64B66B_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axi_chip2chip_64B66B_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axi_chip2chip_64B66B_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1675.594 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 1675.594 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1675.594 ; gain = 475.945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xcku115-flva2104-1-c INFO: [Synth 8-6742] Reading net delay rules and data --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1675.594 ; gain = 475.945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/dont_touch.xdc, line 9). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for inst/\slave_fpga_gen.axi_chip2chip_slave_inst /axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1675.594 ; gain = 475.945 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_chip2chip_v5_0_9_asitv10_axisc_register_slice' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_chip2chip_v5_0_9_asitv10_axisc_register_slice__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized0__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_chip2chip_v5_0_9_phy_init' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_chip2chip_v5_0_9_asitv10_axisc_register_slice' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_chip2chip_v5_0_9_asitv10_axisc_register_slice__parameterized0' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__2' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__3' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized0__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__4' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__4' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized0' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * IDLE | 00000001 | 00000001 PAT0 | 00000100 | 00000100 PAT1 | 00001000 | 00001000 RX_READY | 00010000 | 00010000 PHY_ERROR | 00100000 | 00100000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'axi_chip2chip_v5_0_9_phy_init' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1675.594 ; gain = 475.945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 24 Bit Adders := 1 4 Input 10 Bit Adders := 6 2 Input 10 Bit Adders := 2 3 Input 10 Bit Adders := 4 4 Input 9 Bit Adders := 15 2 Input 9 Bit Adders := 3 3 Input 9 Bit Adders := 8 4 Input 8 Bit Adders := 9 3 Input 8 Bit Adders := 3 2 Input 7 Bit Adders := 1 2 Input 4 Bit Adders := 2 4 Input 2 Bit Adders := 5 +---XORs : 2 Input 56 Bit XORs := 1 2 Input 10 Bit XORs := 4 2 Input 9 Bit XORs := 10 2 Input 8 Bit XORs := 7 2 Input 1 Bit XORs := 166 8 Input 1 Bit XORs := 3 7 Input 1 Bit XORs := 3 13 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 2 31 Input 1 Bit XORs := 2 28 Input 1 Bit XORs := 1 3 Input 1 Bit XORs := 2 26 Input 1 Bit XORs := 1 67 Input 1 Bit XORs := 1 5 Input 1 Bit XORs := 2 16 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 5 11 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 1 24 Input 1 Bit XORs := 1 62 Input 1 Bit XORs := 1 +---Registers : 128 Bit Registers := 1 64 Bit Registers := 3 56 Bit Registers := 4 51 Bit Registers := 1 50 Bit Registers := 5 41 Bit Registers := 4 24 Bit Registers := 1 23 Bit Registers := 1 15 Bit Registers := 1 13 Bit Registers := 1 12 Bit Registers := 1 10 Bit Registers := 34 9 Bit Registers := 79 8 Bit Registers := 45 7 Bit Registers := 1 6 Bit Registers := 1 4 Bit Registers := 21 3 Bit Registers := 11 2 Bit Registers := 23 1 Bit Registers := 138 +---RAMs : 20K Bit (512 X 41 bit) RAMs := 2 12K Bit (256 X 50 bit) RAMs := 2 +---Muxes : 2 Input 64 Bit Muxes := 1 2 Input 56 Bit Muxes := 2 2 Input 50 Bit Muxes := 2 6 Input 8 Bit Muxes := 1 3 Input 6 Bit Muxes := 2 6 Input 5 Bit Muxes := 5 2 Input 5 Bit Muxes := 41 3 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 4 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 6 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 170 8 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 41 5 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 38 4 Input 1 Bit Muxes := 21 6 Input 1 Bit Muxes := 15 5 Input 1 Bit Muxes := 10 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 5520 (col length:120) BRAMs: 4320 (col length: RAMB18 240 RAMB36 120) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1675.594 ; gain = 475.945 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ |inst/\slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | User Attribute | 256 x 8 | RAM64X1D x 4 RAM64M8 x 4 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1783.563 ; gain = 583.914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1808.730 ; gain = 609.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 50(NO_CHANGE) | W | | 256 x 50(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | |xpm_memory_base__parameterized0: | gen_wr_a.gen_word_narrow.mem_reg | 512 x 41(NO_CHANGE) | W | | 512 x 41(NO_CHANGE) | | R | Port A and B | 0 | 1 | | +---------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+ Distributed RAM: Final Mapping Report +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ |inst/\slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | User Attribute | 256 x 8 | RAM64X1D x 4 RAM64M8 x 4 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+----------------+----------------------+---------------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1819.531 ; gain = 619.883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |axi_chip2chip_v5_0_9 | slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[127] | 125 | 1 | NO | NO | YES | 0 | 4 | +---------------------+--------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY8 | 37| |2 |LUT1 | 51| |3 |LUT2 | 428| |4 |LUT3 | 259| |5 |LUT4 | 273| |6 |LUT5 | 222| |7 |LUT6 | 374| |8 |RAM64M8 | 4| |9 |RAM64X1D | 4| |10 |RAMB36E2 | 4| |11 |SRLC32E | 4| |12 |FDCE | 8| |13 |FDPE | 14| |14 |FDRE | 2195| |15 |FDSE | 45| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1823.426 ; gain = 508.422 Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1823.426 ; gain = 623.777 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1837.477 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 45 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1875.914 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 8 instances were transformed. RAM64M8 => RAM64M8 (RAMD64E(x8)): 4 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 4 instances INFO: [Common 17-83] Releasing license: Synthesis 160 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 1875.914 ; gain = 846.629 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/axi_chip2chip_64B66B.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axi_chip2chip_64B66B, cache-ID = 2c613e9611b90f1d INFO: [Coretcl 2-1174] Renamed 132 cell refs. INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.runs/axi_chip2chip_64B66B_synth_1/axi_chip2chip_64B66B.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file axi_chip2chip_64B66B_utilization_synth.rpt -pb axi_chip2chip_64B66B_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Fri Mar 12 21:30:38 2021...