xpm_cdc.sv,systemverilog,xpm,../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
axi_chip2chip_v5_0_rfs.v,verilog,axi_chip2chip_v5_0_9,../../../ipstatic/hdl/axi_chip2chip_v5_0_rfs.v,
axi_chip2chip_64B66B.v,verilog,xil_defaultlib,../../../../ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/sim/axi_chip2chip_64B66B.v,
glbl.v,Verilog,xil_defaultlib,glbl.v