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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7 // IP Revision: 9 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG ttc_mgt your_instance_name ( .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), // input wire [0 : 0] gtwiz_userclk_tx_active_in .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in), // input wire [0 : 0] gtwiz_userclk_rx_active_in .gtwiz_buffbypass_rx_reset_in(gtwiz_buffbypass_rx_reset_in), // input wire [0 : 0] gtwiz_buffbypass_rx_reset_in .gtwiz_buffbypass_rx_start_user_in(gtwiz_buffbypass_rx_start_user_in), // input wire [0 : 0] gtwiz_buffbypass_rx_start_user_in .gtwiz_buffbypass_rx_done_out(gtwiz_buffbypass_rx_done_out), // output wire [0 : 0] gtwiz_buffbypass_rx_done_out .gtwiz_buffbypass_rx_error_out(gtwiz_buffbypass_rx_error_out), // output wire [0 : 0] gtwiz_buffbypass_rx_error_out .gtwiz_reset_tx_done_in(gtwiz_reset_tx_done_in), // input wire [0 : 0] gtwiz_reset_tx_done_in .gtwiz_reset_rx_done_in(gtwiz_reset_rx_done_in), // input wire [0 : 0] gtwiz_reset_rx_done_in .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), // input wire [31 : 0] gtwiz_userdata_tx_in .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), // output wire [31 : 0] gtwiz_userdata_rx_out .gtrefclk00_in(gtrefclk00_in), // input wire [0 : 0] gtrefclk00_in .gtrefclk01_in(gtrefclk01_in), // input wire [0 : 0] gtrefclk01_in .gtsouthrefclk00_in(gtsouthrefclk00_in), // input wire [0 : 0] gtsouthrefclk00_in .gtsouthrefclk01_in(gtsouthrefclk01_in), // input wire [0 : 0] gtsouthrefclk01_in .gtsouthrefclk10_in(gtsouthrefclk10_in), // input wire [0 : 0] gtsouthrefclk10_in .gtsouthrefclk11_in(gtsouthrefclk11_in), // input wire [0 : 0] gtsouthrefclk11_in .qpll0refclksel_in(qpll0refclksel_in), // input wire [2 : 0] qpll0refclksel_in .qpll0reset_in(qpll0reset_in), // input wire [0 : 0] qpll0reset_in .qpll1refclksel_in(qpll1refclksel_in), // input wire [2 : 0] qpll1refclksel_in .qpll1reset_in(qpll1reset_in), // input wire [0 : 0] qpll1reset_in .qpll0lock_out(qpll0lock_out), // output wire [0 : 0] qpll0lock_out .qpll0outclk_out(qpll0outclk_out), // output wire [0 : 0] qpll0outclk_out .qpll0outrefclk_out(qpll0outrefclk_out), // output wire [0 : 0] qpll0outrefclk_out .qpll1lock_out(qpll1lock_out), // output wire [0 : 0] qpll1lock_out .qpll1outclk_out(qpll1outclk_out), // output wire [0 : 0] qpll1outclk_out .qpll1outrefclk_out(qpll1outrefclk_out), // output wire [0 : 0] qpll1outrefclk_out .gthrxn_in(gthrxn_in), // input wire [0 : 0] gthrxn_in .gthrxp_in(gthrxp_in), // input wire [0 : 0] gthrxp_in .gtrxreset_in(gtrxreset_in), // input wire [0 : 0] gtrxreset_in .gttxreset_in(gttxreset_in), // input wire [0 : 0] gttxreset_in .loopback_in(loopback_in), // input wire [2 : 0] loopback_in .rxpolarity_in(rxpolarity_in), // input wire [0 : 0] rxpolarity_in .rxprogdivreset_in(rxprogdivreset_in), // input wire [0 : 0] rxprogdivreset_in .rxslide_in(rxslide_in), // input wire [0 : 0] rxslide_in .rxuserrdy_in(rxuserrdy_in), // input wire [0 : 0] rxuserrdy_in .rxusrclk_in(rxusrclk_in), // input wire [0 : 0] rxusrclk_in .rxusrclk2_in(rxusrclk2_in), // input wire [0 : 0] rxusrclk2_in .txpolarity_in(txpolarity_in), // input wire [0 : 0] txpolarity_in .txprogdivreset_in(txprogdivreset_in), // input wire [0 : 0] txprogdivreset_in .txuserrdy_in(txuserrdy_in), // input wire [0 : 0] txuserrdy_in .txusrclk_in(txusrclk_in), // input wire [0 : 0] txusrclk_in .txusrclk2_in(txusrclk2_in), // input wire [0 : 0] txusrclk2_in .gthtxn_out(gthtxn_out), // output wire [0 : 0] gthtxn_out .gthtxp_out(gthtxp_out), // output wire [0 : 0] gthtxp_out .gtpowergood_out(gtpowergood_out), // output wire [0 : 0] gtpowergood_out .rxcdrlock_out(rxcdrlock_out), // output wire [0 : 0] rxcdrlock_out .rxoutclk_out(rxoutclk_out), // output wire [0 : 0] rxoutclk_out .rxpmaresetdone_out(rxpmaresetdone_out), // output wire [0 : 0] rxpmaresetdone_out .rxrecclkout_out(rxrecclkout_out), // output wire [0 : 0] rxrecclkout_out .rxresetdone_out(rxresetdone_out), // output wire [0 : 0] rxresetdone_out .txoutclk_out(txoutclk_out), // output wire [0 : 0] txoutclk_out .txpmaresetdone_out(txpmaresetdone_out), // output wire [0 : 0] txpmaresetdone_out .txresetdone_out(txresetdone_out) // output wire [0 : 0] txresetdone_out ); // INST_TAG_END ------ End INSTANTIATION Template --------- // You must compile the wrapper file ttc_mgt.v when simulating // the core, ttc_mgt. When compiling the wrapper file, be sure to // reference the Verilog simulation library.