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// IP VLNV: xilinx.com:ip:aurora_64b66b:12.0
// IP Revision: 3

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
aurora_64b66b_0 your_instance_name (
  .rxp(rxp),                                  // input wire [0 : 0] rxp
  .rxn(rxn),                                  // input wire [0 : 0] rxn
  .refclk1_in(refclk1_in),                    // input wire refclk1_in
  .reset_pb(reset_pb),                        // input wire reset_pb
  .power_down(power_down),                    // input wire power_down
  .pma_init(pma_init),                        // input wire pma_init
  .loopback(loopback),                        // input wire [2 : 0] loopback
  .txp(txp),                                  // output wire [0 : 0] txp
  .txn(txn),                                  // output wire [0 : 0] txn
  .hard_err(hard_err),                        // output wire hard_err
  .soft_err(soft_err),                        // output wire soft_err
  .channel_up(channel_up),                    // output wire channel_up
  .lane_up(lane_up),                          // output wire [0 : 0] lane_up
  .tx_out_clk(tx_out_clk),                    // output wire tx_out_clk
  .gt_pll_lock(gt_pll_lock),                  // output wire gt_pll_lock
  .s_axi_tx_tdata(s_axi_tx_tdata),            // input wire [0 : 63] s_axi_tx_tdata
  .s_axi_tx_tvalid(s_axi_tx_tvalid),          // input wire s_axi_tx_tvalid
  .s_axi_tx_tready(s_axi_tx_tready),          // output wire s_axi_tx_tready
  .m_axi_rx_tdata(m_axi_rx_tdata),            // output wire [0 : 63] m_axi_rx_tdata
  .m_axi_rx_tvalid(m_axi_rx_tvalid),          // output wire m_axi_rx_tvalid
  .mmcm_not_locked_out(mmcm_not_locked_out),  // output wire mmcm_not_locked_out
  .gt0_drpaddr(gt0_drpaddr),                  // input wire [8 : 0] gt0_drpaddr
  .gt0_drpdi(gt0_drpdi),                      // input wire [15 : 0] gt0_drpdi
  .gt0_drprdy(gt0_drprdy),                    // output wire gt0_drprdy
  .gt0_drpwe(gt0_drpwe),                      // input wire gt0_drpwe
  .gt0_drpen(gt0_drpen),                      // input wire gt0_drpen
  .gt0_drpdo(gt0_drpdo),                      // output wire [15 : 0] gt0_drpdo
  .init_clk(init_clk),                        // input wire init_clk
  .link_reset_out(link_reset_out),            // output wire link_reset_out
  .user_clk_out(user_clk_out),                // output wire user_clk_out
  .sync_clk_out(sync_clk_out),                // output wire sync_clk_out
  .gt_rxcdrovrden_in(gt_rxcdrovrden_in),      // input wire gt_rxcdrovrden_in
  .sys_reset_out(sys_reset_out),              // output wire sys_reset_out
  .gt_reset_out(gt_reset_out),                // output wire gt_reset_out
  .gt_powergood(gt_powergood)                // output wire [0 : 0] gt_powergood
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file aurora_64b66b_0.v when simulating
// the core, aurora_64b66b_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.