-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -- Date : Fri Mar 12 21:32:40 2021 -- Host : baby running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ aurora_64b66b_0_sim_netlist.vhdl -- Design : aurora_64b66b_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku115-flva2104-1-c -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); blocksync_out_i : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxheadervalid_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM is signal BLOCKSYNC_OUT_i_1_n_0 : STD_LOGIC; signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal RXGEARBOXSLIP_OUT_i_2_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_3_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_4_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_5_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_6_n_0 : STD_LOGIC; signal begin_r : STD_LOGIC; signal \begin_r_i_2__0_n_0\ : STD_LOGIC; signal \^blocksync_out_i\ : STD_LOGIC; signal next_begin_c : STD_LOGIC; signal next_sh_invalid_c : STD_LOGIC; signal next_sh_valid_c : STD_LOGIC; signal next_slip_c : STD_LOGIC; signal next_sync_done_c : STD_LOGIC; signal next_test_sh_c : STD_LOGIC; signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \sh_count_equals_max_i__14\ : STD_LOGIC; signal \sh_invalid_cnt_equals_zero_i__4\ : STD_LOGIC; signal sh_valid_r_i_2_n_0 : STD_LOGIC; signal \slip_count_i[15]_i_1_n_0\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[0]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[10]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[11]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[12]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[13]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[14]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[1]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[2]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[3]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[4]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[5]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[6]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[7]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[8]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[9]\ : STD_LOGIC; signal slip_done_i : STD_LOGIC; signal slip_pulse_i : STD_LOGIC; signal slip_r_i_2_n_0 : STD_LOGIC; signal sync_done_r : STD_LOGIC; signal sync_done_r_i_3_n_0 : STD_LOGIC; signal sync_done_r_i_5_n_0 : STD_LOGIC; signal sync_done_r_i_6_n_0 : STD_LOGIC; signal sync_done_r_i_7_n_0 : STD_LOGIC; signal sync_done_r_i_8_n_0 : STD_LOGIC; signal sync_done_r_i_9_n_0 : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_2\ : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_3\ : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_4\ : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_5\ : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_6\ : STD_LOGIC; signal \sync_header_count_i0_carry__0_n_7\ : STD_LOGIC; signal sync_header_count_i0_carry_n_0 : STD_LOGIC; signal sync_header_count_i0_carry_n_1 : STD_LOGIC; signal sync_header_count_i0_carry_n_2 : STD_LOGIC; signal sync_header_count_i0_carry_n_3 : STD_LOGIC; signal sync_header_count_i0_carry_n_4 : STD_LOGIC; signal sync_header_count_i0_carry_n_5 : STD_LOGIC; signal sync_header_count_i0_carry_n_6 : STD_LOGIC; signal sync_header_count_i0_carry_n_7 : STD_LOGIC; signal \sync_header_count_i[15]_i_1_n_0\ : STD_LOGIC; signal sync_header_count_i_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \sync_header_invalid_count_i[9]_i_2_n_0\ : STD_LOGIC; signal sync_header_invalid_count_i_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); signal system_reset_r : STD_LOGIC; signal system_reset_r2 : STD_LOGIC; signal test_sh_r : STD_LOGIC; signal test_sh_r_i_2_n_0 : STD_LOGIC; signal \NLW_sync_header_count_i0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 ); signal \NLW_sync_header_count_i0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of RXGEARBOXSLIP_OUT_i_2 : label is "soft_lutpair36"; attribute SOFT_HLUTNM of RXGEARBOXSLIP_OUT_i_5 : label is "soft_lutpair38"; attribute SOFT_HLUTNM of RXGEARBOXSLIP_OUT_i_6 : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \begin_r_i_2__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of sync_done_r_i_6 : label is "soft_lutpair37"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of sync_header_count_i0_carry : label is 35; attribute ADDER_THRESHOLD of \sync_header_count_i0_carry__0\ : label is 35; attribute SOFT_HLUTNM of \sync_header_count_i[0]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[1]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[2]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[3]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[4]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[6]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[7]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[8]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[9]_i_1\ : label is "soft_lutpair35"; begin D(0) <= \^d\(0); blocksync_out_i <= \^blocksync_out_i\; BLOCKSYNC_OUT_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"1110" ) port map ( I0 => p_1_in(1), I1 => system_reset_r2, I2 => \^blocksync_out_i\, I3 => sync_done_r, O => BLOCKSYNC_OUT_i_1_n_0 ); BLOCKSYNC_OUT_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => BLOCKSYNC_OUT_i_1_n_0, Q => \^blocksync_out_i\, R => '0' ); RXGEARBOXSLIP_OUT_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => RXGEARBOXSLIP_OUT_i_2_n_0, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => \sh_count_equals_max_i__14\, I3 => p_1_in(3), I4 => RXGEARBOXSLIP_OUT_i_3_n_0, I5 => RXGEARBOXSLIP_OUT_i_4_n_0, O => slip_pulse_i ); RXGEARBOXSLIP_OUT_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => slip_r_i_2_n_0, I1 => p_1_in(1), O => RXGEARBOXSLIP_OUT_i_2_n_0 ); RXGEARBOXSLIP_OUT_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"2000FFFF" ) port map ( I0 => sync_done_r_i_9_n_0, I1 => sync_header_invalid_count_i_reg(3), I2 => sync_header_invalid_count_i_reg(4), I3 => RXGEARBOXSLIP_OUT_i_5_n_0, I4 => \^blocksync_out_i\, O => RXGEARBOXSLIP_OUT_i_3_n_0 ); RXGEARBOXSLIP_OUT_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"F4444444F4F4F4F4" ) port map ( I0 => slip_done_i, I1 => p_1_in(1), I2 => p_1_in(2), I3 => sync_done_r_i_9_n_0, I4 => RXGEARBOXSLIP_OUT_i_6_n_0, I5 => \^blocksync_out_i\, O => RXGEARBOXSLIP_OUT_i_4_n_0 ); RXGEARBOXSLIP_OUT_i_5: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => sync_header_invalid_count_i_reg(2), I1 => sync_header_invalid_count_i_reg(1), I2 => sync_header_invalid_count_i_reg(0), O => RXGEARBOXSLIP_OUT_i_5_n_0 ); RXGEARBOXSLIP_OUT_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => sync_header_invalid_count_i_reg(3), I1 => sync_header_invalid_count_i_reg(4), I2 => sync_header_invalid_count_i_reg(0), I3 => sync_header_invalid_count_i_reg(1), I4 => sync_header_invalid_count_i_reg(2), O => RXGEARBOXSLIP_OUT_i_6_n_0 ); RXGEARBOXSLIP_OUT_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => slip_pulse_i, Q => \^d\(0), R => '0' ); \begin_r_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAFFBAAAAA" ) port map ( I0 => \begin_r_i_2__0_n_0\, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => p_1_in(3), I3 => p_1_in(2), I4 => \sh_count_equals_max_i__14\, I5 => RXGEARBOXSLIP_OUT_i_3_n_0, O => next_begin_c ); \begin_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FDDD" ) port map ( I0 => slip_r_i_2_n_0, I1 => sync_done_r, I2 => slip_done_i, I3 => p_1_in(1), O => \begin_r_i_2__0_n_0\ ); begin_r_reg: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_begin_c, Q => begin_r, S => system_reset_r2 ); sh_invalid_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000009000" ) port map ( I0 => Q(0), I1 => Q(1), I2 => sh_valid_r_i_2_n_0, I3 => test_sh_r, I4 => begin_r, I5 => p_1_in(1), O => next_sh_invalid_c ); sh_invalid_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_sh_invalid_c, Q => p_1_in(2), R => system_reset_r2 ); sh_valid_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000006000" ) port map ( I0 => Q(0), I1 => Q(1), I2 => sh_valid_r_i_2_n_0, I3 => test_sh_r, I4 => begin_r, I5 => p_1_in(1), O => next_sh_valid_c ); sh_valid_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => sync_done_r, I1 => rxheadervalid_i, I2 => p_1_in(3), I3 => p_1_in(2), O => sh_valid_r_i_2_n_0 ); sh_valid_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_sh_valid_c, Q => p_1_in(3), R => system_reset_r2 ); \slip_count_i[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_1_in(1), O => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \^d\(0), Q => \slip_count_i_reg_n_0_[0]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[9]\, Q => \slip_count_i_reg_n_0_[10]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[10]\, Q => \slip_count_i_reg_n_0_[11]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[11]\, Q => \slip_count_i_reg_n_0_[12]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[12]\, Q => \slip_count_i_reg_n_0_[13]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[13]\, Q => \slip_count_i_reg_n_0_[14]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[14]\, Q => slip_done_i, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[0]\, Q => \slip_count_i_reg_n_0_[1]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[1]\, Q => \slip_count_i_reg_n_0_[2]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[2]\, Q => \slip_count_i_reg_n_0_[3]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[3]\, Q => \slip_count_i_reg_n_0_[4]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[4]\, Q => \slip_count_i_reg_n_0_[5]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[5]\, Q => \slip_count_i_reg_n_0_[6]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[6]\, Q => \slip_count_i_reg_n_0_[7]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[7]\, Q => \slip_count_i_reg_n_0_[8]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \slip_count_i_reg_n_0_[8]\, Q => \slip_count_i_reg_n_0_[9]\, R => \slip_count_i[15]_i_1_n_0\ ); slip_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => slip_r_i_2_n_0, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => \sh_count_equals_max_i__14\, I3 => p_1_in(3), I4 => RXGEARBOXSLIP_OUT_i_3_n_0, I5 => RXGEARBOXSLIP_OUT_i_4_n_0, O => next_slip_c ); slip_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100010116" ) port map ( I0 => sync_done_r, I1 => p_1_in(1), I2 => p_1_in(2), I3 => p_1_in(3), I4 => test_sh_r, I5 => begin_r, O => slip_r_i_2_n_0 ); slip_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_slip_c, Q => p_1_in(1), R => system_reset_r2 ); sync_done_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \sh_count_equals_max_i__14\, I1 => sync_done_r_i_3_n_0, I2 => \sh_invalid_cnt_equals_zero_i__4\, O => next_sync_done_c ); sync_done_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => sync_done_r_i_5_n_0, I1 => sync_done_r_i_6_n_0, I2 => sync_done_r_i_7_n_0, I3 => sync_done_r_i_8_n_0, O => \sh_count_equals_max_i__14\ ); sync_done_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => p_1_in(3), I1 => p_1_in(2), I2 => sync_done_r, I3 => p_1_in(1), I4 => begin_r, I5 => test_sh_r, O => sync_done_r_i_3_n_0 ); sync_done_r_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => sync_header_invalid_count_i_reg(2), I1 => sync_header_invalid_count_i_reg(1), I2 => sync_header_invalid_count_i_reg(0), I3 => sync_header_invalid_count_i_reg(3), I4 => sync_header_invalid_count_i_reg(4), I5 => sync_done_r_i_9_n_0, O => \sh_invalid_cnt_equals_zero_i__4\ ); sync_done_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sync_header_count_i_reg(7), I1 => sync_header_count_i_reg(6), I2 => sync_header_count_i_reg(4), I3 => sync_header_count_i_reg(5), O => sync_done_r_i_5_n_0 ); sync_done_r_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => sync_header_count_i_reg(1), I1 => sync_header_count_i_reg(0), I2 => sync_header_count_i_reg(3), I3 => sync_header_count_i_reg(2), O => sync_done_r_i_6_n_0 ); sync_done_r_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sync_header_count_i_reg(10), I1 => sync_header_count_i_reg(11), I2 => sync_header_count_i_reg(8), I3 => sync_header_count_i_reg(9), O => sync_done_r_i_7_n_0 ); sync_done_r_i_8: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => sync_header_count_i_reg(15), I1 => sync_header_count_i_reg(14), I2 => sync_header_count_i_reg(12), I3 => sync_header_count_i_reg(13), O => sync_done_r_i_8_n_0 ); sync_done_r_i_9: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => sync_header_invalid_count_i_reg(5), I1 => sync_header_invalid_count_i_reg(6), I2 => sync_header_invalid_count_i_reg(7), I3 => sync_header_invalid_count_i_reg(9), I4 => sync_header_invalid_count_i_reg(8), O => sync_done_r_i_9_n_0 ); sync_done_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_sync_done_c, Q => sync_done_r, R => system_reset_r2 ); sync_header_count_i0_carry: unisim.vcomponents.CARRY8 port map ( CI => sync_header_count_i_reg(0), CI_TOP => '0', CO(7) => sync_header_count_i0_carry_n_0, CO(6) => sync_header_count_i0_carry_n_1, CO(5) => sync_header_count_i0_carry_n_2, CO(4) => sync_header_count_i0_carry_n_3, CO(3) => sync_header_count_i0_carry_n_4, CO(2) => sync_header_count_i0_carry_n_5, CO(1) => sync_header_count_i0_carry_n_6, CO(0) => sync_header_count_i0_carry_n_7, DI(7 downto 0) => B"00000000", O(7 downto 0) => \p_0_in__6\(8 downto 1), S(7 downto 0) => sync_header_count_i_reg(8 downto 1) ); \sync_header_count_i0_carry__0\: unisim.vcomponents.CARRY8 port map ( CI => sync_header_count_i0_carry_n_0, CI_TOP => '0', CO(7 downto 6) => \NLW_sync_header_count_i0_carry__0_CO_UNCONNECTED\(7 downto 6), CO(5) => \sync_header_count_i0_carry__0_n_2\, CO(4) => \sync_header_count_i0_carry__0_n_3\, CO(3) => \sync_header_count_i0_carry__0_n_4\, CO(2) => \sync_header_count_i0_carry__0_n_5\, CO(1) => \sync_header_count_i0_carry__0_n_6\, CO(0) => \sync_header_count_i0_carry__0_n_7\, DI(7 downto 0) => B"00000000", O(7) => \NLW_sync_header_count_i0_carry__0_O_UNCONNECTED\(7), O(6 downto 0) => \p_0_in__6\(15 downto 9), S(7) => '0', S(6 downto 0) => sync_header_count_i_reg(15 downto 9) ); \sync_header_count_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sync_header_count_i_reg(0), O => \p_0_in__6\(0) ); \sync_header_count_i[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_1_in(3), I1 => p_1_in(2), O => \sync_header_count_i[15]_i_1_n_0\ ); \sync_header_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(0), Q => sync_header_count_i_reg(0), R => begin_r ); \sync_header_count_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(10), Q => sync_header_count_i_reg(10), R => begin_r ); \sync_header_count_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(11), Q => sync_header_count_i_reg(11), R => begin_r ); \sync_header_count_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(12), Q => sync_header_count_i_reg(12), R => begin_r ); \sync_header_count_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(13), Q => sync_header_count_i_reg(13), R => begin_r ); \sync_header_count_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(14), Q => sync_header_count_i_reg(14), R => begin_r ); \sync_header_count_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(15), Q => sync_header_count_i_reg(15), R => begin_r ); \sync_header_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(1), Q => sync_header_count_i_reg(1), R => begin_r ); \sync_header_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(2), Q => sync_header_count_i_reg(2), R => begin_r ); \sync_header_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(3), Q => sync_header_count_i_reg(3), R => begin_r ); \sync_header_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(4), Q => sync_header_count_i_reg(4), R => begin_r ); \sync_header_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(5), Q => sync_header_count_i_reg(5), R => begin_r ); \sync_header_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(6), Q => sync_header_count_i_reg(6), R => begin_r ); \sync_header_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(7), Q => sync_header_count_i_reg(7), R => begin_r ); \sync_header_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(8), Q => sync_header_count_i_reg(8), R => begin_r ); \sync_header_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \sync_header_count_i[15]_i_1_n_0\, D => \p_0_in__6\(9), Q => sync_header_count_i_reg(9), R => begin_r ); \sync_header_invalid_count_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sync_header_invalid_count_i_reg(0), O => \p_0_in__7\(0) ); \sync_header_invalid_count_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sync_header_invalid_count_i_reg(0), I1 => sync_header_invalid_count_i_reg(1), O => \p_0_in__7\(1) ); \sync_header_invalid_count_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sync_header_invalid_count_i_reg(0), I1 => sync_header_invalid_count_i_reg(1), I2 => sync_header_invalid_count_i_reg(2), O => \p_0_in__7\(2) ); \sync_header_invalid_count_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sync_header_invalid_count_i_reg(1), I1 => sync_header_invalid_count_i_reg(0), I2 => sync_header_invalid_count_i_reg(2), I3 => sync_header_invalid_count_i_reg(3), O => \p_0_in__7\(3) ); \sync_header_invalid_count_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sync_header_invalid_count_i_reg(2), I1 => sync_header_invalid_count_i_reg(0), I2 => sync_header_invalid_count_i_reg(1), I3 => sync_header_invalid_count_i_reg(3), I4 => sync_header_invalid_count_i_reg(4), O => \p_0_in__7\(4) ); \sync_header_invalid_count_i[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => sync_header_invalid_count_i_reg(3), I1 => sync_header_invalid_count_i_reg(1), I2 => sync_header_invalid_count_i_reg(0), I3 => sync_header_invalid_count_i_reg(2), I4 => sync_header_invalid_count_i_reg(4), I5 => sync_header_invalid_count_i_reg(5), O => \p_0_in__7\(5) ); \sync_header_invalid_count_i[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \sync_header_invalid_count_i[9]_i_2_n_0\, I1 => sync_header_invalid_count_i_reg(6), O => \p_0_in__7\(6) ); \sync_header_invalid_count_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \sync_header_invalid_count_i[9]_i_2_n_0\, I1 => sync_header_invalid_count_i_reg(6), I2 => sync_header_invalid_count_i_reg(7), O => \p_0_in__7\(7) ); \sync_header_invalid_count_i[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sync_header_invalid_count_i_reg(6), I1 => \sync_header_invalid_count_i[9]_i_2_n_0\, I2 => sync_header_invalid_count_i_reg(7), I3 => sync_header_invalid_count_i_reg(8), O => \p_0_in__7\(8) ); \sync_header_invalid_count_i[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sync_header_invalid_count_i_reg(7), I1 => \sync_header_invalid_count_i[9]_i_2_n_0\, I2 => sync_header_invalid_count_i_reg(6), I3 => sync_header_invalid_count_i_reg(8), I4 => sync_header_invalid_count_i_reg(9), O => \p_0_in__7\(9) ); \sync_header_invalid_count_i[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => sync_header_invalid_count_i_reg(5), I1 => sync_header_invalid_count_i_reg(3), I2 => sync_header_invalid_count_i_reg(1), I3 => sync_header_invalid_count_i_reg(0), I4 => sync_header_invalid_count_i_reg(2), I5 => sync_header_invalid_count_i_reg(4), O => \sync_header_invalid_count_i[9]_i_2_n_0\ ); \sync_header_invalid_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(0), Q => sync_header_invalid_count_i_reg(0), R => begin_r ); \sync_header_invalid_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(1), Q => sync_header_invalid_count_i_reg(1), R => begin_r ); \sync_header_invalid_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(2), Q => sync_header_invalid_count_i_reg(2), R => begin_r ); \sync_header_invalid_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(3), Q => sync_header_invalid_count_i_reg(3), R => begin_r ); \sync_header_invalid_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(4), Q => sync_header_invalid_count_i_reg(4), R => begin_r ); \sync_header_invalid_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(5), Q => sync_header_invalid_count_i_reg(5), R => begin_r ); \sync_header_invalid_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(6), Q => sync_header_invalid_count_i_reg(6), R => begin_r ); \sync_header_invalid_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(7), Q => sync_header_invalid_count_i_reg(7), R => begin_r ); \sync_header_invalid_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(8), Q => sync_header_invalid_count_i_reg(8), R => begin_r ); \sync_header_invalid_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => p_1_in(2), D => \p_0_in__7\(9), Q => sync_header_invalid_count_i_reg(9), R => begin_r ); system_reset_r2_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => system_reset_r, Q => system_reset_r2, R => '0' ); system_reset_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => SR(0), Q => system_reset_r, R => '0' ); test_sh_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAA2222AAAA0020" ) port map ( I0 => slip_r_i_2_n_0, I1 => \sh_count_equals_max_i__14\, I2 => p_1_in(2), I3 => RXGEARBOXSLIP_OUT_i_3_n_0, I4 => test_sh_r_i_2_n_0, I5 => p_1_in(3), O => next_test_sh_c ); test_sh_r_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"F4" ) port map ( I0 => rxheadervalid_i, I1 => test_sh_r, I2 => begin_r, O => test_sh_r_i_2_n_0 ); test_sh_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => next_test_sh_c, Q => test_sh_r, R => system_reset_r2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN is port ( gen_ch_bond_int_reg_0 : out STD_LOGIC; data_v_r_reg_0 : in STD_LOGIC; TXDATAVALID_IN : in STD_LOGIC; \free_count_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); gen_ch_bond_int_reg_1 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN is signal data_v_r : STD_LOGIC; signal \free_count_r[0]_i_1_n_0\ : STD_LOGIC; signal \free_count_r[0]_i_3_n_0\ : STD_LOGIC; signal free_count_r_reg : STD_LOGIC_VECTOR ( 0 to 4 ); signal gen_ch_bond_int_i_1_n_0 : STD_LOGIC; signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \free_count_r[0]_i_2\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \free_count_r[0]_i_3\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \free_count_r[1]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \free_count_r[2]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \free_count_r[3]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \free_count_r[4]_i_1\ : label is "soft_lutpair119"; begin data_v_r_reg: unisim.vcomponents.FDRE port map ( C => data_v_r_reg_0, CE => '1', D => TXDATAVALID_IN, Q => data_v_r, R => '0' ); \free_count_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FF20" ) port map ( I0 => data_v_r, I1 => free_count_r_reg(0), I2 => \free_count_r[0]_i_3_n_0\, I3 => \free_count_r_reg[4]_0\(0), O => \free_count_r[0]_i_1_n_0\ ); \free_count_r[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => free_count_r_reg(1), I1 => free_count_r_reg(3), I2 => free_count_r_reg(4), I3 => free_count_r_reg(2), I4 => free_count_r_reg(0), O => \p_0_in__3\(4) ); \free_count_r[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => free_count_r_reg(3), I1 => free_count_r_reg(4), I2 => free_count_r_reg(2), I3 => free_count_r_reg(1), O => \free_count_r[0]_i_3_n_0\ ); \free_count_r[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => free_count_r_reg(2), I1 => free_count_r_reg(4), I2 => free_count_r_reg(3), I3 => free_count_r_reg(1), O => \p_0_in__3\(3) ); \free_count_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => free_count_r_reg(3), I1 => free_count_r_reg(4), I2 => free_count_r_reg(2), O => \p_0_in__3\(2) ); \free_count_r[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => free_count_r_reg(4), I1 => free_count_r_reg(3), O => \p_0_in__3\(1) ); \free_count_r[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => free_count_r_reg(4), O => \p_0_in__3\(0) ); \free_count_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => data_v_r_reg_0, CE => data_v_r, D => \p_0_in__3\(4), Q => free_count_r_reg(0), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => data_v_r_reg_0, CE => data_v_r, D => \p_0_in__3\(3), Q => free_count_r_reg(1), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => data_v_r_reg_0, CE => data_v_r, D => \p_0_in__3\(2), Q => free_count_r_reg(2), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => data_v_r_reg_0, CE => data_v_r, D => \p_0_in__3\(1), Q => free_count_r_reg(3), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => data_v_r_reg_0, CE => data_v_r, D => \p_0_in__3\(0), Q => free_count_r_reg(4), R => \free_count_r[0]_i_1_n_0\ ); gen_ch_bond_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => free_count_r_reg(1), I1 => free_count_r_reg(2), I2 => free_count_r_reg(4), I3 => free_count_r_reg(3), I4 => gen_ch_bond_int_reg_1, I5 => free_count_r_reg(0), O => gen_ch_bond_int_i_1_n_0 ); gen_ch_bond_int_reg: unisim.vcomponents.FDRE port map ( C => data_v_r_reg_0, CE => '1', D => gen_ch_bond_int_i_1_n_0, Q => gen_ch_bond_int_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT is port ( hard_err : out STD_LOGIC; hard_err_i : in STD_LOGIC; CHANNEL_HARD_ERR_reg_0 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT is begin CHANNEL_HARD_ERR_reg: unisim.vcomponents.FDRE port map ( C => CHANNEL_HARD_ERR_reg_0, CE => '1', D => hard_err_i, Q => hard_err, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); wait_for_lane_up_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_0 : out STD_LOGIC; CHANNEL_UP_TX_IF_reg_0 : out STD_LOGIC; gen_cc_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_1 : out STD_LOGIC; R0 : out STD_LOGIC; gen_ch_bond_int_reg : out STD_LOGIC; CHANNEL_UP_RX_IF_reg_2 : out STD_LOGIC; reset_lanes_c : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_3 : in STD_LOGIC; wait_for_lane_up_r_reg_1 : in STD_LOGIC; remote_ready_i : in STD_LOGIC; RX_IDLE : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); \TX_DATA_reg[63]\ : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; gen_cc_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); tx_pe_data_v_i : in STD_LOGIC; rx_pe_data_v_i : in STD_LOGIC; \TX_DATA_reg[63]_0\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM is signal \^channel_up_rx_if_reg_0\ : STD_LOGIC; signal \^channel_up_tx_if_reg_0\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \TX_DATA[55]_i_4_n_0\ : STD_LOGIC; signal \TX_DATA[63]_i_2_n_0\ : STD_LOGIC; signal any_idles_r : STD_LOGIC; signal chan_bond_timeout_val : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of chan_bond_timeout_val : signal is "true"; signal channel_up_c : STD_LOGIC; signal idle_xmit_cntr : STD_LOGIC; signal \idle_xmit_cntr[0]_i_2_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[0]_i_3_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[0]_i_4_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[1]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[2]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[3]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[4]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[5]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[4]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[5]\ : STD_LOGIC; signal next_ready_c : STD_LOGIC; signal next_wait_for_remote_c : STD_LOGIC; signal ready_r : STD_LOGIC; signal ready_r_i_2_n_0 : STD_LOGIC; signal remote_ready_r : STD_LOGIC; signal \^wait_for_lane_up_r_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wait_for_remote_r : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \RX_D[0]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of RX_SRC_RDY_N_inv_i_1 : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \TX_DATA[63]_i_2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of gen_cc_flop_0_i_i_1 : label is "soft_lutpair121"; attribute BOX_TYPE : string; attribute BOX_TYPE of reset_lanes_flop_0_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_lanes_flop_0_i : label is "FD"; begin CHANNEL_UP_RX_IF_reg_0 <= \^channel_up_rx_if_reg_0\; CHANNEL_UP_TX_IF_reg_0 <= \^channel_up_tx_if_reg_0\; SR(0) <= \^sr\(0); wait_for_lane_up_r_reg_0(0) <= \^wait_for_lane_up_r_reg_0\(0); CHANNEL_UP_RX_IF_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => remote_ready_r, Q => \^channel_up_rx_if_reg_0\, R => CHANNEL_UP_RX_IF_reg_4(0) ); CHANNEL_UP_TX_IF_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00404040" ) port map ( I0 => \^wait_for_lane_up_r_reg_0\(0), I1 => remote_ready_r, I2 => ready_r, I3 => wait_for_remote_r, I4 => \idle_xmit_cntr[0]_i_3_n_0\, O => channel_up_c ); CHANNEL_UP_TX_IF_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => channel_up_c, Q => \^channel_up_tx_if_reg_0\, R => CHANNEL_UP_RX_IF_reg_4(0) ); DO_CC_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^channel_up_rx_if_reg_0\, O => CHANNEL_UP_RX_IF_reg_1 ); \RX_D[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^channel_up_rx_if_reg_0\, I1 => rx_pe_data_v_i, O => E(0) ); RX_SRC_RDY_N_inv_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^channel_up_rx_if_reg_0\, I1 => rx_pe_data_v_i, I2 => \^sr\(0), O => CHANNEL_UP_RX_IF_reg_2 ); \TX_DATA[54]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000A000A000E000A" ) port map ( I0 => \TX_DATA_reg[63]\, I1 => \^channel_up_tx_if_reg_0\, I2 => rst_pma_init_usrclk, I3 => gen_cc_i, I4 => Q(0), I5 => \TX_DATA[55]_i_4_n_0\, O => gen_cc_flop_0_i(0) ); \TX_DATA[55]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0A0A0A0A0A0E0A0A" ) port map ( I0 => gen_cc_i, I1 => \^channel_up_tx_if_reg_0\, I2 => rst_pma_init_usrclk, I3 => \TX_DATA_reg[63]\, I4 => Q(1), I5 => \TX_DATA[55]_i_4_n_0\, O => gen_cc_flop_0_i(1) ); \TX_DATA[55]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^wait_for_lane_up_r_reg_0\(0), I1 => tx_pe_data_v_i, O => \TX_DATA[55]_i_4_n_0\ ); \TX_DATA[63]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAA8AAAAAAAAAA" ) port map ( I0 => \TX_DATA_reg[63]_0\, I1 => \TX_DATA_reg[63]\, I2 => gen_cc_i, I3 => tx_pe_data_v_i, I4 => \^wait_for_lane_up_r_reg_0\(0), I5 => \TX_DATA[63]_i_2_n_0\, O => gen_ch_bond_int_reg ); \TX_DATA[63]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^channel_up_tx_if_reg_0\, I1 => rst_pma_init_usrclk, O => \TX_DATA[63]_i_2_n_0\ ); any_idles_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => RX_IDLE, Q => any_idles_r, R => '0' ); gen_cc_flop_0_i_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^channel_up_tx_if_reg_0\, O => R0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(8) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(7) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(6) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(5) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(4) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(3) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(1) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(0) ); \idle_xmit_cntr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFC8FF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[5]\, I1 => wait_for_remote_r, I2 => any_idles_r, I3 => \idle_xmit_cntr[0]_i_3_n_0\, I4 => \idle_xmit_cntr[0]_i_4_n_0\, O => idle_xmit_cntr ); \idle_xmit_cntr[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF80000000" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[3]\, I1 => \idle_xmit_cntr_reg_n_0_[5]\, I2 => \idle_xmit_cntr_reg_n_0_[4]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[1]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[0]_i_2_n_0\ ); \idle_xmit_cntr[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[0]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[2]\, I3 => \idle_xmit_cntr_reg_n_0_[4]\, I4 => \idle_xmit_cntr_reg_n_0_[5]\, I5 => \idle_xmit_cntr_reg_n_0_[3]\, O => \idle_xmit_cntr[0]_i_3_n_0\ ); \idle_xmit_cntr[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF0000FFFE0000" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[4]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[0]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => wait_for_remote_r, I5 => \idle_xmit_cntr_reg_n_0_[3]\, O => \idle_xmit_cntr[0]_i_4_n_0\ ); \idle_xmit_cntr[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAAAAAAA6AAAAAAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[1]\, I1 => \idle_xmit_cntr_reg_n_0_[3]\, I2 => \idle_xmit_cntr_reg_n_0_[5]\, I3 => \idle_xmit_cntr_reg_n_0_[4]\, I4 => \idle_xmit_cntr_reg_n_0_[2]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[1]_i_1_n_0\ ); \idle_xmit_cntr[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAAA6AAA6AAA6AAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[2]\, I1 => \idle_xmit_cntr_reg_n_0_[4]\, I2 => \idle_xmit_cntr_reg_n_0_[5]\, I3 => \idle_xmit_cntr_reg_n_0_[3]\, I4 => \idle_xmit_cntr_reg_n_0_[1]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[2]_i_1_n_0\ ); \idle_xmit_cntr[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EA6A6A6A6A6A6A6A" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[3]\, I1 => \idle_xmit_cntr_reg_n_0_[5]\, I2 => \idle_xmit_cntr_reg_n_0_[4]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[0]\, I5 => \idle_xmit_cntr_reg_n_0_[1]\, O => \idle_xmit_cntr[3]_i_1_n_0\ ); \idle_xmit_cntr[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D5555555AAAAAAAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[5]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[0]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[3]\, I5 => \idle_xmit_cntr_reg_n_0_[4]\, O => \idle_xmit_cntr[4]_i_1_n_0\ ); \idle_xmit_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"80000000FFFFFFFF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[1]\, I1 => \idle_xmit_cntr_reg_n_0_[0]\, I2 => \idle_xmit_cntr_reg_n_0_[2]\, I3 => \idle_xmit_cntr_reg_n_0_[3]\, I4 => \idle_xmit_cntr_reg_n_0_[4]\, I5 => \idle_xmit_cntr_reg_n_0_[5]\, O => \idle_xmit_cntr[5]_i_1_n_0\ ); \idle_xmit_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[0]_i_2_n_0\, Q => \idle_xmit_cntr_reg_n_0_[0]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[1]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[1]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[2]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[2]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[3]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[3]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[4]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[4]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => idle_xmit_cntr, D => \idle_xmit_cntr[5]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[5]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \ready_r_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAEA0000AAAA0000" ) port map ( I0 => ready_r, I1 => \idle_xmit_cntr_reg_n_0_[0]\, I2 => \idle_xmit_cntr_reg_n_0_[1]\, I3 => ready_r_i_2_n_0, I4 => remote_ready_r, I5 => wait_for_remote_r, O => next_ready_c ); ready_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[3]\, I1 => \idle_xmit_cntr_reg_n_0_[5]\, I2 => \idle_xmit_cntr_reg_n_0_[4]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, O => ready_r_i_2_n_0 ); ready_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => next_ready_c, Q => ready_r, R => wait_for_lane_up_r_reg_1 ); remote_ready_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => remote_ready_i, Q => remote_ready_r, R => '0' ); reset_lanes_flop_0_i: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => reset_lanes_c, Q => \^sr\(0), R => '0' ); wait_for_lane_up_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => wait_for_lane_up_r_reg_1, Q => \^wait_for_lane_up_r_reg_0\(0), R => '0' ); wait_for_remote_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF544" ) port map ( I0 => remote_ready_r, I1 => ready_r, I2 => \idle_xmit_cntr[0]_i_3_n_0\, I3 => wait_for_remote_r, I4 => \^wait_for_lane_up_r_reg_0\(0), O => next_wait_for_remote_c ); wait_for_remote_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => CHANNEL_UP_RX_IF_reg_3, CE => '1', D => next_wait_for_remote_c, Q => wait_for_remote_r, R => wait_for_lane_up_r_reg_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B is port ( D : out STD_LOGIC_VECTOR ( 1 downto 0 ); valid_btf_detect_c : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); CB_detect0 : out STD_LOGIC; \descrambler_reg[39]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); in0 : in STD_LOGIC; CC_detect_dlyd1 : in STD_LOGIC; rxdatavalid_to_fifo_i : in STD_LOGIC; CB_detect_dlyd0p5 : in STD_LOGIC; CB_detect_dlyd0p5_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; \descrambler_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \unscrambled_data_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B is signal CC_detect_dlyd1_i_2_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_3_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_4_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_5_n_0 : STD_LOGIC; signal CC_detect_pulse_r_i_2_n_0 : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \descrambler[57]_i_1_n_0\ : STD_LOGIC; signal \^descrambler_reg[39]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \descrambler_reg_n_0_[40]\ : STD_LOGIC; signal \descrambler_reg_n_0_[41]\ : STD_LOGIC; signal \descrambler_reg_n_0_[42]\ : STD_LOGIC; signal \descrambler_reg_n_0_[43]\ : STD_LOGIC; signal \descrambler_reg_n_0_[44]\ : STD_LOGIC; signal \descrambler_reg_n_0_[45]\ : STD_LOGIC; signal \descrambler_reg_n_0_[46]\ : STD_LOGIC; signal \descrambler_reg_n_0_[47]\ : STD_LOGIC; signal \descrambler_reg_n_0_[48]\ : STD_LOGIC; signal \descrambler_reg_n_0_[49]\ : STD_LOGIC; signal \descrambler_reg_n_0_[50]\ : STD_LOGIC; signal \descrambler_reg_n_0_[51]\ : STD_LOGIC; signal \descrambler_reg_n_0_[52]\ : STD_LOGIC; signal \descrambler_reg_n_0_[53]\ : STD_LOGIC; signal \descrambler_reg_n_0_[54]\ : STD_LOGIC; signal \descrambler_reg_n_0_[55]\ : STD_LOGIC; signal \descrambler_reg_n_0_[56]\ : STD_LOGIC; signal \descrambler_reg_n_0_[57]\ : STD_LOGIC; signal p_100_in : STD_LOGIC; signal p_67_in : STD_LOGIC; signal p_69_in : STD_LOGIC; signal p_73_in : STD_LOGIC; signal p_75_in : STD_LOGIC; signal p_78_in : STD_LOGIC; signal p_80_in : STD_LOGIC; signal p_84_in : STD_LOGIC; signal p_86_in : STD_LOGIC; signal p_89_in : STD_LOGIC; signal p_91_in : STD_LOGIC; signal p_95_in : STD_LOGIC; signal p_97_in : STD_LOGIC; signal poly : STD_LOGIC_VECTOR ( 57 downto 32 ); signal tempData : STD_LOGIC_VECTOR ( 0 to 17 ); signal unscrambled_data_i0 : STD_LOGIC; signal unscrambled_data_i012_out : STD_LOGIC; signal unscrambled_data_i016_out : STD_LOGIC; signal unscrambled_data_i020_out : STD_LOGIC; signal unscrambled_data_i024_out : STD_LOGIC; signal unscrambled_data_i028_out : STD_LOGIC; signal unscrambled_data_i032_out : STD_LOGIC; signal unscrambled_data_i036_out : STD_LOGIC; signal unscrambled_data_i040_out : STD_LOGIC; signal unscrambled_data_i044_out : STD_LOGIC; signal unscrambled_data_i048_out : STD_LOGIC; signal unscrambled_data_i04_out : STD_LOGIC; signal unscrambled_data_i08_out : STD_LOGIC; signal \wdth_conv_1stage[38]_i_2_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of CC_detect_pulse_r_i_1 : label is "soft_lutpair58"; attribute SOFT_HLUTNM of CC_detect_pulse_r_i_2 : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \unscrambled_data_i[0]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \unscrambled_data_i[10]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \unscrambled_data_i[11]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \unscrambled_data_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \unscrambled_data_i[19]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \unscrambled_data_i[1]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \unscrambled_data_i[20]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \unscrambled_data_i[21]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \unscrambled_data_i[22]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \unscrambled_data_i[23]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \unscrambled_data_i[24]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \unscrambled_data_i[25]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \unscrambled_data_i[26]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \unscrambled_data_i[27]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \unscrambled_data_i[28]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \unscrambled_data_i[29]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \unscrambled_data_i[2]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \unscrambled_data_i[30]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \unscrambled_data_i[31]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \unscrambled_data_i[3]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \unscrambled_data_i[4]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \unscrambled_data_i[5]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \unscrambled_data_i[6]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \unscrambled_data_i[7]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \unscrambled_data_i[8]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \unscrambled_data_i[9]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \wdth_conv_1stage[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \wdth_conv_1stage[38]_i_2\ : label is "soft_lutpair57"; begin Q(31 downto 0) <= \^q\(31 downto 0); \descrambler_reg[39]_0\(1 downto 0) <= \^descrambler_reg[39]_0\(1 downto 0); CB_detect_dlyd0p5_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => CC_detect_dlyd1_i_2_n_0, I1 => CC_detect_dlyd1_i_4_n_0, I2 => \^q\(22), I3 => \^q\(23), I4 => rxdatavalid_to_fifo_i, I5 => CC_detect_dlyd1_i_3_n_0, O => CB_detect0 ); CC_detect_dlyd1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => CC_detect_dlyd1_i_2_n_0, I1 => CC_detect_dlyd1_i_3_n_0, I2 => rxdatavalid_to_fifo_i, I3 => \^q\(22), I4 => \^q\(23), I5 => CC_detect_dlyd1_i_4_n_0, O => valid_btf_detect_c ); CC_detect_dlyd1_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \^q\(24), I1 => \^q\(26), I2 => \^q\(16), I3 => \^q\(20), I4 => CC_detect_dlyd1_i_5_n_0, O => CC_detect_dlyd1_i_2_n_0 ); CC_detect_dlyd1_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => \^q\(28), I1 => CB_detect_dlyd0p5_reg(1), I2 => \^q\(29), I3 => CB_detect_dlyd0p5_reg(0), O => CC_detect_dlyd1_i_3_n_0 ); CC_detect_dlyd1_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FFF7" ) port map ( I0 => \^q\(27), I1 => \^q\(30), I2 => \^q\(19), I3 => \^q\(21), O => CC_detect_dlyd1_i_4_n_0 ); CC_detect_dlyd1_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \^q\(18), I1 => \^q\(25), I2 => \^q\(31), I3 => \^q\(17), O => CC_detect_dlyd1_i_5_n_0 ); CC_detect_pulse_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => CC_detect_pulse_r_i_2_n_0, I1 => CC_detect_dlyd1_i_2_n_0, I2 => CC_detect_dlyd1, O => D(1) ); CC_detect_pulse_r_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFBFF" ) port map ( I0 => CC_detect_dlyd1_i_4_n_0, I1 => \^q\(23), I2 => \^q\(22), I3 => rxdatavalid_to_fifo_i, I4 => CC_detect_dlyd1_i_3_n_0, O => CC_detect_pulse_r_i_2_n_0 ); \descrambler[57]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => in0, O => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[0]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(0), Q => poly(32), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[10]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(10), Q => poly(42), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(11), Q => poly(43), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[12]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(12), Q => poly(44), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(13), Q => poly(45), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[14]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(14), Q => poly(46), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(15), Q => poly(47), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[16]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(16), Q => poly(48), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[17]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(17), Q => poly(49), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[18]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(18), Q => poly(50), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[19]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(19), Q => poly(51), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(1), Q => poly(33), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[20]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(20), Q => \^descrambler_reg[39]_0\(0), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[21]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(21), Q => poly(53), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[22]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(22), Q => poly(54), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[23]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(23), Q => poly(55), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[24]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(24), Q => poly(56), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[25]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(25), Q => poly(57), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[26]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(26), Q => p_67_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[27]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(27), Q => p_69_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[28]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(28), Q => p_73_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[29]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(29), Q => p_75_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[2]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(2), Q => poly(34), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[30]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(30), Q => p_78_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[31]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(31), Q => p_80_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[32]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(32), Q => p_84_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[33]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(33), Q => p_86_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[34]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(34), Q => p_89_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[35]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(35), Q => p_91_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[36]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(36), Q => p_95_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[37]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(37), Q => p_97_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[38]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(38), Q => p_100_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[39]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(39), Q => \^descrambler_reg[39]_0\(1), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(3), Q => poly(35), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[40]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(40), Q => \descrambler_reg_n_0_[40]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[41]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(41), Q => \descrambler_reg_n_0_[41]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[42]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(42), Q => \descrambler_reg_n_0_[42]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[43]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(43), Q => \descrambler_reg_n_0_[43]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[44]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(44), Q => \descrambler_reg_n_0_[44]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[45]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(45), Q => \descrambler_reg_n_0_[45]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[46]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(46), Q => \descrambler_reg_n_0_[46]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[47]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(47), Q => \descrambler_reg_n_0_[47]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[48]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(48), Q => \descrambler_reg_n_0_[48]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[49]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(49), Q => \descrambler_reg_n_0_[49]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[4]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(4), Q => poly(36), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[50]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(50), Q => \descrambler_reg_n_0_[50]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[51]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(51), Q => \descrambler_reg_n_0_[51]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[52]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \^descrambler_reg[39]_0\(0), Q => \descrambler_reg_n_0_[52]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[53]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(53), Q => \descrambler_reg_n_0_[53]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[54]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(54), Q => \descrambler_reg_n_0_[54]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[55]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(55), Q => \descrambler_reg_n_0_[55]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[56]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(56), Q => \descrambler_reg_n_0_[56]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[57]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => poly(57), Q => \descrambler_reg_n_0_[57]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(5), Q => poly(37), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[6]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(6), Q => poly(38), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(7), Q => poly(39), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[8]\: unisim.vcomponents.FDSE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(8), Q => poly(40), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \descrambler_reg[31]_0\(9), Q => poly(41), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(39), I1 => \descrambler_reg[31]_0\(0), I2 => p_67_in, O => unscrambled_data_i0 ); \unscrambled_data_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(49), I1 => \descrambler_reg[31]_0\(10), I2 => p_95_in, O => unscrambled_data_i040_out ); \unscrambled_data_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(50), I1 => \descrambler_reg[31]_0\(11), I2 => p_97_in, O => unscrambled_data_i044_out ); \unscrambled_data_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(51), I1 => \descrambler_reg[31]_0\(12), I2 => p_100_in, O => unscrambled_data_i048_out ); \unscrambled_data_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(53), I1 => \descrambler_reg[31]_0\(14), I2 => \descrambler_reg_n_0_[40]\, O => tempData(17) ); \unscrambled_data_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(54), I1 => \descrambler_reg[31]_0\(15), I2 => \descrambler_reg_n_0_[41]\, O => tempData(16) ); \unscrambled_data_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(55), I1 => \descrambler_reg[31]_0\(16), I2 => \descrambler_reg_n_0_[42]\, O => tempData(15) ); \unscrambled_data_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(56), I1 => \descrambler_reg[31]_0\(17), I2 => \descrambler_reg_n_0_[43]\, O => tempData(14) ); \unscrambled_data_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(57), I1 => \descrambler_reg[31]_0\(18), I2 => \descrambler_reg_n_0_[44]\, O => tempData(13) ); \unscrambled_data_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_67_in, I1 => \descrambler_reg[31]_0\(19), I2 => \descrambler_reg_n_0_[45]\, O => tempData(12) ); \unscrambled_data_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(40), I1 => \descrambler_reg[31]_0\(1), I2 => p_69_in, O => unscrambled_data_i04_out ); \unscrambled_data_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_69_in, I1 => \descrambler_reg[31]_0\(20), I2 => \descrambler_reg_n_0_[46]\, O => tempData(11) ); \unscrambled_data_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_73_in, I1 => \descrambler_reg[31]_0\(21), I2 => \descrambler_reg_n_0_[47]\, O => tempData(10) ); \unscrambled_data_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_75_in, I1 => \descrambler_reg[31]_0\(22), I2 => \descrambler_reg_n_0_[48]\, O => tempData(9) ); \unscrambled_data_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_78_in, I1 => \descrambler_reg[31]_0\(23), I2 => \descrambler_reg_n_0_[49]\, O => tempData(8) ); \unscrambled_data_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_80_in, I1 => \descrambler_reg[31]_0\(24), I2 => \descrambler_reg_n_0_[50]\, O => tempData(7) ); \unscrambled_data_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_84_in, I1 => \descrambler_reg[31]_0\(25), I2 => \descrambler_reg_n_0_[51]\, O => tempData(6) ); \unscrambled_data_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_86_in, I1 => \descrambler_reg[31]_0\(26), I2 => \descrambler_reg_n_0_[52]\, O => tempData(5) ); \unscrambled_data_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_89_in, I1 => \descrambler_reg[31]_0\(27), I2 => \descrambler_reg_n_0_[53]\, O => tempData(4) ); \unscrambled_data_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_91_in, I1 => \descrambler_reg[31]_0\(28), I2 => \descrambler_reg_n_0_[54]\, O => tempData(3) ); \unscrambled_data_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_95_in, I1 => \descrambler_reg[31]_0\(29), I2 => \descrambler_reg_n_0_[55]\, O => tempData(2) ); \unscrambled_data_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(41), I1 => \descrambler_reg[31]_0\(2), I2 => p_73_in, O => unscrambled_data_i08_out ); \unscrambled_data_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_97_in, I1 => \descrambler_reg[31]_0\(30), I2 => \descrambler_reg_n_0_[56]\, O => tempData(1) ); \unscrambled_data_i[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_100_in, I1 => \descrambler_reg[31]_0\(31), I2 => \descrambler_reg_n_0_[57]\, O => tempData(0) ); \unscrambled_data_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(42), I1 => \descrambler_reg[31]_0\(3), I2 => p_75_in, O => unscrambled_data_i012_out ); \unscrambled_data_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(43), I1 => \descrambler_reg[31]_0\(4), I2 => p_78_in, O => unscrambled_data_i016_out ); \unscrambled_data_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(44), I1 => \descrambler_reg[31]_0\(5), I2 => p_80_in, O => unscrambled_data_i020_out ); \unscrambled_data_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(45), I1 => \descrambler_reg[31]_0\(6), I2 => p_84_in, O => unscrambled_data_i024_out ); \unscrambled_data_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(46), I1 => \descrambler_reg[31]_0\(7), I2 => p_86_in, O => unscrambled_data_i028_out ); \unscrambled_data_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(47), I1 => \descrambler_reg[31]_0\(8), I2 => p_89_in, O => unscrambled_data_i032_out ); \unscrambled_data_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(48), I1 => \descrambler_reg[31]_0\(9), I2 => p_91_in, O => unscrambled_data_i036_out ); \unscrambled_data_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i0, Q => \^q\(0), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i040_out, Q => \^q\(10), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i044_out, Q => \^q\(11), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i048_out, Q => \^q\(12), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => \unscrambled_data_i_reg[13]_0\(0), Q => \^q\(13), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(17), Q => \^q\(14), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(16), Q => \^q\(15), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(15), Q => \^q\(16), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(14), Q => \^q\(17), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(13), Q => \^q\(18), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(12), Q => \^q\(19), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i04_out, Q => \^q\(1), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(11), Q => \^q\(20), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(10), Q => \^q\(21), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(9), Q => \^q\(22), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(8), Q => \^q\(23), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(7), Q => \^q\(24), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(6), Q => \^q\(25), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(5), Q => \^q\(26), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(4), Q => \^q\(27), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(3), Q => \^q\(28), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(2), Q => \^q\(29), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i08_out, Q => \^q\(2), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(1), Q => \^q\(30), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => tempData(0), Q => \^q\(31), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i012_out, Q => \^q\(3), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i016_out, Q => \^q\(4), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i020_out, Q => \^q\(5), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i024_out, Q => \^q\(6), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i028_out, Q => \^q\(7), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i032_out, Q => \^q\(8), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => E(0), D => unscrambled_data_i036_out, Q => \^q\(9), R => \descrambler[57]_i_1_n_0\ ); \wdth_conv_1stage[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => CB_detect_dlyd0p5, I1 => \wdth_conv_1stage[38]_i_2_n_0\, I2 => CC_detect_dlyd1_i_2_n_0, O => D(0) ); \wdth_conv_1stage[38]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFBFF" ) port map ( I0 => CC_detect_dlyd1_i_3_n_0, I1 => rxdatavalid_to_fifo_i, I2 => \^q\(23), I3 => \^q\(22), I4 => CC_detect_dlyd1_i_4_n_0, O => \wdth_conv_1stage[38]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT is port ( hard_err_i : out STD_LOGIC; SOFT_ERR_reg_0 : out STD_LOGIC; SOFT_ERR_reg_1 : in STD_LOGIC; HARD_ERR_reg_0 : in STD_LOGIC; HARD_ERR_reg_1 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT is signal soft_err_i : STD_LOGIC; begin HARD_ERR_reg: unisim.vcomponents.FDRE port map ( C => HARD_ERR_reg_0, CE => '1', D => HARD_ERR_reg_1, Q => hard_err_i, R => '0' ); SOFT_ERR_reg: unisim.vcomponents.FDRE port map ( C => HARD_ERR_reg_0, CE => '1', D => SOFT_ERR_reg_1, Q => soft_err_i, R => '0' ); soft_err_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => soft_err_i, I1 => channel_up_tx_if, O => SOFT_ERR_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH is port ( m_axi_rx_tvalid : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); RX_SRC_RDY_N_reg_inv_0 : in STD_LOGIC; RX_SRC_RDY_N_reg_inv_1 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 63 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH is attribute inverted : string; attribute inverted of RX_SRC_RDY_N_reg_inv : label is "yes"; begin \RX_D_reg[0]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(63), Q => m_axi_rx_tdata(0), R => SR(0) ); \RX_D_reg[10]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(53), Q => m_axi_rx_tdata(10), R => SR(0) ); \RX_D_reg[11]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(52), Q => m_axi_rx_tdata(11), R => SR(0) ); \RX_D_reg[12]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(51), Q => m_axi_rx_tdata(12), R => SR(0) ); \RX_D_reg[13]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(50), Q => m_axi_rx_tdata(13), R => SR(0) ); \RX_D_reg[14]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(49), Q => m_axi_rx_tdata(14), R => SR(0) ); \RX_D_reg[15]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(48), Q => m_axi_rx_tdata(15), R => SR(0) ); \RX_D_reg[16]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(47), Q => m_axi_rx_tdata(16), R => SR(0) ); \RX_D_reg[17]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(46), Q => m_axi_rx_tdata(17), R => SR(0) ); \RX_D_reg[18]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(45), Q => m_axi_rx_tdata(18), R => SR(0) ); \RX_D_reg[19]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(44), Q => m_axi_rx_tdata(19), R => SR(0) ); \RX_D_reg[1]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(62), Q => m_axi_rx_tdata(1), R => SR(0) ); \RX_D_reg[20]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(43), Q => m_axi_rx_tdata(20), R => SR(0) ); \RX_D_reg[21]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(42), Q => m_axi_rx_tdata(21), R => SR(0) ); \RX_D_reg[22]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(41), Q => m_axi_rx_tdata(22), R => SR(0) ); \RX_D_reg[23]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(40), Q => m_axi_rx_tdata(23), R => SR(0) ); \RX_D_reg[24]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(39), Q => m_axi_rx_tdata(24), R => SR(0) ); \RX_D_reg[25]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(38), Q => m_axi_rx_tdata(25), R => SR(0) ); \RX_D_reg[26]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(37), Q => m_axi_rx_tdata(26), R => SR(0) ); \RX_D_reg[27]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(36), Q => m_axi_rx_tdata(27), R => SR(0) ); \RX_D_reg[28]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(35), Q => m_axi_rx_tdata(28), R => SR(0) ); \RX_D_reg[29]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(34), Q => m_axi_rx_tdata(29), R => SR(0) ); \RX_D_reg[2]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(61), Q => m_axi_rx_tdata(2), R => SR(0) ); \RX_D_reg[30]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(33), Q => m_axi_rx_tdata(30), R => SR(0) ); \RX_D_reg[31]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(32), Q => m_axi_rx_tdata(31), R => SR(0) ); \RX_D_reg[32]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(31), Q => m_axi_rx_tdata(32), R => SR(0) ); \RX_D_reg[33]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(30), Q => m_axi_rx_tdata(33), R => SR(0) ); \RX_D_reg[34]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(29), Q => m_axi_rx_tdata(34), R => SR(0) ); \RX_D_reg[35]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(28), Q => m_axi_rx_tdata(35), R => SR(0) ); \RX_D_reg[36]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(27), Q => m_axi_rx_tdata(36), R => SR(0) ); \RX_D_reg[37]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(26), Q => m_axi_rx_tdata(37), R => SR(0) ); \RX_D_reg[38]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(25), Q => m_axi_rx_tdata(38), R => SR(0) ); \RX_D_reg[39]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(24), Q => m_axi_rx_tdata(39), R => SR(0) ); \RX_D_reg[3]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(60), Q => m_axi_rx_tdata(3), R => SR(0) ); \RX_D_reg[40]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(23), Q => m_axi_rx_tdata(40), R => SR(0) ); \RX_D_reg[41]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(22), Q => m_axi_rx_tdata(41), R => SR(0) ); \RX_D_reg[42]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(21), Q => m_axi_rx_tdata(42), R => SR(0) ); \RX_D_reg[43]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(20), Q => m_axi_rx_tdata(43), R => SR(0) ); \RX_D_reg[44]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(19), Q => m_axi_rx_tdata(44), R => SR(0) ); \RX_D_reg[45]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(18), Q => m_axi_rx_tdata(45), R => SR(0) ); \RX_D_reg[46]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(17), Q => m_axi_rx_tdata(46), R => SR(0) ); \RX_D_reg[47]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(16), Q => m_axi_rx_tdata(47), R => SR(0) ); \RX_D_reg[48]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(15), Q => m_axi_rx_tdata(48), R => SR(0) ); \RX_D_reg[49]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(14), Q => m_axi_rx_tdata(49), R => SR(0) ); \RX_D_reg[4]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(59), Q => m_axi_rx_tdata(4), R => SR(0) ); \RX_D_reg[50]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(13), Q => m_axi_rx_tdata(50), R => SR(0) ); \RX_D_reg[51]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(12), Q => m_axi_rx_tdata(51), R => SR(0) ); \RX_D_reg[52]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(11), Q => m_axi_rx_tdata(52), R => SR(0) ); \RX_D_reg[53]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(10), Q => m_axi_rx_tdata(53), R => SR(0) ); \RX_D_reg[54]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(9), Q => m_axi_rx_tdata(54), R => SR(0) ); \RX_D_reg[55]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(8), Q => m_axi_rx_tdata(55), R => SR(0) ); \RX_D_reg[56]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(7), Q => m_axi_rx_tdata(56), R => SR(0) ); \RX_D_reg[57]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(6), Q => m_axi_rx_tdata(57), R => SR(0) ); \RX_D_reg[58]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(5), Q => m_axi_rx_tdata(58), R => SR(0) ); \RX_D_reg[59]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(4), Q => m_axi_rx_tdata(59), R => SR(0) ); \RX_D_reg[5]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(58), Q => m_axi_rx_tdata(5), R => SR(0) ); \RX_D_reg[60]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(3), Q => m_axi_rx_tdata(60), R => SR(0) ); \RX_D_reg[61]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(2), Q => m_axi_rx_tdata(61), R => SR(0) ); \RX_D_reg[62]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(1), Q => m_axi_rx_tdata(62), R => SR(0) ); \RX_D_reg[63]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(0), Q => m_axi_rx_tdata(63), R => SR(0) ); \RX_D_reg[6]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(57), Q => m_axi_rx_tdata(6), R => SR(0) ); \RX_D_reg[7]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(56), Q => m_axi_rx_tdata(7), R => SR(0) ); \RX_D_reg[8]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(55), Q => m_axi_rx_tdata(8), R => SR(0) ); \RX_D_reg[9]\: unisim.vcomponents.FDRE port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => E(0), D => D(54), Q => m_axi_rx_tdata(9), R => SR(0) ); RX_SRC_RDY_N_reg_inv: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => RX_SRC_RDY_N_reg_inv_1, CE => '1', D => RX_SRC_RDY_N_reg_inv_0, Q => m_axi_rx_tvalid, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B is port ( \txseq_counter_i_reg[0]\ : out STD_LOGIC; scrambler : out STD_LOGIC_VECTOR ( 11 downto 0 ); \SCRAMBLED_DATA_OUT_reg[63]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); tx_data_i : in STD_LOGIC_VECTOR ( 57 downto 0 ); \SCRAMBLED_DATA_OUT_reg[63]_1\ : in STD_LOGIC; tempData : in STD_LOGIC_VECTOR ( 5 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B is signal data_valid_i : STD_LOGIC; signal p_101_in : STD_LOGIC; signal p_105_in : STD_LOGIC; signal p_109_in : STD_LOGIC; signal p_113_in : STD_LOGIC; signal p_117_in : STD_LOGIC; signal p_121_in : STD_LOGIC; signal p_125_in : STD_LOGIC; signal p_129_in : STD_LOGIC; signal p_133_in : STD_LOGIC; signal p_137_in : STD_LOGIC; signal p_141_in : STD_LOGIC; signal p_145_in : STD_LOGIC; signal p_149_in : STD_LOGIC; signal p_177_in : STD_LOGIC; signal p_181_in : STD_LOGIC; signal p_185_in : STD_LOGIC; signal p_189_in : STD_LOGIC; signal p_193_in : STD_LOGIC; signal p_197_in : STD_LOGIC; signal p_201_in : STD_LOGIC; signal p_205_in : STD_LOGIC; signal p_209_in : STD_LOGIC; signal p_213_in : STD_LOGIC; signal p_217_in : STD_LOGIC; signal p_221_in : STD_LOGIC; signal p_225_in : STD_LOGIC; signal p_229_in : STD_LOGIC; signal p_233_in : STD_LOGIC; signal p_237_in : STD_LOGIC; signal p_241_in : STD_LOGIC; signal p_245_in : STD_LOGIC; signal p_249_in : STD_LOGIC; signal p_97_in : STD_LOGIC; signal \^scrambler\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \scrambler_reg_n_0_[39]\ : STD_LOGIC; signal \scrambler_reg_n_0_[40]\ : STD_LOGIC; signal \scrambler_reg_n_0_[41]\ : STD_LOGIC; signal \scrambler_reg_n_0_[42]\ : STD_LOGIC; signal \scrambler_reg_n_0_[43]\ : STD_LOGIC; signal \scrambler_reg_n_0_[44]\ : STD_LOGIC; signal \scrambler_reg_n_0_[45]\ : STD_LOGIC; signal \scrambler_reg_n_0_[46]\ : STD_LOGIC; signal \scrambler_reg_n_0_[47]\ : STD_LOGIC; signal \scrambler_reg_n_0_[48]\ : STD_LOGIC; signal \scrambler_reg_n_0_[49]\ : STD_LOGIC; signal \scrambler_reg_n_0_[50]\ : STD_LOGIC; signal \scrambler_reg_n_0_[51]\ : STD_LOGIC; signal tempData0100_out : STD_LOGIC; signal tempData0104_out : STD_LOGIC; signal tempData0108_out : STD_LOGIC; signal tempData0112_out : STD_LOGIC; signal tempData0116_out : STD_LOGIC; signal tempData0120_out : STD_LOGIC; signal tempData0124_out : STD_LOGIC; signal tempData0128_out : STD_LOGIC; signal tempData0132_out : STD_LOGIC; signal tempData0136_out : STD_LOGIC; signal tempData0140_out : STD_LOGIC; signal tempData0144_out : STD_LOGIC; signal tempData0148_out : STD_LOGIC; signal tempData0152_out : STD_LOGIC; signal tempData0156_out : STD_LOGIC; signal tempData0160_out : STD_LOGIC; signal tempData0164_out : STD_LOGIC; signal tempData0168_out : STD_LOGIC; signal tempData0172_out : STD_LOGIC; signal tempData0176_out : STD_LOGIC; signal tempData0180_out : STD_LOGIC; signal tempData0184_out : STD_LOGIC; signal tempData0188_out : STD_LOGIC; signal tempData0192_out : STD_LOGIC; signal tempData0196_out : STD_LOGIC; signal tempData0200_out : STD_LOGIC; signal tempData0204_out : STD_LOGIC; signal tempData0208_out : STD_LOGIC; signal tempData0212_out : STD_LOGIC; signal tempData0216_out : STD_LOGIC; signal tempData0220_out : STD_LOGIC; signal tempData0224_out : STD_LOGIC; signal tempData0228_out : STD_LOGIC; signal tempData0232_out : STD_LOGIC; signal tempData0236_out : STD_LOGIC; signal tempData0240_out : STD_LOGIC; signal tempData0244_out : STD_LOGIC; signal tempData0248_out : STD_LOGIC; signal tempData024_out : STD_LOGIC; signal tempData0252_out : STD_LOGIC; signal tempData028_out : STD_LOGIC; signal tempData032_out : STD_LOGIC; signal tempData036_out : STD_LOGIC; signal tempData040_out : STD_LOGIC; signal tempData044_out : STD_LOGIC; signal tempData048_out : STD_LOGIC; signal tempData052_out : STD_LOGIC; signal tempData056_out : STD_LOGIC; signal tempData060_out : STD_LOGIC; signal tempData064_out : STD_LOGIC; signal tempData068_out : STD_LOGIC; signal tempData072_out : STD_LOGIC; signal tempData076_out : STD_LOGIC; signal tempData080_out : STD_LOGIC; signal tempData084_out : STD_LOGIC; signal tempData088_out : STD_LOGIC; signal tempData092_out : STD_LOGIC; signal tempData096_out : STD_LOGIC; signal \^txseq_counter_i_reg[0]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[58]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[59]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[60]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[61]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[62]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[63]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \scrambler[10]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \scrambler[11]_i_1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \scrambler[12]_i_1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \scrambler[13]_i_1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \scrambler[14]_i_1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \scrambler[15]_i_1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \scrambler[16]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \scrambler[17]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \scrambler[18]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \scrambler[19]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \scrambler[20]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \scrambler[21]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \scrambler[22]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \scrambler[23]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \scrambler[24]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \scrambler[25]_i_1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \scrambler[44]_i_1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \scrambler[45]_i_1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \scrambler[46]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \scrambler[47]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \scrambler[48]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \scrambler[49]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \scrambler[50]_i_1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \scrambler[51]_i_1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \scrambler[52]_i_1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \scrambler[53]_i_1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \scrambler[54]_i_1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \scrambler[55]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \scrambler[56]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \scrambler[57]_i_2\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \scrambler[6]_i_1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \scrambler[7]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \scrambler[8]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \scrambler[9]_i_1\ : label is "soft_lutpair87"; begin scrambler(11 downto 0) <= \^scrambler\(11 downto 0); \txseq_counter_i_reg[0]\ <= \^txseq_counter_i_reg[0]\; \SCRAMBLED_DATA_OUT[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_229_in, I1 => tx_data_i(52), I2 => \^scrambler\(6), O => tempData0232_out ); \SCRAMBLED_DATA_OUT[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_233_in, I1 => tx_data_i(53), I2 => \^scrambler\(7), O => tempData0236_out ); \SCRAMBLED_DATA_OUT[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_237_in, I1 => tx_data_i(54), I2 => \^scrambler\(8), O => tempData0240_out ); \SCRAMBLED_DATA_OUT[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_241_in, I1 => tx_data_i(55), I2 => \^scrambler\(9), O => tempData0244_out ); \SCRAMBLED_DATA_OUT[62]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_245_in, I1 => tx_data_i(56), I2 => \^scrambler\(10), O => tempData0248_out ); \SCRAMBLED_DATA_OUT[63]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_249_in, I1 => tx_data_i(57), I2 => \^scrambler\(11), O => tempData0252_out ); \SCRAMBLED_DATA_OUT_reg[0]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(0), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(0), R => '0' ); \SCRAMBLED_DATA_OUT_reg[10]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData040_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(10), R => '0' ); \SCRAMBLED_DATA_OUT_reg[11]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData044_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(11), R => '0' ); \SCRAMBLED_DATA_OUT_reg[12]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData048_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(12), R => '0' ); \SCRAMBLED_DATA_OUT_reg[13]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData052_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(13), R => '0' ); \SCRAMBLED_DATA_OUT_reg[14]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData056_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(14), R => '0' ); \SCRAMBLED_DATA_OUT_reg[15]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData060_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(15), R => '0' ); \SCRAMBLED_DATA_OUT_reg[16]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData064_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(16), R => '0' ); \SCRAMBLED_DATA_OUT_reg[17]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData068_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(17), R => '0' ); \SCRAMBLED_DATA_OUT_reg[18]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData072_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(18), R => '0' ); \SCRAMBLED_DATA_OUT_reg[19]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData076_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(19), R => '0' ); \SCRAMBLED_DATA_OUT_reg[1]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(1), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(1), R => '0' ); \SCRAMBLED_DATA_OUT_reg[20]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData080_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(20), R => '0' ); \SCRAMBLED_DATA_OUT_reg[21]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData084_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(21), R => '0' ); \SCRAMBLED_DATA_OUT_reg[22]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData088_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(22), R => '0' ); \SCRAMBLED_DATA_OUT_reg[23]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData092_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(23), R => '0' ); \SCRAMBLED_DATA_OUT_reg[24]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData096_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(24), R => '0' ); \SCRAMBLED_DATA_OUT_reg[25]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0100_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(25), R => '0' ); \SCRAMBLED_DATA_OUT_reg[26]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0104_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(26), R => '0' ); \SCRAMBLED_DATA_OUT_reg[27]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0108_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(27), R => '0' ); \SCRAMBLED_DATA_OUT_reg[28]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0112_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(28), R => '0' ); \SCRAMBLED_DATA_OUT_reg[29]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0116_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(29), R => '0' ); \SCRAMBLED_DATA_OUT_reg[2]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(2), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(2), R => '0' ); \SCRAMBLED_DATA_OUT_reg[30]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0120_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(30), R => '0' ); \SCRAMBLED_DATA_OUT_reg[31]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0124_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(31), R => '0' ); \SCRAMBLED_DATA_OUT_reg[32]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0128_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(32), R => '0' ); \SCRAMBLED_DATA_OUT_reg[33]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0132_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(33), R => '0' ); \SCRAMBLED_DATA_OUT_reg[34]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0136_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(34), R => '0' ); \SCRAMBLED_DATA_OUT_reg[35]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0140_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(35), R => '0' ); \SCRAMBLED_DATA_OUT_reg[36]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0144_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(36), R => '0' ); \SCRAMBLED_DATA_OUT_reg[37]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0148_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(37), R => '0' ); \SCRAMBLED_DATA_OUT_reg[38]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0152_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(38), R => '0' ); \SCRAMBLED_DATA_OUT_reg[39]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0156_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(39), R => '0' ); \SCRAMBLED_DATA_OUT_reg[3]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(3), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(3), R => '0' ); \SCRAMBLED_DATA_OUT_reg[40]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0160_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(40), R => '0' ); \SCRAMBLED_DATA_OUT_reg[41]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0164_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(41), R => '0' ); \SCRAMBLED_DATA_OUT_reg[42]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0168_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(42), R => '0' ); \SCRAMBLED_DATA_OUT_reg[43]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0172_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(43), R => '0' ); \SCRAMBLED_DATA_OUT_reg[44]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0176_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(44), R => '0' ); \SCRAMBLED_DATA_OUT_reg[45]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0180_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(45), R => '0' ); \SCRAMBLED_DATA_OUT_reg[46]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0184_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(46), R => '0' ); \SCRAMBLED_DATA_OUT_reg[47]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0188_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(47), R => '0' ); \SCRAMBLED_DATA_OUT_reg[48]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0192_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(48), R => '0' ); \SCRAMBLED_DATA_OUT_reg[49]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0196_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(49), R => '0' ); \SCRAMBLED_DATA_OUT_reg[4]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(4), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(4), R => '0' ); \SCRAMBLED_DATA_OUT_reg[50]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0200_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(50), R => '0' ); \SCRAMBLED_DATA_OUT_reg[51]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0204_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(51), R => '0' ); \SCRAMBLED_DATA_OUT_reg[52]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0208_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(52), R => '0' ); \SCRAMBLED_DATA_OUT_reg[53]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0212_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(53), R => '0' ); \SCRAMBLED_DATA_OUT_reg[54]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0216_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(54), R => '0' ); \SCRAMBLED_DATA_OUT_reg[55]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0220_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(55), R => '0' ); \SCRAMBLED_DATA_OUT_reg[56]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0224_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(56), R => '0' ); \SCRAMBLED_DATA_OUT_reg[57]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0228_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(57), R => '0' ); \SCRAMBLED_DATA_OUT_reg[58]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0232_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(58), R => '0' ); \SCRAMBLED_DATA_OUT_reg[59]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0236_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(59), R => '0' ); \SCRAMBLED_DATA_OUT_reg[5]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(5), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(5), R => '0' ); \SCRAMBLED_DATA_OUT_reg[60]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0240_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(60), R => '0' ); \SCRAMBLED_DATA_OUT_reg[61]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0244_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(61), R => '0' ); \SCRAMBLED_DATA_OUT_reg[62]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0248_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(62), R => '0' ); \SCRAMBLED_DATA_OUT_reg[63]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0252_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(63), R => '0' ); \SCRAMBLED_DATA_OUT_reg[6]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData024_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(6), R => '0' ); \SCRAMBLED_DATA_OUT_reg[7]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData028_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(7), R => '0' ); \SCRAMBLED_DATA_OUT_reg[8]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData032_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(8), R => '0' ); \SCRAMBLED_DATA_OUT_reg[9]\: unisim.vcomponents.FDRE port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData036_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(9), R => '0' ); \scrambler[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[43]\, I1 => tx_data_i(43), I2 => p_193_in, I3 => tx_data_i(4), I4 => p_113_in, O => tempData040_out ); \scrambler[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[44]\, I1 => tx_data_i(44), I2 => p_197_in, I3 => tx_data_i(5), I4 => p_117_in, O => tempData044_out ); \scrambler[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[45]\, I1 => tx_data_i(45), I2 => p_201_in, I3 => tx_data_i(6), I4 => p_121_in, O => tempData048_out ); \scrambler[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[46]\, I1 => tx_data_i(46), I2 => p_205_in, I3 => tx_data_i(7), I4 => p_125_in, O => tempData052_out ); \scrambler[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[47]\, I1 => tx_data_i(47), I2 => p_209_in, I3 => tx_data_i(8), I4 => p_129_in, O => tempData056_out ); \scrambler[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[48]\, I1 => tx_data_i(48), I2 => p_213_in, I3 => tx_data_i(9), I4 => p_133_in, O => tempData060_out ); \scrambler[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[49]\, I1 => tx_data_i(49), I2 => p_217_in, I3 => tx_data_i(10), I4 => p_137_in, O => tempData064_out ); \scrambler[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[50]\, I1 => tx_data_i(50), I2 => p_221_in, I3 => tx_data_i(11), I4 => p_141_in, O => tempData068_out ); \scrambler[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[51]\, I1 => tx_data_i(51), I2 => p_225_in, I3 => tx_data_i(12), I4 => p_145_in, O => tempData072_out ); \scrambler[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(6), I1 => tx_data_i(52), I2 => p_229_in, I3 => tx_data_i(13), I4 => p_149_in, O => tempData076_out ); \scrambler[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(7), I1 => tx_data_i(53), I2 => p_233_in, I3 => tx_data_i(14), I4 => \^scrambler\(0), O => tempData080_out ); \scrambler[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(8), I1 => tx_data_i(54), I2 => p_237_in, I3 => tx_data_i(15), I4 => \^scrambler\(1), O => tempData084_out ); \scrambler[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(9), I1 => tx_data_i(55), I2 => p_241_in, I3 => tx_data_i(16), I4 => \^scrambler\(2), O => tempData088_out ); \scrambler[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(10), I1 => tx_data_i(56), I2 => p_245_in, I3 => tx_data_i(17), I4 => \^scrambler\(3), O => tempData092_out ); \scrambler[24]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(11), I1 => tx_data_i(57), I2 => p_249_in, I3 => tx_data_i(18), I4 => \^scrambler\(4), O => tempData096_out ); \scrambler[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_97_in, I1 => tx_data_i(19), I2 => \^scrambler\(5), O => tempData0100_out ); \scrambler[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_101_in, I1 => tx_data_i(20), I2 => p_177_in, O => tempData0104_out ); \scrambler[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_105_in, I1 => tx_data_i(21), I2 => p_181_in, O => tempData0108_out ); \scrambler[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_109_in, I1 => tx_data_i(22), I2 => p_185_in, O => tempData0112_out ); \scrambler[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_113_in, I1 => tx_data_i(23), I2 => p_189_in, O => tempData0116_out ); \scrambler[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_117_in, I1 => tx_data_i(24), I2 => p_193_in, O => tempData0120_out ); \scrambler[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_121_in, I1 => tx_data_i(25), I2 => p_197_in, O => tempData0124_out ); \scrambler[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_125_in, I1 => tx_data_i(26), I2 => p_201_in, O => tempData0128_out ); \scrambler[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_129_in, I1 => tx_data_i(27), I2 => p_205_in, O => tempData0132_out ); \scrambler[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_133_in, I1 => tx_data_i(28), I2 => p_209_in, O => tempData0136_out ); \scrambler[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_137_in, I1 => tx_data_i(29), I2 => p_213_in, O => tempData0140_out ); \scrambler[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_141_in, I1 => tx_data_i(30), I2 => p_217_in, O => tempData0144_out ); \scrambler[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_145_in, I1 => tx_data_i(31), I2 => p_221_in, O => tempData0148_out ); \scrambler[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_149_in, I1 => tx_data_i(32), I2 => p_225_in, O => tempData0152_out ); \scrambler[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(0), I1 => tx_data_i(33), I2 => p_229_in, O => tempData0156_out ); \scrambler[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(1), I1 => tx_data_i(34), I2 => p_233_in, O => tempData0160_out ); \scrambler[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(2), I1 => tx_data_i(35), I2 => p_237_in, O => tempData0164_out ); \scrambler[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(3), I1 => tx_data_i(36), I2 => p_241_in, O => tempData0168_out ); \scrambler[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(4), I1 => tx_data_i(37), I2 => p_245_in, O => tempData0172_out ); \scrambler[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(5), I1 => tx_data_i(38), I2 => p_249_in, O => tempData0176_out ); \scrambler[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_177_in, I1 => tx_data_i(39), I2 => \scrambler_reg_n_0_[39]\, O => tempData0180_out ); \scrambler[46]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_181_in, I1 => tx_data_i(40), I2 => \scrambler_reg_n_0_[40]\, O => tempData0184_out ); \scrambler[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_185_in, I1 => tx_data_i(41), I2 => \scrambler_reg_n_0_[41]\, O => tempData0188_out ); \scrambler[48]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_189_in, I1 => tx_data_i(42), I2 => \scrambler_reg_n_0_[42]\, O => tempData0192_out ); \scrambler[49]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_193_in, I1 => tx_data_i(43), I2 => \scrambler_reg_n_0_[43]\, O => tempData0196_out ); \scrambler[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_197_in, I1 => tx_data_i(44), I2 => \scrambler_reg_n_0_[44]\, O => tempData0200_out ); \scrambler[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_201_in, I1 => tx_data_i(45), I2 => \scrambler_reg_n_0_[45]\, O => tempData0204_out ); \scrambler[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_205_in, I1 => tx_data_i(46), I2 => \scrambler_reg_n_0_[46]\, O => tempData0208_out ); \scrambler[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_209_in, I1 => tx_data_i(47), I2 => \scrambler_reg_n_0_[47]\, O => tempData0212_out ); \scrambler[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_213_in, I1 => tx_data_i(48), I2 => \scrambler_reg_n_0_[48]\, O => tempData0216_out ); \scrambler[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_217_in, I1 => tx_data_i(49), I2 => \scrambler_reg_n_0_[49]\, O => tempData0220_out ); \scrambler[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_221_in, I1 => tx_data_i(50), I2 => \scrambler_reg_n_0_[50]\, O => tempData0224_out ); \scrambler[57]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FEFFFFFFFFFFFFFF" ) port map ( I0 => Q(6), I1 => \^txseq_counter_i_reg[0]\, I2 => Q(5), I3 => Q(3), I4 => Q(2), I5 => Q(4), O => data_valid_i ); \scrambler[57]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_225_in, I1 => tx_data_i(51), I2 => \scrambler_reg_n_0_[51]\, O => tempData0228_out ); \scrambler[57]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => Q(0), I1 => Q(1), O => \^txseq_counter_i_reg[0]\ ); \scrambler[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[39]\, I1 => tx_data_i(39), I2 => p_177_in, I3 => tx_data_i(0), I4 => p_97_in, O => tempData024_out ); \scrambler[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[40]\, I1 => tx_data_i(40), I2 => p_181_in, I3 => tx_data_i(1), I4 => p_101_in, O => tempData028_out ); \scrambler[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[41]\, I1 => tx_data_i(41), I2 => p_185_in, I3 => tx_data_i(2), I4 => p_105_in, O => tempData032_out ); \scrambler[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[42]\, I1 => tx_data_i(42), I2 => p_189_in, I3 => tx_data_i(3), I4 => p_109_in, O => tempData036_out ); \scrambler_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(0), Q => p_97_in, R => '0' ); \scrambler_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData040_out, Q => p_137_in, R => '0' ); \scrambler_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData044_out, Q => p_141_in, R => '0' ); \scrambler_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData048_out, Q => p_145_in, R => '0' ); \scrambler_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData052_out, Q => p_149_in, R => '0' ); \scrambler_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData056_out, Q => \^scrambler\(0), R => '0' ); \scrambler_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData060_out, Q => \^scrambler\(1), R => '0' ); \scrambler_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData064_out, Q => \^scrambler\(2), R => '0' ); \scrambler_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData068_out, Q => \^scrambler\(3), R => '0' ); \scrambler_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData072_out, Q => \^scrambler\(4), R => '0' ); \scrambler_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData076_out, Q => \^scrambler\(5), R => '0' ); \scrambler_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(1), Q => p_101_in, R => '0' ); \scrambler_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData080_out, Q => p_177_in, R => '0' ); \scrambler_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData084_out, Q => p_181_in, R => '0' ); \scrambler_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData088_out, Q => p_185_in, R => '0' ); \scrambler_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData092_out, Q => p_189_in, R => '0' ); \scrambler_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData096_out, Q => p_193_in, R => '0' ); \scrambler_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0100_out, Q => p_197_in, R => '0' ); \scrambler_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0104_out, Q => p_201_in, R => '0' ); \scrambler_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0108_out, Q => p_205_in, R => '0' ); \scrambler_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0112_out, Q => p_209_in, R => '0' ); \scrambler_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0116_out, Q => p_213_in, R => '0' ); \scrambler_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(2), Q => p_105_in, R => '0' ); \scrambler_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0120_out, Q => p_217_in, R => '0' ); \scrambler_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0124_out, Q => p_221_in, R => '0' ); \scrambler_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0128_out, Q => p_225_in, R => '0' ); \scrambler_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0132_out, Q => p_229_in, R => '0' ); \scrambler_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0136_out, Q => p_233_in, R => '0' ); \scrambler_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0140_out, Q => p_237_in, R => '0' ); \scrambler_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0144_out, Q => p_241_in, R => '0' ); \scrambler_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0148_out, Q => p_245_in, R => '0' ); \scrambler_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0152_out, Q => p_249_in, R => '0' ); \scrambler_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0156_out, Q => \scrambler_reg_n_0_[39]\, R => '0' ); \scrambler_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(3), Q => p_109_in, R => '0' ); \scrambler_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0160_out, Q => \scrambler_reg_n_0_[40]\, R => '0' ); \scrambler_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0164_out, Q => \scrambler_reg_n_0_[41]\, R => '0' ); \scrambler_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0168_out, Q => \scrambler_reg_n_0_[42]\, R => '0' ); \scrambler_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0172_out, Q => \scrambler_reg_n_0_[43]\, R => '0' ); \scrambler_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0176_out, Q => \scrambler_reg_n_0_[44]\, R => '0' ); \scrambler_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0180_out, Q => \scrambler_reg_n_0_[45]\, R => '0' ); \scrambler_reg[46]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0184_out, Q => \scrambler_reg_n_0_[46]\, R => '0' ); \scrambler_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0188_out, Q => \scrambler_reg_n_0_[47]\, R => '0' ); \scrambler_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0192_out, Q => \scrambler_reg_n_0_[48]\, R => '0' ); \scrambler_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0196_out, Q => \scrambler_reg_n_0_[49]\, R => '0' ); \scrambler_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(4), Q => p_113_in, R => '0' ); \scrambler_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0200_out, Q => \scrambler_reg_n_0_[50]\, R => '0' ); \scrambler_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0204_out, Q => \scrambler_reg_n_0_[51]\, R => '0' ); \scrambler_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0208_out, Q => \^scrambler\(6), R => '0' ); \scrambler_reg[53]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0212_out, Q => \^scrambler\(7), R => '0' ); \scrambler_reg[54]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0216_out, Q => \^scrambler\(8), R => '0' ); \scrambler_reg[55]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0220_out, Q => \^scrambler\(9), R => '0' ); \scrambler_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0224_out, Q => \^scrambler\(10), R => '0' ); \scrambler_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData0228_out, Q => \^scrambler\(11), R => '0' ); \scrambler_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData(5), Q => p_117_in, R => '0' ); \scrambler_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData024_out, Q => p_121_in, R => '0' ); \scrambler_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData028_out, Q => p_125_in, R => '0' ); \scrambler_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData032_out, Q => p_129_in, R => '0' ); \scrambler_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \SCRAMBLED_DATA_OUT_reg[63]_1\, CE => data_valid_i, D => tempData036_out, Q => p_133_in, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE is port ( do_cc_r_reg0 : out STD_LOGIC; Q : out STD_LOGIC; SR : in STD_LOGIC; \count_24d_srl_r_reg[0]_0\ : in STD_LOGIC; extend_cc_r : in STD_LOGIC; \count_16d_srl_r_reg[0]_0\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE is signal DO_CC0_n_0 : STD_LOGIC; signal DO_CC_i_2_n_0 : STD_LOGIC; signal \^q\ : STD_LOGIC; signal \cc_count_r_reg_n_0_[5]\ : STD_LOGIC; signal count_13d_flop_r : STD_LOGIC; signal count_13d_flop_r_i_1_n_0 : STD_LOGIC; signal count_13d_flop_r_i_2_n_0 : STD_LOGIC; signal count_13d_flop_r_i_3_n_0 : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal count_16d_flop_r : STD_LOGIC; signal count_16d_flop_r0 : STD_LOGIC; signal count_16d_flop_r_i_1_n_0 : STD_LOGIC; signal count_16d_flop_r_i_3_n_0 : STD_LOGIC; signal count_16d_flop_r_i_4_n_0 : STD_LOGIC; signal \count_16d_srl_r[0]_i_1_n_0\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[12]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[13]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[14]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal count_24d_flop_r : STD_LOGIC; signal count_24d_flop_r0 : STD_LOGIC; signal count_24d_flop_r_i_1_n_0 : STD_LOGIC; signal count_24d_flop_r_i_3_n_0 : STD_LOGIC; signal count_24d_flop_r_i_4_n_0 : STD_LOGIC; signal count_24d_flop_r_i_5_n_0 : STD_LOGIC; signal count_24d_flop_r_i_6_n_0 : STD_LOGIC; signal count_24d_srl_r0 : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[12]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[13]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[14]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[15]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[16]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[17]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[18]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[19]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[20]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[21]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[22]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_2_out : STD_LOGIC_VECTOR ( 5 to 5 ); signal reset_r : STD_LOGIC; begin Q <= \^q\; DO_CC0: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => p_1_in(0), I1 => \cc_count_r_reg_n_0_[5]\, I2 => p_1_in(3), I3 => p_1_in(4), I4 => p_1_in(1), I5 => p_1_in(2), O => DO_CC0_n_0 ); DO_CC_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FEEEEEEE" ) port map ( I0 => DO_CC0_n_0, I1 => reset_r, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg_n_0_[14]\, I4 => \count_24d_srl_r_reg_n_0_[22]\, O => DO_CC_i_2_n_0 ); DO_CC_reg: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => DO_CC_i_2_n_0, Q => \^q\, R => SR ); \cc_count_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"80FF" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[22]\, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg[0]_0\, O => p_2_out(5) ); \cc_count_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_2_out(5), Q => p_1_in(4), R => '0' ); \cc_count_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_1_in(4), Q => p_1_in(3), R => '0' ); \cc_count_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_1_in(3), Q => p_1_in(2), R => '0' ); \cc_count_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_1_in(2), Q => p_1_in(1), R => '0' ); \cc_count_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_1_in(1), Q => p_1_in(0), R => '0' ); \cc_count_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => p_1_in(0), Q => \cc_count_r_reg_n_0_[5]\, R => '0' ); count_13d_flop_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => count_13d_flop_r_i_2_n_0, I2 => count_13d_flop_r_i_3_n_0, I3 => reset_r, O => count_13d_flop_r_i_1_n_0 ); count_13d_flop_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[9]\, I1 => \count_13d_srl_r_reg_n_0_[8]\, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_13d_srl_r_reg_n_0_[10]\, I4 => \count_13d_srl_r_reg_n_0_[6]\, I5 => \count_13d_srl_r_reg_n_0_[7]\, O => count_13d_flop_r_i_2_n_0 ); count_13d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[3]\, I1 => \count_13d_srl_r_reg_n_0_[2]\, I2 => \count_13d_srl_r_reg_n_0_[5]\, I3 => \count_13d_srl_r_reg_n_0_[4]\, I4 => \count_13d_srl_r_reg_n_0_[0]\, I5 => \count_13d_srl_r_reg_n_0_[1]\, O => count_13d_flop_r_i_3_n_0 ); count_13d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => count_13d_flop_r_i_1_n_0, Q => count_13d_flop_r, R => SR ); \count_13d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => count_13d_flop_r, Q => \count_13d_srl_r_reg_n_0_[0]\, R => '0' ); \count_13d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[9]\, Q => \count_13d_srl_r_reg_n_0_[10]\, R => '0' ); \count_13d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[10]\, Q => \count_13d_srl_r_reg_n_0_[11]\, R => '0' ); \count_13d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[0]\, Q => \count_13d_srl_r_reg_n_0_[1]\, R => '0' ); \count_13d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[1]\, Q => \count_13d_srl_r_reg_n_0_[2]\, R => '0' ); \count_13d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[2]\, Q => \count_13d_srl_r_reg_n_0_[3]\, R => '0' ); \count_13d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[3]\, Q => \count_13d_srl_r_reg_n_0_[4]\, R => '0' ); \count_13d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[4]\, Q => \count_13d_srl_r_reg_n_0_[5]\, R => '0' ); \count_13d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[5]\, Q => \count_13d_srl_r_reg_n_0_[6]\, R => '0' ); \count_13d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[6]\, Q => \count_13d_srl_r_reg_n_0_[7]\, R => '0' ); \count_13d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[7]\, Q => \count_13d_srl_r_reg_n_0_[8]\, R => '0' ); \count_13d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => \count_13d_srl_r_reg_n_0_[8]\, Q => \count_13d_srl_r_reg_n_0_[9]\, R => '0' ); count_16d_flop_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FBF8" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[14]\, I1 => \count_13d_srl_r_reg_n_0_[11]\, I2 => count_16d_flop_r0, I3 => count_16d_flop_r, O => count_16d_flop_r_i_1_n_0 ); count_16d_flop_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => count_16d_flop_r_i_3_n_0, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => reset_r, I3 => \count_16d_srl_r_reg_n_0_[12]\, I4 => \count_16d_srl_r_reg_n_0_[13]\, I5 => count_16d_flop_r_i_4_n_0, O => count_16d_flop_r0 ); count_16d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[3]\, I1 => \count_16d_srl_r_reg_n_0_[2]\, I2 => \count_16d_srl_r_reg_n_0_[5]\, I3 => \count_16d_srl_r_reg_n_0_[4]\, I4 => \count_16d_srl_r_reg_n_0_[0]\, I5 => \count_16d_srl_r_reg_n_0_[1]\, O => count_16d_flop_r_i_3_n_0 ); count_16d_flop_r_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[9]\, I1 => \count_16d_srl_r_reg_n_0_[8]\, I2 => \count_16d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg_n_0_[10]\, I4 => \count_16d_srl_r_reg_n_0_[6]\, I5 => \count_16d_srl_r_reg_n_0_[7]\, O => count_16d_flop_r_i_4_n_0 ); count_16d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => count_16d_flop_r_i_1_n_0, Q => count_16d_flop_r, R => SR ); \count_16d_srl_r[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => \count_16d_srl_r_reg[0]_0\, O => \count_16d_srl_r[0]_i_1_n_0\ ); \count_16d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => count_16d_flop_r, Q => \count_16d_srl_r_reg_n_0_[0]\, R => '0' ); \count_16d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[9]\, Q => \count_16d_srl_r_reg_n_0_[10]\, R => '0' ); \count_16d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[10]\, Q => \count_16d_srl_r_reg_n_0_[11]\, R => '0' ); \count_16d_srl_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[11]\, Q => \count_16d_srl_r_reg_n_0_[12]\, R => '0' ); \count_16d_srl_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[12]\, Q => \count_16d_srl_r_reg_n_0_[13]\, R => '0' ); \count_16d_srl_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[13]\, Q => \count_16d_srl_r_reg_n_0_[14]\, R => '0' ); \count_16d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[0]\, Q => \count_16d_srl_r_reg_n_0_[1]\, R => '0' ); \count_16d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[1]\, Q => \count_16d_srl_r_reg_n_0_[2]\, R => '0' ); \count_16d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[2]\, Q => \count_16d_srl_r_reg_n_0_[3]\, R => '0' ); \count_16d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[3]\, Q => \count_16d_srl_r_reg_n_0_[4]\, R => '0' ); \count_16d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[4]\, Q => \count_16d_srl_r_reg_n_0_[5]\, R => '0' ); \count_16d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[5]\, Q => \count_16d_srl_r_reg_n_0_[6]\, R => '0' ); \count_16d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[6]\, Q => \count_16d_srl_r_reg_n_0_[7]\, R => '0' ); \count_16d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[7]\, Q => \count_16d_srl_r_reg_n_0_[8]\, R => '0' ); \count_16d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[8]\, Q => \count_16d_srl_r_reg_n_0_[9]\, R => '0' ); count_24d_flop_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFBFFF80" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[22]\, I1 => \count_13d_srl_r_reg_n_0_[11]\, I2 => \count_16d_srl_r_reg_n_0_[14]\, I3 => count_24d_flop_r0, I4 => count_24d_flop_r, O => count_24d_flop_r_i_1_n_0 ); count_24d_flop_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => count_24d_flop_r_i_3_n_0, I1 => count_24d_flop_r_i_4_n_0, I2 => count_24d_flop_r_i_5_n_0, I3 => count_24d_flop_r_i_6_n_0, O => count_24d_flop_r0 ); count_24d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[9]\, I1 => \count_24d_srl_r_reg_n_0_[8]\, I2 => \count_24d_srl_r_reg_n_0_[11]\, I3 => \count_24d_srl_r_reg_n_0_[10]\, I4 => \count_24d_srl_r_reg_n_0_[6]\, I5 => \count_24d_srl_r_reg_n_0_[7]\, O => count_24d_flop_r_i_3_n_0 ); count_24d_flop_r_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000010" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[21]\, I1 => \count_24d_srl_r_reg_n_0_[20]\, I2 => reset_r, I3 => \count_24d_srl_r_reg_n_0_[22]\, I4 => \count_24d_srl_r_reg_n_0_[18]\, I5 => \count_24d_srl_r_reg_n_0_[19]\, O => count_24d_flop_r_i_4_n_0 ); count_24d_flop_r_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[15]\, I1 => \count_24d_srl_r_reg_n_0_[14]\, I2 => \count_24d_srl_r_reg_n_0_[17]\, I3 => \count_24d_srl_r_reg_n_0_[16]\, I4 => \count_24d_srl_r_reg_n_0_[12]\, I5 => \count_24d_srl_r_reg_n_0_[13]\, O => count_24d_flop_r_i_5_n_0 ); count_24d_flop_r_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[3]\, I1 => \count_24d_srl_r_reg_n_0_[2]\, I2 => \count_24d_srl_r_reg_n_0_[5]\, I3 => \count_24d_srl_r_reg_n_0_[4]\, I4 => \count_24d_srl_r_reg_n_0_[0]\, I5 => \count_24d_srl_r_reg_n_0_[1]\, O => count_24d_flop_r_i_6_n_0 ); count_24d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => count_24d_flop_r_i_1_n_0, Q => count_24d_flop_r, R => SR ); \count_24d_srl_r[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => \count_16d_srl_r_reg[0]_0\, O => count_24d_srl_r0 ); \count_24d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => count_24d_flop_r, Q => \count_24d_srl_r_reg_n_0_[0]\, R => '0' ); \count_24d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[9]\, Q => \count_24d_srl_r_reg_n_0_[10]\, R => '0' ); \count_24d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[10]\, Q => \count_24d_srl_r_reg_n_0_[11]\, R => '0' ); \count_24d_srl_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[11]\, Q => \count_24d_srl_r_reg_n_0_[12]\, R => '0' ); \count_24d_srl_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[12]\, Q => \count_24d_srl_r_reg_n_0_[13]\, R => '0' ); \count_24d_srl_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[13]\, Q => \count_24d_srl_r_reg_n_0_[14]\, R => '0' ); \count_24d_srl_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[14]\, Q => \count_24d_srl_r_reg_n_0_[15]\, R => '0' ); \count_24d_srl_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[15]\, Q => \count_24d_srl_r_reg_n_0_[16]\, R => '0' ); \count_24d_srl_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[16]\, Q => \count_24d_srl_r_reg_n_0_[17]\, R => '0' ); \count_24d_srl_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[17]\, Q => \count_24d_srl_r_reg_n_0_[18]\, R => '0' ); \count_24d_srl_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[18]\, Q => \count_24d_srl_r_reg_n_0_[19]\, R => '0' ); \count_24d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[0]\, Q => \count_24d_srl_r_reg_n_0_[1]\, R => '0' ); \count_24d_srl_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[19]\, Q => \count_24d_srl_r_reg_n_0_[20]\, R => '0' ); \count_24d_srl_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[20]\, Q => \count_24d_srl_r_reg_n_0_[21]\, R => '0' ); \count_24d_srl_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[21]\, Q => \count_24d_srl_r_reg_n_0_[22]\, R => '0' ); \count_24d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[1]\, Q => \count_24d_srl_r_reg_n_0_[2]\, R => '0' ); \count_24d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[2]\, Q => \count_24d_srl_r_reg_n_0_[3]\, R => '0' ); \count_24d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[3]\, Q => \count_24d_srl_r_reg_n_0_[4]\, R => '0' ); \count_24d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[4]\, Q => \count_24d_srl_r_reg_n_0_[5]\, R => '0' ); \count_24d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[5]\, Q => \count_24d_srl_r_reg_n_0_[6]\, R => '0' ); \count_24d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[6]\, Q => \count_24d_srl_r_reg_n_0_[7]\, R => '0' ); \count_24d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[7]\, Q => \count_24d_srl_r_reg_n_0_[8]\, R => '0' ); \count_24d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[8]\, Q => \count_24d_srl_r_reg_n_0_[9]\, R => '0' ); do_cc_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^q\, I1 => extend_cc_r, O => do_cc_r_reg0 ); reset_r_reg: unisim.vcomponents.FDRE port map ( C => \count_24d_srl_r_reg[0]_0\, CE => '1', D => SR, Q => reset_r, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC is port ( rx_pe_data_v_i : out STD_LOGIC; illegal_btf_i : out STD_LOGIC; RX_IDLE : out STD_LOGIC; remote_ready_i : out STD_LOGIC; \RX_PE_DATA_reg[0]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); rxdatavalid_i : in STD_LOGIC; \RX_DATA_REG_reg[0]_0\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \RX_DATA_REG_reg[0]_1\ : in STD_LOGIC; dout : in STD_LOGIC_VECTOR ( 65 downto 0 ); \remote_rdy_cntr_reg[2]_0\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC is signal ILLEGAL_BTF0 : STD_LOGIC; signal ILLEGAL_BTF_i_2_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_3_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_4_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_5_n_0 : STD_LOGIC; signal RXDATAVALID_IN_REG : STD_LOGIC; signal RX_IDLE_i_2_n_0 : STD_LOGIC; signal RX_NA_IDLE : STD_LOGIC; signal RX_NA_IDLE_i_2_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal remote_rdy_cntr : STD_LOGIC_VECTOR ( 0 to 2 ); signal remote_rdy_cntr01_out : STD_LOGIC; signal \remote_rdy_cntr[0]_i_1_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[0]_i_3_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[0]_i_4_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[1]_i_1_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[2]_i_1_n_0\ : STD_LOGIC; signal remote_ready_det : STD_LOGIC; signal remote_ready_det0 : STD_LOGIC; signal rx_idle_c : STD_LOGIC; signal rx_na_idle_c : STD_LOGIC; signal \rx_na_idles_cntr[4]_i_1_n_0\ : STD_LOGIC; signal rx_na_idles_cntr_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rxdata_s : STD_LOGIC_VECTOR ( 63 downto 16 ); signal sync_header_c : STD_LOGIC_VECTOR ( 0 to 1 ); signal valid_d : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of ILLEGAL_BTF_i_3 : label is "soft_lutpair109"; attribute SOFT_HLUTNM of RX_NA_IDLE_i_2 : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \remote_rdy_cntr[0]_i_3\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \remote_rdy_cntr[0]_i_4\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \remote_rdy_cntr[1]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \remote_rdy_cntr[2]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of remote_ready_r_i_1 : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[0]_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[1]_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[2]_i_1\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[3]_i_1\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[4]_i_2\ : label is "soft_lutpair108"; begin ILLEGAL_BTF_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEF0000EEEB0000" ) port map ( I0 => ILLEGAL_BTF_i_2_n_0, I1 => p_0_in(6), I2 => p_0_in(4), I3 => p_0_in(7), I4 => ILLEGAL_BTF_i_3_n_0, I5 => p_0_in(5), O => ILLEGAL_BTF0 ); ILLEGAL_BTF_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFEFF" ) port map ( I0 => ILLEGAL_BTF_i_4_n_0, I1 => p_0_in(9), I2 => p_0_in(8), I3 => p_0_in(11), I4 => p_0_in(10), I5 => ILLEGAL_BTF_i_5_n_0, O => ILLEGAL_BTF_i_2_n_0 ); ILLEGAL_BTF_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => RXDATAVALID_IN_REG, I1 => sync_header_c(0), I2 => sync_header_c(1), I3 => \remote_rdy_cntr_reg[2]_0\, O => ILLEGAL_BTF_i_3_n_0 ); ILLEGAL_BTF_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => p_0_in(13), I1 => p_0_in(12), I2 => p_0_in(14), I3 => p_0_in(15), O => ILLEGAL_BTF_i_4_n_0 ); ILLEGAL_BTF_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => p_0_in(1), I1 => p_0_in(0), I2 => p_0_in(3), I3 => p_0_in(2), O => ILLEGAL_BTF_i_5_n_0 ); ILLEGAL_BTF_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => ILLEGAL_BTF0, Q => illegal_btf_i, R => SR(0) ); RXDATAVALID_IN_REG_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => rxdatavalid_i, Q => RXDATAVALID_IN_REG, R => '0' ); \RX_DATA_REG_reg[0]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(0), Q => rxdata_s(56), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[10]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(10), Q => rxdata_s(50), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[11]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(11), Q => rxdata_s(51), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[12]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(12), Q => rxdata_s(52), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[13]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(13), Q => rxdata_s(53), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[14]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(14), Q => rxdata_s(54), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[15]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(15), Q => rxdata_s(55), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[16]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(16), Q => rxdata_s(40), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[17]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(17), Q => rxdata_s(41), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[18]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(18), Q => rxdata_s(42), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[19]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(19), Q => rxdata_s(43), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[1]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(1), Q => rxdata_s(57), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[20]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(20), Q => rxdata_s(44), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[21]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(21), Q => rxdata_s(45), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[22]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(22), Q => rxdata_s(46), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[23]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(23), Q => rxdata_s(47), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[24]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(24), Q => rxdata_s(32), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[25]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(25), Q => rxdata_s(33), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[26]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(26), Q => rxdata_s(34), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[27]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(27), Q => rxdata_s(35), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[28]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(28), Q => rxdata_s(36), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[29]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(29), Q => rxdata_s(37), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[2]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(2), Q => rxdata_s(58), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[30]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(30), Q => rxdata_s(38), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[31]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(31), Q => rxdata_s(39), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[32]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(32), Q => rxdata_s(24), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[33]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(33), Q => rxdata_s(25), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[34]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(34), Q => rxdata_s(26), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[35]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(35), Q => rxdata_s(27), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[36]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(36), Q => rxdata_s(28), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[37]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(37), Q => rxdata_s(29), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[38]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(38), Q => rxdata_s(30), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[39]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(39), Q => rxdata_s(31), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[3]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(3), Q => rxdata_s(59), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[40]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(40), Q => rxdata_s(16), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[41]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(41), Q => rxdata_s(17), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[42]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(42), Q => rxdata_s(18), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[43]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(43), Q => rxdata_s(19), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[44]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(44), Q => rxdata_s(20), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[45]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(45), Q => rxdata_s(21), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[46]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(46), Q => rxdata_s(22), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[47]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(47), Q => rxdata_s(23), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[48]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(48), Q => p_0_in(0), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[49]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(49), Q => p_0_in(1), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[4]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(4), Q => rxdata_s(60), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[50]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(50), Q => p_0_in(2), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[51]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(51), Q => p_0_in(3), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[52]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(52), Q => p_0_in(4), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[53]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(53), Q => p_0_in(5), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[54]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(54), Q => p_0_in(6), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[55]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(55), Q => p_0_in(7), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[56]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(56), Q => p_0_in(8), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[57]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(57), Q => p_0_in(9), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[58]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(58), Q => p_0_in(10), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[59]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(59), Q => p_0_in(11), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[5]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(5), Q => rxdata_s(61), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[60]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(60), Q => p_0_in(12), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[61]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(61), Q => p_0_in(13), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[62]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(62), Q => p_0_in(14), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[63]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(63), Q => p_0_in(15), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[6]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(6), Q => rxdata_s(62), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[7]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(7), Q => rxdata_s(63), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[8]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(8), Q => rxdata_s(48), R => \RX_DATA_REG_reg[0]_1\ ); \RX_DATA_REG_reg[9]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(9), Q => rxdata_s(49), R => \RX_DATA_REG_reg[0]_1\ ); RX_HEADER_0_REG_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(64), Q => sync_header_c(1), R => \RX_DATA_REG_reg[0]_1\ ); RX_HEADER_1_REG_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => dout(65), Q => sync_header_c(0), R => \RX_DATA_REG_reg[0]_1\ ); RX_IDLE_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => RX_IDLE_i_2_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => sync_header_c(1), I4 => sync_header_c(0), I5 => ILLEGAL_BTF_i_2_n_0, O => rx_idle_c ); RX_IDLE_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in(6), I1 => p_0_in(7), O => RX_IDLE_i_2_n_0 ); RX_IDLE_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => rx_idle_c, Q => RX_IDLE, R => SR(0) ); RX_NA_IDLE_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000080" ) port map ( I0 => RX_NA_IDLE_i_2_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => p_0_in(7), I4 => p_0_in(6), I5 => ILLEGAL_BTF_i_2_n_0, O => rx_na_idle_c ); RX_NA_IDLE_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sync_header_c(1), I1 => sync_header_c(0), I2 => RXDATAVALID_IN_REG, O => RX_NA_IDLE_i_2_n_0 ); RX_NA_IDLE_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => rx_na_idle_c, Q => RX_NA_IDLE, R => SR(0) ); RX_PE_DATA_V_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sync_header_c(0), I1 => RXDATAVALID_IN_REG, I2 => sync_header_c(1), O => valid_d ); RX_PE_DATA_V_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => valid_d, Q => rx_pe_data_v_i, R => SR(0) ); \RX_PE_DATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(63), Q => \RX_PE_DATA_reg[0]_0\(63), R => SR(0) ); \RX_PE_DATA_reg[10]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(53), Q => \RX_PE_DATA_reg[0]_0\(53), R => SR(0) ); \RX_PE_DATA_reg[11]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(52), Q => \RX_PE_DATA_reg[0]_0\(52), R => SR(0) ); \RX_PE_DATA_reg[12]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(51), Q => \RX_PE_DATA_reg[0]_0\(51), R => SR(0) ); \RX_PE_DATA_reg[13]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(50), Q => \RX_PE_DATA_reg[0]_0\(50), R => SR(0) ); \RX_PE_DATA_reg[14]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(49), Q => \RX_PE_DATA_reg[0]_0\(49), R => SR(0) ); \RX_PE_DATA_reg[15]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(48), Q => \RX_PE_DATA_reg[0]_0\(48), R => SR(0) ); \RX_PE_DATA_reg[16]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(47), Q => \RX_PE_DATA_reg[0]_0\(47), R => SR(0) ); \RX_PE_DATA_reg[17]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(46), Q => \RX_PE_DATA_reg[0]_0\(46), R => SR(0) ); \RX_PE_DATA_reg[18]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(45), Q => \RX_PE_DATA_reg[0]_0\(45), R => SR(0) ); \RX_PE_DATA_reg[19]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(44), Q => \RX_PE_DATA_reg[0]_0\(44), R => SR(0) ); \RX_PE_DATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(62), Q => \RX_PE_DATA_reg[0]_0\(62), R => SR(0) ); \RX_PE_DATA_reg[20]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(43), Q => \RX_PE_DATA_reg[0]_0\(43), R => SR(0) ); \RX_PE_DATA_reg[21]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(42), Q => \RX_PE_DATA_reg[0]_0\(42), R => SR(0) ); \RX_PE_DATA_reg[22]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(41), Q => \RX_PE_DATA_reg[0]_0\(41), R => SR(0) ); \RX_PE_DATA_reg[23]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(40), Q => \RX_PE_DATA_reg[0]_0\(40), R => SR(0) ); \RX_PE_DATA_reg[24]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(39), Q => \RX_PE_DATA_reg[0]_0\(39), R => SR(0) ); \RX_PE_DATA_reg[25]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(38), Q => \RX_PE_DATA_reg[0]_0\(38), R => SR(0) ); \RX_PE_DATA_reg[26]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(37), Q => \RX_PE_DATA_reg[0]_0\(37), R => SR(0) ); \RX_PE_DATA_reg[27]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(36), Q => \RX_PE_DATA_reg[0]_0\(36), R => SR(0) ); \RX_PE_DATA_reg[28]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(35), Q => \RX_PE_DATA_reg[0]_0\(35), R => SR(0) ); \RX_PE_DATA_reg[29]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(34), Q => \RX_PE_DATA_reg[0]_0\(34), R => SR(0) ); \RX_PE_DATA_reg[2]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(61), Q => \RX_PE_DATA_reg[0]_0\(61), R => SR(0) ); \RX_PE_DATA_reg[30]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(33), Q => \RX_PE_DATA_reg[0]_0\(33), R => SR(0) ); \RX_PE_DATA_reg[31]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(32), Q => \RX_PE_DATA_reg[0]_0\(32), R => SR(0) ); \RX_PE_DATA_reg[32]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(31), Q => \RX_PE_DATA_reg[0]_0\(31), R => SR(0) ); \RX_PE_DATA_reg[33]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(30), Q => \RX_PE_DATA_reg[0]_0\(30), R => SR(0) ); \RX_PE_DATA_reg[34]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(29), Q => \RX_PE_DATA_reg[0]_0\(29), R => SR(0) ); \RX_PE_DATA_reg[35]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(28), Q => \RX_PE_DATA_reg[0]_0\(28), R => SR(0) ); \RX_PE_DATA_reg[36]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(27), Q => \RX_PE_DATA_reg[0]_0\(27), R => SR(0) ); \RX_PE_DATA_reg[37]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(26), Q => \RX_PE_DATA_reg[0]_0\(26), R => SR(0) ); \RX_PE_DATA_reg[38]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(25), Q => \RX_PE_DATA_reg[0]_0\(25), R => SR(0) ); \RX_PE_DATA_reg[39]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(24), Q => \RX_PE_DATA_reg[0]_0\(24), R => SR(0) ); \RX_PE_DATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(60), Q => \RX_PE_DATA_reg[0]_0\(60), R => SR(0) ); \RX_PE_DATA_reg[40]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(23), Q => \RX_PE_DATA_reg[0]_0\(23), R => SR(0) ); \RX_PE_DATA_reg[41]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(22), Q => \RX_PE_DATA_reg[0]_0\(22), R => SR(0) ); \RX_PE_DATA_reg[42]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(21), Q => \RX_PE_DATA_reg[0]_0\(21), R => SR(0) ); \RX_PE_DATA_reg[43]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(20), Q => \RX_PE_DATA_reg[0]_0\(20), R => SR(0) ); \RX_PE_DATA_reg[44]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(19), Q => \RX_PE_DATA_reg[0]_0\(19), R => SR(0) ); \RX_PE_DATA_reg[45]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(18), Q => \RX_PE_DATA_reg[0]_0\(18), R => SR(0) ); \RX_PE_DATA_reg[46]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(17), Q => \RX_PE_DATA_reg[0]_0\(17), R => SR(0) ); \RX_PE_DATA_reg[47]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(16), Q => \RX_PE_DATA_reg[0]_0\(16), R => SR(0) ); \RX_PE_DATA_reg[48]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(7), Q => \RX_PE_DATA_reg[0]_0\(15), R => SR(0) ); \RX_PE_DATA_reg[49]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(6), Q => \RX_PE_DATA_reg[0]_0\(14), R => SR(0) ); \RX_PE_DATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(59), Q => \RX_PE_DATA_reg[0]_0\(59), R => SR(0) ); \RX_PE_DATA_reg[50]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(5), Q => \RX_PE_DATA_reg[0]_0\(13), R => SR(0) ); \RX_PE_DATA_reg[51]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(4), Q => \RX_PE_DATA_reg[0]_0\(12), R => SR(0) ); \RX_PE_DATA_reg[52]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(3), Q => \RX_PE_DATA_reg[0]_0\(11), R => SR(0) ); \RX_PE_DATA_reg[53]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(2), Q => \RX_PE_DATA_reg[0]_0\(10), R => SR(0) ); \RX_PE_DATA_reg[54]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(1), Q => \RX_PE_DATA_reg[0]_0\(9), R => SR(0) ); \RX_PE_DATA_reg[55]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(0), Q => \RX_PE_DATA_reg[0]_0\(8), R => SR(0) ); \RX_PE_DATA_reg[56]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(15), Q => \RX_PE_DATA_reg[0]_0\(7), R => SR(0) ); \RX_PE_DATA_reg[57]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(14), Q => \RX_PE_DATA_reg[0]_0\(6), R => SR(0) ); \RX_PE_DATA_reg[58]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(13), Q => \RX_PE_DATA_reg[0]_0\(5), R => SR(0) ); \RX_PE_DATA_reg[59]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(12), Q => \RX_PE_DATA_reg[0]_0\(4), R => SR(0) ); \RX_PE_DATA_reg[5]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(58), Q => \RX_PE_DATA_reg[0]_0\(58), R => SR(0) ); \RX_PE_DATA_reg[60]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(11), Q => \RX_PE_DATA_reg[0]_0\(3), R => SR(0) ); \RX_PE_DATA_reg[61]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(10), Q => \RX_PE_DATA_reg[0]_0\(2), R => SR(0) ); \RX_PE_DATA_reg[62]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(9), Q => \RX_PE_DATA_reg[0]_0\(1), R => SR(0) ); \RX_PE_DATA_reg[63]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => p_0_in(8), Q => \RX_PE_DATA_reg[0]_0\(0), R => SR(0) ); \RX_PE_DATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(57), Q => \RX_PE_DATA_reg[0]_0\(57), R => SR(0) ); \RX_PE_DATA_reg[7]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(56), Q => \RX_PE_DATA_reg[0]_0\(56), R => SR(0) ); \RX_PE_DATA_reg[8]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(55), Q => \RX_PE_DATA_reg[0]_0\(55), R => SR(0) ); \RX_PE_DATA_reg[9]\: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => valid_d, D => rxdata_s(54), Q => \RX_PE_DATA_reg[0]_0\(54), R => SR(0) ); \remote_rdy_cntr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00004000FFFFFFFF" ) port map ( I0 => \remote_rdy_cntr[0]_i_4_n_0\, I1 => remote_rdy_cntr(0), I2 => remote_rdy_cntr(2), I3 => remote_rdy_cntr(1), I4 => rx_na_idles_cntr_reg(4), I5 => \remote_rdy_cntr_reg[2]_0\, O => \remote_rdy_cntr[0]_i_1_n_0\ ); \remote_rdy_cntr[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F00" ) port map ( I0 => remote_rdy_cntr(0), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(1), I3 => remote_ready_det, O => remote_rdy_cntr01_out ); \remote_rdy_cntr[0]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => remote_rdy_cntr(1), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(0), O => \remote_rdy_cntr[0]_i_3_n_0\ ); \remote_rdy_cntr[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => rx_na_idles_cntr_reg(2), I1 => rx_na_idles_cntr_reg(0), I2 => rx_na_idles_cntr_reg(1), I3 => rx_na_idles_cntr_reg(3), O => \remote_rdy_cntr[0]_i_4_n_0\ ); \remote_rdy_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => remote_rdy_cntr(2), I1 => remote_rdy_cntr(1), O => \remote_rdy_cntr[1]_i_1_n_0\ ); \remote_rdy_cntr[2]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => remote_rdy_cntr(2), O => \remote_rdy_cntr[2]_i_1_n_0\ ); \remote_rdy_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => remote_rdy_cntr01_out, D => \remote_rdy_cntr[0]_i_3_n_0\, Q => remote_rdy_cntr(0), R => \remote_rdy_cntr[0]_i_1_n_0\ ); \remote_rdy_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => remote_rdy_cntr01_out, D => \remote_rdy_cntr[1]_i_1_n_0\, Q => remote_rdy_cntr(1), R => \remote_rdy_cntr[0]_i_1_n_0\ ); \remote_rdy_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => remote_rdy_cntr01_out, D => \remote_rdy_cntr[2]_i_1_n_0\, Q => remote_rdy_cntr(2), R => \remote_rdy_cntr[0]_i_1_n_0\ ); remote_ready_det_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => ILLEGAL_BTF_i_3_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => p_0_in(7), I4 => p_0_in(6), I5 => ILLEGAL_BTF_i_2_n_0, O => remote_ready_det0 ); remote_ready_det_reg: unisim.vcomponents.FDRE port map ( C => \RX_DATA_REG_reg[0]_0\, CE => '1', D => remote_ready_det0, Q => remote_ready_det, R => SR(0) ); remote_ready_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => remote_rdy_cntr(0), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(1), O => remote_ready_i ); \rx_na_idles_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rx_na_idles_cntr_reg(0), O => \p_0_in__0\(0) ); \rx_na_idles_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rx_na_idles_cntr_reg(0), I1 => rx_na_idles_cntr_reg(1), O => \p_0_in__0\(1) ); \rx_na_idles_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => rx_na_idles_cntr_reg(1), I1 => rx_na_idles_cntr_reg(0), I2 => rx_na_idles_cntr_reg(2), O => \p_0_in__0\(2) ); \rx_na_idles_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => rx_na_idles_cntr_reg(2), I1 => rx_na_idles_cntr_reg(0), I2 => rx_na_idles_cntr_reg(1), I3 => rx_na_idles_cntr_reg(3), O => \p_0_in__0\(3) ); \rx_na_idles_cntr[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => remote_rdy_cntr(0), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(1), I3 => \remote_rdy_cntr_reg[2]_0\, O => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => rx_na_idles_cntr_reg(3), I1 => rx_na_idles_cntr_reg(1), I2 => rx_na_idles_cntr_reg(0), I3 => rx_na_idles_cntr_reg(2), I4 => rx_na_idles_cntr_reg(4), O => \p_0_in__0\(4) ); \rx_na_idles_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => RX_NA_IDLE, D => \p_0_in__0\(0), Q => rx_na_idles_cntr_reg(0), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => RX_NA_IDLE, D => \p_0_in__0\(1), Q => rx_na_idles_cntr_reg(1), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => RX_NA_IDLE, D => \p_0_in__0\(2), Q => rx_na_idles_cntr_reg(2), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => RX_NA_IDLE, D => \p_0_in__0\(3), Q => rx_na_idles_cntr_reg(3), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \RX_DATA_REG_reg[0]_0\, CE => RX_NA_IDLE, D => \p_0_in__0\(4), Q => rx_na_idles_cntr_reg(4), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM is port ( gen_cc_i : out STD_LOGIC; do_cc_r : out STD_LOGIC; extend_cc_r : out STD_LOGIC; gen_cc_flop_0_i_0 : out STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; s_axi_tx_tvalid_0 : out STD_LOGIC; R0 : in STD_LOGIC; do_cc_r_reg_0 : in STD_LOGIC; tx_dst_rdy_n_r0 : in STD_LOGIC; do_cc_r_reg0 : in STD_LOGIC; extend_cc_r_reg_0 : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; s_axi_tx_tvalid : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM is signal \^do_cc_r\ : STD_LOGIC; signal \^gen_cc_i\ : STD_LOGIC; signal tx_dst_rdy_n_i : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of TX_PE_DATA_V_i_1 : label is "soft_lutpair122"; attribute BOX_TYPE : string; attribute BOX_TYPE of gen_cc_flop_0_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of gen_cc_flop_0_i : label is "FDR"; attribute SOFT_HLUTNM of s_axi_tx_tready_INST_0 : label is "soft_lutpair122"; begin do_cc_r <= \^do_cc_r\; gen_cc_i <= \^gen_cc_i\; \TX_DATA[53]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^gen_cc_i\, I1 => gen_ch_bond_i, O => gen_cc_flop_0_i_0 ); TX_PE_DATA_V_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_tx_tvalid, I1 => tx_dst_rdy_n_i, O => s_axi_tx_tvalid_0 ); do_cc_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => do_cc_r_reg_0, CE => '1', D => do_cc_r_reg0, Q => \^do_cc_r\, R => '0' ); extend_cc_r_reg: unisim.vcomponents.FDRE port map ( C => do_cc_r_reg_0, CE => '1', D => extend_cc_r_reg_0, Q => extend_cc_r, R => '0' ); gen_cc_flop_0_i: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => do_cc_r_reg_0, CE => '1', D => \^do_cc_r\, Q => \^gen_cc_i\, R => R0 ); s_axi_tx_tready_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => tx_dst_rdy_n_i, O => s_axi_tx_tready ); tx_dst_rdy_n_r_reg: unisim.vcomponents.FDSE port map ( C => do_cc_r_reg_0, CE => '1', D => tx_dst_rdy_n_r0, Q => tx_dst_rdy_n_i, S => R0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH is port ( tx_pe_data_v_i : out STD_LOGIC; wait_for_lane_up_r_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); Q : out STD_LOGIC_VECTOR ( 61 downto 0 ); TX_PE_DATA_V_reg_0 : in STD_LOGIC; TX_PE_DATA_V_reg_1 : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; \TX_DATA_reg[53]\ : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH is signal TX_PE_DATA : STD_LOGIC_VECTOR ( 50 to 51 ); signal \^tx_pe_data_v_i\ : STD_LOGIC; begin tx_pe_data_v_i <= \^tx_pe_data_v_i\; \TX_DATA[52]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000F000D000D000D" ) port map ( I0 => \^tx_pe_data_v_i\, I1 => gen_na_idles_i, I2 => \TX_DATA_reg[53]\, I3 => rst_pma_init_usrclk, I4 => channel_up_tx_if, I5 => TX_PE_DATA(51), O => wait_for_lane_up_r_reg(0) ); \TX_DATA[53]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000322200002222" ) port map ( I0 => gen_na_idles_i, I1 => \TX_DATA_reg[53]\, I2 => \^tx_pe_data_v_i\, I3 => TX_PE_DATA(50), I4 => rst_pma_init_usrclk, I5 => channel_up_tx_if, O => wait_for_lane_up_r_reg(1) ); TX_PE_DATA_V_reg: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => TX_PE_DATA_V_reg_0, Q => \^tx_pe_data_v_i\, R => '0' ); \TX_PE_DATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(0), Q => Q(61), R => '0' ); \TX_PE_DATA_reg[10]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(10), Q => Q(51), R => '0' ); \TX_PE_DATA_reg[11]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(11), Q => Q(50), R => '0' ); \TX_PE_DATA_reg[12]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(12), Q => Q(49), R => '0' ); \TX_PE_DATA_reg[13]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(13), Q => Q(48), R => '0' ); \TX_PE_DATA_reg[14]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(14), Q => Q(47), R => '0' ); \TX_PE_DATA_reg[15]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(15), Q => Q(46), R => '0' ); \TX_PE_DATA_reg[16]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(16), Q => Q(45), R => '0' ); \TX_PE_DATA_reg[17]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(17), Q => Q(44), R => '0' ); \TX_PE_DATA_reg[18]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(18), Q => Q(43), R => '0' ); \TX_PE_DATA_reg[19]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(19), Q => Q(42), R => '0' ); \TX_PE_DATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(1), Q => Q(60), R => '0' ); \TX_PE_DATA_reg[20]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(20), Q => Q(41), R => '0' ); \TX_PE_DATA_reg[21]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(21), Q => Q(40), R => '0' ); \TX_PE_DATA_reg[22]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(22), Q => Q(39), R => '0' ); \TX_PE_DATA_reg[23]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(23), Q => Q(38), R => '0' ); \TX_PE_DATA_reg[24]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(24), Q => Q(37), R => '0' ); \TX_PE_DATA_reg[25]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(25), Q => Q(36), R => '0' ); \TX_PE_DATA_reg[26]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(26), Q => Q(35), R => '0' ); \TX_PE_DATA_reg[27]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(27), Q => Q(34), R => '0' ); \TX_PE_DATA_reg[28]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(28), Q => Q(33), R => '0' ); \TX_PE_DATA_reg[29]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(29), Q => Q(32), R => '0' ); \TX_PE_DATA_reg[2]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(2), Q => Q(59), R => '0' ); \TX_PE_DATA_reg[30]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(30), Q => Q(31), R => '0' ); \TX_PE_DATA_reg[31]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(31), Q => Q(30), R => '0' ); \TX_PE_DATA_reg[32]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(32), Q => Q(29), R => '0' ); \TX_PE_DATA_reg[33]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(33), Q => Q(28), R => '0' ); \TX_PE_DATA_reg[34]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(34), Q => Q(27), R => '0' ); \TX_PE_DATA_reg[35]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(35), Q => Q(26), R => '0' ); \TX_PE_DATA_reg[36]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(36), Q => Q(25), R => '0' ); \TX_PE_DATA_reg[37]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(37), Q => Q(24), R => '0' ); \TX_PE_DATA_reg[38]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(38), Q => Q(23), R => '0' ); \TX_PE_DATA_reg[39]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(39), Q => Q(22), R => '0' ); \TX_PE_DATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(3), Q => Q(58), R => '0' ); \TX_PE_DATA_reg[40]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(40), Q => Q(21), R => '0' ); \TX_PE_DATA_reg[41]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(41), Q => Q(20), R => '0' ); \TX_PE_DATA_reg[42]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(42), Q => Q(19), R => '0' ); \TX_PE_DATA_reg[43]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(43), Q => Q(18), R => '0' ); \TX_PE_DATA_reg[44]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(44), Q => Q(17), R => '0' ); \TX_PE_DATA_reg[45]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(45), Q => Q(16), R => '0' ); \TX_PE_DATA_reg[46]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(46), Q => Q(15), R => '0' ); \TX_PE_DATA_reg[47]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(47), Q => Q(14), R => '0' ); \TX_PE_DATA_reg[48]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(48), Q => Q(13), R => '0' ); \TX_PE_DATA_reg[49]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(49), Q => Q(12), R => '0' ); \TX_PE_DATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(4), Q => Q(57), R => '0' ); \TX_PE_DATA_reg[50]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(50), Q => TX_PE_DATA(50), R => '0' ); \TX_PE_DATA_reg[51]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(51), Q => TX_PE_DATA(51), R => '0' ); \TX_PE_DATA_reg[52]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(52), Q => Q(11), R => '0' ); \TX_PE_DATA_reg[53]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(53), Q => Q(10), R => '0' ); \TX_PE_DATA_reg[54]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(54), Q => Q(9), R => '0' ); \TX_PE_DATA_reg[55]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(55), Q => Q(8), R => '0' ); \TX_PE_DATA_reg[56]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(56), Q => Q(7), R => '0' ); \TX_PE_DATA_reg[57]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(57), Q => Q(6), R => '0' ); \TX_PE_DATA_reg[58]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(58), Q => Q(5), R => '0' ); \TX_PE_DATA_reg[59]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(59), Q => Q(4), R => '0' ); \TX_PE_DATA_reg[5]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(5), Q => Q(56), R => '0' ); \TX_PE_DATA_reg[60]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(60), Q => Q(3), R => '0' ); \TX_PE_DATA_reg[61]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(61), Q => Q(2), R => '0' ); \TX_PE_DATA_reg[62]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(62), Q => Q(1), R => '0' ); \TX_PE_DATA_reg[63]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(63), Q => Q(0), R => '0' ); \TX_PE_DATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(6), Q => Q(55), R => '0' ); \TX_PE_DATA_reg[7]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(7), Q => Q(54), R => '0' ); \TX_PE_DATA_reg[8]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(8), Q => Q(53), R => '0' ); \TX_PE_DATA_reg[9]\: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg_1, CE => '1', D => s_axi_tx_tdata(9), Q => Q(52), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync is port ( next_ready_c : out STD_LOGIC; next_begin_c : out STD_LOGIC; SYSTEM_RESET_reg : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC; ready_r_reg : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; ready_r : in STD_LOGIC; align_r : in STD_LOGIC; polarity_r : in STD_LOGIC; rx_polarity_dlyd_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; begin_r_reg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rx_polarity_r_reg : in STD_LOGIC; prev_rx_polarity_r : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync is signal begin_r_i_2_n_0 : STD_LOGIC; signal p_level_in_int : STD_LOGIC; signal ready_r_i_3_n_0 : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; begin_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFCA0A0" ) port map ( I0 => rx_lossofsync_i, I1 => polarity_r, I2 => ready_r, I3 => align_r, I4 => reset_lanes_i, I5 => begin_r_i_2_n_0, O => next_begin_c ); begin_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"80FF" ) port map ( I0 => s_level_out_d2, I1 => rx_polarity_dlyd_i, I2 => polarity_r, I3 => begin_r_reg, O => begin_r_i_2_n_0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); \ready_r_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8888888888888C88" ) port map ( I0 => ready_r_i_3_n_0, I1 => ready_r_reg, I2 => rx_lossofsync_i, I3 => ready_r, I4 => align_r, I5 => polarity_r, O => next_ready_c ); ready_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"00000040" ) port map ( I0 => s_level_out_d2, I1 => rx_polarity_dlyd_i, I2 => polarity_r, I3 => align_r, I4 => ready_r, O => ready_r_i_3_n_0 ); rx_polarity_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0454" ) port map ( I0 => SR(0), I1 => rx_polarity_r_reg, I2 => s_level_out_d2, I3 => prev_rx_polarity_r, O => SYSTEM_RESET_reg ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 is port ( \rxheader_from_gtx_i_reg[0]\ : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxheadervalid_i : in STD_LOGIC; RX_NEG_OUT_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 : entity is "aurora_64b66b_0_cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= in0; RX_NEG_OUT_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FF002000" ) port map ( I0 => Q(0), I1 => Q(1), I2 => rxheadervalid_i, I3 => s_level_out_d2, I4 => RX_NEG_OUT_reg, O => \rxheader_from_gtx_i_reg[0]\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ is port ( \out\ : out STD_LOGIC; cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); init_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; p_level_in_int <= cplllock_out(0); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_20\ is port ( \cb_bit_err_ext_cnt_reg[3]\ : out STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); reset_cbcc_comb_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_20\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_20\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_20\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => p_level_in_int ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_199: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); reset_cbcc_comb_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => Q(3), I1 => Q(2), I2 => Q(0), I3 => Q(1), I4 => s_level_out_d5, I5 => reset_cbcc_comb_reg(0), O => \cb_bit_err_ext_cnt_reg[3]\ ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_27\ is port ( s_level_out_d5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; s_level_out_d5_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_27\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_27\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_27\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= in0; CC_RXLOSSOFSYNC_OUT_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_level_out_d5, O => s_level_out_d5_reg_0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_1, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_7\ is port ( hard_err_rst_int_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; init_clk : in STD_LOGIC; hard_err_rst_int : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); hard_err_rst_int0 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \hard_err_cntr_r_reg[0]\ : in STD_LOGIC; \hard_err_cntr_r_reg[0]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_7\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_7\ is signal hard_err_rst_int_i_2_n_0 : STD_LOGIC; signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= in0; \hard_err_cntr_r[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAFFFFFFFFFFFFFC" ) port map ( I0 => \hard_err_cntr_r_reg[0]\, I1 => \hard_err_cntr_r_reg[0]_0\, I2 => s_level_out_d5, I3 => Q(0), I4 => Q(1), I5 => Q(2), O => E(0) ); hard_err_rst_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFFE0002" ) port map ( I0 => hard_err_rst_int, I1 => Q(0), I2 => Q(1), I3 => hard_err_rst_int_i_2_n_0, I4 => hard_err_rst_int0, I5 => SR(0), O => hard_err_rst_int_reg ); hard_err_rst_int_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => s_level_out_d5, I1 => Q(2), I2 => \hard_err_cntr_r_reg[0]_0\, O => hard_err_rst_int_i_2_n_0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_8\ is port ( rx_fsm_resetdone_ii : out STD_LOGIC; \out\ : in STD_LOGIC; init_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_8\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_8\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_8\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= \out\; rx_fsm_resetdone_ii <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_9\ is port ( tx_fsm_resetdone_ii : out STD_LOGIC; \out\ : in STD_LOGIC; init_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_9\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_9\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= \out\; tx_fsm_resetdone_ii <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ is port ( \out\ : out STD_LOGIC; rxbufstatus_out : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); p_level_in_d1_cdc_from_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => rxbufstatus_out(0), Q => p_level_in_int, R => '0' ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ is port ( \out\ : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d3; p_level_in_int <= s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ is port ( cbcc_reset_cbstg2_rd_clk : in STD_LOGIC; full : in STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ is signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => full, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => cbcc_reset_cbstg2_rd_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_28\ is port ( \out\ : out STD_LOGIC; cbcc_fifo_reset_rd_clk : in STD_LOGIC; overflow : in STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_28\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_28\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_28\ is signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => overflow, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => cbcc_fifo_reset_rd_clk ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => cbcc_fifo_reset_rd_clk ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => cbcc_fifo_reset_rd_clk ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => cbcc_fifo_reset_rd_clk ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => cbcc_fifo_reset_rd_clk ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => cbcc_fifo_reset_rd_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc is port ( cb_bit_err_out : out STD_LOGIC; in0 : out STD_LOGIC; master_do_rd_en_i : out STD_LOGIC; all_vld_btf_flag_i : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; START_CB_WRITES_OUT : in STD_LOGIC; cbcc_fifo_reset_rd_clk : in STD_LOGIC; master_do_rd_en_out_reg_0 : in STD_LOGIC; master_do_rd_en_out_reg_1 : in STD_LOGIC; ANY_VLD_BTF_FLAG : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc is signal second_cb_write_failed : STD_LOGIC; begin all_start_cb_writes_out_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => START_CB_WRITES_OUT, Q => in0, R => SR(0) ); all_vld_btf_out_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => ANY_VLD_BTF_FLAG, Q => all_vld_btf_flag_i, R => SR(0) ); cb_bit_err_out_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => second_cb_write_failed, Q => cb_bit_err_out, R => SR(0) ); master_do_rd_en_out_reg: unisim.vcomponents.FDRE port map ( C => master_do_rd_en_out_reg_1, CE => '1', D => master_do_rd_en_out_reg_0, Q => master_do_rd_en_i, R => cbcc_fifo_reset_rd_clk ); second_cb_write_failed_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \out\, Q => second_cb_write_failed, R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); pma_init : in STD_LOGIC; init_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => pma_init, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg4_reg_n_0, Q => D(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); reset_pb : in STD_LOGIC; CLK : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => reset_pb, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg3, Q => stg4, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg4, Q => D(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 is port ( SS : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; CLK : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => stg4_reg_n_0, Q => SS(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 is port ( link_reset_sync : out STD_LOGIC; link_reset_out : in STD_LOGIC; stg5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => link_reset_out, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg4_reg_n_0, Q => link_reset_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 is port ( power_down_sync : out STD_LOGIC; power_down : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => power_down, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => power_down_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 is port ( fsm_resetdone_sync : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => fsm_resetdone_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 is port ( stg5_reg_0 : out STD_LOGIC; TX_HEADER_1_reg : out STD_LOGIC; stg5_reg_1 : out STD_LOGIC; stg5_reg_2 : out STD_LOGIC; stg5_reg_3 : out STD_LOGIC; stg5_reg_4 : out STD_LOGIC; stg5_reg_5 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg5_reg_6 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \TX_DATA[59]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \TX_DATA[60]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \TX_DATA[61]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \TX_DATA[62]_i_2\ : label is "soft_lutpair115"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; \TX_DATA[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(0), O => stg5_reg_2 ); \TX_DATA[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(1), O => stg5_reg_3 ); \TX_DATA[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(2), O => stg5_reg_4 ); \TX_DATA[62]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(3), O => stg5_reg_5 ); TX_HEADER_0_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000050044444444" ) port map ( I0 => \^stg5_reg_0\, I1 => D(0), I2 => TX_HEADER_1_reg_0, I3 => tx_pe_data_v_i, I4 => gen_na_idles_i, I5 => txdatavalid_symgen_i, O => stg5_reg_1 ); TX_HEADER_1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EEEEE2EE" ) port map ( I0 => D(1), I1 => txdatavalid_symgen_i, I2 => gen_na_idles_i, I3 => tx_pe_data_v_i, I4 => TX_HEADER_1_reg_0, I5 => \^stg5_reg_0\, O => TX_HEADER_1_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_6, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_6, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_6, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_6, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_6, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ is port ( stg3_reg_0 : out STD_LOGIC; \out\ : in STD_LOGIC; stg3_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg3_reg_0 <= stg3; stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ is port ( \out\ : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ is port ( stg3_reg_0 : out STD_LOGIC; \out\ : in STD_LOGIC; stg2_reg_0 : in STD_LOGIC; FSM_RESETDONE_j_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin \prmry_in_inferred_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => stg3, I1 => FSM_RESETDONE_j_reg, O => stg3_reg_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ is port ( \out\ : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; init_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \FSM_onehot_cdr_reset_fsm_r_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ is signal blocksync_all_lanes_instableclk : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin \FSM_onehot_cdr_reset_fsm_r[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => Q(1), I1 => \FSM_onehot_cdr_reset_fsm_r_reg[0]\, I2 => blocksync_all_lanes_instableclk, I3 => Q(0), I4 => Q(2), O => E(0) ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg4_reg_n_0, Q => blocksync_all_lanes_instableclk, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ is port ( rxlossofsync_out_i : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; blocksync_out_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ is signal allow_block_sync_propagation_inrxclk : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin rxlossofsync_out_q_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => allow_block_sync_propagation_inrxclk, I1 => blocksync_out_i, O => rxlossofsync_out_i ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg4_reg_n_0, Q => allow_block_sync_propagation_inrxclk, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ is port ( stg5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; fsm_resetdone_to_rxreset_in : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ is signal fsm_resetdone_to_new_gtx_rx_comb : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin new_gtx_rx_pcsreset_comb_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"DF" ) port map ( I0 => fsm_resetdone_to_new_gtx_rx_comb, I1 => fsm_resetdone_to_rxreset_in, I2 => \out\(0), O => stg5_reg_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg4_reg_n_0, Q => fsm_resetdone_to_new_gtx_rx_comb, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ is port ( fsm_resetdone_initclk : out STD_LOGIC; \dly_gt_rst_r_reg[18]\ : out STD_LOGIC; in0 : in STD_LOGIC; init_clk : in STD_LOGIC; \count_for_reset_r_reg[23]\ : in STD_LOGIC; \count_for_reset_r_reg[23]_0\ : in STD_LOGIC; reset_initclk : in STD_LOGIC; \out\ : in STD_LOGIC; valid_btf_detect_dlyd1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ is signal \^fsm_resetdone_initclk\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin fsm_resetdone_initclk <= \^fsm_resetdone_initclk\; \count_for_reset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEEEEFFEF" ) port map ( I0 => \count_for_reset_r_reg[23]\, I1 => \count_for_reset_r_reg[23]_0\, I2 => \^fsm_resetdone_initclk\, I3 => reset_initclk, I4 => \out\, I5 => valid_btf_detect_dlyd1, O => \dly_gt_rst_r_reg[18]\ ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg4_reg_n_0, Q => \^fsm_resetdone_initclk\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; stg3_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg4_reg_n_0, Q => SR(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ is port ( reset_initclk : out STD_LOGIC; stg5_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); init_clk : in STD_LOGIC; \out\ : in STD_LOGIC; fsm_resetdone_initclk : in STD_LOGIC; \hard_err_cntr_r_reg[7]\ : in STD_LOGIC; \hard_err_cntr_r_reg[7]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ is signal \^reset_initclk\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin reset_initclk <= \^reset_initclk\; \hard_err_cntr_r[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFF45" ) port map ( I0 => \out\, I1 => \^reset_initclk\, I2 => fsm_resetdone_initclk, I3 => \hard_err_cntr_r_reg[7]\, I4 => \hard_err_cntr_r_reg[7]_0\, O => stg5_reg_0(0) ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => SR(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg4_reg_n_0, Q => \^reset_initclk\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ is port ( fsm_resetdone_to_rxreset_in : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg4_reg_n_0, Q => fsm_resetdone_to_rxreset_in, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ is port ( in0 : out STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); init_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => E(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg4_reg_n_0, Q => in0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ is port ( stg5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg5_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_22\ is port ( stg5_reg_0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); stg3_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_22\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_22\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_22\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ is port ( stg5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ is signal fifo_reset_wr_sync3 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin prmry_in_inferred_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => fifo_reset_wr_sync3, I1 => stg1_aurora_64b66b_0_cdc_to_reg_0, O => stg5_reg_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg4_reg_n_0, Q => fifo_reset_wr_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_24\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg3_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_24\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_24\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_24\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_rd_clk/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => stg3_reg_1, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_wr_clk/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_26\ is port ( stg5_reg_0 : out STD_LOGIC; rd_stg1_reg : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg5_reg_1 : in STD_LOGIC; rd_stg1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_26\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_26\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_26\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; cbcc_reset_cbstg2_rd_clk_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rd_stg1, I1 => \^stg5_reg_0\, O => rd_stg1_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_29\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; init_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_29\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_29\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_29\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => init_clk, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => init_clk, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ is port ( stg11_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ is signal stg10_reg_srl7_n_0 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute srl_name : string; attribute srl_name of stg10_reg_srl7 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_fifo_reset_user_clk/stg10_reg_srl7 "; attribute shift_extract of stg11_reg : label is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg10_reg_srl7: unisim.vcomponents.SRL16E generic map( INIT => X"007F" ) port map ( A0 => '0', A1 => '1', A2 => '1', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => stg3, Q => stg10_reg_srl7_n_0 ); stg11_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg10_reg_srl7_n_0, Q => stg11_reg_0, R => '0' ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ is port ( fifo_reset_comb_user_clk_int : out STD_LOGIC; dbg_srst_assert0 : out STD_LOGIC; in0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; dbg_srst_assert_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ is signal \^fifo_reset_comb_user_clk_int\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg20_reg_srl17_n_0 : STD_LOGIC; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal NLW_stg20_reg_srl17_Q31_UNCONNECTED : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg20_reg_srl17 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_fifo_reset_comb_user_clk_in/stg20_reg_srl17 "; attribute shift_extract of stg21_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin fifo_reset_comb_user_clk_int <= \^fifo_reset_comb_user_clk_int\; dbg_srst_assert_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => dbg_srst_assert_reg, I1 => \^fifo_reset_comb_user_clk_int\, O => dbg_srst_assert0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg20_reg_srl17: unisim.vcomponents.SRLC32E generic map( INIT => X"0001FFFF" ) port map ( A(4 downto 0) => B"10000", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => stg3, Q => stg20_reg_srl17_n_0, Q31 => NLW_stg20_reg_srl17_Q31_UNCONNECTED ); stg21_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg20_reg_srl17_n_0, Q => \^fifo_reset_comb_user_clk_int\, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized4\ is port ( stg9_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized4\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized4\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg8_reg_srl5_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg8_reg_srl5 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_wr_clk/stg8_reg_srl5 "; attribute shift_extract of stg9_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg2, Q => stg3, R => '0' ); stg8_reg_srl5: unisim.vcomponents.SRL16E generic map( INIT => X"001F" ) port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => stg3, Q => stg8_reg_srl5_n_0 ); stg9_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => stg8_reg_srl5_n_0, Q => stg9_reg_0(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized5\ is port ( cbcc_fifo_reset_to_fifo_rd_clk : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg31_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized5\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized5\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized5\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg30_reg_srl27_n_0 : STD_LOGIC; signal NLW_stg30_reg_srl27_Q31_UNCONNECTED : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg30_reg_srl27 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_rd_clk/stg30_reg_srl27 "; attribute shift_extract of stg31_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg30_reg_srl27: unisim.vcomponents.SRLC32E generic map( INIT => X"07FFFFFF" ) port map ( A(4 downto 0) => B"11010", CE => '1', CLK => stg31_reg_0, D => stg3, Q => stg30_reg_srl27_n_0, Q31 => NLW_stg30_reg_srl27_Q31_UNCONNECTED ); stg31_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg30_reg_srl27_n_0, Q => cbcc_fifo_reset_to_fifo_rd_clk, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk is port ( gtwiz_reset_clk_freerun_in : in STD_LOGIC; gtwiz_userclk_rx_srcclk_in : in STD_LOGIC; gtwiz_userclk_rx_reset_in : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : out STD_LOGIC; gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC; gtwiz_userclk_rx_active_out : out STD_LOGIC; lopt : out STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : in STD_LOGIC ); attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is "yes"; attribute P_CONTENTS : integer; attribute P_CONTENTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is 0; attribute P_FREQ_RATIO_SOURCE_TO_USRCLK : integer; attribute P_FREQ_RATIO_SOURCE_TO_USRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is 1; attribute P_FREQ_RATIO_USRCLK_TO_USRCLK2 : integer; attribute P_FREQ_RATIO_USRCLK_TO_USRCLK2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is 1; attribute P_USRCLK2_DIV : string; attribute P_USRCLK2_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is "3'b000"; attribute P_USRCLK2_INT_DIV : integer; attribute P_USRCLK2_INT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is 0; attribute P_USRCLK_DIV : string; attribute P_USRCLK_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is "3'b000"; attribute P_USRCLK_INT_DIV : integer; attribute P_USRCLK_INT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk : entity is "soft"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk is signal \\ : STD_LOGIC; signal \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to\ : STD_LOGIC; attribute async_reg : string; attribute async_reg of \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to\ : signal is "true"; signal \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2\ : STD_LOGIC; attribute async_reg of \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2\ : signal is "true"; signal \^gtwiz_userclk_rx_usrclk2_out\ : STD_LOGIC; signal \^lopt\ : STD_LOGIC; signal \^lopt_1\ : STD_LOGIC; attribute BOX_TYPE : string; attribute BOX_TYPE of \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\ : label is "PRIMITIVE"; attribute OPT_MODIFIED : string; attribute OPT_MODIFIED of \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\ : label is "MLO"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to_reg\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2_reg\ : label is std.standard.true; attribute KEEP of \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2_reg\ : label is "yes"; begin \^lopt\ <= lopt_1; \^lopt_1\ <= lopt_2; gtwiz_userclk_rx_usrclk2_out <= \^gtwiz_userclk_rx_usrclk2_out\; gtwiz_userclk_rx_usrclk_out <= \^gtwiz_userclk_rx_usrclk2_out\; lopt <= \\; VCC: unisim.vcomponents.VCC port map ( P => \\ ); \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\: unisim.vcomponents.BUFG_GT generic map( SIM_DEVICE => "ULTRASCALE", STARTUP_SYNC => "FALSE" ) port map ( CE => \^lopt\, CEMASK => '0', CLR => \^lopt_1\, CLRMASK => '0', DIV(2 downto 0) => B"000", I => gtwiz_userclk_rx_srcclk_in, O => \^gtwiz_userclk_rx_usrclk2_out\ ); \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^gtwiz_userclk_rx_usrclk2_out\, CE => '1', CLR => gtwiz_userclk_rx_reset_in, D => \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2\, Q => gtwiz_userclk_rx_active_out ); \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^gtwiz_userclk_rx_usrclk2_out\, CE => '1', CLR => gtwiz_userclk_rx_reset_in, D => '1', Q => \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to\ ); \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^gtwiz_userclk_rx_usrclk2_out\, CE => '1', CLR => gtwiz_userclk_rx_reset_in, D => \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to\, Q => \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_tx_userclk is port ( init_clk : out STD_LOGIC; sync_clk_out : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; mmcm_not_locked_out2 : out STD_LOGIC; bufg_gt_clr_out : in STD_LOGIC; tx_out_clk : in STD_LOGIC; lopt : out STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_tx_userclk; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_tx_userclk is signal \\ : STD_LOGIC; signal \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to\ : STD_LOGIC; attribute async_reg : string; attribute async_reg of \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to\ : signal is "true"; signal \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2\ : STD_LOGIC; attribute async_reg of \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2\ : signal is "true"; signal \^init_clk\ : STD_LOGIC; signal \^lopt\ : STD_LOGIC; signal \^lopt_1\ : STD_LOGIC; signal \^mmcm_not_locked_out\ : STD_LOGIC; attribute async_reg of mmcm_not_locked_out : signal is "true"; attribute BOX_TYPE : string; attribute BOX_TYPE of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst\ : label is "PRIMITIVE"; attribute OPT_MODIFIED : string; attribute OPT_MODIFIED of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst\ : label is "MLO"; attribute BOX_TYPE of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\ : label is "PRIMITIVE"; attribute OPT_MODIFIED of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\ : label is "MLO"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to_reg\ : label is std.standard.true; attribute KEEP of \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2_reg\ : label is std.standard.true; attribute KEEP of \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2_reg\ : label is "yes"; begin \^lopt\ <= lopt_1; \^lopt_1\ <= lopt_2; init_clk <= \^init_clk\; lopt <= \\; mmcm_not_locked_out <= \^mmcm_not_locked_out\; VCC: unisim.vcomponents.VCC port map ( P => \\ ); \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst\: unisim.vcomponents.BUFG_GT generic map( SIM_DEVICE => "ULTRASCALE", STARTUP_SYNC => "FALSE" ) port map ( CE => \^lopt\, CEMASK => '0', CLR => \^lopt_1\, CLRMASK => '0', DIV(2 downto 0) => B"001", I => tx_out_clk, O => \^init_clk\ ); \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\: unisim.vcomponents.BUFG_GT generic map( SIM_DEVICE => "ULTRASCALE", STARTUP_SYNC => "FALSE" ) port map ( CE => \^lopt\, CEMASK => '0', CLR => \^lopt_1\, CLRMASK => '0', DIV(2 downto 0) => B"000", I => tx_out_clk, O => sync_clk_out ); \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^init_clk\, CE => '1', CLR => bufg_gt_clr_out, D => \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2\, Q => \^mmcm_not_locked_out\ ); \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^init_clk\, CE => '1', CLR => bufg_gt_clr_out, D => '1', Q => \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to\ ); \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2_reg\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => \^init_clk\, CE => '1', CLR => bufg_gt_clr_out, D => \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to\, Q => \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2\ ); mmcm_not_locked_out2_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^mmcm_not_locked_out\, O => mmcm_not_locked_out2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer is port ( \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC; rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rxresetdone_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 is port ( \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC; txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => txresetdone_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_sequential_sm_reset_all_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \FSM_sequential_sm_reset_all_reg[0]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 is signal gtpowergood_sync : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_all[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AF0FAF00CFFFCFFF" ) port map ( I0 => gtpowergood_sync, I1 => \FSM_sequential_sm_reset_all_reg[0]\, I2 => Q(2), I3 => Q(0), I4 => \FSM_sequential_sm_reset_all_reg[0]_0\, I5 => Q(1), O => E(0) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtpowergood_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtpowergood_sync, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 is port ( gtwiz_reset_rx_datapath_dly : out STD_LOGIC; in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_rx_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 is port ( D : out STD_LOGIC_VECTOR ( 1 downto 0 ); i_in_out_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); gtwiz_reset_rx_datapath_dly : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 is signal gtwiz_reset_rx_pll_and_datapath_dly : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_rx[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0088FF00FFFFF0" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => gtwiz_reset_rx_pll_and_datapath_dly, I3 => Q(2), I4 => Q(0), I5 => Q(1), O => D(0) ); \FSM_sequential_sm_reset_rx[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFF8F8F000F" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => Q(2), I3 => gtwiz_reset_rx_pll_and_datapath_dly, I4 => Q(1), I5 => Q(0), O => D(1) ); \FSM_sequential_sm_reset_rx[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000000E" ) port map ( I0 => gtwiz_reset_rx_pll_and_datapath_dly, I1 => gtwiz_reset_rx_datapath_dly, I2 => Q(2), I3 => Q(1), I4 => Q(0), I5 => \FSM_sequential_sm_reset_rx_reg[0]_0\, O => i_in_out_reg_0 ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_rx_pll_and_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC; gtwiz_reset_tx_pll_and_datapath_dly : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 is signal gtwiz_reset_tx_datapath_dly : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_tx[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF1110" ) port map ( I0 => Q(0), I1 => \FSM_sequential_sm_reset_tx_reg[0]\, I2 => gtwiz_reset_tx_datapath_dly, I3 => gtwiz_reset_tx_pll_and_datapath_dly, I4 => \FSM_sequential_sm_reset_tx_reg[0]_0\, I5 => \FSM_sequential_sm_reset_tx_reg[0]_1\, O => E(0) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_tx_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 is port ( gtwiz_reset_tx_pll_and_datapath_dly : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 is signal \^gtwiz_reset_tx_pll_and_datapath_dly\ : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[0]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[1]_i_1\ : label is "soft_lutpair0"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin gtwiz_reset_tx_pll_and_datapath_dly <= \^gtwiz_reset_tx_pll_and_datapath_dly\; \FSM_sequential_sm_reset_tx[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1F1E" ) port map ( I0 => Q(1), I1 => Q(2), I2 => Q(0), I3 => \^gtwiz_reset_tx_pll_and_datapath_dly\, O => D(0) ); \FSM_sequential_sm_reset_tx[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0FF1" ) port map ( I0 => Q(2), I1 => \^gtwiz_reset_tx_pll_and_datapath_dly\, I2 => Q(1), I3 => Q(0), O => D(1) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^gtwiz_reset_tx_pll_and_datapath_dly\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 is port ( \FSM_sequential_sm_reset_rx_reg[0]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sm_reset_rx_timer_clr_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_rx_timer_clr_reg_0 : in STD_LOGIC; gtwiz_reset_rx_any_sync : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_1\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_2\ : in STD_LOGIC; sm_reset_rx_pll_timer_sat : in STD_LOGIC; sm_reset_rx_timer_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 is signal \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ : STD_LOGIC; signal gtwiz_reset_userclk_rx_active_sync : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_rx_timer_clr_i_2_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_rx[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\, I1 => \FSM_sequential_sm_reset_rx_reg[0]_0\, I2 => \FSM_sequential_sm_reset_rx_reg[0]_1\, O => E(0) ); \FSM_sequential_sm_reset_rx[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2023202000000000" ) port map ( I0 => sm_reset_rx_timer_clr_i_2_n_0, I1 => Q(1), I2 => Q(2), I3 => \FSM_sequential_sm_reset_rx_reg[0]_2\, I4 => sm_reset_rx_pll_timer_sat, I5 => Q(0), O => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_userclk_rx_active_in(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_userclk_rx_active_sync, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); rxuserrdy_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFAAF00000800" ) port map ( I0 => Q(2), I1 => sm_reset_rx_timer_clr_i_2_n_0, I2 => Q(1), I3 => Q(0), I4 => gtwiz_reset_rx_any_sync, I5 => \gen_gtwizard_gthe3.rxuserrdy_int\, O => \FSM_sequential_sm_reset_rx_reg[2]\ ); sm_reset_rx_timer_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FCCCEFFE0CCCE00E" ) port map ( I0 => sm_reset_rx_timer_clr_i_2_n_0, I1 => sm_reset_rx_timer_clr_reg, I2 => Q(0), I3 => Q(2), I4 => Q(1), I5 => sm_reset_rx_timer_clr_reg_0, O => \FSM_sequential_sm_reset_rx_reg[0]\ ); sm_reset_rx_timer_clr_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_rx_timer_clr_reg_0, I1 => sm_reset_rx_timer_sat, I2 => gtwiz_reset_userclk_rx_active_sync, O => sm_reset_rx_timer_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 is port ( gtwiz_reset_userclk_tx_active_sync : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[2]\ : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_tx_timer_clr_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC; sm_reset_tx_timer_clr_reg_0 : in STD_LOGIC; plllock_tx_sync : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_1\ : in STD_LOGIC; sm_reset_tx_pll_timer_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 is signal \^gtwiz_reset_userclk_tx_active_sync\ : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_tx_timer_clr_i_2_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin gtwiz_reset_userclk_tx_active_sync <= \^gtwiz_reset_userclk_tx_active_sync\; \FSM_sequential_sm_reset_tx[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"000F000088888888" ) port map ( I0 => \FSM_sequential_sm_reset_tx_reg[0]\, I1 => \^gtwiz_reset_userclk_tx_active_sync\, I2 => \FSM_sequential_sm_reset_tx_reg[0]_0\, I3 => \FSM_sequential_sm_reset_tx_reg[0]_1\, I4 => sm_reset_tx_pll_timer_sat, I5 => Q(0), O => i_in_out_reg_0 ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_userclk_tx_active_in(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^gtwiz_reset_userclk_tx_active_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); sm_reset_tx_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EBEB282B" ) port map ( I0 => sm_reset_tx_timer_clr_i_2_n_0, I1 => Q(2), I2 => Q(1), I3 => Q(0), I4 => sm_reset_tx_timer_clr_reg, O => \FSM_sequential_sm_reset_tx_reg[2]\ ); sm_reset_tx_timer_clr_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"A0C0A0C0F0F000F0" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I1 => \^gtwiz_reset_userclk_tx_active_sync\, I2 => sm_reset_tx_timer_clr_reg_0, I3 => Q(0), I4 => plllock_tx_sync, I5 => Q(2), O => sm_reset_tx_timer_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 is port ( plllock_rx_sync : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_int_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); gtwiz_reset_rx_done_int_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 is signal gtwiz_reset_rx_done_int : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal \^plllock_rx_sync\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin plllock_rx_sync <= \^plllock_rx_sync\; gtwiz_reset_rx_done_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAC0FFFFAAC00000" ) port map ( I0 => \^plllock_rx_sync\, I1 => gtwiz_reset_rx_done_int_reg, I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I3 => Q(0), I4 => gtwiz_reset_rx_done_int, I5 => gtwiz_reset_rx_done_int_reg_0, O => i_in_out_reg_0 ); gtwiz_reset_rx_done_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4C40000040400000" ) port map ( I0 => \^plllock_rx_sync\, I1 => Q(2), I2 => Q(0), I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I4 => Q(1), I5 => gtwiz_reset_rx_done_int_reg, O => gtwiz_reset_rx_done_int ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => cplllock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^plllock_rx_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); sm_reset_rx_timer_clr_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"88880000F5FF5555" ) port map ( I0 => Q(1), I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I2 => \^plllock_rx_sync\, I3 => Q(0), I4 => gtwiz_reset_rx_done_int_reg, I5 => Q(2), O => \FSM_sequential_sm_reset_rx_reg[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 is port ( plllock_tx_sync : out STD_LOGIC; gtwiz_reset_tx_done_int_reg : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_int_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_tx_timer_sat : in STD_LOGIC; gtwiz_reset_tx_done_int_reg_1 : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 is signal gtwiz_reset_tx_done_int : STD_LOGIC; signal gtwiz_reset_tx_done_int_i_2_n_0 : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal \^plllock_tx_sync\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin plllock_tx_sync <= \^plllock_tx_sync\; \FSM_sequential_sm_reset_tx[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"00CFA00000000000" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I1 => \^plllock_tx_sync\, I2 => Q(0), I3 => Q(2), I4 => Q(1), I5 => \FSM_sequential_sm_reset_tx_reg[0]\, O => i_in_out_reg_0 ); gtwiz_reset_tx_done_int_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => gtwiz_reset_tx_done_int_i_2_n_0, I1 => gtwiz_reset_tx_done_int, I2 => gtwiz_reset_tx_done_int_reg_0, O => gtwiz_reset_tx_done_int_reg ); gtwiz_reset_tx_done_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444F44444" ) port map ( I0 => Q(0), I1 => \^plllock_tx_sync\, I2 => sm_reset_tx_timer_sat, I3 => gtwiz_reset_tx_done_int_reg_1, I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I5 => Q(1), O => gtwiz_reset_tx_done_int_i_2_n_0 ); gtwiz_reset_tx_done_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"3000404000004040" ) port map ( I0 => \^plllock_tx_sync\, I1 => Q(1), I2 => Q(2), I3 => \FSM_sequential_sm_reset_tx_reg[0]\, I4 => Q(0), I5 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, O => gtwiz_reset_tx_done_int ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => cplllock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^plllock_tx_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 is port ( \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; sm_reset_rx_cdr_to_sat_reg : out STD_LOGIC; rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sm_reset_rx_cdr_to_clr_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); plllock_rx_sync : in STD_LOGIC; sm_reset_rx_cdr_to_clr : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC; sm_reset_rx_cdr_to_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_out_reg_n_0 : STD_LOGIC; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_rx_cdr_to_clr_i_2_n_0 : STD_LOGIC; signal \^sm_reset_rx_cdr_to_sat_reg\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of rxprogdivreset_out_i_2 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_2 : label is "soft_lutpair1"; begin sm_reset_rx_cdr_to_sat_reg <= \^sm_reset_rx_cdr_to_sat_reg\; \FSM_sequential_sm_reset_rx[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"000A000AC0C000C0" ) port map ( I0 => \^sm_reset_rx_cdr_to_sat_reg\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => Q(1), I3 => Q(0), I4 => plllock_rx_sync, I5 => Q(2), O => \FSM_sequential_sm_reset_rx_reg[1]\ ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rxcdrlock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => i_in_out_reg_n_0, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); rxprogdivreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => i_in_out_reg_n_0, O => \^sm_reset_rx_cdr_to_sat_reg\ ); sm_reset_rx_cdr_to_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF0800AAAA" ) port map ( I0 => sm_reset_rx_cdr_to_clr_i_2_n_0, I1 => sm_reset_rx_cdr_to_clr_reg, I2 => Q(2), I3 => plllock_rx_sync, I4 => Q(0), I5 => sm_reset_rx_cdr_to_clr, O => \FSM_sequential_sm_reset_rx_reg[2]\ ); sm_reset_rx_cdr_to_clr_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"00EF" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => i_in_out_reg_n_0, I2 => Q(2), I3 => Q(1), O => sm_reset_rx_cdr_to_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel is port ( cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rst_in0 : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.txprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC; txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txheader_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC; lopt_5 : in STD_LOGIC; lopt_6 : out STD_LOGIC; lopt_7 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel is signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC; signal \^lopt_2\ : STD_LOGIC; signal \^lopt_3\ : STD_LOGIC; signal \^rxoutclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^txoutclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \xlnx_opt_\ : STD_LOGIC; signal \xlnx_opt__1\ : STD_LOGIC; signal \xlnx_opt__2\ : STD_LOGIC; signal \xlnx_opt__3\ : STD_LOGIC; attribute OPT_MODIFIED : string; attribute OPT_MODIFIED of BUFG_GT_SYNC : label is "MLO"; attribute OPT_MODIFIED of BUFG_GT_SYNC_1 : label is "MLO"; attribute BOX_TYPE : string; attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE"; begin \^lopt_2\ <= lopt_4; \^lopt_3\ <= lopt_5; cplllock_out(0) <= \^cplllock_out\(0); lopt_2 <= \xlnx_opt_\; lopt_3 <= \xlnx_opt__1\; lopt_6 <= \xlnx_opt__2\; lopt_7 <= \xlnx_opt__3\; rxoutclk_out(0) <= \^rxoutclk_out\(0); txoutclk_out(0) <= \^txoutclk_out\(0); BUFG_GT_SYNC: unisim.vcomponents.BUFG_GT_SYNC port map ( CE => lopt, CESYNC => \xlnx_opt_\, CLK => \^rxoutclk_out\(0), CLR => lopt_1, CLRSYNC => \xlnx_opt__1\ ); BUFG_GT_SYNC_1: unisim.vcomponents.BUFG_GT_SYNC port map ( CE => \^lopt_2\, CESYNC => \xlnx_opt__2\, CLK => \^txoutclk_out\(0), CLR => \^lopt_3\, CLRSYNC => \xlnx_opt__3\ ); \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL generic map( ACJTAG_DEBUG_MODE => '0', ACJTAG_MODE => '0', ACJTAG_RESET => '0', ADAPT_CFG0 => X"F800", ADAPT_CFG1 => X"0000", ALIGN_COMMA_DOUBLE => "FALSE", ALIGN_COMMA_ENABLE => B"0000000000", ALIGN_COMMA_WORD => 1, ALIGN_MCOMMA_DET => "FALSE", ALIGN_MCOMMA_VALUE => B"1010000011", ALIGN_PCOMMA_DET => "FALSE", ALIGN_PCOMMA_VALUE => B"0101111100", A_RXOSCALRESET => '0', A_RXPROGDIVRESET => '0', A_TXPROGDIVRESET => '0', CBCC_DATA_SOURCE_SEL => "ENCODED", CDR_SWAP_MODE_EN => '0', CHAN_BOND_KEEP_ALIGN => "FALSE", CHAN_BOND_MAX_SKEW => 1, CHAN_BOND_SEQ_1_1 => B"0000000000", CHAN_BOND_SEQ_1_2 => B"0000000000", CHAN_BOND_SEQ_1_3 => B"0000000000", CHAN_BOND_SEQ_1_4 => B"0000000000", CHAN_BOND_SEQ_1_ENABLE => B"1111", CHAN_BOND_SEQ_2_1 => B"0000000000", CHAN_BOND_SEQ_2_2 => B"0000000000", CHAN_BOND_SEQ_2_3 => B"0000000000", CHAN_BOND_SEQ_2_4 => B"0000000000", CHAN_BOND_SEQ_2_ENABLE => B"1111", CHAN_BOND_SEQ_2_USE => "FALSE", CHAN_BOND_SEQ_LEN => 1, CLK_CORRECT_USE => "FALSE", CLK_COR_KEEP_IDLE => "FALSE", CLK_COR_MAX_LAT => 12, CLK_COR_MIN_LAT => 8, CLK_COR_PRECEDENCE => "TRUE", CLK_COR_REPEAT_WAIT => 0, CLK_COR_SEQ_1_1 => B"0000000000", CLK_COR_SEQ_1_2 => B"0000000000", CLK_COR_SEQ_1_3 => B"0000000000", CLK_COR_SEQ_1_4 => B"0000000000", CLK_COR_SEQ_1_ENABLE => B"1111", CLK_COR_SEQ_2_1 => B"0000000000", CLK_COR_SEQ_2_2 => B"0000000000", CLK_COR_SEQ_2_3 => B"0000000000", CLK_COR_SEQ_2_4 => B"0000000000", CLK_COR_SEQ_2_ENABLE => B"1111", CLK_COR_SEQ_2_USE => "FALSE", CLK_COR_SEQ_LEN => 1, CPLL_CFG0 => X"67F8", CPLL_CFG1 => X"A4AC", CPLL_CFG2 => X"0007", CPLL_CFG3 => B"00" & X"0", CPLL_FBDIV => 5, CPLL_FBDIV_45 => 4, CPLL_INIT_CFG0 => X"02B2", CPLL_INIT_CFG1 => X"00", CPLL_LOCK_CFG => X"01E8", CPLL_REFCLK_DIV => 1, DDI_CTRL => B"00", DDI_REALIGN_WAIT => 15, DEC_MCOMMA_DETECT => "FALSE", DEC_PCOMMA_DETECT => "FALSE", DEC_VALID_COMMA_ONLY => "FALSE", DFE_D_X_REL_POS => '0', DFE_VCM_COMP_EN => '0', DMONITOR_CFG0 => B"00" & X"00", DMONITOR_CFG1 => X"00", ES_CLK_PHASE_SEL => '0', ES_CONTROL => B"000000", ES_ERRDET_EN => "FALSE", ES_EYE_SCAN_EN => "FALSE", ES_HORZ_OFFSET => X"000", ES_PMA_CFG => B"0000000000", ES_PRESCALE => B"00000", ES_QUALIFIER0 => X"0000", ES_QUALIFIER1 => X"0000", ES_QUALIFIER2 => X"0000", ES_QUALIFIER3 => X"0000", ES_QUALIFIER4 => X"0000", ES_QUAL_MASK0 => X"0000", ES_QUAL_MASK1 => X"0000", ES_QUAL_MASK2 => X"0000", ES_QUAL_MASK3 => X"0000", ES_QUAL_MASK4 => X"0000", ES_SDATA_MASK0 => X"0000", ES_SDATA_MASK1 => X"0000", ES_SDATA_MASK2 => X"0000", ES_SDATA_MASK3 => X"0000", ES_SDATA_MASK4 => X"0000", EVODD_PHI_CFG => B"00000000000", EYE_SCAN_SWAP_EN => '0', FTS_DESKEW_SEQ_ENABLE => B"1111", FTS_LANE_DESKEW_CFG => B"1111", FTS_LANE_DESKEW_EN => "FALSE", GEARBOX_MODE => B"00001", GM_BIAS_SELECT => '0', LOCAL_MASTER => '1', OOBDIVCTL => B"00", OOB_PWRUP => '0', PCI3_AUTO_REALIGN => "OVR_1K_BLK", PCI3_PIPE_RX_ELECIDLE => '0', PCI3_RX_ASYNC_EBUF_BYPASS => B"00", PCI3_RX_ELECIDLE_EI2_ENABLE => '0', PCI3_RX_ELECIDLE_H2L_COUNT => B"000000", PCI3_RX_ELECIDLE_H2L_DISABLE => B"000", PCI3_RX_ELECIDLE_HI_COUNT => B"000000", PCI3_RX_ELECIDLE_LP4_DISABLE => '0', PCI3_RX_FIFO_DISABLE => '0', PCIE_BUFG_DIV_CTRL => X"1000", PCIE_RXPCS_CFG_GEN3 => X"02A4", PCIE_RXPMA_CFG => X"000A", PCIE_TXPCS_CFG_GEN3 => X"24A4", PCIE_TXPMA_CFG => X"000A", PCS_PCIE_EN => "FALSE", PCS_RSVD0 => B"0000000000000000", PCS_RSVD1 => B"000", PD_TRANS_TIME_FROM_P2 => X"03C", PD_TRANS_TIME_NONE_P2 => X"19", PD_TRANS_TIME_TO_P2 => X"64", PLL_SEL_MODE_GEN12 => B"00", PLL_SEL_MODE_GEN3 => B"11", PMA_RSV1 => X"F000", PROCESS_PAR => B"010", RATE_SW_USE_DRP => '1', RESET_POWERSAVE_DISABLE => '0', RXBUFRESET_TIME => B"00011", RXBUF_ADDR_MODE => "FAST", RXBUF_EIDLE_HI_CNT => B"1000", RXBUF_EIDLE_LO_CNT => B"0000", RXBUF_EN => "TRUE", RXBUF_RESET_ON_CB_CHANGE => "TRUE", RXBUF_RESET_ON_COMMAALIGN => "FALSE", RXBUF_RESET_ON_EIDLE => "FALSE", RXBUF_RESET_ON_RATE_CHANGE => "TRUE", RXBUF_THRESH_OVFLW => 57, RXBUF_THRESH_OVRD => "TRUE", RXBUF_THRESH_UNDFLW => 3, RXCDRFREQRESET_TIME => B"00001", RXCDRPHRESET_TIME => B"00001", RXCDR_CFG0 => X"0000", RXCDR_CFG0_GEN3 => X"0000", RXCDR_CFG1 => X"0000", RXCDR_CFG1_GEN3 => X"0000", RXCDR_CFG2 => X"07E6", RXCDR_CFG2_GEN3 => X"07E6", RXCDR_CFG3 => X"0000", RXCDR_CFG3_GEN3 => X"0000", RXCDR_CFG4 => X"0000", RXCDR_CFG4_GEN3 => X"0000", RXCDR_CFG5 => X"0000", RXCDR_CFG5_GEN3 => X"0000", RXCDR_FR_RESET_ON_EIDLE => '0', RXCDR_HOLD_DURING_EIDLE => '0', RXCDR_LOCK_CFG0 => X"4480", RXCDR_LOCK_CFG1 => X"5FFF", RXCDR_LOCK_CFG2 => X"77C3", RXCDR_PH_RESET_ON_EIDLE => '0', RXCFOK_CFG0 => X"4000", RXCFOK_CFG1 => X"0065", RXCFOK_CFG2 => X"002E", RXDFELPMRESET_TIME => B"0001111", RXDFELPM_KL_CFG0 => X"0000", RXDFELPM_KL_CFG1 => X"0002", RXDFELPM_KL_CFG2 => X"0000", RXDFE_CFG0 => X"0A00", RXDFE_CFG1 => X"0000", RXDFE_GC_CFG0 => X"0000", RXDFE_GC_CFG1 => X"7870", RXDFE_GC_CFG2 => X"0000", RXDFE_H2_CFG0 => X"0000", RXDFE_H2_CFG1 => X"0000", RXDFE_H3_CFG0 => X"4000", RXDFE_H3_CFG1 => X"0000", RXDFE_H4_CFG0 => X"2000", RXDFE_H4_CFG1 => X"0003", RXDFE_H5_CFG0 => X"2000", RXDFE_H5_CFG1 => X"0003", RXDFE_H6_CFG0 => X"2000", RXDFE_H6_CFG1 => X"0000", RXDFE_H7_CFG0 => X"2000", RXDFE_H7_CFG1 => X"0000", RXDFE_H8_CFG0 => X"2000", RXDFE_H8_CFG1 => X"0000", RXDFE_H9_CFG0 => X"2000", RXDFE_H9_CFG1 => X"0000", RXDFE_HA_CFG0 => X"2000", RXDFE_HA_CFG1 => X"0000", RXDFE_HB_CFG0 => X"2000", RXDFE_HB_CFG1 => X"0000", RXDFE_HC_CFG0 => X"0000", RXDFE_HC_CFG1 => X"0000", RXDFE_HD_CFG0 => X"0000", RXDFE_HD_CFG1 => X"0000", RXDFE_HE_CFG0 => X"0000", RXDFE_HE_CFG1 => X"0000", RXDFE_HF_CFG0 => X"0000", RXDFE_HF_CFG1 => X"0000", RXDFE_OS_CFG0 => X"8000", RXDFE_OS_CFG1 => X"0000", RXDFE_UT_CFG0 => X"8000", RXDFE_UT_CFG1 => X"0003", RXDFE_VP_CFG0 => X"AA00", RXDFE_VP_CFG1 => X"0033", RXDLY_CFG => X"001F", RXDLY_LCFG => X"0030", RXELECIDLE_CFG => "Sigcfg_4", RXGBOX_FIFO_INIT_RD_ADDR => 4, RXGEARBOX_EN => "TRUE", RXISCANRESET_TIME => B"00001", RXLPM_CFG => X"0000", RXLPM_GC_CFG => X"1000", RXLPM_KH_CFG0 => X"0000", RXLPM_KH_CFG1 => X"0002", RXLPM_OS_CFG0 => X"8000", RXLPM_OS_CFG1 => X"0002", RXOOB_CFG => B"000000110", RXOOB_CLK_CFG => "PMA", RXOSCALRESET_TIME => B"00011", RXOUT_DIV => 1, RXPCSRESET_TIME => B"00011", RXPHBEACON_CFG => X"0000", RXPHDLY_CFG => X"2020", RXPHSAMP_CFG => X"2100", RXPHSLIP_CFG => X"6622", RXPH_MONITOR_SEL => B"00000", RXPI_CFG0 => B"00", RXPI_CFG1 => B"00", RXPI_CFG2 => B"00", RXPI_CFG3 => B"00", RXPI_CFG4 => '1', RXPI_CFG5 => '1', RXPI_CFG6 => B"011", RXPI_LPM => '0', RXPI_VREFSEL => '0', RXPMACLK_SEL => "DATA", RXPMARESET_TIME => B"00011", RXPRBS_ERR_LOOPBACK => '0', RXPRBS_LINKACQ_CNT => 15, RXSLIDE_AUTO_WAIT => 7, RXSLIDE_MODE => "OFF", RXSYNC_MULTILANE => '0', RXSYNC_OVRD => '0', RXSYNC_SKIP_DA => '0', RX_AFE_CM_EN => '0', RX_BIAS_CFG0 => X"0AB4", RX_BUFFER_CFG => B"000000", RX_CAPFF_SARC_ENB => '0', RX_CLK25_DIV => 5, RX_CLKMUX_EN => '1', RX_CLK_SLIP_OVRD => B"00000", RX_CM_BUF_CFG => B"1010", RX_CM_BUF_PD => '0', RX_CM_SEL => B"11", RX_CM_TRIM => B"1010", RX_CTLE3_LPF => B"00000001", RX_DATA_WIDTH => 32, RX_DDI_SEL => B"000000", RX_DEFER_RESET_BUF_EN => "TRUE", RX_DFELPM_CFG0 => B"0110", RX_DFELPM_CFG1 => '1', RX_DFELPM_KLKH_AGC_STUP_EN => '1', RX_DFE_AGC_CFG0 => B"10", RX_DFE_AGC_CFG1 => B"100", RX_DFE_KL_LPM_KH_CFG0 => B"01", RX_DFE_KL_LPM_KH_CFG1 => B"100", RX_DFE_KL_LPM_KL_CFG0 => B"01", RX_DFE_KL_LPM_KL_CFG1 => B"100", RX_DFE_LPM_HOLD_DURING_EIDLE => '0', RX_DISPERR_SEQ_MATCH => "TRUE", RX_DIVRESET_TIME => B"00001", RX_EN_HI_LR => '0', RX_EYESCAN_VS_CODE => B"0000000", RX_EYESCAN_VS_NEG_DIR => '0', RX_EYESCAN_VS_RANGE => B"00", RX_EYESCAN_VS_UT_SIGN => '0', RX_FABINT_USRCLK_FLOP => '0', RX_INT_DATAWIDTH => 1, RX_PMA_POWER_SAVE => '0', RX_PROGDIV_CFG => 0.000000, RX_SAMPLE_PERIOD => B"111", RX_SIG_VALID_DLY => 11, RX_SUM_DFETAPREP_EN => '0', RX_SUM_IREF_TUNE => B"0000", RX_SUM_RES_CTRL => B"00", RX_SUM_VCMTUNE => B"0000", RX_SUM_VCM_OVWR => '0', RX_SUM_VREF_TUNE => B"000", RX_TUNE_AFE_OS => B"10", RX_WIDEMODE_CDR => '0', RX_XCLK_SEL => "RXDES", SAS_MAX_COM => 64, SAS_MIN_COM => 36, SATA_BURST_SEQ_LEN => B"1110", SATA_BURST_VAL => B"100", SATA_CPLL_CFG => "VCO_3000MHZ", SATA_EIDLE_VAL => B"100", SATA_MAX_BURST => 8, SATA_MAX_INIT => 21, SATA_MAX_WAKE => 7, SATA_MIN_BURST => 4, SATA_MIN_INIT => 12, SATA_MIN_WAKE => 4, SHOW_REALIGN_COMMA => "TRUE", SIM_MODE => "FAST", SIM_RECEIVER_DETECT_PASS => "TRUE", SIM_RESET_SPEEDUP => "TRUE", SIM_TX_EIDLE_DRIVE_LEVEL => '0', SIM_VERSION => 2, TAPDLY_SET_TX => B"00", TEMPERATUR_PAR => B"0010", TERM_RCAL_CFG => B"100001000010000", TERM_RCAL_OVRD => B"000", TRANS_TIME_RATE => X"0E", TST_RSV0 => X"00", TST_RSV1 => X"00", TXBUF_EN => "TRUE", TXBUF_RESET_ON_RATE_CHANGE => "TRUE", TXDLY_CFG => X"0009", TXDLY_LCFG => X"0050", TXDRVBIAS_N => B"1010", TXDRVBIAS_P => B"1010", TXFIFO_ADDR_CFG => "LOW", TXGBOX_FIFO_INIT_RD_ADDR => 4, TXGEARBOX_EN => "TRUE", TXOUT_DIV => 1, TXPCSRESET_TIME => B"00011", TXPHDLY_CFG0 => X"2020", TXPHDLY_CFG1 => X"0075", TXPH_CFG => X"0980", TXPH_MONITOR_SEL => B"00000", TXPI_CFG0 => B"00", TXPI_CFG1 => B"00", TXPI_CFG2 => B"00", TXPI_CFG3 => '1', TXPI_CFG4 => '1', TXPI_CFG5 => B"011", TXPI_GRAY_SEL => '0', TXPI_INVSTROBE_SEL => '1', TXPI_LPM => '0', TXPI_PPMCLK_SEL => "TXUSRCLK2", TXPI_PPM_CFG => B"00000000", TXPI_SYNFREQ_PPM => B"001", TXPI_VREFSEL => '0', TXPMARESET_TIME => B"00011", TXSYNC_MULTILANE => '0', TXSYNC_OVRD => '0', TXSYNC_SKIP_DA => '0', TX_CLK25_DIV => 5, TX_CLKMUX_EN => '1', TX_DATA_WIDTH => 64, TX_DCD_CFG => B"000010", TX_DCD_EN => '0', TX_DEEMPH0 => B"000000", TX_DEEMPH1 => B"000000", TX_DIVRESET_TIME => B"00001", TX_DRIVE_MODE => "DIRECT", TX_EIDLE_ASSERT_DELAY => B"100", TX_EIDLE_DEASSERT_DELAY => B"011", TX_EML_PHI_TUNE => '0', TX_FABINT_USRCLK_FLOP => '0', TX_IDLE_DATA_ZERO => '0', TX_INT_DATAWIDTH => 1, TX_LOOPBACK_DRIVE_HIZ => "FALSE", TX_MAINCURSOR_SEL => '0', TX_MARGIN_FULL_0 => B"1001111", TX_MARGIN_FULL_1 => B"1001110", TX_MARGIN_FULL_2 => B"1001100", TX_MARGIN_FULL_3 => B"1001010", TX_MARGIN_FULL_4 => B"1001000", TX_MARGIN_LOW_0 => B"1000110", TX_MARGIN_LOW_1 => B"1000101", TX_MARGIN_LOW_2 => B"1000011", TX_MARGIN_LOW_3 => B"1000010", TX_MARGIN_LOW_4 => B"1000000", TX_MODE_SEL => B"000", TX_PMADATA_OPT => '0', TX_PMA_POWER_SAVE => '0', TX_PROGCLK_SEL => "PREPI", TX_PROGDIV_CFG => 0.000000, TX_QPI_STATUS_EN => '0', TX_RXDETECT_CFG => B"00" & X"032", TX_RXDETECT_REF => B"100", TX_SAMPLE_PERIOD => B"111", TX_SARC_LPBK_ENB => '0', TX_XCLK_SEL => "TXOUT", USE_PCS_CLK_PHASE_SEL => '0', WB_MODE => B"00" ) port map ( BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\, BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\, BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\, BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\, BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\, BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\, BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\, BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\, BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\, BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\, BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\, BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\, BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\, BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\, BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\, BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\, BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\, BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\, BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\, BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\, BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\, CFGRESET => '0', CLKRSVD0 => '0', CLKRSVD1 => '0', CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\, CPLLLOCK => \^cplllock_out\(0), CPLLLOCKDETCLK => '0', CPLLLOCKEN => '1', CPLLPD => \gen_gtwizard_gthe3.cpllpd_ch_int\, CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\, CPLLREFCLKSEL(2 downto 0) => B"001", CPLLRESET => '0', DMONFIFORESET => '0', DMONITORCLK => '0', DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\, DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\, DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\, DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\, DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\, DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\, DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\, DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\, DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\, DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\, DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\, DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\, DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\, DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\, DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\, DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\, DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\, DRPADDR(8 downto 0) => drpaddr_in(8 downto 0), DRPCLK => drpclk_in(0), DRPDI(15 downto 0) => drpdi_in(15 downto 0), DRPDO(15 downto 0) => drpdo_out(15 downto 0), DRPEN => drpen_in(0), DRPRDY => drprdy_out(0), DRPWE => drpwe_in(0), EVODDPHICALDONE => '0', EVODDPHICALSTART => '0', EVODDPHIDRDEN => '0', EVODDPHIDWREN => '0', EVODDPHIXRDEN => '0', EVODDPHIXWREN => '0', EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\, EYESCANMODE => '0', EYESCANRESET => '0', EYESCANTRIGGER => '0', GTGREFCLK => '0', GTHRXN => gthrxn_in(0), GTHRXP => gthrxp_in(0), GTHTXN => gthtxn_out(0), GTHTXP => gthtxp_out(0), GTNORTHREFCLK0 => '0', GTNORTHREFCLK1 => '0', GTPOWERGOOD => gtpowergood_out(0), GTREFCLK0 => gtrefclk0_in(0), GTREFCLK1 => '0', GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\, GTRESETSEL => '0', GTRSVD(15 downto 0) => B"0000000000000000", GTRXRESET => \gen_gtwizard_gthe3.gtrxreset_int\, GTSOUTHREFCLK0 => '0', GTSOUTHREFCLK1 => '0', GTTXRESET => \gen_gtwizard_gthe3.gttxreset_int\, LOOPBACK(2 downto 0) => loopback_in(2 downto 0), LPBKRXTXSEREN => '0', LPBKTXRXSEREN => '0', PCIEEQRXEQADAPTDONE => '0', PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\, PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\, PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\, PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\, PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\, PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\, PCIERSTIDLE => '0', PCIERSTTXSYNCSTART => '0', PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\, PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\, PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\, PCIEUSERRATEDONE => '0', PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\, PCSRSVDIN(15 downto 0) => B"0000000000000000", PCSRSVDIN2(4 downto 0) => B"00000", PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\, PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\, PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\, PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\, PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\, PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\, PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\, PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\, PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\, PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\, PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\, PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\, PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\, PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\, PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\, PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\, PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\, PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\, PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\, PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\, PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\, PMARSVDIN(4 downto 0) => B"00000", QPLL0CLK => '0', QPLL0REFCLK => '0', QPLL1CLK => '0', QPLL1REFCLK => '0', RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\, RESETOVRD => '0', RSTCLKENTX => '0', RX8B10BEN => '0', RXBUFRESET => '0', RXBUFSTATUS(2) => rxbufstatus_out(0), RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\, RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\, RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\, RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\, RXCDRFREQRESET => '0', RXCDRHOLD => '0', RXCDRLOCK => rxcdrlock_out(0), RXCDROVRDEN => rxcdrovrden_in(0), RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\, RXCDRRESET => '0', RXCDRRESETRSV => '0', RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\, RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\, RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\, RXCHBONDEN => '0', RXCHBONDI(4 downto 0) => B"00000", RXCHBONDLEVEL(2 downto 0) => B"000", RXCHBONDMASTER => '0', RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\, RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\, RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\, RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\, RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\, RXCHBONDSLAVE => '0', RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\, RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\, RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\, RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\, RXCOMMADETEN => '0', RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\, RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\, RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\, RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\, RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\, RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\, RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\, RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\, RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\, RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\, RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\, RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\, RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\, RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\, RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\, RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\, RXCTRL0(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240\, RXCTRL0(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241\, RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\, RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\, RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\, RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\, RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\, RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\, RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\, RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\, RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\, RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\, RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\, RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\, RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\, RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\, RXCTRL1(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256\, RXCTRL1(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257\, RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\, RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\, RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\, RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\, RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\, RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\, RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\, RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\, RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\, RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\, RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\, RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\, RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\, RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\, RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\, RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\, RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\, RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\, RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\, RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\, RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\, RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\, RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\, RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\, RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\, RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\, RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\, RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\, RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\, RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\, RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\, RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\, RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\, RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\, RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\, RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\, RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\, RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\, RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\, RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\, RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\, RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\, RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\, RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\, RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\, RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\, RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\, RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\, RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\, RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\, RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\, RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\, RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\, RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\, RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\, RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\, RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\, RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\, RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\, RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\, RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\, RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\, RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\, RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\, RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\, RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\, RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\, RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\, RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\, RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\, RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\, RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\, RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\, RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\, RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\, RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\, RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\, RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\, RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\, RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\, RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\, RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\, RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\, RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\, RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\, RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\, RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\, RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\, RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\, RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\, RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\, RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\, RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\, RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\, RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\, RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\, RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\, RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\, RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\, RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\, RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\, RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\, RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\, RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\, RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\, RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\, RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\, RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\, RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\, RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\, RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\, RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\, RXDATA(31 downto 0) => gtwiz_userdata_rx_out(31 downto 0), RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\, RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\, RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\, RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\, RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\, RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\, RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\, RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\, RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\, RXDATAVALID(0) => rxdatavalid_out(0), RXDFEAGCCTRL(1 downto 0) => B"01", RXDFEAGCHOLD => '0', RXDFEAGCOVRDEN => '0', RXDFELFHOLD => '0', RXDFELFOVRDEN => '0', RXDFELPMRESET => '0', RXDFETAP10HOLD => '0', RXDFETAP10OVRDEN => '0', RXDFETAP11HOLD => '0', RXDFETAP11OVRDEN => '0', RXDFETAP12HOLD => '0', RXDFETAP12OVRDEN => '0', RXDFETAP13HOLD => '0', RXDFETAP13OVRDEN => '0', RXDFETAP14HOLD => '0', RXDFETAP14OVRDEN => '0', RXDFETAP15HOLD => '0', RXDFETAP15OVRDEN => '0', RXDFETAP2HOLD => '0', RXDFETAP2OVRDEN => '0', RXDFETAP3HOLD => '0', RXDFETAP3OVRDEN => '0', RXDFETAP4HOLD => '0', RXDFETAP4OVRDEN => '0', RXDFETAP5HOLD => '0', RXDFETAP5OVRDEN => '0', RXDFETAP6HOLD => '0', RXDFETAP6OVRDEN => '0', RXDFETAP7HOLD => '0', RXDFETAP7OVRDEN => '0', RXDFETAP8HOLD => '0', RXDFETAP8OVRDEN => '0', RXDFETAP9HOLD => '0', RXDFETAP9OVRDEN => '0', RXDFEUTHOLD => '0', RXDFEUTOVRDEN => '0', RXDFEVPHOLD => '0', RXDFEVPOVRDEN => '0', RXDFEVSEN => '0', RXDFEXYDEN => '1', RXDLYBYPASS => '1', RXDLYEN => '0', RXDLYOVRDEN => '0', RXDLYSRESET => '0', RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\, RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\, RXELECIDLEMODE(1 downto 0) => B"11", RXGEARBOXSLIP => rxgearboxslip_in(0), RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\, RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\, RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\, RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\, RXHEADER(1 downto 0) => rxheader_out(1 downto 0), RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\, RXHEADERVALID(0) => rxheadervalid_out(0), RXLATCLK => '0', RXLPMEN => '0', RXLPMGCHOLD => '0', RXLPMGCOVRDEN => '0', RXLPMHFHOLD => '0', RXLPMHFOVRDEN => '0', RXLPMLFHOLD => '0', RXLPMLFKLOVRDEN => '0', RXLPMOSHOLD => '0', RXLPMOSOVRDEN => '0', RXMCOMMAALIGNEN => '0', RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\, RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\, RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\, RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\, RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\, RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\, RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\, RXMONITORSEL(1 downto 0) => B"00", RXOOBRESET => '0', RXOSCALRESET => '0', RXOSHOLD => '0', RXOSINTCFG(3 downto 0) => B"1101", RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\, RXOSINTEN => '1', RXOSINTHOLD => '0', RXOSINTOVRDEN => '0', RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\, RXOSINTSTROBE => '0', RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\, RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\, RXOSINTTESTOVRDEN => '0', RXOSOVRDEN => '0', RXOUTCLK => \^rxoutclk_out\(0), RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\, RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\, RXOUTCLKSEL(2 downto 0) => B"010", RXPCOMMAALIGNEN => '0', RXPCSRESET => '0', RXPD(1 downto 0) => B"00", RXPHALIGN => '0', RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\, RXPHALIGNEN => '0', RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\, RXPHDLYPD => '1', RXPHDLYRESET => '0', RXPHOVRDEN => '0', RXPLLCLKSEL(1 downto 0) => B"00", RXPMARESET => '0', RXPMARESETDONE => rxpmaresetdone_out(0), RXPOLARITY => rxpolarity_in(0), RXPRBSCNTRESET => '0', RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\, RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\, RXPRBSSEL(3 downto 0) => B"0000", RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\, RXPROGDIVRESET => \gen_gtwizard_gthe3.rxprogdivreset_int\, RXQPIEN => '0', RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\, RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\, RXRATE(2 downto 0) => B"000", RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\, RXRATEMODE => '0', RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\, RXRESETDONE => rxresetdone_out(0), RXSLIDE => '0', RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\, RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\, RXSLIPOUTCLK => '0', RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\, RXSLIPPMA => '0', RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\, RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\, RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\, RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\, RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\, RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\, RXSYNCALLIN => '0', RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\, RXSYNCIN => '0', RXSYNCMODE => '0', RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\, RXSYSCLKSEL(1 downto 0) => B"00", RXUSERRDY => \gen_gtwizard_gthe3.rxuserrdy_int\, RXUSRCLK => rxusrclk_in(0), RXUSRCLK2 => rxusrclk2_in(0), RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\, SIGVALIDCLK => '0', TSTIN(19 downto 0) => B"00000000000000000000", TX8B10BBYPASS(7 downto 0) => B"00000000", TX8B10BEN => '0', TXBUFDIFFCTRL(2 downto 0) => B"000", TXBUFSTATUS(1) => txbufstatus_out(0), TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\, TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\, TXCOMINIT => '0', TXCOMSAS => '0', TXCOMWAKE => '0', TXCTRL0(15 downto 0) => B"0000000000000000", TXCTRL1(15 downto 0) => B"0000000000000000", TXCTRL2(7 downto 0) => B"00000000", TXDATA(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000", TXDATA(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0), TXDATAEXTENDRSVD(7 downto 0) => B"00000000", TXDEEMPH => '0', TXDETECTRX => '0', TXDIFFCTRL(3 downto 0) => B"1000", TXDIFFPD => '0', TXDLYBYPASS => '1', TXDLYEN => '0', TXDLYHOLD => '0', TXDLYOVRDEN => '0', TXDLYSRESET => '0', TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\, TXDLYUPDOWN => '0', TXELECIDLE => '0', TXHEADER(5 downto 2) => B"0000", TXHEADER(1 downto 0) => txheader_in(1 downto 0), TXINHIBIT => '0', TXLATCLK => '0', TXMAINCURSOR(6 downto 0) => B"1000000", TXMARGIN(2 downto 0) => B"000", TXOUTCLK => \^txoutclk_out\(0), TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\, TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\, TXOUTCLKSEL(2 downto 0) => B"010", TXPCSRESET => '0', TXPD(1 downto 0) => B"00", TXPDELECIDLEMODE => '0', TXPHALIGN => '0', TXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60\, TXPHALIGNEN => '0', TXPHDLYPD => '1', TXPHDLYRESET => '0', TXPHDLYTSTCLK => '0', TXPHINIT => '0', TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\, TXPHOVRDEN => '0', TXPIPPMEN => '0', TXPIPPMOVRDEN => '0', TXPIPPMPD => '0', TXPIPPMSEL => '0', TXPIPPMSTEPSIZE(4 downto 0) => B"00000", TXPISOPD => '0', TXPLLCLKSEL(1 downto 0) => B"00", TXPMARESET => '0', TXPMARESETDONE => txpmaresetdone_out(0), TXPOLARITY => '0', TXPOSTCURSOR(4 downto 0) => B"00000", TXPOSTCURSORINV => '0', TXPRBSFORCEERR => '0', TXPRBSSEL(3 downto 0) => B"0000", TXPRECURSOR(4 downto 0) => B"00000", TXPRECURSORINV => '0', TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\, TXPROGDIVRESET => \gen_gtwizard_gthe3.txprogdivreset_int\, TXQPIBIASEN => '0', TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\, TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\, TXQPISTRONGPDOWN => '0', TXQPIWEAKPUP => '0', TXRATE(2 downto 0) => B"000", TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\, TXRATEMODE => '0', TXRESETDONE => txresetdone_out(0), TXSEQUENCE(6 downto 0) => txsequence_in(6 downto 0), TXSWING => '0', TXSYNCALLIN => '0', TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68\, TXSYNCIN => '0', TXSYNCMODE => '0', TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\, TXSYSCLKSEL(1 downto 0) => B"00", TXUSERRDY => \gen_gtwizard_gthe3.txuserrdy_int\, TXUSRCLK => txusrclk_in(0), TXUSRCLK2 => txusrclk2_in(0) ); \rst_in_meta_i_1__2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cplllock_out\(0), O => rst_in0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer is port ( gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_sync2_reg_0 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_out_i_1_n_0 : STD_LOGIC; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk2_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => '1', Q => rst_in_meta ); rst_in_out_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rst_in_sync2_reg_0, O => rst_in_out_i_1_n_0 ); rst_in_out_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk2_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync3, Q => gtwiz_reset_rx_done_out(0) ); rst_in_sync1_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk2_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_meta, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk2_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync1, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk2_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync2, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 is port ( gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_sync2_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 : entity is "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal \rst_in_out_i_1__0_n_0\ : STD_LOGIC; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => txusrclk2_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => '1', Q => rst_in_meta ); \rst_in_out_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rst_in_sync2_reg_0, O => \rst_in_out_i_1__0_n_0\ ); rst_in_out_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => txusrclk2_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync3, Q => gtwiz_reset_tx_done_out(0) ); rst_in_sync1_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => txusrclk2_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_meta, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => txusrclk2_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync1, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => txusrclk2_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync2, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer is port ( gtwiz_reset_all_sync : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_rx_pll_and_datapath_in(0), Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_rx_pll_and_datapath_in(0), Q => gtwiz_reset_all_sync ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_rx_pll_and_datapath_in(0), Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_rx_pll_and_datapath_in(0), Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_rx_pll_and_datapath_in(0), Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 is port ( gtwiz_reset_rx_any_sync : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]_0\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]_1\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : in STD_LOGIC; rxprogdivreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; plllock_rx_sync : in STD_LOGIC; gtrxreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; rst_in_out_reg_0 : in STD_LOGIC; gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 is signal gtrxreset_out_i_2_n_0 : STD_LOGIC; signal gtwiz_reset_rx_any : STD_LOGIC; signal \^gtwiz_reset_rx_any_sync\ : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of gtrxreset_out_i_2 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pllreset_rx_out_i_1 : label is "soft_lutpair2"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin gtwiz_reset_rx_any_sync <= \^gtwiz_reset_rx_any_sync\; gtrxreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF44884488" ) port map ( I0 => Q(1), I1 => gtrxreset_out_i_2_n_0, I2 => plllock_rx_sync, I3 => Q(0), I4 => gtrxreset_out_reg, I5 => \gen_gtwizard_gthe3.gtrxreset_int\, O => \FSM_sequential_sm_reset_rx_reg[1]_1\ ); gtrxreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^gtwiz_reset_rx_any_sync\, I1 => Q(2), O => gtrxreset_out_i_2_n_0 ); pllreset_rx_out_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FDFF0100" ) port map ( I0 => Q(1), I1 => Q(2), I2 => \^gtwiz_reset_rx_any_sync\, I3 => Q(0), I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, O => \FSM_sequential_sm_reset_rx_reg[1]\ ); rst_in_meta_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rst_in_out_reg_0, I1 => gtwiz_reset_rx_datapath_in(0), I2 => gtwiz_reset_rx_pll_and_datapath_in(0), I3 => rst_in_out_reg_1, O => gtwiz_reset_rx_any ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_rx_any, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_rx_any, Q => \^gtwiz_reset_rx_any_sync\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_rx_any, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_rx_any, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_rx_any, Q => rst_in_sync3 ); rxprogdivreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFF00120012" ) port map ( I0 => Q(1), I1 => Q(2), I2 => Q(0), I3 => \^gtwiz_reset_rx_any_sync\, I4 => rxprogdivreset_out_reg, I5 => \gen_gtwizard_gthe3.rxprogdivreset_int\, O => \FSM_sequential_sm_reset_rx_reg[1]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 is signal rst_in0_1 : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin \rst_in_meta_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => gtwiz_reset_rx_datapath_in(0), I1 => rst_in_out_reg_0, O => rst_in0_1 ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in0_1, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in0_1, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in0_1, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in0_1, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in0_1, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC; gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 is signal p_0_in_0 : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin \rst_in_meta_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rst_in_out_reg_0, I1 => gtwiz_reset_rx_pll_and_datapath_in(0), O => p_0_in_0 ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => p_0_in_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => p_0_in_0, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => p_0_in_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => p_0_in_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => p_0_in_0, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 is port ( gtwiz_reset_tx_any_sync : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[1]_0\ : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : in STD_LOGIC; plllock_tx_sync : in STD_LOGIC; gttxreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; txuserrdy_out_reg : in STD_LOGIC; gtwiz_reset_userclk_tx_active_sync : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 is signal gttxreset_out_i_2_n_0 : STD_LOGIC; signal \^gtwiz_reset_tx_any_sync\ : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; signal txuserrdy_out_i_2_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of pllreset_tx_out_i_1 : label is "soft_lutpair3"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; attribute SOFT_HLUTNM of txuserrdy_out_i_2 : label is "soft_lutpair3"; begin gtwiz_reset_tx_any_sync <= \^gtwiz_reset_tx_any_sync\; gttxreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF44884488" ) port map ( I0 => Q(1), I1 => gttxreset_out_i_2_n_0, I2 => plllock_tx_sync, I3 => Q(0), I4 => gttxreset_out_reg, I5 => \gen_gtwizard_gthe3.gttxreset_int\, O => \FSM_sequential_sm_reset_tx_reg[1]_0\ ); gttxreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^gtwiz_reset_tx_any_sync\, I1 => Q(2), O => gttxreset_out_i_2_n_0 ); pllreset_tx_out_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FDFF0100" ) port map ( I0 => Q(1), I1 => Q(2), I2 => \^gtwiz_reset_tx_any_sync\, I3 => Q(0), I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, O => \FSM_sequential_sm_reset_tx_reg[1]\ ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in_out_reg_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in_out_reg_0, Q => \^gtwiz_reset_tx_any_sync\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in_out_reg_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in_out_reg_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in_out_reg_0, Q => rst_in_sync3 ); txuserrdy_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"DD55DD5588008C00" ) port map ( I0 => txuserrdy_out_i_2_n_0, I1 => txuserrdy_out_reg, I2 => Q(0), I3 => gtwiz_reset_userclk_tx_active_sync, I4 => \^gtwiz_reset_tx_any_sync\, I5 => \gen_gtwizard_gthe3.txuserrdy_int\, O => \FSM_sequential_sm_reset_tx_reg[0]\ ); txuserrdy_out_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0110" ) port map ( I0 => Q(2), I1 => \^gtwiz_reset_tx_any_sync\, I2 => Q(1), I3 => Q(0), O => txuserrdy_out_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', Q => rst_in_meta, R => '0' ); rst_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, Q => in0, R => '0' ); rst_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, Q => rst_in_sync1, R => '0' ); rst_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, Q => rst_in_sync2, R => '0' ); rst_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, Q => rst_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in_out_reg_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in_out_reg_0, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in_out_reg_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in_out_reg_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in_out_reg_0, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 is port ( \gen_gtwizard_gthe3.txprogdivreset_int\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in0, Q => \gen_gtwizard_gthe3.txprogdivreset_int\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in0, Q => rst_in_sync3 ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block SFoQ2tXDMrL2nCJbfpmHXuteJlKaWDWl3o9OY1miFvmYb8EDywmDpLUHQktJ/VoW+17fK5WHgFVI FZV1B91GDQ== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block mxGWDRjEAsKmBqldxevT1RKZvqK7vn0KlTODVXNGlRcGf9zOAmj0Z7Ppu79POBDb8oNQyCY+2q1q BddzhQfh5WLIVX9BNUMIF6M6IF0elM4GMSLHGeYEwqSaMPC+thuR8FGj1J7z6rH+43gDYhtIeyY+ ZuZUz/Pqg8Lu63Xwe+0= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block HLwPjQzkuqv5FEDBriEJS2DikBeIHB/bWuVWooHY5ChdoHatcmqCHpSvnGxVzLwObZWHFys2nR9y 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DIL655zzSthlULn5OfMTzG5GnQ8Qg6zE2Mt7+4w0rrZRRynMtrxUNLTX924oLTpQSKPvcPZQZUoS 2z76Vz58hXzeIG4m+kHA1uDSzi6FsJ7hw2ci0Hv3Xi1hy1rQgZkE5RLZ5kuB/2FIMRQWtKPI6pGM PJpc1KF15gaH1vpo8FN5c1fi7GDbNNnuwhUcUEBCz4O66ZX2 `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE is port ( CLK : out STD_LOGIC; sync_clk_out : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; mmcm_not_locked_out2 : out STD_LOGIC; bufg_gt_clr_out : in STD_LOGIC; tx_out_clk : in STD_LOGIC; lopt : out STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE is begin ultrascale_tx_userclk_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_tx_userclk port map ( bufg_gt_clr_out => bufg_gt_clr_out, init_clk => CLK, lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, mmcm_not_locked_out => mmcm_not_locked_out, mmcm_not_locked_out2 => mmcm_not_locked_out2, sync_clk_out => sync_clk_out, tx_out_clk => tx_out_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); gen_na_idles_i : out STD_LOGIC; gen_ch_bond_i : out STD_LOGIC; CHANNEL_UP_RX_IF_reg : out STD_LOGIC; channel_up_tx_if : out STD_LOGIC; hard_err : out STD_LOGIC; gen_cc_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_0 : out STD_LOGIC; R0 : out STD_LOGIC; gen_ch_bond_int_reg : out STD_LOGIC; CHANNEL_UP_RX_IF_reg_1 : out STD_LOGIC; reset_lanes_c : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_2 : in STD_LOGIC; wait_for_lane_up_r_reg : in STD_LOGIC; remote_ready_i : in STD_LOGIC; RX_IDLE : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 ); TXDATAVALID_IN : in STD_LOGIC; hard_err_i : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; gen_cc_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); tx_pe_data_v_i : in STD_LOGIC; rx_pe_data_v_i : in STD_LOGIC; \TX_DATA_reg[63]\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC is signal \^channel_up_tx_if\ : STD_LOGIC; signal \^gen_ch_bond_i\ : STD_LOGIC; begin channel_up_tx_if <= \^channel_up_tx_if\; gen_ch_bond_i <= \^gen_ch_bond_i\; channel_bond_gen_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN port map ( TXDATAVALID_IN => TXDATAVALID_IN, data_v_r_reg_0 => CHANNEL_UP_RX_IF_reg_2, \free_count_r_reg[4]_0\(0) => CHANNEL_UP_RX_IF_reg_3(0), gen_ch_bond_int_reg_0 => \^gen_ch_bond_i\, gen_ch_bond_int_reg_1 => \^channel_up_tx_if\ ); channel_err_detect_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT port map ( CHANNEL_HARD_ERR_reg_0 => CHANNEL_UP_RX_IF_reg_2, hard_err => hard_err, hard_err_i => hard_err_i ); channel_init_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM port map ( CHANNEL_UP_RX_IF_reg_0 => CHANNEL_UP_RX_IF_reg, CHANNEL_UP_RX_IF_reg_1 => CHANNEL_UP_RX_IF_reg_0, CHANNEL_UP_RX_IF_reg_2 => CHANNEL_UP_RX_IF_reg_1, CHANNEL_UP_RX_IF_reg_3 => CHANNEL_UP_RX_IF_reg_2, CHANNEL_UP_RX_IF_reg_4(0) => CHANNEL_UP_RX_IF_reg_3(0), CHANNEL_UP_TX_IF_reg_0 => \^channel_up_tx_if\, E(0) => E(0), Q(1 downto 0) => Q(1 downto 0), R0 => R0, RX_IDLE => RX_IDLE, SR(0) => SR(0), \TX_DATA_reg[63]\ => \^gen_ch_bond_i\, \TX_DATA_reg[63]_0\ => \TX_DATA_reg[63]\, gen_cc_flop_0_i(1 downto 0) => gen_cc_flop_0_i(1 downto 0), gen_cc_i => gen_cc_i, gen_ch_bond_int_reg => gen_ch_bond_int_reg, remote_ready_i => remote_ready_i, reset_lanes_c => reset_lanes_c, rst_pma_init_usrclk => rst_pma_init_usrclk, rx_pe_data_v_i => rx_pe_data_v_i, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg_0(0) => gen_na_idles_i, wait_for_lane_up_r_reg_1 => wait_for_lane_up_r_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM is port ( lane_up_flop_i_0 : out STD_LOGIC; rst_r_reg_0 : out STD_LOGIC; enable_err_detect_i : out STD_LOGIC; rx_polarity_r_reg_0 : out STD_LOGIC; in0 : out STD_LOGIC; reset_lanes_c : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; s_level_out_d5_reg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); reset_count_r0 : in STD_LOGIC; ready_r_reg0 : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM is signal align_r : STD_LOGIC; signal align_r_i_2_n_0 : STD_LOGIC; signal begin_r : STD_LOGIC; signal check_polarity_r_i_1_n_0 : STD_LOGIC; signal count_8d_done_r : STD_LOGIC; signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC; signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC; signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC; signal \^in0\ : STD_LOGIC; signal \^lane_up_flop_i_0\ : STD_LOGIC; signal next_align_c : STD_LOGIC; signal next_begin_c : STD_LOGIC; signal \next_begin_c_inferred__1/i__n_0\ : STD_LOGIC; signal next_polarity_c : STD_LOGIC; signal next_ready_c : STD_LOGIC; signal next_rst_c : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); signal polarity_r : STD_LOGIC; signal prev_rx_polarity_r : STD_LOGIC; signal prev_rx_polarity_r_i_1_n_0 : STD_LOGIC; signal ready_r : STD_LOGIC; signal ready_r_i_4_n_0 : STD_LOGIC; signal reset_count_r : STD_LOGIC; signal rst_r_i_2_n_0 : STD_LOGIC; signal \^rst_r_reg_0\ : STD_LOGIC; signal rx_polarity_dlyd_i : STD_LOGIC; signal \^rx_polarity_r_reg_0\ : STD_LOGIC; signal u_cdc_rxlossofsync_in_n_2 : STD_LOGIC; signal NLW_SRLC32E_inst_0_Q31_UNCONNECTED : STD_LOGIC; attribute BOX_TYPE : string; attribute BOX_TYPE of SRLC32E_inst_0 : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of SRLC32E_inst_0 : label is "inst/\aurora_64b66b_0_core_i/aurora_lane_0_i/lane_init_sm_i/SRLC32E_inst_0 "; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of align_r_i_2 : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \counter1_r[0]_i_1\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \counter1_r[1]_i_1\ : label is "soft_lutpair107"; attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR"; attribute SOFT_HLUTNM of \next_begin_c_inferred__1/i_\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of rst_r_i_1 : label is "soft_lutpair106"; attribute SOFT_HLUTNM of rst_r_i_2 : label is "soft_lutpair105"; begin in0 <= \^in0\; lane_up_flop_i_0 <= \^lane_up_flop_i_0\; rst_r_reg_0 <= \^rst_r_reg_0\; rx_polarity_r_reg_0 <= \^rx_polarity_r_reg_0\; ENABLE_ERR_DETECT_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => ready_r, Q => enable_err_detect_i, R => '0' ); SRLC32E_inst_0: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => s_level_out_d5_reg, D => polarity_r, Q => rx_polarity_dlyd_i, Q31 => NLW_SRLC32E_inst_0_Q31_UNCONNECTED ); align_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000C0000000A0A" ) port map ( I0 => align_r_i_2_n_0, I1 => ready_r_i_4_n_0, I2 => ready_r, I3 => rx_lossofsync_i, I4 => polarity_r, I5 => align_r, O => next_align_c ); align_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => begin_r, I1 => \^rst_r_reg_0\, I2 => count_8d_done_r, I3 => reset_lanes_i, O => align_r_i_2_n_0 ); align_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => next_align_c, Q => align_r, R => ready_r_reg0 ); begin_r_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d5_reg, CE => '1', D => next_begin_c, Q => begin_r, S => ready_r_reg0 ); check_polarity_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => polarity_r, I1 => rx_polarity_dlyd_i, I2 => \^in0\, O => check_polarity_r_i_1_n_0 ); check_polarity_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => check_polarity_r_i_1_n_0, Q => \^in0\, R => SR(0) ); \counter1_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \counter1_r_reg_n_0_[1]\, I1 => \counter1_r_reg_n_0_[3]\, I2 => \counter1_r_reg_n_0_[2]\, I3 => count_8d_done_r, O => p_0_in(3) ); \counter1_r[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \counter1_r_reg_n_0_[2]\, I1 => \counter1_r_reg_n_0_[3]\, I2 => \counter1_r_reg_n_0_[1]\, O => p_0_in(2) ); \counter1_r[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \counter1_r_reg_n_0_[3]\, I1 => \counter1_r_reg_n_0_[2]\, O => p_0_in(1) ); \counter1_r[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter1_r_reg_n_0_[3]\, O => p_0_in(0) ); \counter1_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => p_0_in(3), Q => count_8d_done_r, R => reset_count_r ); \counter1_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => p_0_in(2), Q => \counter1_r_reg_n_0_[1]\, R => reset_count_r ); \counter1_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => p_0_in(1), Q => \counter1_r_reg_n_0_[2]\, R => reset_count_r ); \counter1_r_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_level_out_d5_reg, CE => '1', D => p_0_in(0), Q => \counter1_r_reg_n_0_[3]\, S => reset_count_r ); lane_up_flop_i: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => ready_r, Q => \^lane_up_flop_i_0\, R => SR(0) ); \next_begin_c_inferred__1/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => ready_r, I1 => polarity_r, I2 => align_r, I3 => \^rst_r_reg_0\, I4 => begin_r, O => \next_begin_c_inferred__1/i__n_0\ ); polarity_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000C04040000" ) port map ( I0 => rx_polarity_dlyd_i, I1 => ready_r_i_4_n_0, I2 => ready_r, I3 => rx_lossofsync_i, I4 => polarity_r, I5 => align_r, O => next_polarity_c ); polarity_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => next_polarity_c, Q => polarity_r, R => ready_r_reg0 ); prev_rx_polarity_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFEF0020" ) port map ( I0 => \^rx_polarity_r_reg_0\, I1 => polarity_r, I2 => \^rst_r_reg_0\, I3 => rx_polarity_dlyd_i, I4 => prev_rx_polarity_r, O => prev_rx_polarity_r_i_1_n_0 ); prev_rx_polarity_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => prev_rx_polarity_r_i_1_n_0, Q => prev_rx_polarity_r, R => SR(0) ); ready_r_i_4: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => \^rst_r_reg_0\, I1 => reset_lanes_i, I2 => begin_r, O => ready_r_i_4_n_0 ); ready_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => next_ready_c, Q => ready_r, R => ready_r_reg0 ); reset_count_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => reset_count_r0, Q => reset_count_r, R => '0' ); reset_lanes_flop_0_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F1" ) port map ( I0 => \^lane_up_flop_i_0\, I1 => gen_na_idles_i, I2 => SR(0), O => reset_lanes_c ); rst_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"14140414" ) port map ( I0 => rst_r_i_2_n_0, I1 => begin_r, I2 => \^rst_r_reg_0\, I3 => count_8d_done_r, I4 => reset_lanes_i, O => next_rst_c ); rst_r_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => align_r, I1 => ready_r, I2 => polarity_r, O => rst_r_i_2_n_0 ); rst_r_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => next_rst_c, Q => \^rst_r_reg_0\, R => ready_r_reg0 ); rx_polarity_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => u_cdc_rxlossofsync_in_n_2, Q => \^rx_polarity_r_reg_0\, R => '0' ); u_cdc_rxlossofsync_in: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync port map ( SR(0) => SR(0), SYSTEM_RESET_reg => u_cdc_rxlossofsync_in_n_2, align_r => align_r, begin_r_reg => \next_begin_c_inferred__1/i__n_0\, next_begin_c => next_begin_c, next_ready_c => next_ready_c, polarity_r => polarity_r, prev_rx_polarity_r => prev_rx_polarity_r, ready_r => ready_r, ready_r_reg => ready_r_i_4_n_0, reset_lanes_i => reset_lanes_i, rx_lossofsync_i => rx_lossofsync_i, rx_polarity_dlyd_i => rx_polarity_dlyd_i, rx_polarity_r_reg => \^rx_polarity_r_reg_0\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg, s_level_out_d5_reg_0 => s_level_out_d5_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); ready_r_reg0 : out STD_LOGIC; reset_count_r0 : out STD_LOGIC; SYSTEM_RESET_reg_0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; link_reset_out : in STD_LOGIC; power_down : in STD_LOGIC; sysreset_from_support : in STD_LOGIC; stg4_reg : in STD_LOGIC; hard_err_i : in STD_LOGIC; tx_reset_i : in STD_LOGIC; wait_for_lane_up_r_reg : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC is signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal SYSTEM_RESET0_n_0 : STD_LOGIC; signal fsm_resetdone_sync : STD_LOGIC; signal link_reset_sync : STD_LOGIC; signal power_down_sync : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of ready_r_i_1 : label is "soft_lutpair116"; attribute SOFT_HLUTNM of wait_for_lane_up_r_i_1 : label is "soft_lutpair116"; begin SR(0) <= \^sr\(0); SYSTEM_RESET0: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => link_reset_sync, I1 => sysreset_from_support, I2 => fsm_resetdone_sync, I3 => power_down_sync, O => SYSTEM_RESET0_n_0 ); SYSTEM_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg, CE => '1', D => SYSTEM_RESET0_n_0, Q => \^sr\(0), R => '0' ); ready_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^sr\(0), I1 => hard_err_i, O => ready_r_reg0 ); reset_count_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^sr\(0), I1 => tx_reset_i, O => reset_count_r0 ); u_link_rst_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 port map ( link_reset_out => link_reset_out, link_reset_sync => link_reset_sync, stg5_reg_0 => stg4_reg ); u_pd_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 port map ( power_down => power_down, power_down_sync => power_down_sync, stg4_reg_0 => stg4_reg ); u_rst_done_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 port map ( fsm_resetdone_sync => fsm_resetdone_sync, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg, stg4_reg_0 => stg4_reg ); wait_for_lane_up_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^sr\(0), I1 => wait_for_lane_up_r_reg, O => SYSTEM_RESET_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM is port ( m_axi_rx_tvalid : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); RX_SRC_RDY_N_reg_inv : in STD_LOGIC; RX_SRC_RDY_N_reg_inv_0 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 63 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM is begin rx_stream_datapath_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH port map ( D(63 downto 0) => D(63 downto 0), E(0) => E(0), RX_SRC_RDY_N_reg_inv_0 => RX_SRC_RDY_N_reg_inv, RX_SRC_RDY_N_reg_inv_1 => RX_SRC_RDY_N_reg_inv_0, SR(0) => SR(0), m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC is port ( sysreset_from_support : out STD_LOGIC; gt_reset_out : out STD_LOGIC; CLK : in STD_LOGIC; init_clk : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); \debounce_gt_rst_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC is signal SYSTEM_RESET0_n_0 : STD_LOGIC; signal debounce_gt_rst_r : STD_LOGIC_VECTOR ( 0 to 3 ); attribute async_reg : string; attribute async_reg of debounce_gt_rst_r : signal is "true"; attribute shift_extract : string; attribute shift_extract of debounce_gt_rst_r : signal is "{no}"; signal \dly_gt_rst_r_reg[17]_srl18_n_0\ : STD_LOGIC; signal gt_rst_r : STD_LOGIC; signal gt_rst_r0_n_0 : STD_LOGIC; signal reset_debounce_r : STD_LOGIC_VECTOR ( 0 to 3 ); signal u_rst_sync_gt_n_0 : STD_LOGIC; signal \NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \debounce_gt_rst_r_reg[0]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[0]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[1]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[1]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[1]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[2]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[2]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[2]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[3]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[3]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[3]\ : label is "{no}"; attribute srl_bus_name : string; attribute srl_bus_name of \dly_gt_rst_r_reg[17]_srl18\ : label is "inst/\support_reset_logic_i/dly_gt_rst_r_reg "; attribute srl_name : string; attribute srl_name of \dly_gt_rst_r_reg[17]_srl18\ : label is "inst/\support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18 "; begin SYSTEM_RESET0: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => reset_debounce_r(2), I1 => reset_debounce_r(3), I2 => reset_debounce_r(0), I3 => reset_debounce_r(1), O => SYSTEM_RESET0_n_0 ); SYSTEM_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => CLK, CE => '1', D => SYSTEM_RESET0_n_0, Q => sysreset_from_support, R => '0' ); \debounce_gt_rst_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => \debounce_gt_rst_r_reg[0]_0\(0), Q => debounce_gt_rst_r(0), R => '0' ); \debounce_gt_rst_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => debounce_gt_rst_r(0), Q => debounce_gt_rst_r(1), R => '0' ); \debounce_gt_rst_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => debounce_gt_rst_r(1), Q => debounce_gt_rst_r(2), R => '0' ); \debounce_gt_rst_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => debounce_gt_rst_r(2), Q => debounce_gt_rst_r(3), R => '0' ); \dly_gt_rst_r_reg[17]_srl18\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"10001", CE => '1', CLK => init_clk, D => gt_rst_r, Q => \dly_gt_rst_r_reg[17]_srl18_n_0\, Q31 => \NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED\ ); \dly_gt_rst_r_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => \dly_gt_rst_r_reg[17]_srl18_n_0\, Q => gt_reset_out, R => '0' ); gt_rst_r0: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => debounce_gt_rst_r(2), I1 => debounce_gt_rst_r(3), I2 => debounce_gt_rst_r(0), I3 => debounce_gt_rst_r(1), O => gt_rst_r0_n_0 ); gt_rst_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => gt_rst_r0_n_0, Q => gt_rst_r, R => '0' ); \reset_debounce_r_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => CLK, CE => '1', D => D(0), Q => reset_debounce_r(0), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => CLK, CE => '1', D => reset_debounce_r(0), Q => reset_debounce_r(1), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => CLK, CE => '1', D => reset_debounce_r(1), Q => reset_debounce_r(2), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => CLK, CE => '1', D => reset_debounce_r(2), Q => reset_debounce_r(3), S => u_rst_sync_gt_n_0 ); u_rst_sync_gt: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 port map ( CLK => CLK, SS(0) => u_rst_sync_gt_n_0, in0 => gt_rst_r ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN is port ( stg5_reg : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); tempData : out STD_LOGIC_VECTOR ( 5 downto 0 ); \TX_DATA_reg[63]_0\ : out STD_LOGIC_VECTOR ( 57 downto 0 ); stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; stg5_reg_0 : in STD_LOGIC; txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 59 downto 0 ); scrambler : in STD_LOGIC_VECTOR ( 11 downto 0 ); \TX_DATA_reg[59]_0\ : in STD_LOGIC; \TX_DATA_reg[55]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \TX_DATA_reg[63]_1\ : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; gen_cc_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN is signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \TX_DATA[62]_i_1_n_0\ : STD_LOGIC; signal \^tx_data_reg[63]_0\ : STD_LOGIC_VECTOR ( 57 downto 0 ); signal \^stg5_reg\ : STD_LOGIC; signal tx_data_i : STD_LOGIC_VECTOR ( 58 to 63 ); signal u_pma_init_data_sync_n_1 : STD_LOGIC; signal u_pma_init_data_sync_n_2 : STD_LOGIC; signal u_pma_init_data_sync_n_3 : STD_LOGIC; signal u_pma_init_data_sync_n_4 : STD_LOGIC; signal u_pma_init_data_sync_n_5 : STD_LOGIC; signal u_pma_init_data_sync_n_6 : STD_LOGIC; begin D(1 downto 0) <= \^d\(1 downto 0); \TX_DATA_reg[63]_0\(57 downto 0) <= \^tx_data_reg[63]_0\(57 downto 0); stg5_reg <= \^stg5_reg\; \TX_DATA[62]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"5555545500000000" ) port map ( I0 => \^stg5_reg\, I1 => gen_ch_bond_i, I2 => gen_cc_i, I3 => tx_pe_data_v_i, I4 => gen_na_idles_i, I5 => \TX_DATA_reg[59]_0\, O => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(52), Q => tx_data_i(63), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(46), Q => \^tx_data_reg[63]_0\(4), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(47), Q => \^tx_data_reg[63]_0\(5), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(48), Q => \^tx_data_reg[63]_0\(6), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(49), Q => \^tx_data_reg[63]_0\(7), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(50), Q => \^tx_data_reg[63]_0\(8), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(51), Q => \^tx_data_reg[63]_0\(9), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(36), Q => \^tx_data_reg[63]_0\(10), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(37), Q => \^tx_data_reg[63]_0\(11), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(38), Q => \^tx_data_reg[63]_0\(12), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(39), Q => \^tx_data_reg[63]_0\(13), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(53), Q => tx_data_i(62), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(40), Q => \^tx_data_reg[63]_0\(14), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(41), Q => \^tx_data_reg[63]_0\(15), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(42), Q => \^tx_data_reg[63]_0\(16), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(43), Q => \^tx_data_reg[63]_0\(17), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(28), Q => \^tx_data_reg[63]_0\(18), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(29), Q => \^tx_data_reg[63]_0\(19), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(30), Q => \^tx_data_reg[63]_0\(20), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(31), Q => \^tx_data_reg[63]_0\(21), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(32), Q => \^tx_data_reg[63]_0\(22), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(33), Q => \^tx_data_reg[63]_0\(23), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(54), Q => tx_data_i(61), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(34), Q => \^tx_data_reg[63]_0\(24), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(35), Q => \^tx_data_reg[63]_0\(25), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(20), Q => \^tx_data_reg[63]_0\(26), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(21), Q => \^tx_data_reg[63]_0\(27), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(22), Q => \^tx_data_reg[63]_0\(28), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(23), Q => \^tx_data_reg[63]_0\(29), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(24), Q => \^tx_data_reg[63]_0\(30), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(25), Q => \^tx_data_reg[63]_0\(31), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(26), Q => \^tx_data_reg[63]_0\(32), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(27), Q => \^tx_data_reg[63]_0\(33), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(55), Q => tx_data_i(60), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(12), Q => \^tx_data_reg[63]_0\(34), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(13), Q => \^tx_data_reg[63]_0\(35), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(14), Q => \^tx_data_reg[63]_0\(36), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(15), Q => \^tx_data_reg[63]_0\(37), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(16), Q => \^tx_data_reg[63]_0\(38), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(17), Q => \^tx_data_reg[63]_0\(39), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[46]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(18), Q => \^tx_data_reg[63]_0\(40), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(19), Q => \^tx_data_reg[63]_0\(41), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(8), Q => \^tx_data_reg[63]_0\(42), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(9), Q => \^tx_data_reg[63]_0\(43), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(56), Q => tx_data_i(59), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(10), Q => \^tx_data_reg[63]_0\(44), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(11), Q => \^tx_data_reg[63]_0\(45), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(0), Q => \^tx_data_reg[63]_0\(46), R => '0' ); \TX_DATA_reg[53]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(1), Q => \^tx_data_reg[63]_0\(47), R => '0' ); \TX_DATA_reg[54]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(2), Q => \^tx_data_reg[63]_0\(48), R => '0' ); \TX_DATA_reg[55]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(3), Q => \^tx_data_reg[63]_0\(49), R => '0' ); \TX_DATA_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(0), Q => \^tx_data_reg[63]_0\(50), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(1), Q => \^tx_data_reg[63]_0\(51), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[58]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(2), Q => \^tx_data_reg[63]_0\(52), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[59]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_3, Q => \^tx_data_reg[63]_0\(53), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(57), Q => tx_data_i(58), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[60]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_4, Q => \^tx_data_reg[63]_0\(54), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[61]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_5, Q => \^tx_data_reg[63]_0\(55), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[62]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_6, Q => \^tx_data_reg[63]_0\(56), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[63]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(7), Q => \^tx_data_reg[63]_0\(57), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(58), Q => \^tx_data_reg[63]_0\(0), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(59), Q => \^tx_data_reg[63]_0\(1), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(44), Q => \^tx_data_reg[63]_0\(2), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \TX_DATA_reg[59]_0\, D => Q(45), Q => \^tx_data_reg[63]_0\(3), R => \TX_DATA_reg[63]_1\ ); TX_HEADER_0_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => u_pma_init_data_sync_n_2, Q => \^d\(0), R => '0' ); TX_HEADER_1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => u_pma_init_data_sync_n_1, Q => \^d\(1), R => '0' ); \scrambler[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(33), I1 => scrambler(0), I2 => tx_data_i(63), I3 => \^tx_data_reg[63]_0\(52), I4 => scrambler(6), O => tempData(0) ); \scrambler[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(34), I1 => scrambler(1), I2 => tx_data_i(62), I3 => \^tx_data_reg[63]_0\(53), I4 => scrambler(7), O => tempData(1) ); \scrambler[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(35), I1 => scrambler(2), I2 => tx_data_i(61), I3 => \^tx_data_reg[63]_0\(54), I4 => scrambler(8), O => tempData(2) ); \scrambler[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(36), I1 => scrambler(3), I2 => tx_data_i(60), I3 => \^tx_data_reg[63]_0\(55), I4 => scrambler(9), O => tempData(3) ); \scrambler[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(37), I1 => scrambler(4), I2 => tx_data_i(59), I3 => \^tx_data_reg[63]_0\(56), I4 => scrambler(10), O => tempData(4) ); \scrambler[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(38), I1 => scrambler(5), I2 => tx_data_i(58), I3 => \^tx_data_reg[63]_0\(57), I4 => scrambler(11), O => tempData(5) ); u_pma_init_data_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 port map ( D(1 downto 0) => \^d\(1 downto 0), Q(3 downto 0) => Q(6 downto 3), TX_HEADER_1_reg => u_pma_init_data_sync_n_1, TX_HEADER_1_reg_0 => TX_HEADER_1_reg_0, channel_up_tx_if => channel_up_tx_if, gen_na_idles_i => gen_na_idles_i, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg_0 => \^stg5_reg\, stg5_reg_1 => u_pma_init_data_sync_n_2, stg5_reg_2 => u_pma_init_data_sync_n_3, stg5_reg_3 => u_pma_init_data_sync_n_4, stg5_reg_4 => u_pma_init_data_sync_n_5, stg5_reg_5 => u_pma_init_data_sync_n_6, stg5_reg_6 => stg5_reg_0, tx_pe_data_v_i => tx_pe_data_v_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM is port ( gen_cc_i : out STD_LOGIC; do_cc_r : out STD_LOGIC; tx_pe_data_v_i : out STD_LOGIC; extend_cc_r : out STD_LOGIC; wait_for_lane_up_r_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); gen_cc_flop_0_i : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 61 downto 0 ); s_axi_tx_tready : out STD_LOGIC; R0 : in STD_LOGIC; TX_PE_DATA_V_reg : in STD_LOGIC; tx_dst_rdy_n_r0 : in STD_LOGIC; do_cc_r_reg0 : in STD_LOGIC; extend_cc_r_reg : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM is signal \^gen_cc_flop_0_i\ : STD_LOGIC; signal tx_stream_control_sm_i_n_5 : STD_LOGIC; begin gen_cc_flop_0_i <= \^gen_cc_flop_0_i\; tx_stream_control_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM port map ( R0 => R0, do_cc_r => do_cc_r, do_cc_r_reg0 => do_cc_r_reg0, do_cc_r_reg_0 => TX_PE_DATA_V_reg, extend_cc_r => extend_cc_r, extend_cc_r_reg_0 => extend_cc_r_reg, gen_cc_flop_0_i_0 => \^gen_cc_flop_0_i\, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, s_axi_tx_tvalid_0 => tx_stream_control_sm_i_n_5, tx_dst_rdy_n_r0 => tx_dst_rdy_n_r0 ); tx_stream_datapath_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH port map ( Q(61 downto 0) => Q(61 downto 0), \TX_DATA_reg[53]\ => \^gen_cc_flop_0_i\, TX_PE_DATA_V_reg_0 => tx_stream_control_sm_i_n_5, TX_PE_DATA_V_reg_1 => TX_PE_DATA_V_reg, channel_up_tx_if => channel_up_tx_if, gen_na_idles_i => gen_na_idles_i, rst_pma_init_usrclk => rst_pma_init_usrclk, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg(1 downto 0) => wait_for_lane_up_r_reg(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc is port ( stg5_reg : out STD_LOGIC; srst : out STD_LOGIC; stg9_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); cbcc_reset_cbstg2_rd_clk : out STD_LOGIC; cbcc_fifo_reset_rd_clk : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); stg5_reg_0 : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; cb_bit_err_out : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc is signal cb_bit_err_ext_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cb_bit_err_ext_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[3]_i_1_n_0\ : STD_LOGIC; signal cbc_rd_if_reset : STD_LOGIC; signal cbc_rd_if_reset_i_1_n_0 : STD_LOGIC; signal cbc_wr_if_reset : STD_LOGIC; signal cbc_wr_if_reset_i_1_n_0 : STD_LOGIC; signal cbcc_data_srst0 : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_rd_clk : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_rd_clk_dlyd : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_wr_clk_dlyd : STD_LOGIC; signal \^cbcc_reset_cbstg2_rd_clk\ : STD_LOGIC; signal dbg_extend_srst0 : STD_LOGIC; signal dbg_extend_srst_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); signal dbg_srst_assert : STD_LOGIC; signal dbg_srst_assert0 : STD_LOGIC; signal fifo_reset_comb : STD_LOGIC; signal fifo_reset_comb_read_clk : STD_LOGIC; signal fifo_reset_comb_user_clk : STD_LOGIC; signal fifo_reset_comb_user_clk_int : STD_LOGIC; signal fifo_reset_comb_user_clk_int_22q : STD_LOGIC; signal fifo_reset_rd : STD_LOGIC; signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal rd_stg1 : STD_LOGIC; signal reset_cbcc_comb : STD_LOGIC; signal \^stg9_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal u_cdc_chan_bond_reset_n_0 : STD_LOGIC; signal u_rst_sync_reset_rd_clk_n_0 : STD_LOGIC; signal u_rst_sync_reset_wr_clk_n_0 : STD_LOGIC; signal u_rst_sync_rst_cbcc_rd_clk_n_0 : STD_LOGIC; signal u_rst_sync_rst_cbcc_rd_clk_n_1 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[0]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[1]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[2]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[3]_i_1\ : label is "soft_lutpair53"; attribute shift_extract : string; attribute shift_extract of cbc_rd_if_reset_reg : label is "{no}"; attribute shift_extract of cbc_wr_if_reset_reg : label is "{no}"; attribute shift_extract of cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg : label is "{no}"; attribute shift_extract of cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg : label is "{no}"; attribute shift_extract of cbcc_reset_cbstg2_rd_clk_reg : label is "{no}"; attribute SOFT_HLUTNM of \dbg_extend_srst[0]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \dbg_extend_srst[1]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \dbg_extend_srst[2]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \dbg_extend_srst[3]_i_2\ : label is "soft_lutpair55"; attribute shift_extract of rd_stg1_reg : label is "{no}"; attribute shift_extract of reset_cbcc_comb_reg : label is "{no}"; begin cbcc_reset_cbstg2_rd_clk <= \^cbcc_reset_cbstg2_rd_clk\; stg9_reg(0) <= \^stg9_reg\(0); \cb_bit_err_ext_cnt[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF5554" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(2), I2 => cb_bit_err_ext_cnt(3), I3 => cb_bit_err_ext_cnt(1), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[0]_i_1_n_0\ ); \cb_bit_err_ext_cnt[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF9998" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(1), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[1]_i_1_n_0\ ); \cb_bit_err_ext_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFE1E0" ) port map ( I0 => cb_bit_err_ext_cnt(1), I1 => cb_bit_err_ext_cnt(0), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[2]_i_1_n_0\ ); \cb_bit_err_ext_cnt[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFE00" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(1), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[3]_i_1_n_0\ ); \cb_bit_err_ext_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \cb_bit_err_ext_cnt[0]_i_1_n_0\, Q => cb_bit_err_ext_cnt(0), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \cb_bit_err_ext_cnt[1]_i_1_n_0\, Q => cb_bit_err_ext_cnt(1), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \cb_bit_err_ext_cnt[2]_i_1_n_0\, Q => cb_bit_err_ext_cnt(2), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \cb_bit_err_ext_cnt[3]_i_1_n_0\, Q => cb_bit_err_ext_cnt(3), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); cbc_rd_if_reset_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFD0" ) port map ( I0 => cbcc_fifo_reset_to_fifo_rd_clk_dlyd, I1 => cbcc_fifo_reset_to_fifo_rd_clk, I2 => cbc_rd_if_reset, I3 => fifo_reset_comb_read_clk, O => cbc_rd_if_reset_i_1_n_0 ); cbc_rd_if_reset_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => cbc_rd_if_reset_i_1_n_0, Q => cbc_rd_if_reset, R => '0' ); cbc_wr_if_reset_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFD0" ) port map ( I0 => cbcc_fifo_reset_to_fifo_wr_clk_dlyd, I1 => \^stg9_reg\(0), I2 => cbc_wr_if_reset, I3 => fifo_reset_comb_user_clk, O => cbc_wr_if_reset_i_1_n_0 ); cbc_wr_if_reset_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => cbc_wr_if_reset_i_1_n_0, Q => cbc_wr_if_reset, R => '0' ); cbcc_data_srst_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"BBBBBFFF" ) port map ( I0 => dbg_srst_assert, I1 => dbg_extend_srst_reg(3), I2 => dbg_extend_srst_reg(0), I3 => dbg_extend_srst_reg(1), I4 => dbg_extend_srst_reg(2), O => cbcc_data_srst0 ); cbcc_data_srst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => cbcc_data_srst0, Q => srst, R => '0' ); cbcc_fifo_reset_rd_clk_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => u_rst_sync_reset_rd_clk_n_0, Q => cbcc_fifo_reset_rd_clk, R => '0' ); cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => cbcc_fifo_reset_to_fifo_rd_clk, Q => cbcc_fifo_reset_to_fifo_rd_clk_dlyd, R => '0' ); cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \^stg9_reg\(0), Q => cbcc_fifo_reset_to_fifo_wr_clk_dlyd, R => '0' ); cbcc_fifo_reset_wr_clk_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => u_rst_sync_reset_wr_clk_n_0, Q => SR(0), R => '0' ); cbcc_reset_cbstg2_rd_clk_reg: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => '1', D => u_rst_sync_rst_cbcc_rd_clk_n_1, Q => \^cbcc_reset_cbstg2_rd_clk\, R => '0' ); \dbg_extend_srst[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => dbg_extend_srst_reg(0), O => \p_0_in__5\(0) ); \dbg_extend_srst[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => dbg_extend_srst_reg(0), I1 => dbg_extend_srst_reg(1), O => \p_0_in__5\(1) ); \dbg_extend_srst[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => dbg_extend_srst_reg(2), I1 => dbg_extend_srst_reg(0), I2 => dbg_extend_srst_reg(1), O => \p_0_in__5\(2) ); \dbg_extend_srst[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"15FF" ) port map ( I0 => dbg_extend_srst_reg(2), I1 => dbg_extend_srst_reg(1), I2 => dbg_extend_srst_reg(0), I3 => dbg_extend_srst_reg(3), O => dbg_extend_srst0 ); \dbg_extend_srst[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => dbg_extend_srst_reg(1), I1 => dbg_extend_srst_reg(0), I2 => dbg_extend_srst_reg(2), I3 => dbg_extend_srst_reg(3), O => \p_0_in__5\(3) ); \dbg_extend_srst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => dbg_extend_srst0, D => \p_0_in__5\(0), Q => dbg_extend_srst_reg(0), R => dbg_srst_assert ); \dbg_extend_srst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => dbg_extend_srst0, D => \p_0_in__5\(1), Q => dbg_extend_srst_reg(1), R => dbg_srst_assert ); \dbg_extend_srst_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => dbg_extend_srst0, D => \p_0_in__5\(2), Q => dbg_extend_srst_reg(2), R => dbg_srst_assert ); \dbg_extend_srst_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => dbg_extend_srst0, D => \p_0_in__5\(3), Q => dbg_extend_srst_reg(3), R => dbg_srst_assert ); dbg_srst_assert_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => dbg_srst_assert0, Q => dbg_srst_assert, R => '0' ); fifo_reset_comb_user_clk_int_22q_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => fifo_reset_comb_user_clk_int, Q => fifo_reset_comb_user_clk_int_22q, R => '0' ); fifo_reset_rd_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => '0', Q => fifo_reset_rd, S => \^cbcc_reset_cbstg2_rd_clk\ ); rd_stg1_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => u_rst_sync_rst_cbcc_rd_clk_n_0, Q => rd_stg1, R => '0' ); reset_cbcc_comb_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => u_cdc_chan_bond_reset_n_0, Q => reset_cbcc_comb, R => '0' ); u_cdc_chan_bond_reset: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_20\ port map ( Q(3 downto 0) => cb_bit_err_ext_cnt(3 downto 0), \cb_bit_err_ext_cnt_reg[3]\ => u_cdc_chan_bond_reset_n_0, gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, reset_cbcc_comb_reg(0) => stg1_aurora_64b66b_0_cdc_to_reg(0) ); u_rst_sync_cbcc_fifo_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ port map ( in0 => fifo_reset_comb_user_clk, stg5_reg_0 => fifo_reset_comb_read_clk, stg5_reg_1 => stg5_reg_0 ); u_rst_sync_cbcc_only_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_22\ port map ( stg1_aurora_64b66b_0_cdc_to_reg_0(0) => stg1_aurora_64b66b_0_cdc_to_reg(0), stg3_reg_0 => stg5_reg_0, stg5_reg_0 => stg5_reg ); u_rst_sync_fifo_reset_comb_user_clk_in: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ port map ( dbg_srst_assert0 => dbg_srst_assert0, dbg_srst_assert_reg => fifo_reset_comb_user_clk_int_22q, fifo_reset_comb_user_clk_int => fifo_reset_comb_user_clk_int, gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, in0 => fifo_reset_comb_user_clk ); u_rst_sync_fifo_reset_user_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ port map ( gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, in0 => fifo_reset_comb, stg11_reg_0 => fifo_reset_comb_user_clk ); u_rst_sync_r_sync3: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ port map ( gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, in0 => fifo_reset_rd, stg1_aurora_64b66b_0_cdc_to_reg_0 => reset_cbcc_comb, stg5_reg_0 => fifo_reset_comb ); u_rst_sync_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_24\ port map ( in0 => cbc_rd_if_reset, stg3_reg_0 => u_rst_sync_reset_rd_clk_n_0, stg3_reg_1 => stg5_reg_0 ); u_rst_sync_reset_to_fifo_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized5\ port map ( cbcc_fifo_reset_to_fifo_rd_clk => cbcc_fifo_reset_to_fifo_rd_clk, stg1_aurora_64b66b_0_cdc_to_reg_0 => fifo_reset_comb_read_clk, stg31_reg_0 => stg5_reg_0 ); u_rst_sync_reset_to_fifo_wr_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized4\ port map ( gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, stg1_aurora_64b66b_0_cdc_to_reg_0 => fifo_reset_comb_user_clk_int_22q, stg9_reg_0(0) => \^stg9_reg\(0) ); u_rst_sync_reset_wr_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ port map ( gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out, in0 => cbc_wr_if_reset, stg3_reg_0 => u_rst_sync_reset_wr_clk_n_0 ); u_rst_sync_rst_cbcc_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_26\ port map ( rd_stg1 => rd_stg1, rd_stg1_reg => u_rst_sync_rst_cbcc_rd_clk_n_1, stg1_aurora_64b66b_0_cdc_to_reg_0 => reset_cbcc_comb, stg5_reg_0 => u_rst_sync_rst_cbcc_rd_clk_n_0, stg5_reg_1 => stg5_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gthe3_channel_wrapper is port ( cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rst_in0 : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.txprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC; txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txheader_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC; lopt_5 : in STD_LOGIC; lopt_6 : out STD_LOGIC; lopt_7 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gthe3_channel_wrapper; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gthe3_channel_wrapper is begin channel_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel port map ( cplllock_out(0) => cplllock_out(0), drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpclk_in(0) => drpclk_in(0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in(0) => drpen_in(0), drprdy_out(0) => drprdy_out(0), drpwe_in(0) => drpwe_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => gtpowergood_out(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_userdata_rx_out(31 downto 0) => gtwiz_userdata_rx_out(31 downto 0), gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0), loopback_in(2 downto 0) => loopback_in(2 downto 0), lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, lopt_4 => lopt_4, lopt_5 => lopt_5, lopt_6 => lopt_6, lopt_7 => lopt_7, rst_in0 => rst_in0, rxbufstatus_out(0) => rxbufstatus_out(0), rxcdrlock_out(0) => rxcdrlock_out(0), rxcdrovrden_in(0) => rxcdrovrden_in(0), rxdatavalid_out(0) => rxdatavalid_out(0), rxgearboxslip_in(0) => rxgearboxslip_in(0), rxheader_out(1 downto 0) => rxheader_out(1 downto 0), rxheadervalid_out(0) => rxheadervalid_out(0), rxoutclk_out(0) => rxoutclk_out(0), rxpmaresetdone_out(0) => rxpmaresetdone_out(0), rxpolarity_in(0) => rxpolarity_in(0), rxresetdone_out(0) => rxresetdone_out(0), rxusrclk2_in(0) => rxusrclk2_in(0), rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => txbufstatus_out(0), txheader_in(1 downto 0) => txheader_in(1 downto 0), txoutclk_out(0) => txoutclk_out(0), txpmaresetdone_out(0) => txpmaresetdone_out(0), txresetdone_out(0) => txresetdone_out(0), txsequence_in(6 downto 0) => txsequence_in(6 downto 0), txusrclk2_in(0) => txusrclk2_in(0), txusrclk_in(0) => txusrclk_in(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset is port ( \gen_gtwizard_gthe3.txprogdivreset_int\ : out STD_LOGIC; gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gttxreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.rxprogdivreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.gtrxreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : out STD_LOGIC; gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in0 : in STD_LOGIC; txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset is signal \FSM_sequential_sm_reset_all[2]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_all[2]_i_4_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_rx[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_rx[2]_i_6_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_tx[2]_i_3_n_0\ : STD_LOGIC; signal bit_synchronizer_gtpowergood_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2 : STD_LOGIC; signal bit_synchronizer_plllock_rx_inst_n_1 : STD_LOGIC; signal bit_synchronizer_plllock_rx_inst_n_2 : STD_LOGIC; signal bit_synchronizer_plllock_tx_inst_n_1 : STD_LOGIC; signal bit_synchronizer_plllock_tx_inst_n_2 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_0 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_1 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_2 : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.gtrxreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.gttxreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.rxprogdivreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.rxuserrdy_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.txuserrdy_int\ : STD_LOGIC; signal gttxreset_out_i_3_n_0 : STD_LOGIC; signal gtwiz_reset_all_sync : STD_LOGIC; signal gtwiz_reset_rx_any_sync : STD_LOGIC; signal gtwiz_reset_rx_datapath_dly : STD_LOGIC; signal gtwiz_reset_rx_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_rx_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_datapath_sync : STD_LOGIC; signal gtwiz_reset_rx_done_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_sync : STD_LOGIC; signal gtwiz_reset_tx_any_sync : STD_LOGIC; signal gtwiz_reset_tx_datapath_sync : STD_LOGIC; signal gtwiz_reset_tx_done_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_dly : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_sync : STD_LOGIC; signal gtwiz_reset_userclk_tx_active_sync : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 ); signal plllock_rx_sync : STD_LOGIC; signal plllock_tx_sync : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_1 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_2 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_3 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_1 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_2 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_3 : STD_LOGIC; signal sel : STD_LOGIC; signal sm_reset_all : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_all__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_all_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_all_timer_clr_i_2_n_0 : STD_LOGIC; signal sm_reset_all_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_all_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_all_timer_ctr0_n_0 : STD_LOGIC; signal \sm_reset_all_timer_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_all_timer_ctr[1]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_all_timer_ctr[2]_i_1_n_0\ : STD_LOGIC; signal sm_reset_all_timer_sat : STD_LOGIC; signal sm_reset_all_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_rx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_rx_cdr_to_clr : STD_LOGIC; signal sm_reset_rx_cdr_to_clr_i_3_n_0 : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ : STD_LOGIC; signal sm_reset_rx_cdr_to_ctr_reg : STD_LOGIC_VECTOR ( 25 downto 0 ); signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\ : STD_LOGIC; signal sm_reset_rx_cdr_to_sat : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_4_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_5_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_6_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_clr_reg_n_0 : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC; signal sm_reset_rx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); signal sm_reset_rx_pll_timer_sat : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_rx_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_rx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_rx_timer_ctr0_n_0 : STD_LOGIC; signal \sm_reset_rx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC; signal sm_reset_rx_timer_sat : STD_LOGIC; signal sm_reset_rx_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_tx_pll_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_clr_reg_n_0 : STD_LOGIC; signal \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC; signal sm_reset_tx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); signal sm_reset_tx_pll_timer_sat : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_tx_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_tx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_tx_timer_sat : STD_LOGIC; signal sm_reset_tx_timer_sat_i_1_n_0 : STD_LOGIC; signal txuserrdy_out_i_3_n_0 : STD_LOGIC; signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[1]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_2\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_3\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_4\ : label is "soft_lutpair16"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[0]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[1]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[2]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[1]_i_2\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[2]_i_6\ : label is "soft_lutpair4"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[0]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[1]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[2]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_2\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_3\ : label is "soft_lutpair7"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[0]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[1]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[2]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute SOFT_HLUTNM of gttxreset_out_i_3 : label is "soft_lutpair10"; attribute SOFT_HLUTNM of gtwiz_reset_rx_datapath_int_i_1 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of gtwiz_reset_tx_pll_and_datapath_int_i_1 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[1]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[2]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_3 : label is "soft_lutpair4"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\ : label is 16; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of sm_reset_rx_pll_timer_sat_i_2 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[1]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[2]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of sm_reset_rx_timer_sat_i_1 : label is "soft_lutpair11"; attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_clr_i_1 : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_sat_i_2 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[1]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[2]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of sm_reset_tx_timer_sat_i_1 : label is "soft_lutpair10"; attribute SOFT_HLUTNM of txuserrdy_out_i_3 : label is "soft_lutpair12"; begin \gen_gtwizard_gthe3.gtrxreset_int\ <= \^gen_gtwizard_gthe3.gtrxreset_int\; \gen_gtwizard_gthe3.gttxreset_int\ <= \^gen_gtwizard_gthe3.gttxreset_int\; \gen_gtwizard_gthe3.rxprogdivreset_int\ <= \^gen_gtwizard_gthe3.rxprogdivreset_int\; \gen_gtwizard_gthe3.rxuserrdy_int\ <= \^gen_gtwizard_gthe3.rxuserrdy_int\; \gen_gtwizard_gthe3.txuserrdy_int\ <= \^gen_gtwizard_gthe3.txuserrdy_int\; \FSM_sequential_sm_reset_all[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00FFF70000FFFFFF" ) port map ( I0 => gtwiz_reset_rx_done_int_reg_n_0, I1 => sm_reset_all_timer_sat, I2 => sm_reset_all_timer_clr_reg_n_0, I3 => sm_reset_all(2), I4 => sm_reset_all(1), I5 => sm_reset_all(0), O => \sm_reset_all__0\(0) ); \FSM_sequential_sm_reset_all[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"34" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(1), I2 => sm_reset_all(0), O => \sm_reset_all__0\(1) ); \FSM_sequential_sm_reset_all[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"4A" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(0), I2 => sm_reset_all(1), O => \sm_reset_all__0\(2) ); \FSM_sequential_sm_reset_all[2]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => sm_reset_all_timer_sat, I1 => gtwiz_reset_rx_done_int_reg_n_0, I2 => sm_reset_all_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_all[2]_i_3_n_0\ ); \FSM_sequential_sm_reset_all[2]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_all_timer_clr_reg_n_0, I1 => sm_reset_all_timer_sat, I2 => gtwiz_reset_tx_done_int_reg_n_0, O => \FSM_sequential_sm_reset_all[2]_i_4_n_0\ ); \FSM_sequential_sm_reset_all_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(0), Q => sm_reset_all(0), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_all_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(1), Q => sm_reset_all(1), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_all_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(2), Q => sm_reset_all(2), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_rx[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => sm_reset_rx_timer_sat, I1 => sm_reset_rx_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\ ); \FSM_sequential_sm_reset_rx[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"DDFD8888DDDD8888" ) port map ( I0 => sm_reset_rx(1), I1 => sm_reset_rx(0), I2 => sm_reset_rx_timer_sat, I3 => sm_reset_rx_timer_clr_reg_n_0, I4 => sm_reset_rx(2), I5 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, O => \sm_reset_rx__0\(2) ); \FSM_sequential_sm_reset_rx[2]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"00004000" ) port map ( I0 => sm_reset_rx(0), I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I2 => sm_reset_rx(1), I3 => sm_reset_rx_timer_sat, I4 => sm_reset_rx_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_rx[2]_i_6_n_0\ ); \FSM_sequential_sm_reset_rx_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(0), Q => sm_reset_rx(0), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_rx_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(1), Q => sm_reset_rx(1), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_rx_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(2), Q => sm_reset_rx(2), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_tx[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"38" ) port map ( I0 => sm_reset_tx(0), I1 => sm_reset_tx(1), I2 => sm_reset_tx(2), O => \sm_reset_tx__0\(2) ); \FSM_sequential_sm_reset_tx[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), O => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\ ); \FSM_sequential_sm_reset_tx_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(0), Q => sm_reset_tx(0), R => gtwiz_reset_tx_any_sync ); \FSM_sequential_sm_reset_tx_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(1), Q => sm_reset_tx(1), R => gtwiz_reset_tx_any_sync ); \FSM_sequential_sm_reset_tx_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(2), Q => sm_reset_tx(2), R => gtwiz_reset_tx_any_sync ); bit_synchronizer_gtpowergood_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 port map ( E(0) => bit_synchronizer_gtpowergood_inst_n_0, \FSM_sequential_sm_reset_all_reg[0]\ => \FSM_sequential_sm_reset_all[2]_i_3_n_0\, \FSM_sequential_sm_reset_all_reg[0]_0\ => \FSM_sequential_sm_reset_all[2]_i_4_n_0\, Q(2 downto 0) => sm_reset_all(2 downto 0), drpclk_in(0) => drpclk_in(0), gtpowergood_out(0) => gtpowergood_out(0) ); bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_rx_datapath_dly => gtwiz_reset_rx_datapath_dly, in0 => gtwiz_reset_rx_datapath_sync ); bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 port map ( D(1 downto 0) => \sm_reset_rx__0\(1 downto 0), \FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, \FSM_sequential_sm_reset_rx_reg[0]_0\ => \FSM_sequential_sm_reset_rx[2]_i_6_n_0\, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, gtwiz_reset_rx_datapath_dly => gtwiz_reset_rx_datapath_dly, i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2, in0 => gtwiz_reset_rx_pll_and_datapath_sync ); bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 port map ( E(0) => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, \FSM_sequential_sm_reset_tx_reg[0]\ => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\, \FSM_sequential_sm_reset_tx_reg[0]_0\ => bit_synchronizer_plllock_tx_inst_n_2, \FSM_sequential_sm_reset_tx_reg[0]_1\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2, Q(0) => sm_reset_tx(0), drpclk_in(0) => drpclk_in(0), gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly, in0 => gtwiz_reset_tx_datapath_sync ); bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 port map ( D(1 downto 0) => \sm_reset_tx__0\(1 downto 0), Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly, in0 => gtwiz_reset_tx_pll_and_datapath_sync ); bit_synchronizer_gtwiz_reset_userclk_rx_active_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 port map ( E(0) => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0, \FSM_sequential_sm_reset_rx_reg[0]_0\ => bit_synchronizer_rxcdrlock_inst_n_1, \FSM_sequential_sm_reset_rx_reg[0]_1\ => bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2, \FSM_sequential_sm_reset_rx_reg[0]_2\ => sm_reset_rx_pll_timer_clr_reg_n_0, \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.rxuserrdy_int\ => \^gen_gtwizard_gthe3.rxuserrdy_int\, gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync, gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0), sm_reset_rx_pll_timer_sat => sm_reset_rx_pll_timer_sat, sm_reset_rx_timer_clr_reg => bit_synchronizer_plllock_rx_inst_n_2, sm_reset_rx_timer_clr_reg_0 => sm_reset_rx_timer_clr_reg_n_0, sm_reset_rx_timer_sat => sm_reset_rx_timer_sat ); bit_synchronizer_gtwiz_reset_userclk_tx_active_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => txuserrdy_out_i_3_n_0, \FSM_sequential_sm_reset_tx_reg[0]_0\ => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\, \FSM_sequential_sm_reset_tx_reg[0]_1\ => sm_reset_tx_pll_timer_clr_reg_n_0, \FSM_sequential_sm_reset_tx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1, Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, gtwiz_reset_userclk_tx_active_sync => gtwiz_reset_userclk_tx_active_sync, gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2, plllock_tx_sync => plllock_tx_sync, sm_reset_tx_pll_timer_sat => sm_reset_tx_pll_timer_sat, sm_reset_tx_timer_clr_reg => sm_reset_tx_timer_clr_reg_n_0, sm_reset_tx_timer_clr_reg_0 => gttxreset_out_i_3_n_0 ); bit_synchronizer_plllock_rx_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 port map ( \FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_plllock_rx_inst_n_2, Q(2 downto 0) => sm_reset_rx(2 downto 0), cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, gtwiz_reset_rx_done_int_reg => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, gtwiz_reset_rx_done_int_reg_0 => gtwiz_reset_rx_done_int_reg_n_0, i_in_out_reg_0 => bit_synchronizer_plllock_rx_inst_n_1, plllock_rx_sync => plllock_rx_sync ); bit_synchronizer_plllock_tx_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => gttxreset_out_i_3_n_0, Q(2 downto 0) => sm_reset_tx(2 downto 0), cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, gtwiz_reset_tx_done_int_reg => bit_synchronizer_plllock_tx_inst_n_1, gtwiz_reset_tx_done_int_reg_0 => gtwiz_reset_tx_done_int_reg_n_0, gtwiz_reset_tx_done_int_reg_1 => sm_reset_tx_timer_clr_reg_n_0, i_in_out_reg_0 => bit_synchronizer_plllock_tx_inst_n_2, plllock_tx_sync => plllock_tx_sync, sm_reset_tx_timer_sat => sm_reset_tx_timer_sat ); bit_synchronizer_rxcdrlock_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 port map ( \FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, \FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_rxcdrlock_inst_n_1, \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_rxcdrlock_inst_n_0, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), plllock_rx_sync => plllock_rx_sync, rxcdrlock_out(0) => rxcdrlock_out(0), sm_reset_rx_cdr_to_clr => sm_reset_rx_cdr_to_clr, sm_reset_rx_cdr_to_clr_reg => sm_reset_rx_cdr_to_clr_i_3_n_0, sm_reset_rx_cdr_to_sat => sm_reset_rx_cdr_to_sat, sm_reset_rx_cdr_to_sat_reg => bit_synchronizer_rxcdrlock_inst_n_2 ); \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, O => \gen_gtwizard_gthe3.cpllpd_ch_int\ ); gtrxreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3, Q => \^gen_gtwizard_gthe3.gtrxreset_int\, R => '0' ); gttxreset_out_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => sm_reset_tx_timer_sat, I1 => sm_reset_tx_timer_clr_reg_n_0, O => gttxreset_out_i_3_n_0 ); gttxreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2, Q => \^gen_gtwizard_gthe3.gttxreset_int\, R => '0' ); gtwiz_reset_rx_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F740" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(0), I2 => sm_reset_all(1), I3 => gtwiz_reset_rx_datapath_int_reg_n_0, O => gtwiz_reset_rx_datapath_int_i_1_n_0 ); gtwiz_reset_rx_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_rx_datapath_int_i_1_n_0, Q => gtwiz_reset_rx_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); gtwiz_reset_rx_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_plllock_rx_inst_n_1, Q => gtwiz_reset_rx_done_int_reg_n_0, R => gtwiz_reset_rx_any_sync ); gtwiz_reset_rx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F704" ) port map ( I0 => sm_reset_all(0), I1 => sm_reset_all(2), I2 => sm_reset_all(1), I3 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, O => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 ); gtwiz_reset_rx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0, Q => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); gtwiz_reset_tx_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_plllock_tx_inst_n_1, Q => gtwiz_reset_tx_done_int_reg_n_0, R => gtwiz_reset_tx_any_sync ); gtwiz_reset_tx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FB02" ) port map ( I0 => sm_reset_all(0), I1 => sm_reset_all(1), I2 => sm_reset_all(2), I3 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, O => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 ); gtwiz_reset_tx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0, Q => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); pllreset_rx_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, R => '0' ); pllreset_tx_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, R => '0' ); reset_synchronizer_gtwiz_reset_all_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_all_sync => gtwiz_reset_all_sync, gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0) ); reset_synchronizer_gtwiz_reset_rx_any_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 port map ( \FSM_sequential_sm_reset_rx_reg[1]\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1, \FSM_sequential_sm_reset_rx_reg[1]_0\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2, \FSM_sequential_sm_reset_rx_reg[1]_1\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \^gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \^gen_gtwizard_gthe3.rxprogdivreset_int\, gtrxreset_out_reg => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync, gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0), plllock_rx_sync => plllock_rx_sync, rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0, rst_in_out_reg_1 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, rxprogdivreset_out_reg => bit_synchronizer_rxcdrlock_inst_n_2 ); reset_synchronizer_gtwiz_reset_rx_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), in0 => gtwiz_reset_rx_datapath_sync, rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0 ); reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0), in0 => gtwiz_reset_rx_pll_and_datapath_sync, rst_in_out_reg_0 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 ); reset_synchronizer_gtwiz_reset_tx_any_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_3, \FSM_sequential_sm_reset_tx_reg[1]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1, \FSM_sequential_sm_reset_tx_reg[1]_0\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2, Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \^gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \^gen_gtwizard_gthe3.txuserrdy_int\, gttxreset_out_reg => gttxreset_out_i_3_n_0, gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync, gtwiz_reset_userclk_tx_active_sync => gtwiz_reset_userclk_tx_active_sync, plllock_tx_sync => plllock_tx_sync, rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, txuserrdy_out_reg => txuserrdy_out_i_3_n_0 ); reset_synchronizer_gtwiz_reset_tx_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 port map ( drpclk_in(0) => drpclk_in(0), in0 => gtwiz_reset_tx_datapath_sync ); reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 port map ( drpclk_in(0) => drpclk_in(0), in0 => gtwiz_reset_tx_pll_and_datapath_sync, rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 ); reset_synchronizer_rx_done_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer port map ( gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), rst_in_sync2_reg_0 => gtwiz_reset_rx_done_int_reg_n_0, rxusrclk2_in(0) => rxusrclk2_in(0) ); reset_synchronizer_tx_done_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 port map ( gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), rst_in_sync2_reg_0 => gtwiz_reset_tx_done_int_reg_n_0, txusrclk2_in(0) => txusrclk2_in(0) ); reset_synchronizer_txprogdivreset_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, rst_in0 => rst_in0 ); rxprogdivreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2, Q => \^gen_gtwizard_gthe3.rxprogdivreset_int\, R => '0' ); rxuserrdy_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1, Q => \^gen_gtwizard_gthe3.rxuserrdy_int\, R => '0' ); sm_reset_all_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EFFA200A" ) port map ( I0 => sm_reset_all_timer_clr_i_2_n_0, I1 => sm_reset_all(1), I2 => sm_reset_all(2), I3 => sm_reset_all(0), I4 => sm_reset_all_timer_clr_reg_n_0, O => sm_reset_all_timer_clr_i_1_n_0 ); sm_reset_all_timer_clr_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000B0003333BB33" ) port map ( I0 => gtwiz_reset_rx_done_int_reg_n_0, I1 => sm_reset_all(2), I2 => gtwiz_reset_tx_done_int_reg_n_0, I3 => sm_reset_all_timer_sat, I4 => sm_reset_all_timer_clr_reg_n_0, I5 => sm_reset_all(1), O => sm_reset_all_timer_clr_i_2_n_0 ); sm_reset_all_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_all_timer_clr_i_1_n_0, Q => sm_reset_all_timer_clr_reg_n_0, S => gtwiz_reset_all_sync ); sm_reset_all_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_all_timer_ctr(2), I1 => sm_reset_all_timer_ctr(0), I2 => sm_reset_all_timer_ctr(1), O => sm_reset_all_timer_ctr0_n_0 ); \sm_reset_all_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_all_timer_ctr(0), O => \sm_reset_all_timer_ctr[0]_i_1_n_0\ ); \sm_reset_all_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_all_timer_ctr(0), I1 => sm_reset_all_timer_ctr(1), O => \sm_reset_all_timer_ctr[1]_i_1_n_0\ ); \sm_reset_all_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_all_timer_ctr(0), I1 => sm_reset_all_timer_ctr(1), I2 => sm_reset_all_timer_ctr(2), O => \sm_reset_all_timer_ctr[2]_i_1_n_0\ ); \sm_reset_all_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[0]_i_1_n_0\, Q => sm_reset_all_timer_ctr(0), R => sm_reset_all_timer_clr_reg_n_0 ); \sm_reset_all_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[1]_i_1_n_0\, Q => sm_reset_all_timer_ctr(1), R => sm_reset_all_timer_clr_reg_n_0 ); \sm_reset_all_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[2]_i_1_n_0\, Q => sm_reset_all_timer_ctr(2), R => sm_reset_all_timer_clr_reg_n_0 ); sm_reset_all_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_all_timer_ctr(2), I1 => sm_reset_all_timer_ctr(0), I2 => sm_reset_all_timer_ctr(1), I3 => sm_reset_all_timer_sat, I4 => sm_reset_all_timer_clr_reg_n_0, O => sm_reset_all_timer_sat_i_1_n_0 ); sm_reset_all_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_all_timer_sat_i_1_n_0, Q => sm_reset_all_timer_sat, R => '0' ); sm_reset_rx_cdr_to_clr_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_rx_timer_clr_reg_n_0, I1 => sm_reset_rx_timer_sat, I2 => sm_reset_rx(1), O => sm_reset_rx_cdr_to_clr_i_3_n_0 ); sm_reset_rx_cdr_to_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_rxcdrlock_inst_n_0, Q => sm_reset_rx_cdr_to_clr, S => gtwiz_reset_rx_any_sync ); \sm_reset_rx_cdr_to_ctr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(0), I1 => sm_reset_rx_cdr_to_ctr_reg(1), I2 => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\, I3 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\, I4 => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\, I5 => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\, O => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFDFFFFFFFFF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(18), I1 => sm_reset_rx_cdr_to_ctr_reg(19), I2 => sm_reset_rx_cdr_to_ctr_reg(16), I3 => sm_reset_rx_cdr_to_ctr_reg(17), I4 => sm_reset_rx_cdr_to_ctr_reg(14), I5 => sm_reset_rx_cdr_to_ctr_reg(15), O => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(24), I1 => sm_reset_rx_cdr_to_ctr_reg(25), I2 => sm_reset_rx_cdr_to_ctr_reg(22), I3 => sm_reset_rx_cdr_to_ctr_reg(23), I4 => sm_reset_rx_cdr_to_ctr_reg(21), I5 => sm_reset_rx_cdr_to_ctr_reg(20), O => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFDFFFFFFFFF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(13), I1 => sm_reset_rx_cdr_to_ctr_reg(12), I2 => sm_reset_rx_cdr_to_ctr_reg(10), I3 => sm_reset_rx_cdr_to_ctr_reg(11), I4 => sm_reset_rx_cdr_to_ctr_reg(9), I5 => sm_reset_rx_cdr_to_ctr_reg(8), O => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFDF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(6), I1 => sm_reset_rx_cdr_to_ctr_reg(7), I2 => sm_reset_rx_cdr_to_ctr_reg(4), I3 => sm_reset_rx_cdr_to_ctr_reg(5), I4 => sm_reset_rx_cdr_to_ctr_reg(3), I5 => sm_reset_rx_cdr_to_ctr_reg(2), O => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(0), O => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ ); \sm_reset_rx_cdr_to_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(0), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\, DI(7 downto 0) => B"00000001", O(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\, S(7 downto 1) => sm_reset_rx_cdr_to_ctr_reg(7 downto 1), S(0) => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ ); \sm_reset_rx_cdr_to_ctr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(10), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(11), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(12), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(13), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(14), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(15), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(16), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\, CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\, S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(23 downto 16) ); \sm_reset_rx_cdr_to_ctr_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(17), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(18), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(19), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(1), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(20), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(21), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(22), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(23), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(24), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\(7 downto 1), CO(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7 downto 2) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\(7 downto 2), O(1) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\, S(7 downto 2) => B"000000", S(1 downto 0) => sm_reset_rx_cdr_to_ctr_reg(25 downto 24) ); \sm_reset_rx_cdr_to_ctr_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(25), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(2), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(3), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(4), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(5), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(6), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(7), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(8), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\, CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\, S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(15 downto 8) ); \sm_reset_rx_cdr_to_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(9), R => sm_reset_rx_cdr_to_clr ); sm_reset_rx_cdr_to_sat_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"0E" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => sm_reset_rx_cdr_to_sat_i_2_n_0, I2 => sm_reset_rx_cdr_to_clr, O => sm_reset_rx_cdr_to_sat_i_1_n_0 ); sm_reset_rx_cdr_to_sat_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000008000" ) port map ( I0 => sm_reset_rx_cdr_to_sat_i_3_n_0, I1 => sm_reset_rx_cdr_to_sat_i_4_n_0, I2 => sm_reset_rx_cdr_to_sat_i_5_n_0, I3 => sm_reset_rx_cdr_to_sat_i_6_n_0, I4 => sm_reset_rx_cdr_to_ctr_reg(0), I5 => sm_reset_rx_cdr_to_ctr_reg(1), O => sm_reset_rx_cdr_to_sat_i_2_n_0 ); sm_reset_rx_cdr_to_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000200000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(4), I1 => sm_reset_rx_cdr_to_ctr_reg(5), I2 => sm_reset_rx_cdr_to_ctr_reg(2), I3 => sm_reset_rx_cdr_to_ctr_reg(3), I4 => sm_reset_rx_cdr_to_ctr_reg(7), I5 => sm_reset_rx_cdr_to_ctr_reg(6), O => sm_reset_rx_cdr_to_sat_i_3_n_0 ); sm_reset_rx_cdr_to_sat_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(22), I1 => sm_reset_rx_cdr_to_ctr_reg(23), I2 => sm_reset_rx_cdr_to_ctr_reg(20), I3 => sm_reset_rx_cdr_to_ctr_reg(21), I4 => sm_reset_rx_cdr_to_ctr_reg(25), I5 => sm_reset_rx_cdr_to_ctr_reg(24), O => sm_reset_rx_cdr_to_sat_i_4_n_0 ); sm_reset_rx_cdr_to_sat_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(16), I1 => sm_reset_rx_cdr_to_ctr_reg(17), I2 => sm_reset_rx_cdr_to_ctr_reg(15), I3 => sm_reset_rx_cdr_to_ctr_reg(14), I4 => sm_reset_rx_cdr_to_ctr_reg(19), I5 => sm_reset_rx_cdr_to_ctr_reg(18), O => sm_reset_rx_cdr_to_sat_i_5_n_0 ); sm_reset_rx_cdr_to_sat_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(10), I1 => sm_reset_rx_cdr_to_ctr_reg(11), I2 => sm_reset_rx_cdr_to_ctr_reg(8), I3 => sm_reset_rx_cdr_to_ctr_reg(9), I4 => sm_reset_rx_cdr_to_ctr_reg(12), I5 => sm_reset_rx_cdr_to_ctr_reg(13), O => sm_reset_rx_cdr_to_sat_i_6_n_0 ); sm_reset_rx_cdr_to_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_cdr_to_sat_i_1_n_0, Q => sm_reset_rx_cdr_to_sat, R => '0' ); sm_reset_rx_pll_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFF3000B" ) port map ( I0 => sm_reset_rx_pll_timer_sat, I1 => sm_reset_rx(0), I2 => sm_reset_rx(1), I3 => sm_reset_rx(2), I4 => sm_reset_rx_pll_timer_clr_reg_n_0, O => sm_reset_rx_pll_timer_clr_i_1_n_0 ); sm_reset_rx_pll_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_pll_timer_clr_i_1_n_0, Q => sm_reset_rx_pll_timer_clr_reg_n_0, S => gtwiz_reset_rx_any_sync ); \sm_reset_rx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(0), O => \p_0_in__1\(0) ); \sm_reset_rx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(1), I1 => sm_reset_rx_pll_timer_ctr_reg(0), O => \p_0_in__1\(1) ); \sm_reset_rx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(1), I1 => sm_reset_rx_pll_timer_ctr_reg(0), I2 => sm_reset_rx_pll_timer_ctr_reg(2), O => \p_0_in__1\(2) ); \sm_reset_rx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(2), I1 => sm_reset_rx_pll_timer_ctr_reg(0), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(3), O => \p_0_in__1\(3) ); \sm_reset_rx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(1), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(2), I4 => sm_reset_rx_pll_timer_ctr_reg(4), O => \p_0_in__1\(4) ); \sm_reset_rx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(4), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(1), I4 => sm_reset_rx_pll_timer_ctr_reg(3), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \p_0_in__1\(5) ); \sm_reset_rx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I1 => sm_reset_rx_pll_timer_ctr_reg(6), O => \p_0_in__1\(6) ); \sm_reset_rx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(6), I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_rx_pll_timer_ctr_reg(7), O => \p_0_in__1\(7) ); \sm_reset_rx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(7), I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_rx_pll_timer_ctr_reg(6), I3 => sm_reset_rx_pll_timer_ctr_reg(8), O => \p_0_in__1\(8) ); \sm_reset_rx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFBF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(0), I4 => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\, O => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ ); \sm_reset_rx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(8), I1 => sm_reset_rx_pll_timer_ctr_reg(6), I2 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I3 => sm_reset_rx_pll_timer_ctr_reg(7), I4 => sm_reset_rx_pll_timer_ctr_reg(9), O => \p_0_in__1\(9) ); \sm_reset_rx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEFFFFFFFFF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(8), I1 => sm_reset_rx_pll_timer_ctr_reg(9), I2 => sm_reset_rx_pll_timer_ctr_reg(6), I3 => sm_reset_rx_pll_timer_ctr_reg(7), I4 => sm_reset_rx_pll_timer_ctr_reg(4), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ ); \sm_reset_rx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(4), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(1), I4 => sm_reset_rx_pll_timer_ctr_reg(3), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ ); \sm_reset_rx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(0), Q => sm_reset_rx_pll_timer_ctr_reg(0), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(1), Q => sm_reset_rx_pll_timer_ctr_reg(1), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(2), Q => sm_reset_rx_pll_timer_ctr_reg(2), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(3), Q => sm_reset_rx_pll_timer_ctr_reg(3), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(4), Q => sm_reset_rx_pll_timer_ctr_reg(4), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(5), Q => sm_reset_rx_pll_timer_ctr_reg(5), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(6), Q => sm_reset_rx_pll_timer_ctr_reg(6), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(7), Q => sm_reset_rx_pll_timer_ctr_reg(7), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(8), Q => sm_reset_rx_pll_timer_ctr_reg(8), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(9), Q => sm_reset_rx_pll_timer_ctr_reg(9), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); sm_reset_rx_pll_timer_sat_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00EA" ) port map ( I0 => sm_reset_rx_pll_timer_sat, I1 => sm_reset_rx_pll_timer_sat_i_2_n_0, I2 => sm_reset_rx_pll_timer_sat_i_3_n_0, I3 => sm_reset_rx_pll_timer_clr_reg_n_0, O => sm_reset_rx_pll_timer_sat_i_1_n_0 ); sm_reset_rx_pll_timer_sat_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(0), O => sm_reset_rx_pll_timer_sat_i_2_n_0 ); sm_reset_rx_pll_timer_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(6), I1 => sm_reset_rx_pll_timer_ctr_reg(7), I2 => sm_reset_rx_pll_timer_ctr_reg(5), I3 => sm_reset_rx_pll_timer_ctr_reg(4), I4 => sm_reset_rx_pll_timer_ctr_reg(9), I5 => sm_reset_rx_pll_timer_ctr_reg(8), O => sm_reset_rx_pll_timer_sat_i_3_n_0 ); sm_reset_rx_pll_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_pll_timer_sat_i_1_n_0, Q => sm_reset_rx_pll_timer_sat, R => '0' ); sm_reset_rx_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0, Q => sm_reset_rx_timer_clr_reg_n_0, S => gtwiz_reset_rx_any_sync ); sm_reset_rx_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_rx_timer_ctr(2), I1 => sm_reset_rx_timer_ctr(0), I2 => sm_reset_rx_timer_ctr(1), O => sm_reset_rx_timer_ctr0_n_0 ); \sm_reset_rx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_timer_ctr(0), O => \sm_reset_rx_timer_ctr[0]_i_1_n_0\ ); \sm_reset_rx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_rx_timer_ctr(0), I1 => sm_reset_rx_timer_ctr(1), O => \sm_reset_rx_timer_ctr[1]_i_1_n_0\ ); \sm_reset_rx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_rx_timer_ctr(0), I1 => sm_reset_rx_timer_ctr(1), I2 => sm_reset_rx_timer_ctr(2), O => \sm_reset_rx_timer_ctr[2]_i_1_n_0\ ); \sm_reset_rx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[0]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(0), R => sm_reset_rx_timer_clr_reg_n_0 ); \sm_reset_rx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[1]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(1), R => sm_reset_rx_timer_clr_reg_n_0 ); \sm_reset_rx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[2]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(2), R => sm_reset_rx_timer_clr_reg_n_0 ); sm_reset_rx_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_rx_timer_ctr(2), I1 => sm_reset_rx_timer_ctr(0), I2 => sm_reset_rx_timer_ctr(1), I3 => sm_reset_rx_timer_sat, I4 => sm_reset_rx_timer_clr_reg_n_0, O => sm_reset_rx_timer_sat_i_1_n_0 ); sm_reset_rx_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_timer_sat_i_1_n_0, Q => sm_reset_rx_timer_sat, R => '0' ); sm_reset_tx_pll_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EFEF1101" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), I2 => sm_reset_tx(0), I3 => sm_reset_tx_pll_timer_sat, I4 => sm_reset_tx_pll_timer_clr_reg_n_0, O => sm_reset_tx_pll_timer_clr_i_1_n_0 ); sm_reset_tx_pll_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_pll_timer_clr_i_1_n_0, Q => sm_reset_tx_pll_timer_clr_reg_n_0, S => gtwiz_reset_tx_any_sync ); \sm_reset_tx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(0), O => \p_0_in__0\(0) ); \sm_reset_tx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(1), I1 => sm_reset_tx_pll_timer_ctr_reg(0), O => \p_0_in__0\(1) ); \sm_reset_tx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(1), I1 => sm_reset_tx_pll_timer_ctr_reg(0), I2 => sm_reset_tx_pll_timer_ctr_reg(2), O => \p_0_in__0\(2) ); \sm_reset_tx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(2), I1 => sm_reset_tx_pll_timer_ctr_reg(0), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(3), O => \p_0_in__0\(3) ); \sm_reset_tx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(1), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(2), I4 => sm_reset_tx_pll_timer_ctr_reg(4), O => \p_0_in__0\(4) ); \sm_reset_tx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(4), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(1), I4 => sm_reset_tx_pll_timer_ctr_reg(3), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \p_0_in__0\(5) ); \sm_reset_tx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I1 => sm_reset_tx_pll_timer_ctr_reg(6), O => \p_0_in__0\(6) ); \sm_reset_tx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(6), I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_tx_pll_timer_ctr_reg(7), O => \p_0_in__0\(7) ); \sm_reset_tx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(7), I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_tx_pll_timer_ctr_reg(6), I3 => sm_reset_tx_pll_timer_ctr_reg(8), O => \p_0_in__0\(8) ); \sm_reset_tx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFBF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(0), I4 => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\, O => sel ); \sm_reset_tx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(8), I1 => sm_reset_tx_pll_timer_ctr_reg(6), I2 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I3 => sm_reset_tx_pll_timer_ctr_reg(7), I4 => sm_reset_tx_pll_timer_ctr_reg(9), O => \p_0_in__0\(9) ); \sm_reset_tx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEFFFFFFFFF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(8), I1 => sm_reset_tx_pll_timer_ctr_reg(9), I2 => sm_reset_tx_pll_timer_ctr_reg(6), I3 => sm_reset_tx_pll_timer_ctr_reg(7), I4 => sm_reset_tx_pll_timer_ctr_reg(4), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ ); \sm_reset_tx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(4), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(1), I4 => sm_reset_tx_pll_timer_ctr_reg(3), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ ); \sm_reset_tx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(0), Q => sm_reset_tx_pll_timer_ctr_reg(0), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(1), Q => sm_reset_tx_pll_timer_ctr_reg(1), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(2), Q => sm_reset_tx_pll_timer_ctr_reg(2), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(3), Q => sm_reset_tx_pll_timer_ctr_reg(3), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(4), Q => sm_reset_tx_pll_timer_ctr_reg(4), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(5), Q => sm_reset_tx_pll_timer_ctr_reg(5), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(6), Q => sm_reset_tx_pll_timer_ctr_reg(6), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(7), Q => sm_reset_tx_pll_timer_ctr_reg(7), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(8), Q => sm_reset_tx_pll_timer_ctr_reg(8), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(9), Q => sm_reset_tx_pll_timer_ctr_reg(9), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); sm_reset_tx_pll_timer_sat_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00EA" ) port map ( I0 => sm_reset_tx_pll_timer_sat, I1 => sm_reset_tx_pll_timer_sat_i_2_n_0, I2 => sm_reset_tx_pll_timer_sat_i_3_n_0, I3 => sm_reset_tx_pll_timer_clr_reg_n_0, O => sm_reset_tx_pll_timer_sat_i_1_n_0 ); sm_reset_tx_pll_timer_sat_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(0), O => sm_reset_tx_pll_timer_sat_i_2_n_0 ); sm_reset_tx_pll_timer_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(6), I1 => sm_reset_tx_pll_timer_ctr_reg(7), I2 => sm_reset_tx_pll_timer_ctr_reg(5), I3 => sm_reset_tx_pll_timer_ctr_reg(4), I4 => sm_reset_tx_pll_timer_ctr_reg(9), I5 => sm_reset_tx_pll_timer_ctr_reg(8), O => sm_reset_tx_pll_timer_sat_i_3_n_0 ); sm_reset_tx_pll_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_pll_timer_sat_i_1_n_0, Q => sm_reset_tx_pll_timer_sat, R => '0' ); sm_reset_tx_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1, Q => sm_reset_tx_timer_clr_reg_n_0, S => gtwiz_reset_tx_any_sync ); sm_reset_tx_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_tx_timer_ctr(2), I1 => sm_reset_tx_timer_ctr(0), I2 => sm_reset_tx_timer_ctr(1), O => p_0_in ); \sm_reset_tx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_tx_timer_ctr(0), O => p_1_in(0) ); \sm_reset_tx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_tx_timer_ctr(0), I1 => sm_reset_tx_timer_ctr(1), O => p_1_in(1) ); \sm_reset_tx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_tx_timer_ctr(0), I1 => sm_reset_tx_timer_ctr(1), I2 => sm_reset_tx_timer_ctr(2), O => p_1_in(2) ); \sm_reset_tx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(0), Q => sm_reset_tx_timer_ctr(0), R => sm_reset_tx_timer_clr_reg_n_0 ); \sm_reset_tx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(1), Q => sm_reset_tx_timer_ctr(1), R => sm_reset_tx_timer_clr_reg_n_0 ); \sm_reset_tx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(2), Q => sm_reset_tx_timer_ctr(2), R => sm_reset_tx_timer_clr_reg_n_0 ); sm_reset_tx_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_tx_timer_ctr(2), I1 => sm_reset_tx_timer_ctr(0), I2 => sm_reset_tx_timer_ctr(1), I3 => sm_reset_tx_timer_sat, I4 => sm_reset_tx_timer_clr_reg_n_0, O => sm_reset_tx_timer_sat_i_1_n_0 ); sm_reset_tx_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_timer_sat_i_1_n_0, Q => sm_reset_tx_timer_sat, R => '0' ); txuserrdy_out_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), I2 => sm_reset_tx_timer_clr_reg_n_0, I3 => sm_reset_tx_timer_sat, O => txuserrdy_out_i_3_n_0 ); txuserrdy_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_3, Q => \^gen_gtwizard_gthe3.txuserrdy_int\, R => '0' ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = 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decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE is port ( lane_up_flop_i : out STD_LOGIC; tx_reset_i : out STD_LOGIC; enable_err_detect_i : out STD_LOGIC; rst_pma_init_usrclk : out STD_LOGIC; rx_pe_data_v_i : out STD_LOGIC; illegal_btf_i : out STD_LOGIC; RX_IDLE : out STD_LOGIC; rx_polarity_r_reg : out STD_LOGIC; in0 : out STD_LOGIC; hard_err_i : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); remote_ready_i : out STD_LOGIC; SOFT_ERR_reg : out STD_LOGIC; reset_lanes_c : out STD_LOGIC; tempData : out STD_LOGIC_VECTOR ( 5 downto 0 ); \TX_DATA_reg[63]\ : out STD_LOGIC_VECTOR ( 57 downto 0 ); \RX_PE_DATA_reg[0]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; stg5_reg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; reset_count_r0 : in STD_LOGIC; ready_r_reg0 : in STD_LOGIC; rxdatavalid_i : in STD_LOGIC; SOFT_ERR_reg_0 : in STD_LOGIC; \RX_DATA_REG_reg[0]\ : in STD_LOGIC; dout : in STD_LOGIC_VECTOR ( 65 downto 0 ); HARD_ERR_reg : in STD_LOGIC; txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 59 downto 0 ); scrambler : in STD_LOGIC_VECTOR ( 11 downto 0 ); \TX_DATA_reg[59]\ : in STD_LOGIC; \TX_DATA_reg[55]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \TX_DATA_reg[63]_0\ : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; gen_cc_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE is signal \^lane_up_flop_i\ : STD_LOGIC; begin lane_up_flop_i <= \^lane_up_flop_i\; err_detect_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT port map ( HARD_ERR_reg_0 => stg5_reg, HARD_ERR_reg_1 => HARD_ERR_reg, SOFT_ERR_reg_0 => SOFT_ERR_reg, SOFT_ERR_reg_1 => SOFT_ERR_reg_0, channel_up_tx_if => channel_up_tx_if, hard_err_i => hard_err_i ); lane_init_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM port map ( SR(0) => SR(0), enable_err_detect_i => enable_err_detect_i, gen_na_idles_i => gen_na_idles_i, in0 => in0, lane_up_flop_i_0 => \^lane_up_flop_i\, ready_r_reg0 => ready_r_reg0, reset_count_r0 => reset_count_r0, reset_lanes_c => reset_lanes_c, reset_lanes_i => reset_lanes_i, rst_r_reg_0 => tx_reset_i, rx_lossofsync_i => rx_lossofsync_i, rx_polarity_r_reg_0 => rx_polarity_r_reg, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => s_level_out_d1_aurora_64b66b_0_cdc_to_reg, s_level_out_d5_reg => stg5_reg ); sym_dec_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC port map ( \RX_DATA_REG_reg[0]_0\ => stg5_reg, \RX_DATA_REG_reg[0]_1\ => \RX_DATA_REG_reg[0]\, RX_IDLE => RX_IDLE, \RX_PE_DATA_reg[0]_0\(63 downto 0) => \RX_PE_DATA_reg[0]\(63 downto 0), SR(0) => SR(0), dout(65 downto 0) => dout(65 downto 0), illegal_btf_i => illegal_btf_i, \remote_rdy_cntr_reg[2]_0\ => \^lane_up_flop_i\, remote_ready_i => remote_ready_i, rx_pe_data_v_i => rx_pe_data_v_i, rxdatavalid_i => rxdatavalid_i ); sym_gen_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN port map ( D(1 downto 0) => D(1 downto 0), Q(59 downto 0) => Q(59 downto 0), \TX_DATA_reg[55]_0\(3 downto 0) => \TX_DATA_reg[55]\(3 downto 0), \TX_DATA_reg[59]_0\ => \TX_DATA_reg[59]\, \TX_DATA_reg[63]_0\(57 downto 0) => \TX_DATA_reg[63]\(57 downto 0), \TX_DATA_reg[63]_1\ => \TX_DATA_reg[63]_0\, TX_HEADER_1_reg_0 => TX_HEADER_1_reg, channel_up_tx_if => channel_up_tx_if, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, scrambler(11 downto 0) => scrambler(11 downto 0), stg1_aurora_64b66b_0_cdc_to_reg => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg => rst_pma_init_usrclk, stg5_reg_0 => stg5_reg, tempData(5 downto 0) => tempData(5 downto 0), tx_pe_data_v_i => tx_pe_data_v_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_gthe3 is port ( cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txheader_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC; lopt_5 : in STD_LOGIC; lopt_6 : out STD_LOGIC; lopt_7 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_gthe3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_gthe3 is signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_gtwizard_gthe3.cpllpd_ch_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gtrxreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gttxreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.rxprogdivreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.rxuserrdy_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.txprogdivreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.txuserrdy_int\ : STD_LOGIC; signal \^gtpowergood_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_in0 : STD_LOGIC; begin cplllock_out(0) <= \^cplllock_out\(0); gtpowergood_out(0) <= \^gtpowergood_out\(0); \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gthe3_channel_wrapper port map ( cplllock_out(0) => \^cplllock_out\(0), drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpclk_in(0) => drpclk_in(0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in(0) => drpen_in(0), drprdy_out(0) => drprdy_out(0), drpwe_in(0) => drpwe_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => \^gtpowergood_out\(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_userdata_rx_out(31 downto 0) => gtwiz_userdata_rx_out(31 downto 0), gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0), loopback_in(2 downto 0) => loopback_in(2 downto 0), lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, lopt_4 => lopt_4, lopt_5 => lopt_5, lopt_6 => lopt_6, lopt_7 => lopt_7, rst_in0 => rst_in0, rxbufstatus_out(0) => rxbufstatus_out(0), rxcdrlock_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5\, rxcdrovrden_in(0) => rxcdrovrden_in(0), rxdatavalid_out(0) => rxdatavalid_out(0), rxgearboxslip_in(0) => rxgearboxslip_in(0), rxheader_out(1 downto 0) => rxheader_out(1 downto 0), rxheadervalid_out(0) => rxheadervalid_out(0), rxoutclk_out(0) => rxoutclk_out(0), rxpmaresetdone_out(0) => rxpmaresetdone_out(0), rxpolarity_in(0) => rxpolarity_in(0), rxresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8\, rxusrclk2_in(0) => rxusrclk2_in(0), rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => txbufstatus_out(0), txheader_in(1 downto 0) => txheader_in(1 downto 0), txoutclk_out(0) => txoutclk_out(0), txpmaresetdone_out(0) => txpmaresetdone_out(0), txresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11\, txsequence_in(6 downto 0) => txsequence_in(6 downto 0), txusrclk2_in(0) => txusrclk2_in(0), txusrclk_in(0) => txusrclk_in(0) ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, rxresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8\ ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, txresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11\ ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset port map ( cplllock_out(0) => \^cplllock_out\(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gtpowergood_out(0) => \^gtpowergood_out\(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0), gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), rst_in0 => rst_in0, rxcdrlock_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5\, rxusrclk2_in(0) => rxusrclk2_in(0), txusrclk2_in(0) => txusrclk2_in(0) ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" 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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block kyyI/O29YYc5VBwhz19i7AV7MC75r43hHVKAOTBiGBhRu8zZxCwGGcNFqc2HgHcWC6nq4jCIbIXf S3FDzPdasegnERlWvoob9/SXM88zKsyeTbUf+DRu5lB8SPROBMaIhnj375C5XLowL17MXZdmB6fV X5ukCg7cNhCjssKt/bIJibWkfna7hvj4ye+CLWmi3LdEiix8KTwRoBS3ZJrjM4/N6FfZkXerVxs+ txkhdsmG9ga1g/xErhTRilhqrV2WetlpX86qH/64sRGVxrWeEfNoHhMZsqEK0jWDx4WavKt8XY7W NDzMXLZ2m5Dv5HMiJWgFG+ntPwgiYYtBuwu7Eg== `protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block tv6UL1ZWqo3dAIlhN5UTNGzJyqzdHpCqh217JPvIvHiWJgcFh2tw1n7HWnOPcK3VhCt31AGnCEFe HpTiinXvHna65L2X2HhtNUrsgvZlUuh/oQR273wp5JPFDPD97NQ4ELkGI+w26HTYLgZ70K5rQo87 D4AkQNRuzTRS5G12yb4RU7ZYgmkYLuq1UyqjlxyN62Del4XoqZyivOGw5H+7wlfkNRu98iQwqq12 jthZbH/ue5wxZJUcb7NmEwL+3abpyDNmWs1qORHOFoE3t97/9XMmeSCpM2+KnSKJvsV5VbuoTCOT 964fsEh7ey4IVb4aum095gQjLCqTmDm8DWFmaw== `protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block Oxo3AgNmVWgrXtMKDIThYfXr0YJfyFr7Bsjn2ge/G72mb25MA8Dbkd9ZZPtwqU1poazNnTng5Cx5 s8C1zMNEoo38jNY8zEUBjCCuasJgeMo5xsiha+3ZIBiuHS0KLrjLaPFIQZdsYevb44fg6J5YQLn5 jd1M6YdNMd1VwSezDxtbk9sN8ExPrmtwum/6L1ia9j9UlIzPTEaJ60Xz7tloPsgsbkborO2JLiIk kIAY2q1b8tuhHzJ5DoXlvIo49wSDj75ncLrkwbAd26huob7aOmX1bS34pJLF17JzqYH0MoPJbHxb RPdD+qUawXFsMSs2fOLnZrNxeG8L+TyAT0N8tQ== `protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block CIR/vwxo0IBrPr5+bMp2YuBCQTNBRIIbqgEB18Oewkc8CuHzGCAgPyQUBUKaUG3bBy+KDOPVxBP5 cE/d3QYZAT11fyB1OMMTrjmEIZcr0Vk3nVTAnivoxxxkmdzPjkj0OcGcU9fMArPi3dfTgIsKdtCq 94+mV/70WeprgijzuZFWD7uH+gVioY/+rq/Wc1O6x1n949w8YGgSCTurUvhsobx2bonoC317J0Wm IX17XRkSBIFgzqA8iC+GV5oCfxIGkihKmXxjIJbMamlOdCOycEkjkh3JYmm7TLNxmI65iffsabR0 t5+iI0l8eJxFhElzWeREqE43cnJYLaKZBUA+DA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1184) `protect data_block 9tJC3W5EdGweDFFcSDsO5rtMck5mxUF9yEHGI3yD68PuQ/mDzlVntfzSIcIrbvId6jM81OiEpTc3 VqNfNDbls2EdVNB8L3vmTCsgzwBgEi7S6GY27SGEsTbMJJtIBKn9M4GHzos9NQZL9NjqdD8TyH9E 8x+auwy4fpdMqEMf11hBv2pdz9ThAH10Qx3OhSScZCCtHnBuFD64qwDt81Sd68UwXrwdvTsUdTp+ Gfqrjo+VBSLf99IG775Uy96BtVBxrUvS+51j+TYlg09kzhkDCaEagigC5EDGGCFuW3Ym6uJvoNha DyRZQPoqe6kkeg8x+ZOsu9/SRNXXdXicySsfvHTGVRqXYN14yzVgxjAOOsYh7SWwqfvqfPNuimX8 dgwa4lPU7AmW8y64A9q0okRSWXkA2cA+1jIpHthzF9fkzWIJzdXepVP4Q+m2mnlxqkL3v72axgma EuabeyzZHnwiLQ9ZcJ2qWUYCwOt+QuHAcVxMicQhRDCScGiwqEgVmKpxWMpBkrDJK5zSwz9ZiUlR ZVcgDBd8St42214GtTzglFjGlP4ISxPhW2vg9sUE1dljBLD0tbkn16fCbNGHHd2D+zgozSbAo5hI IgsC1XMw+qR4VIZ7kgMu8p3rP04uzwreKIv2Cy4vFhjNFxBxhxtR0tXnGvcjcPPVYaexpSj4+RsX CpF5xP3jB2ZgjG+5Gyk0dYi1jM9CbIzHeSO2wiAZ7hKQifXZ9Jm6sEcUt74GA4bT1QtJ7LH9y0Io qCYo7GmVBJlV4nTuCx5a0AYs4wtuA1VFww83Uyzo5JNTvRpXWxtG08j4PbLTV+IzsuNIyH2URpO2 L2ZHAGQGclIsX6bgGCjUJ+uMCJBMHtkdVLdLlgwQ/ajfWyV5U505XQvmd8Xfkd3U7abvzZ/Q0e4/ /gXOC7w6fOlxz3aq4cMM4bS4oUjonrEYq1vmG5NJd4gt9WooeAppMyuLwMxBo09xTiVfWhPb8tzY /wgIqi9S7ujdtb6qZVAJFCLnM4x4WzvIxyl2GSJphOKmOH60+MazXz5U/9y1sPsbxtIsojdbRCd8 3FM02wBx8Qn4QvnZOPJJKLQEudhPuwF6vIezkCiKA4QcuIe0vrc34KzAx1CmEKWBXLaVpe5vhzvE nTHFjkYwXi1OuTWC7i0aqfnnWHcskHl7zhdTAVPyrZpIp+vJ9xd73ckPCGVxnxQTJqKeyQgPI1EN tVRYjznIjF5IZGVtpnGKkcwMOXYx24baGgVNiZL1dsmx2L2dHxfzsgwTvhxKBOLxjV0ejmCCA0yl xXnULc6t8myWIYG4e228YJ3IGD3pcEEQw8qpcn4X3OpYJ37x9u4Dz7aGg8hwqTNlyziJ6fIx8Ie8 UI4SgqyPqx8LKtipGsNugIWyPs03bkwsnw1EOvFABR/KCbdUGJYtrlOHnsxsTt+efekTDnuitbAM oeY9obhJOdQIfS5GNBnSEuWeeA/F3d43yGK//IY9ckQN+k2r4Jfw4mn6/2YjING7LEiqgDGHISxr Qfu29zfg0219zRpg+lSBezIS2StOxznBkJ6y2kQueor4/LReoAmCcs8siUI= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top is port ( gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll1lock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll1reset_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gthe3_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe3_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe3_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gthe4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gtye4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gtye4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gtye4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); bgbypassb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgmonitorenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgpdb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgrcalovrd_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); bgrcalovrdenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpaddr_common_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpll0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpll1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pmarsvd0_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); pmarsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); qpll0clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0locken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0pd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); qpll0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1locken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1pd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); qpll1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpllrsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); qpllrsvd2_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpllrsvd3_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpllrsvd4_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); rcalenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0data_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0width_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1data_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1width_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tcongpi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconpowerup_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconrsvdin1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubcfgstreamen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubdo_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubdrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubenable_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubgpi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubintr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubiolmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmcapture_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmdbgrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmdbgupdate_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmregen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmshift_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmsysrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtck_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtdi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdo_common_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_common_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pmarsvdout0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); pmarsvdout1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qplldmonitor0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); qplldmonitor1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); refclkoutmonitor0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); refclkoutmonitor1_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclk0_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxrecclk1_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxrecclk0sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclk1sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm0finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm0testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm1finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm1testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 ); tcongpo_out : out STD_LOGIC_VECTOR ( 0 to 0 ); tconrsvdout0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdaddr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubden_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdi_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdwe_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtdo_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubrsvdout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubtxuart_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepdir_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepsq_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepsx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cfgreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllfreqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllocken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllrefclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); cpllreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); dmonfiforeset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drprst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); elpcaldvorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); elpcalpaorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphicaldone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphicalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphidrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphidwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphixrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphixwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescantrigger_in : in STD_LOGIC_VECTOR ( 0 to 0 ); freqos_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrsvd_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); gtrxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); incpctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); looprsvd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); lpbkrxtxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); lpbktxrxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcieeqrxeqadaptdone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierstidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pciersttxsyncstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserratedone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcsrsvdin_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); pcsrsvdin2_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); pmarsvdin_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); resetovrd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rstclkentx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxafecfoken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxbufreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrfreqreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrresetrsv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbonden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondi_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); rxchbondlevel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxchbondmaster_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondslave_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxckcalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxckcalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagcctrl_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagchold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfcnum_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfpulse_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokovren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfekhhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfekhovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap10hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap10ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap11hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap11ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap12hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap12ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap13hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap13ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap14hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap14ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap15hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap15ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap2hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap2ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap3hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap3ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap4hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap4ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap5hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap5ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap6hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap6ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap7hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap7ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap8hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap8ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap9hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap9ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeuthold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeutovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevphold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevpovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevsen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfexyden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxelecidlemode_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxeqtraining_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmgchold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmgcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmhfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmhfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmlfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmlfklovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxoobreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoscalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintcfg_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxosinten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosinthold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosinttestovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbscntreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxqpien_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslide_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslipoutclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslippma_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxtermination_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sigvalidclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tstin_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); tx8b10bbypass_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); tx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txbufdiffctrl_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txcominit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txcomsas_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txcomwake_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); txdata_in : in STD_LOGIC_VECTOR ( 127 downto 0 ); txdataextendrsvd_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); txdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdccreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdeemph_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdetectrx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txdiffpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyupdown_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); txinhibit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpstreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpsu2lpexit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpsu3wake_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); txmargin_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txmuxdcdexhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txmuxdcdorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txoneszeros_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txpdelecidlemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlytstclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphinit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmstepsize_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txpisopd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txpostcursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbsforceerr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txprecursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpibiasen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpistrongpdown_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpiweakpup_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); txswing_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bufgtce_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtcemask_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtdiv_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); bufgtreset_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtrstmask_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); cpllfbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cpllrefclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorout_out : out STD_LOGIC_VECTOR ( 16 downto 0 ); dmonitoroutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); eyescandataerror_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclkmonitor_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierategen3_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierateidle_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpllpd_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); pcierateqpllreset_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); pciesynctxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieusergen3rdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserphystatusrst_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserratestart_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcsrsvdout_out : out STD_LOGIC_VECTOR ( 11 downto 0 ); phystatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pinrsrvdas_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); powerpresent_out : out STD_LOGIC_VECTOR ( 0 to 0 ); resetexception_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrphdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanbondseq_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanrealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondo_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); rxckcaldone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxcominitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcomsasdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcomwakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdata_out : out STD_LOGIC_VECTOR ( 127 downto 0 ); rxdataextendrsvd_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxelecidle_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxlfpstresetdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxlfpsu2lpexitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxlfpsu3wakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); rxosintdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstarted_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobestarted_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxphalignerr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbserr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbslocked_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclkout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxsliderdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslipdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslipoutclkrdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslippmardy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxvalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txcomfinish_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txdccdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txphinitdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC; lopt_5 : in STD_LOGIC; lopt_6 : out STD_LOGIC; lopt_7 : out STD_LOGIC ); attribute C_CHANNEL_ENABLE : string; attribute C_CHANNEL_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_COMMON_SCALING_FACTOR : integer; attribute C_COMMON_SCALING_FACTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_CPLL_VCO_FREQUENCY : string; attribute C_CPLL_VCO_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "2500.000000"; attribute C_ENABLE_COMMON_USRCLK : integer; attribute C_ENABLE_COMMON_USRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_FORCE_COMMONS : integer; attribute C_FORCE_COMMONS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_FREERUN_FREQUENCY : string; attribute C_FREERUN_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "50.000000"; attribute C_GT_REV : integer; attribute C_GT_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 17; attribute C_GT_TYPE : integer; attribute C_GT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_INCLUDE_CPLL_CAL : integer; attribute C_INCLUDE_CPLL_CAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_LOCATE_COMMON : integer; attribute C_LOCATE_COMMON of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_LOCATE_RESET_CONTROLLER : integer; attribute C_LOCATE_RESET_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_RX_USER_CLOCKING : integer; attribute C_LOCATE_RX_USER_CLOCKING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_TX_USER_CLOCKING : integer; attribute C_LOCATE_TX_USER_CLOCKING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer; attribute C_LOCATE_USER_DATA_WIDTH_SIZING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_PCIE_CORECLK_FREQ : integer; attribute C_PCIE_CORECLK_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 250; attribute C_PCIE_ENABLE : integer; attribute C_PCIE_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer; attribute C_RESET_CONTROLLER_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RESET_SEQUENCE_INTERVAL : integer; attribute C_RESET_SEQUENCE_INTERVAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFBYPASS_MODE : integer; attribute C_RX_BUFFBYPASS_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFER_MODE : integer; attribute C_RX_BUFFER_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_DISP : string; attribute C_RX_CB_DISP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CB_K : string; attribute C_RX_CB_K of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CB_LEN_SEQ : integer; attribute C_RX_CB_LEN_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_MAX_LEVEL : integer; attribute C_RX_CB_MAX_LEVEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_NUM_SEQ : integer; attribute C_RX_CB_NUM_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_CB_VAL : string; attribute C_RX_CB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_CC_DISP : string; attribute C_RX_CC_DISP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CC_ENABLE : integer; attribute C_RX_CC_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_CC_K : string; attribute C_RX_CC_K of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CC_LEN_SEQ : integer; attribute C_RX_CC_LEN_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_CC_NUM_SEQ : integer; attribute C_RX_CC_NUM_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_CC_PERIODICITY : integer; attribute C_RX_CC_PERIODICITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 5000; attribute C_RX_CC_VAL : string; attribute C_RX_CC_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_COMMA_M_ENABLE : integer; attribute C_RX_COMMA_M_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_COMMA_M_VAL : string; attribute C_RX_COMMA_M_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "10'b1010000011"; attribute C_RX_COMMA_P_ENABLE : integer; attribute C_RX_COMMA_P_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_COMMA_P_VAL : string; attribute C_RX_COMMA_P_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "10'b0101111100"; attribute C_RX_DATA_DECODING : integer; attribute C_RX_DATA_DECODING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_RX_ENABLE : integer; attribute C_RX_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_INT_DATA_WIDTH : integer; attribute C_RX_INT_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 32; attribute C_RX_LINE_RATE : string; attribute C_RX_LINE_RATE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "5.000000"; attribute C_RX_MASTER_CHANNEL_IDX : integer; attribute C_RX_MASTER_CHANNEL_IDX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 96; attribute C_RX_OUTCLK_BUFG_GT_DIV : integer; attribute C_RX_OUTCLK_BUFG_GT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_OUTCLK_FREQUENCY : string; attribute C_RX_OUTCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_RX_OUTCLK_SOURCE : integer; attribute C_RX_OUTCLK_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_PLL_TYPE : integer; attribute C_RX_PLL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_RX_RECCLK_OUTPUT : string; attribute C_RX_RECCLK_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_REFCLK_FREQUENCY : string; attribute C_RX_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "125.000000"; attribute C_RX_SLIDE_MODE : integer; attribute C_RX_SLIDE_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_CONTENTS : integer; attribute C_RX_USER_CLOCKING_CONTENTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_RX_USER_CLOCKING_SOURCE : integer; attribute C_RX_USER_CLOCKING_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_DATA_WIDTH : integer; attribute C_RX_USER_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 32; attribute C_RX_USRCLK2_FREQUENCY : string; attribute C_RX_USRCLK2_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_RX_USRCLK_FREQUENCY : string; attribute C_RX_USRCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_SECONDARY_QPLL_ENABLE : integer; attribute C_SECONDARY_QPLL_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "257.812500"; attribute C_SIM_CPLL_CAL_BYPASS : integer; attribute C_SIM_CPLL_CAL_BYPASS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TOTAL_NUM_CHANNELS : integer; attribute C_TOTAL_NUM_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TOTAL_NUM_COMMONS : integer; attribute C_TOTAL_NUM_COMMONS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer; attribute C_TOTAL_NUM_COMMONS_EXAMPLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TXPROGDIV_FREQ_ENABLE : integer; attribute C_TXPROGDIV_FREQ_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TXPROGDIV_FREQ_SOURCE : integer; attribute C_TXPROGDIV_FREQ_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_TXPROGDIV_FREQ_VAL : string; attribute C_TXPROGDIV_FREQ_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_TX_BUFFBYPASS_MODE : integer; attribute C_TX_BUFFBYPASS_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TX_BUFFER_MODE : integer; attribute C_TX_BUFFER_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TX_DATA_ENCODING : integer; attribute C_TX_DATA_ENCODING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_TX_ENABLE : integer; attribute C_TX_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TX_INT_DATA_WIDTH : integer; attribute C_TX_INT_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 32; attribute C_TX_LINE_RATE : string; attribute C_TX_LINE_RATE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "5.000000"; attribute C_TX_MASTER_CHANNEL_IDX : integer; attribute C_TX_MASTER_CHANNEL_IDX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 96; attribute C_TX_OUTCLK_BUFG_GT_DIV : integer; attribute C_TX_OUTCLK_BUFG_GT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TX_OUTCLK_FREQUENCY : string; attribute C_TX_OUTCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_TX_OUTCLK_SOURCE : integer; attribute C_TX_OUTCLK_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TX_PLL_TYPE : integer; attribute C_TX_PLL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_TX_REFCLK_FREQUENCY : string; attribute C_TX_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "125.000000"; attribute C_TX_USER_CLOCKING_CONTENTS : integer; attribute C_TX_USER_CLOCKING_CONTENTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 1; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 2; attribute C_TX_USER_CLOCKING_SOURCE : integer; attribute C_TX_USER_CLOCKING_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_DATA_WIDTH : integer; attribute C_TX_USER_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 64; attribute C_TX_USRCLK2_FREQUENCY : string; attribute C_TX_USRCLK2_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "78.125000"; attribute C_TX_USRCLK_FREQUENCY : string; attribute C_TX_USRCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is "156.250000"; attribute C_USER_GTPOWERGOOD_DELAY_EN : integer; attribute C_USER_GTPOWERGOOD_DELAY_EN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top is signal \\ : STD_LOGIC; signal \^rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \^rxdatavalid_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^rxheader_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxheadervalid_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 to 1 ); begin bufgtce_out(2) <= \\; bufgtce_out(1) <= \\; bufgtce_out(0) <= \\; bufgtcemask_out(2) <= \\; bufgtcemask_out(1) <= \\; bufgtcemask_out(0) <= \\; bufgtdiv_out(8) <= \\; bufgtdiv_out(7) <= \\; bufgtdiv_out(6) <= \\; bufgtdiv_out(5) <= \\; bufgtdiv_out(4) <= \\; bufgtdiv_out(3) <= \\; bufgtdiv_out(2) <= \\; bufgtdiv_out(1) <= \\; bufgtdiv_out(0) <= \\; bufgtreset_out(2) <= \\; bufgtreset_out(1) <= \\; bufgtreset_out(0) <= \\; bufgtrstmask_out(2) <= \\; bufgtrstmask_out(1) <= \\; bufgtrstmask_out(0) <= \\; cpllfbclklost_out(0) <= \\; cpllrefclklost_out(0) <= \\; dmonitorout_out(16) <= \\; dmonitorout_out(15) <= \\; dmonitorout_out(14) <= \\; dmonitorout_out(13) <= \\; dmonitorout_out(12) <= \\; dmonitorout_out(11) <= \\; dmonitorout_out(10) <= \\; dmonitorout_out(9) <= \\; dmonitorout_out(8) <= \\; dmonitorout_out(7) <= \\; dmonitorout_out(6) <= \\; dmonitorout_out(5) <= \\; dmonitorout_out(4) <= \\; dmonitorout_out(3) <= \\; dmonitorout_out(2) <= \\; dmonitorout_out(1) <= \\; dmonitorout_out(0) <= \\; dmonitoroutclk_out(0) <= \\; drpdo_common_out(15) <= \\; drpdo_common_out(14) <= \\; drpdo_common_out(13) <= \\; drpdo_common_out(12) <= \\; drpdo_common_out(11) <= \\; drpdo_common_out(10) <= \\; drpdo_common_out(9) <= \\; drpdo_common_out(8) <= \\; drpdo_common_out(7) <= \\; drpdo_common_out(6) <= \\; drpdo_common_out(5) <= \\; drpdo_common_out(4) <= \\; drpdo_common_out(3) <= \\; drpdo_common_out(2) <= \\; drpdo_common_out(1) <= \\; drpdo_common_out(0) <= \\; drprdy_common_out(0) <= \\; eyescandataerror_out(0) <= \\; gtrefclkmonitor_out(0) <= \\; gtwiz_buffbypass_rx_done_out(0) <= \\; gtwiz_buffbypass_rx_error_out(0) <= \\; gtwiz_buffbypass_tx_done_out(0) <= \\; gtwiz_buffbypass_tx_error_out(0) <= \\; gtwiz_reset_qpll0reset_out(0) <= \\; gtwiz_reset_qpll1reset_out(0) <= \\; gtwiz_reset_rx_cdr_stable_out(0) <= \\; gtwiz_userclk_rx_active_out(0) <= \\; gtwiz_userclk_rx_srcclk_out(0) <= \\; gtwiz_userclk_rx_usrclk2_out(0) <= \\; gtwiz_userclk_rx_usrclk_out(0) <= \\; gtwiz_userclk_tx_active_out(0) <= \\; gtwiz_userclk_tx_srcclk_out(0) <= \\; gtwiz_userclk_tx_usrclk2_out(0) <= \\; gtwiz_userclk_tx_usrclk_out(0) <= \\; gtytxn_out(0) <= \\; gtytxp_out(0) <= \\; pcierategen3_out(0) <= \\; pcierateidle_out(0) <= \\; pcierateqpllpd_out(1) <= \\; pcierateqpllpd_out(0) <= \\; pcierateqpllreset_out(1) <= \\; pcierateqpllreset_out(0) <= \\; pciesynctxsyncdone_out(0) <= \\; pcieusergen3rdy_out(0) <= \\; pcieuserphystatusrst_out(0) <= \\; pcieuserratestart_out(0) <= \\; pcsrsvdout_out(11) <= \\; pcsrsvdout_out(10) <= \\; pcsrsvdout_out(9) <= \\; pcsrsvdout_out(8) <= \\; pcsrsvdout_out(7) <= \\; pcsrsvdout_out(6) <= \\; pcsrsvdout_out(5) <= \\; pcsrsvdout_out(4) <= \\; pcsrsvdout_out(3) <= \\; pcsrsvdout_out(2) <= \\; pcsrsvdout_out(1) <= \\; pcsrsvdout_out(0) <= \\; phystatus_out(0) <= \\; pinrsrvdas_out(7) <= \\; pinrsrvdas_out(6) <= \\; pinrsrvdas_out(5) <= \\; pinrsrvdas_out(4) <= \\; pinrsrvdas_out(3) <= \\; pinrsrvdas_out(2) <= \\; pinrsrvdas_out(1) <= \\; pinrsrvdas_out(0) <= \\; pmarsvdout0_out(7) <= \\; pmarsvdout0_out(6) <= \\; pmarsvdout0_out(5) <= \\; pmarsvdout0_out(4) <= \\; pmarsvdout0_out(3) <= \\; pmarsvdout0_out(2) <= \\; pmarsvdout0_out(1) <= \\; pmarsvdout0_out(0) <= \\; pmarsvdout1_out(7) <= \\; pmarsvdout1_out(6) <= \\; pmarsvdout1_out(5) <= \\; pmarsvdout1_out(4) <= \\; pmarsvdout1_out(3) <= \\; pmarsvdout1_out(2) <= \\; pmarsvdout1_out(1) <= \\; pmarsvdout1_out(0) <= \\; powerpresent_out(0) <= \\; qpll0fbclklost_out(0) <= \\; qpll0lock_out(0) <= \\; qpll0outclk_out(0) <= \\; qpll0outrefclk_out(0) <= \\; qpll0refclklost_out(0) <= \\; qpll1fbclklost_out(0) <= \\; qpll1lock_out(0) <= \\; qpll1outclk_out(0) <= \\; qpll1outrefclk_out(0) <= \\; qpll1refclklost_out(0) <= \\; qplldmonitor0_out(7) <= \\; qplldmonitor0_out(6) <= \\; qplldmonitor0_out(5) <= \\; qplldmonitor0_out(4) <= \\; qplldmonitor0_out(3) <= \\; qplldmonitor0_out(2) <= \\; qplldmonitor0_out(1) <= \\; qplldmonitor0_out(0) <= \\; qplldmonitor1_out(7) <= \\; qplldmonitor1_out(6) <= \\; qplldmonitor1_out(5) <= \\; qplldmonitor1_out(4) <= \\; qplldmonitor1_out(3) <= \\; qplldmonitor1_out(2) <= \\; qplldmonitor1_out(1) <= \\; qplldmonitor1_out(0) <= \\; refclkoutmonitor0_out(0) <= \\; refclkoutmonitor1_out(0) <= \\; resetexception_out(0) <= \\; rxbufstatus_out(2) <= \^rxbufstatus_out\(2); rxbufstatus_out(1) <= \\; rxbufstatus_out(0) <= \\; rxbyteisaligned_out(0) <= \\; rxbyterealign_out(0) <= \\; rxcdrlock_out(0) <= \\; rxcdrphdone_out(0) <= \\; rxchanbondseq_out(0) <= \\; rxchanisaligned_out(0) <= \\; rxchanrealign_out(0) <= \\; rxchbondo_out(4) <= \\; rxchbondo_out(3) <= \\; rxchbondo_out(2) <= \\; rxchbondo_out(1) <= \\; rxchbondo_out(0) <= \\; rxckcaldone_out(0) <= \\; rxclkcorcnt_out(1) <= \\; rxclkcorcnt_out(0) <= \\; rxcominitdet_out(0) <= \\; rxcommadet_out(0) <= \\; rxcomsasdet_out(0) <= \\; rxcomwakedet_out(0) <= \\; rxctrl0_out(15) <= \\; rxctrl0_out(14) <= \\; rxctrl0_out(13) <= \\; rxctrl0_out(12) <= \\; rxctrl0_out(11) <= \\; rxctrl0_out(10) <= \\; rxctrl0_out(9) <= \\; rxctrl0_out(8) <= \\; rxctrl0_out(7) <= \\; rxctrl0_out(6) <= \\; rxctrl0_out(5) <= \\; rxctrl0_out(4) <= \\; rxctrl0_out(3) <= \\; rxctrl0_out(2) <= \\; rxctrl0_out(1) <= \\; rxctrl0_out(0) <= \\; rxctrl1_out(15) <= \\; rxctrl1_out(14) <= \\; rxctrl1_out(13) <= \\; rxctrl1_out(12) <= \\; rxctrl1_out(11) <= \\; rxctrl1_out(10) <= \\; rxctrl1_out(9) <= \\; rxctrl1_out(8) <= \\; rxctrl1_out(7) <= \\; rxctrl1_out(6) <= \\; rxctrl1_out(5) <= \\; rxctrl1_out(4) <= \\; rxctrl1_out(3) <= \\; rxctrl1_out(2) <= \\; rxctrl1_out(1) <= \\; rxctrl1_out(0) <= \\; rxctrl2_out(7) <= \\; rxctrl2_out(6) <= \\; rxctrl2_out(5) <= \\; rxctrl2_out(4) <= \\; rxctrl2_out(3) <= \\; rxctrl2_out(2) <= \\; rxctrl2_out(1) <= \\; rxctrl2_out(0) <= \\; rxctrl3_out(7) <= \\; rxctrl3_out(6) <= \\; rxctrl3_out(5) <= \\; rxctrl3_out(4) <= \\; rxctrl3_out(3) <= \\; rxctrl3_out(2) <= \\; rxctrl3_out(1) <= \\; rxctrl3_out(0) <= \\; rxdata_out(127) <= \\; rxdata_out(126) <= \\; rxdata_out(125) <= \\; rxdata_out(124) <= \\; rxdata_out(123) <= \\; rxdata_out(122) <= \\; rxdata_out(121) <= \\; rxdata_out(120) <= \\; rxdata_out(119) <= \\; rxdata_out(118) <= \\; rxdata_out(117) <= \\; rxdata_out(116) <= \\; rxdata_out(115) <= \\; rxdata_out(114) <= \\; rxdata_out(113) <= \\; rxdata_out(112) <= \\; rxdata_out(111) <= \\; rxdata_out(110) <= \\; rxdata_out(109) <= \\; rxdata_out(108) <= \\; rxdata_out(107) <= \\; rxdata_out(106) <= \\; rxdata_out(105) <= \\; rxdata_out(104) <= \\; rxdata_out(103) <= \\; rxdata_out(102) <= \\; rxdata_out(101) <= \\; rxdata_out(100) <= \\; rxdata_out(99) <= \\; rxdata_out(98) <= \\; rxdata_out(97) <= \\; rxdata_out(96) <= \\; rxdata_out(95) <= \\; rxdata_out(94) <= \\; rxdata_out(93) <= \\; rxdata_out(92) <= \\; rxdata_out(91) <= \\; rxdata_out(90) <= \\; rxdata_out(89) <= \\; rxdata_out(88) <= \\; rxdata_out(87) <= \\; rxdata_out(86) <= \\; rxdata_out(85) <= \\; rxdata_out(84) <= \\; rxdata_out(83) <= \\; rxdata_out(82) <= \\; rxdata_out(81) <= \\; rxdata_out(80) <= \\; rxdata_out(79) <= \\; rxdata_out(78) <= \\; rxdata_out(77) <= \\; rxdata_out(76) <= \\; rxdata_out(75) <= \\; rxdata_out(74) <= \\; rxdata_out(73) <= \\; rxdata_out(72) <= \\; rxdata_out(71) <= \\; rxdata_out(70) <= \\; rxdata_out(69) <= \\; rxdata_out(68) <= \\; rxdata_out(67) <= \\; rxdata_out(66) <= \\; rxdata_out(65) <= \\; rxdata_out(64) <= \\; rxdata_out(63) <= \\; rxdata_out(62) <= \\; rxdata_out(61) <= \\; rxdata_out(60) <= \\; rxdata_out(59) <= \\; rxdata_out(58) <= \\; rxdata_out(57) <= \\; rxdata_out(56) <= \\; rxdata_out(55) <= \\; rxdata_out(54) <= \\; rxdata_out(53) <= \\; rxdata_out(52) <= \\; rxdata_out(51) <= \\; rxdata_out(50) <= \\; rxdata_out(49) <= \\; rxdata_out(48) <= \\; rxdata_out(47) <= \\; rxdata_out(46) <= \\; rxdata_out(45) <= \\; rxdata_out(44) <= \\; rxdata_out(43) <= \\; rxdata_out(42) <= \\; rxdata_out(41) <= \\; rxdata_out(40) <= \\; rxdata_out(39) <= \\; rxdata_out(38) <= \\; rxdata_out(37) <= \\; rxdata_out(36) <= \\; rxdata_out(35) <= \\; rxdata_out(34) <= \\; rxdata_out(33) <= \\; rxdata_out(32) <= \\; rxdata_out(31) <= \\; rxdata_out(30) <= \\; rxdata_out(29) <= \\; rxdata_out(28) <= \\; rxdata_out(27) <= \\; rxdata_out(26) <= \\; rxdata_out(25) <= \\; rxdata_out(24) <= \\; rxdata_out(23) <= \\; rxdata_out(22) <= \\; rxdata_out(21) <= \\; rxdata_out(20) <= \\; rxdata_out(19) <= \\; rxdata_out(18) <= \\; rxdata_out(17) <= \\; rxdata_out(16) <= \\; rxdata_out(15) <= \\; rxdata_out(14) <= \\; rxdata_out(13) <= \\; rxdata_out(12) <= \\; rxdata_out(11) <= \\; rxdata_out(10) <= \\; rxdata_out(9) <= \\; rxdata_out(8) <= \\; rxdata_out(7) <= \\; rxdata_out(6) <= \\; rxdata_out(5) <= \\; rxdata_out(4) <= \\; rxdata_out(3) <= \\; rxdata_out(2) <= \\; rxdata_out(1) <= \\; rxdata_out(0) <= \\; rxdataextendrsvd_out(7) <= \\; rxdataextendrsvd_out(6) <= \\; rxdataextendrsvd_out(5) <= \\; rxdataextendrsvd_out(4) <= \\; rxdataextendrsvd_out(3) <= \\; rxdataextendrsvd_out(2) <= \\; rxdataextendrsvd_out(1) <= \\; rxdataextendrsvd_out(0) <= \\; rxdatavalid_out(1) <= \\; rxdatavalid_out(0) <= \^rxdatavalid_out\(0); rxdlysresetdone_out(0) <= \\; rxelecidle_out(0) <= \\; rxheader_out(5) <= \\; rxheader_out(4) <= \\; rxheader_out(3) <= \\; rxheader_out(2) <= \\; rxheader_out(1 downto 0) <= \^rxheader_out\(1 downto 0); rxheadervalid_out(1) <= \\; rxheadervalid_out(0) <= \^rxheadervalid_out\(0); rxlfpstresetdet_out(0) <= \\; rxlfpsu2lpexitdet_out(0) <= \\; rxlfpsu3wakedet_out(0) <= \\; rxmonitorout_out(6) <= \\; rxmonitorout_out(5) <= \\; rxmonitorout_out(4) <= \\; rxmonitorout_out(3) <= \\; rxmonitorout_out(2) <= \\; rxmonitorout_out(1) <= \\; rxmonitorout_out(0) <= \\; rxosintdone_out(0) <= \\; rxosintstarted_out(0) <= \\; rxosintstrobedone_out(0) <= \\; rxosintstrobestarted_out(0) <= \\; rxoutclkfabric_out(0) <= \\; rxoutclkpcs_out(0) <= \\; rxphaligndone_out(0) <= \\; rxphalignerr_out(0) <= \\; rxprbserr_out(0) <= \\; rxprbslocked_out(0) <= \\; rxprgdivresetdone_out(0) <= \\; rxqpisenn_out(0) <= \\; rxqpisenp_out(0) <= \\; rxratedone_out(0) <= \\; rxrecclk0_sel_out(1) <= \\; rxrecclk0_sel_out(0) <= \\; rxrecclk0sel_out(0) <= \\; rxrecclk1_sel_out(1) <= \\; rxrecclk1_sel_out(0) <= \\; rxrecclk1sel_out(0) <= \\; rxrecclkout_out(0) <= \\; rxresetdone_out(0) <= \\; rxsliderdy_out(0) <= \\; rxslipdone_out(0) <= \\; rxslipoutclkrdy_out(0) <= \\; rxslippmardy_out(0) <= \\; rxstartofseq_out(1) <= \\; rxstartofseq_out(0) <= \\; rxstatus_out(2) <= \\; rxstatus_out(1) <= \\; rxstatus_out(0) <= \\; rxsyncdone_out(0) <= \\; rxsyncout_out(0) <= \\; rxvalid_out(0) <= \\; sdm0finalout_out(0) <= \\; sdm0testdata_out(0) <= \\; sdm1finalout_out(0) <= \\; sdm1testdata_out(0) <= \\; tcongpo_out(0) <= \\; tconrsvdout0_out(0) <= \\; txbufstatus_out(1) <= \^txbufstatus_out\(1); txbufstatus_out(0) <= \\; txcomfinish_out(0) <= \\; txdccdone_out(0) <= \\; txdlysresetdone_out(0) <= \\; txoutclkfabric_out(0) <= \\; txoutclkpcs_out(0) <= \\; txphaligndone_out(0) <= \\; txphinitdone_out(0) <= \\; txprgdivresetdone_out(0) <= \\; txqpisenn_out(0) <= \\; txqpisenp_out(0) <= \\; txratedone_out(0) <= \\; txresetdone_out(0) <= \\; txsyncdone_out(0) <= \\; txsyncout_out(0) <= \\; ubdaddr_out(0) <= \\; ubden_out(0) <= \\; ubdi_out(0) <= \\; ubdwe_out(0) <= \\; ubmdmtdo_out(0) <= \\; ubrsvdout_out(0) <= \\; ubtxuart_out(0) <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_gthe3 port map ( cplllock_out(0) => cplllock_out(0), drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpclk_in(0) => drpclk_in(0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in(0) => drpen_in(0), drprdy_out(0) => drprdy_out(0), drpwe_in(0) => drpwe_in(0), gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => gtpowergood_out(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0), gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), gtwiz_userdata_rx_out(31 downto 0) => gtwiz_userdata_rx_out(31 downto 0), gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0), loopback_in(2 downto 0) => loopback_in(2 downto 0), lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, lopt_4 => lopt_4, lopt_5 => lopt_5, lopt_6 => lopt_6, lopt_7 => lopt_7, rxbufstatus_out(0) => \^rxbufstatus_out\(2), rxcdrovrden_in(0) => rxcdrovrden_in(0), rxdatavalid_out(0) => \^rxdatavalid_out\(0), rxgearboxslip_in(0) => rxgearboxslip_in(0), rxheader_out(1 downto 0) => \^rxheader_out\(1 downto 0), rxheadervalid_out(0) => \^rxheadervalid_out\(0), rxoutclk_out(0) => rxoutclk_out(0), rxpmaresetdone_out(0) => rxpmaresetdone_out(0), rxpolarity_in(0) => rxpolarity_in(0), rxusrclk2_in(0) => rxusrclk2_in(0), rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => \^txbufstatus_out\(1), txheader_in(1 downto 0) => txheader_in(1 downto 0), txoutclk_out(0) => txoutclk_out(0), txpmaresetdone_out(0) => txpmaresetdone_out(0), txsequence_in(6 downto 0) => txsequence_in(6 downto 0), txusrclk2_in(0) => txusrclk2_in(0), txusrclk_in(0) => txusrclk_in(0) ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block SFoQ2tXDMrL2nCJbfpmHXuteJlKaWDWl3o9OY1miFvmYb8EDywmDpLUHQktJ/VoW+17fK5WHgFVI FZV1B91GDQ== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block mxGWDRjEAsKmBqldxevT1RKZvqK7vn0KlTODVXNGlRcGf9zOAmj0Z7Ppu79POBDb8oNQyCY+2q1q BddzhQfh5WLIVX9BNUMIF6M6IF0elM4GMSLHGeYEwqSaMPC+thuR8FGj1J7z6rH+43gDYhtIeyY+ ZuZUz/Pqg8Lu63Xwe+0= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block HLwPjQzkuqv5FEDBriEJS2DikBeIHB/bWuVWooHY5ChdoHatcmqCHpSvnGxVzLwObZWHFys2nR9y P3zxywjtgtOWq/n3cYVa5li6eyiUmGXv2OE8nw1nLnAY1kzBvGd6VwQ45t6l4Hx5+oqpIfuU2KI2 7/Qpj2atiTN3Y+q5He/BMXLIxF9vWuU6XL/+HsxriGAumcZDuESdidlxOztbW1bFhYr1/qWwou2q wynnRVKYHL41aWycgFdkDoDEFFxv8ft8+F5Ux+J5Hg5XdgRULJc6uUQE/lDG3zOqzPftlODB52zU d0cm8gFOvSZ2nO8ZB8THnxoAGe33iIZJfMcefA== `protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block jlR0iZ4fp9QXiFgaT07DMAK1YFLyBpsOGOOR9j2PWImFEh8oTBt4cvmGo+2z1Umbt9OMQwOhyepO QIsKLFzUXYUba+SFFLBoCiaww24KICecbUfd3VV5sg2bEJjAdtYTT6mJqyc3vQRvBlONeBFdIGy2 AXqdK7QtXGLsLAIF/z4FG8cfG6nSD6e16gccBC6+kl5MoShdnmebKLyoo6UKFdMbDK88sHvTcD9S LNCau6RK7FkTZg23FV0tf6cTP9Rray9YEcowm2AAh51Wldo2lGJ2W5iiDatRKH/W1bu7FGWZG+OT +VZE+Ckiuf4T6cuu+G5IbrtMv6a4U93R0gtxXQ== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block p/kq+JjPPJbOTWT2SRiPJ99/iH6kkVGEiluRRXpuRN+j+cVPgJD1v4QVjw3zMWLlvTGB7OOqC+JG Lc62Wiizd/BFfGj2JYkTZMatcOWok7A87HK+vRTjr4nZMApD2jKaneJdU1279KsIEeRfImCQ2uRl QRNMH3PPdNGYCnOGgNk= `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block kyyI/O29YYc5VBwhz19i7AV7MC75r43hHVKAOTBiGBhRu8zZxCwGGcNFqc2HgHcWC6nq4jCIbIXf S3FDzPdasegnERlWvoob9/SXM88zKsyeTbUf+DRu5lB8SPROBMaIhnj375C5XLowL17MXZdmB6fV X5ukCg7cNhCjssKt/bIJibWkfna7hvj4ye+CLWmi3LdEiix8KTwRoBS3ZJrjM4/N6FfZkXerVxs+ txkhdsmG9ga1g/xErhTRilhqrV2WetlpX86qH/64sRGVxrWeEfNoHhMZsqEK0jWDx4WavKt8XY7W NDzMXLZ2m5Dv5HMiJWgFG+ntPwgiYYtBuwu7Eg== `protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block tv6UL1ZWqo3dAIlhN5UTNGzJyqzdHpCqh217JPvIvHiWJgcFh2tw1n7HWnOPcK3VhCt31AGnCEFe HpTiinXvHna65L2X2HhtNUrsgvZlUuh/oQR273wp5JPFDPD97NQ4ELkGI+w26HTYLgZ70K5rQo87 D4AkQNRuzTRS5G12yb4RU7ZYgmkYLuq1UyqjlxyN62Del4XoqZyivOGw5H+7wlfkNRu98iQwqq12 jthZbH/ue5wxZJUcb7NmEwL+3abpyDNmWs1qORHOFoE3t97/9XMmeSCpM2+KnSKJvsV5VbuoTCOT 964fsEh7ey4IVb4aum095gQjLCqTmDm8DWFmaw== `protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block Oxo3AgNmVWgrXtMKDIThYfXr0YJfyFr7Bsjn2ge/G72mb25MA8Dbkd9ZZPtwqU1poazNnTng5Cx5 s8C1zMNEoo38jNY8zEUBjCCuasJgeMo5xsiha+3ZIBiuHS0KLrjLaPFIQZdsYevb44fg6J5YQLn5 jd1M6YdNMd1VwSezDxtbk9sN8ExPrmtwum/6L1ia9j9UlIzPTEaJ60Xz7tloPsgsbkborO2JLiIk kIAY2q1b8tuhHzJ5DoXlvIo49wSDj75ncLrkwbAd26huob7aOmX1bS34pJLF17JzqYH0MoPJbHxb RPdD+qUawXFsMSs2fOLnZrNxeG8L+TyAT0N8tQ== `protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block CIR/vwxo0IBrPr5+bMp2YuBCQTNBRIIbqgEB18Oewkc8CuHzGCAgPyQUBUKaUG3bBy+KDOPVxBP5 cE/d3QYZAT11fyB1OMMTrjmEIZcr0Vk3nVTAnivoxxxkmdzPjkj0OcGcU9fMArPi3dfTgIsKdtCq 94+mV/70WeprgijzuZFWD7uH+gVioY/+rq/Wc1O6x1n949w8YGgSCTurUvhsobx2bonoC317J0Wm IX17XRkSBIFgzqA8iC+GV5oCfxIGkihKmXxjIJbMamlOdCOycEkjkh3JYmm7TLNxmI65iffsabR0 t5+iI0l8eJxFhElzWeREqE43cnJYLaKZBUA+DA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1712) `protect data_block 9tJC3W5EdGweDFFcSDsO5rtMck5mxUF9yEHGI3yD68PuQ/mDzlVntfzSIcIrbvId6jM81OiEpTc3 VqNfNDbls2EdVNB8L3vmTCsgzwBgEi7S6GY27SGEsTbMJJtIBKn9M4GHzos9NQZL9NjqdD8TyH9E 8x+auwy4fpdMqEMf11hBv2pdz9ThAH10Qx3OhSScvpx7XN8ZD5BLfIXklkHQK0XyOu/Ui+X1PZZT CasUXzjpSTIH4K6INNAut3WUAdjm+XkVcOJhMRMYwLSovEXbTNqVF+qvRf65nvFtW6O+X0e5hHxw vVLi5FdeTsT62ChfGfXBRr0kZcHz6W5SW+gtu58NFSsR998/Bd0lZxOTDRj8VRG52h2NapprUuKf hEPbCGH0+Mw38JmOXE0k4JhPgxdcNVxFZHyuOoAxCvQ1Wvzaxd7XB8WX1A4uiEWUoF4qxFyYPtKa /0f0/uiSlBGV+fcCntCSDQ5w4F3dmCs8KAizOkWo9bKR/mBcfRn53E7hERHQj7HcNYvPkSgDeRkp 49RTuyIwAUxHCqXuLy2XtZ5eSPjx9C01i2gf3JmzOkkLkdGd2Nczti8kqDJlknDz9CU/tewyz0B9 oW4mzN0IeQmjDzbaqhUeHOWSqPsxj8NvutQHoO1/NsQwu9dGAsUDfGbSTsVdBuAD+U5r7A6rsQIi ImYNbYilavCGT3lvWMLy+FrFa1N5JJ/XD7KAvEwX2WaL0zQWoboOFusJe+qFP4crfJYly9RDcY1L +N5/Bcjb1ff1VuM0n2iygkOxvC4PJeyWJSX0kgfQ9ZfTRiyf30I0dte/1yhj2fOAJpBrIgx2jDkw rNyt6X8IKBs9uGcgP2HTMjw3cXFm2uyaBYXp4DRNTSJ5pIX9XaXM1Niwue8zG+WLFK2lV5avmU9Q vnG+fPSvY2jrXewC6FVAPBm30A1oZgP4fri1FXN5cw0EUQ0ZELIpK1Ye+SQuzoLOmR3u5Obgxdvj cYJXhfq/xhXvokoSLhg66j6+lGkHsHGWBGM6/UIe6RWEN/QVlZGU0U+34EnRFPJsQoQE0ZPkwlgM juYS6etId4m81sD2W3Mk+++elJ4eL7lIvyNkNzhCbIGHHaNaXOWQydCZ/Cu2z149DT8NWj6CnaYH luZwW/y8JSIzQ9mJp6YEXNosmLDi/51EuD7gHOkG6KF9+/367jqBIQO8QGxVAr0Q+UQPOYgUfxOQ XoJbEPqnsCOcQvjwobCrz+h8Z8ky4Qa0FFsPAIXKXSShy1sGwxvldgXhw5xKIGD9698V9LZeyMlc leZZHSTsoUOPvKf/Uj7ZyRY4jTyZT7hcc1XqrlOhkDBUPtSNiy9OeoZFG5nbx0ywGiYlC0BuNW9o MnLJ87XIRQ9dsSWiTUkqD0WP10YzdMLRiP6YQrEaht28i/kG2ubqN2IzYDwfvfsJSwWyYNCynRYj yC0dkZIPo0amf2tRZJB4Jer8XAz/f8IB9NhHvEha4wytl0wEs7/BgyfdFfKjuL0Cl4x7R9CPCDz1 DTKGHfJlsJaMTgeiQoUbDYwdAw/aEt+EfSOgPN3vhGpBMGSMu6IjDiCv3mHp1qywQZhC1mKgBmCu QCVryL1OaM4rZn1CAX59I1Wj4AP/lhPRT1g0XO4xazo8vb+vDWWUYKCrjmwka2htsY7BBbv4WV7q HneQaVF0GtONr08Lxz4CX0z4AngzqqRLIxVToQtR5BVJQlq/0vxZJhjNsWhJSp+ayrvDy6+1lBNc 7MMbR6+2WVwSLu/kWRcwGZHZTkzv1q3oIhqVU3B/ctKMiB3LL63UfQND+tXqIW7DbH7lsBd0UMdx FrQyaMl74ILCBrDOXJdtXn+01RBv2dLSa9TPmR3B6Hza1adC77DejcHIZ49fQzW2W2jQ/9POa3g8 h56VYZY+u5E2MDZXiHXtjf+/M7yf9Wz9ahbI5sP6wriKyZLRCmvbTh4SSo0ofm0wp9M3rRsuUs83 pWY0/wG7C4oDC+R3DrXN7DB7x+MVAFPRk4o+gZN2aFUVPC+4xuFHQYredNTTE13BpL6KbVQmZ4v9 uOp4AE8f0ytaKHANFjRxWxA9AE9lVkTQ3EWgqN9TpCfnoeU+dztP/k9JH0iZUJHwqx0fQPd/FIb3 dxXHIoIlMbr7XB0fA+nTVVK+srjIlWnG87HRShfYVpInQ3WQ5kqFbM5HSzb65MjTrH5BQM4yivIG dqS0OdBTp9J3rHArHjZtQTr4kdclIe0dVxs2gQ6HkiqwFgK1VuiLKkLDAn7uIwRuF4rJ5L/a0iUB sTE= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt is port ( gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescantrigger_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); pcsrsvdin_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); rxbufreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbscntreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); txinhibit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txprbsforceerr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorout_out : out STD_LOGIC_VECTOR ( 16 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); eyescandataerror_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbserr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC; lopt_5 : in STD_LOGIC; lopt_6 : out STD_LOGIC; lopt_7 : out STD_LOGIC ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt : entity is "aurora_64b66b_0_gt,aurora_64b66b_0_gt_gtwizard_top,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt : entity is "aurora_64b66b_0_gt_gtwizard_top,Vivado 2020.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt is signal \\ : STD_LOGIC; signal \^rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \^rxdatavalid_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^rxheader_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxheadervalid_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_inst_bufgtce_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtcemask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtdiv_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_inst_bufgtreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtrstmask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_cpllfbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_cpllrefclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); signal NLW_inst_dmonitoroutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_drpdo_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_inst_drprdy_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtrefclkmonitor_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtytxn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtytxp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierategen3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierateidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierateqpllpd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_pcierateqpllreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_pciesynctxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieusergen3rdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieuserphystatusrst_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieuserratestart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcsrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_phystatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pinrsrvdas_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_pmarsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_pmarsvdout1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_powerpresent_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qplldmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_qplldmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_refclkoutmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_refclkoutmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_resetexception_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcdrlock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcdrphdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanbondseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanrealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchbondo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_inst_rxckcaldone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxclkcorcnt_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxcominitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcomsasdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcomwakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_inst_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_inst_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_rxdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 ); signal NLW_inst_rxdataextendrsvd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_rxdatavalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_inst_rxdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxelecidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxheader_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 2 ); signal NLW_inst_rxheadervalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_inst_rxlfpstresetdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 ); signal NLW_inst_rxosintdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstrobedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstrobestarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxphalignerr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprbslocked_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclk0_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxrecclk0sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclk1_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxrecclk1sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclkout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxsliderdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslipdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslipoutclkrdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslippmardy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxstartofseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_rxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxvalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm0finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm0testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm1finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm1testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_tcongpo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_tconrsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txcomfinish_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txdccdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txphinitdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubden_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdi_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdwe_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubmdmtdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubtxuart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_CHANNEL_ENABLE : string; attribute C_CHANNEL_ENABLE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_COMMON_SCALING_FACTOR : integer; attribute C_COMMON_SCALING_FACTOR of inst : label is 1; attribute C_CPLL_VCO_FREQUENCY : string; attribute C_CPLL_VCO_FREQUENCY of inst : label is "2500.000000"; attribute C_ENABLE_COMMON_USRCLK : integer; attribute C_ENABLE_COMMON_USRCLK of inst : label is 0; attribute C_FORCE_COMMONS : integer; attribute C_FORCE_COMMONS of inst : label is 0; attribute C_FREERUN_FREQUENCY : string; attribute C_FREERUN_FREQUENCY of inst : label is "50.000000"; attribute C_GT_REV : integer; attribute C_GT_REV of inst : label is 17; attribute C_GT_TYPE : integer; attribute C_GT_TYPE of inst : label is 0; attribute C_INCLUDE_CPLL_CAL : integer; attribute C_INCLUDE_CPLL_CAL of inst : label is 2; attribute C_LOCATE_COMMON : integer; attribute C_LOCATE_COMMON of inst : label is 0; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of inst : label is 2; attribute C_LOCATE_RESET_CONTROLLER : integer; attribute C_LOCATE_RESET_CONTROLLER of inst : label is 0; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of inst : label is 0; attribute C_LOCATE_RX_USER_CLOCKING : integer; attribute C_LOCATE_RX_USER_CLOCKING of inst : label is 1; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of inst : label is 0; attribute C_LOCATE_TX_USER_CLOCKING : integer; attribute C_LOCATE_TX_USER_CLOCKING of inst : label is 1; attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer; attribute C_LOCATE_USER_DATA_WIDTH_SIZING of inst : label is 0; attribute C_PCIE_CORECLK_FREQ : integer; attribute C_PCIE_CORECLK_FREQ of inst : label is 250; attribute C_PCIE_ENABLE : integer; attribute C_PCIE_ENABLE of inst : label is 0; attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer; attribute C_RESET_CONTROLLER_INSTANCE_CTRL of inst : label is 0; attribute C_RESET_SEQUENCE_INTERVAL : integer; attribute C_RESET_SEQUENCE_INTERVAL of inst : label is 0; attribute C_RX_BUFFBYPASS_MODE : integer; attribute C_RX_BUFFBYPASS_MODE of inst : label is 0; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0; attribute C_RX_BUFFER_MODE : integer; attribute C_RX_BUFFER_MODE of inst : label is 1; attribute C_RX_CB_DISP : string; attribute C_RX_CB_DISP of inst : label is "8'b00000000"; attribute C_RX_CB_K : string; attribute C_RX_CB_K of inst : label is "8'b00000000"; attribute C_RX_CB_LEN_SEQ : integer; attribute C_RX_CB_LEN_SEQ of inst : label is 1; attribute C_RX_CB_MAX_LEVEL : integer; attribute C_RX_CB_MAX_LEVEL of inst : label is 1; attribute C_RX_CB_NUM_SEQ : integer; attribute C_RX_CB_NUM_SEQ of inst : label is 0; attribute C_RX_CB_VAL : string; attribute C_RX_CB_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_CC_DISP : string; attribute C_RX_CC_DISP of inst : label is "8'b00000000"; attribute C_RX_CC_ENABLE : integer; attribute C_RX_CC_ENABLE of inst : label is 0; attribute C_RX_CC_K : string; attribute C_RX_CC_K of inst : label is "8'b00000000"; attribute C_RX_CC_LEN_SEQ : integer; attribute C_RX_CC_LEN_SEQ of inst : label is 1; attribute C_RX_CC_NUM_SEQ : integer; attribute C_RX_CC_NUM_SEQ of inst : label is 0; attribute C_RX_CC_PERIODICITY : integer; attribute C_RX_CC_PERIODICITY of inst : label is 5000; attribute C_RX_CC_VAL : string; attribute C_RX_CC_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_COMMA_M_ENABLE : integer; attribute C_RX_COMMA_M_ENABLE of inst : label is 0; attribute C_RX_COMMA_M_VAL : string; attribute C_RX_COMMA_M_VAL of inst : label is "10'b1010000011"; attribute C_RX_COMMA_P_ENABLE : integer; attribute C_RX_COMMA_P_ENABLE of inst : label is 0; attribute C_RX_COMMA_P_VAL : string; attribute C_RX_COMMA_P_VAL of inst : label is "10'b0101111100"; attribute C_RX_DATA_DECODING : integer; attribute C_RX_DATA_DECODING of inst : label is 2; attribute C_RX_ENABLE : integer; attribute C_RX_ENABLE of inst : label is 1; attribute C_RX_INT_DATA_WIDTH : integer; attribute C_RX_INT_DATA_WIDTH of inst : label is 32; attribute C_RX_LINE_RATE : string; attribute C_RX_LINE_RATE of inst : label is "5.000000"; attribute C_RX_MASTER_CHANNEL_IDX : integer; attribute C_RX_MASTER_CHANNEL_IDX of inst : label is 96; attribute C_RX_OUTCLK_BUFG_GT_DIV : integer; attribute C_RX_OUTCLK_BUFG_GT_DIV of inst : label is 1; attribute C_RX_OUTCLK_FREQUENCY : string; attribute C_RX_OUTCLK_FREQUENCY of inst : label is "156.250000"; attribute C_RX_OUTCLK_SOURCE : integer; attribute C_RX_OUTCLK_SOURCE of inst : label is 1; attribute C_RX_PLL_TYPE : integer; attribute C_RX_PLL_TYPE of inst : label is 2; attribute C_RX_RECCLK_OUTPUT : string; attribute C_RX_RECCLK_OUTPUT of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_REFCLK_FREQUENCY : string; attribute C_RX_REFCLK_FREQUENCY of inst : label is "125.000000"; attribute C_RX_SLIDE_MODE : integer; attribute C_RX_SLIDE_MODE of inst : label is 0; attribute C_RX_USER_CLOCKING_CONTENTS : integer; attribute C_RX_USER_CLOCKING_CONTENTS of inst : label is 0; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1; attribute C_RX_USER_CLOCKING_SOURCE : integer; attribute C_RX_USER_CLOCKING_SOURCE of inst : label is 0; attribute C_RX_USER_DATA_WIDTH : integer; attribute C_RX_USER_DATA_WIDTH of inst : label is 32; attribute C_RX_USRCLK2_FREQUENCY : string; attribute C_RX_USRCLK2_FREQUENCY of inst : label is "156.250000"; attribute C_RX_USRCLK_FREQUENCY : string; attribute C_RX_USRCLK_FREQUENCY of inst : label is "156.250000"; attribute C_SECONDARY_QPLL_ENABLE : integer; attribute C_SECONDARY_QPLL_ENABLE of inst : label is 0; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of inst : label is "257.812500"; attribute C_SIM_CPLL_CAL_BYPASS : integer; attribute C_SIM_CPLL_CAL_BYPASS of inst : label is 1; attribute C_TOTAL_NUM_CHANNELS : integer; attribute C_TOTAL_NUM_CHANNELS of inst : label is 1; attribute C_TOTAL_NUM_COMMONS : integer; attribute C_TOTAL_NUM_COMMONS of inst : label is 0; attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer; attribute C_TOTAL_NUM_COMMONS_EXAMPLE of inst : label is 0; attribute C_TXPROGDIV_FREQ_ENABLE : integer; attribute C_TXPROGDIV_FREQ_ENABLE of inst : label is 0; attribute C_TXPROGDIV_FREQ_SOURCE : integer; attribute C_TXPROGDIV_FREQ_SOURCE of inst : label is 2; attribute C_TXPROGDIV_FREQ_VAL : string; attribute C_TXPROGDIV_FREQ_VAL of inst : label is "156.250000"; attribute C_TX_BUFFBYPASS_MODE : integer; attribute C_TX_BUFFBYPASS_MODE of inst : label is 0; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0; attribute C_TX_BUFFER_MODE : integer; attribute C_TX_BUFFER_MODE of inst : label is 1; attribute C_TX_DATA_ENCODING : integer; attribute C_TX_DATA_ENCODING of inst : label is 2; attribute C_TX_ENABLE : integer; attribute C_TX_ENABLE of inst : label is 1; attribute C_TX_INT_DATA_WIDTH : integer; attribute C_TX_INT_DATA_WIDTH of inst : label is 32; attribute C_TX_LINE_RATE : string; attribute C_TX_LINE_RATE of inst : label is "5.000000"; attribute C_TX_MASTER_CHANNEL_IDX : integer; attribute C_TX_MASTER_CHANNEL_IDX of inst : label is 96; attribute C_TX_OUTCLK_BUFG_GT_DIV : integer; attribute C_TX_OUTCLK_BUFG_GT_DIV of inst : label is 1; attribute C_TX_OUTCLK_FREQUENCY : string; attribute C_TX_OUTCLK_FREQUENCY of inst : label is "156.250000"; attribute C_TX_OUTCLK_SOURCE : integer; attribute C_TX_OUTCLK_SOURCE of inst : label is 1; attribute C_TX_PLL_TYPE : integer; attribute C_TX_PLL_TYPE of inst : label is 2; attribute C_TX_REFCLK_FREQUENCY : string; attribute C_TX_REFCLK_FREQUENCY of inst : label is "125.000000"; attribute C_TX_USER_CLOCKING_CONTENTS : integer; attribute C_TX_USER_CLOCKING_CONTENTS of inst : label is 0; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 2; attribute C_TX_USER_CLOCKING_SOURCE : integer; attribute C_TX_USER_CLOCKING_SOURCE of inst : label is 0; attribute C_TX_USER_DATA_WIDTH : integer; attribute C_TX_USER_DATA_WIDTH of inst : label is 64; attribute C_TX_USRCLK2_FREQUENCY : string; attribute C_TX_USRCLK2_FREQUENCY of inst : label is "78.125000"; attribute C_TX_USRCLK_FREQUENCY : string; attribute C_TX_USRCLK_FREQUENCY of inst : label is "156.250000"; attribute C_USER_GTPOWERGOOD_DELAY_EN : integer; attribute C_USER_GTPOWERGOOD_DELAY_EN of inst : label is 0; begin dmonitorout_out(16) <= \\; dmonitorout_out(15) <= \\; dmonitorout_out(14) <= \\; dmonitorout_out(13) <= \\; dmonitorout_out(12) <= \\; dmonitorout_out(11) <= \\; dmonitorout_out(10) <= \\; dmonitorout_out(9) <= \\; dmonitorout_out(8) <= \\; dmonitorout_out(7) <= \\; dmonitorout_out(6) <= \\; dmonitorout_out(5) <= \\; dmonitorout_out(4) <= \\; dmonitorout_out(3) <= \\; dmonitorout_out(2) <= \\; dmonitorout_out(1) <= \\; dmonitorout_out(0) <= \\; eyescandataerror_out(0) <= \\; gtwiz_reset_rx_cdr_stable_out(0) <= \\; rxbufstatus_out(2) <= \^rxbufstatus_out\(2); rxbufstatus_out(1) <= \\; rxbufstatus_out(0) <= \\; rxdatavalid_out(1) <= \\; rxdatavalid_out(0) <= \^rxdatavalid_out\(0); rxheader_out(5) <= \\; rxheader_out(4) <= \\; rxheader_out(3) <= \\; rxheader_out(2) <= \\; rxheader_out(1 downto 0) <= \^rxheader_out\(1 downto 0); rxheadervalid_out(1) <= \\; rxheadervalid_out(0) <= \^rxheadervalid_out\(0); rxprbserr_out(0) <= \\; rxresetdone_out(0) <= \\; rxstartofseq_out(1) <= \\; rxstartofseq_out(0) <= \\; txbufstatus_out(1) <= \^txbufstatus_out\(1); txbufstatus_out(0) <= \\; txoutclkfabric_out(0) <= \\; txoutclkpcs_out(0) <= \\; txresetdone_out(0) <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_gtwizard_top port map ( bgbypassb_in(0) => '1', bgmonitorenb_in(0) => '1', bgpdb_in(0) => '1', bgrcalovrd_in(4 downto 0) => B"11111", bgrcalovrdenb_in(0) => '1', bufgtce_out(2 downto 0) => NLW_inst_bufgtce_out_UNCONNECTED(2 downto 0), bufgtcemask_out(2 downto 0) => NLW_inst_bufgtcemask_out_UNCONNECTED(2 downto 0), bufgtdiv_out(8 downto 0) => NLW_inst_bufgtdiv_out_UNCONNECTED(8 downto 0), bufgtreset_out(2 downto 0) => NLW_inst_bufgtreset_out_UNCONNECTED(2 downto 0), bufgtrstmask_out(2 downto 0) => NLW_inst_bufgtrstmask_out_UNCONNECTED(2 downto 0), cdrstepdir_in(0) => '0', cdrstepsq_in(0) => '0', cdrstepsx_in(0) => '0', cfgreset_in(0) => '0', clkrsvd0_in(0) => '0', clkrsvd1_in(0) => '0', cpllfbclklost_out(0) => NLW_inst_cpllfbclklost_out_UNCONNECTED(0), cpllfreqlock_in(0) => '0', cplllock_out(0) => cplllock_out(0), cplllockdetclk_in(0) => '0', cplllocken_in(0) => '1', cpllpd_in(0) => '0', cpllrefclklost_out(0) => NLW_inst_cpllrefclklost_out_UNCONNECTED(0), cpllrefclksel_in(2 downto 0) => B"001", cpllreset_in(0) => '0', dmonfiforeset_in(0) => '0', dmonitorclk_in(0) => '0', dmonitorout_out(16 downto 0) => NLW_inst_dmonitorout_out_UNCONNECTED(16 downto 0), dmonitoroutclk_out(0) => NLW_inst_dmonitoroutclk_out_UNCONNECTED(0), drpaddr_common_in(8 downto 0) => B"000000000", drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpclk_common_in(0) => '0', drpclk_in(0) => drpclk_in(0), drpdi_common_in(15 downto 0) => B"0000000000000000", drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_common_out(15 downto 0) => NLW_inst_drpdo_common_out_UNCONNECTED(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_common_in(0) => '0', drpen_in(0) => drpen_in(0), drprdy_common_out(0) => NLW_inst_drprdy_common_out_UNCONNECTED(0), drprdy_out(0) => drprdy_out(0), drprst_in(0) => '0', drpwe_common_in(0) => '0', drpwe_in(0) => drpwe_in(0), elpcaldvorwren_in(0) => '0', elpcalpaorwren_in(0) => '0', evoddphicaldone_in(0) => '0', evoddphicalstart_in(0) => '0', evoddphidrden_in(0) => '0', evoddphidwren_in(0) => '0', evoddphixrden_in(0) => '0', evoddphixwren_in(0) => '0', eyescandataerror_out(0) => NLW_inst_eyescandataerror_out_UNCONNECTED(0), eyescanmode_in(0) => '0', eyescanreset_in(0) => '0', eyescantrigger_in(0) => '0', freqos_in(0) => '0', gtgrefclk0_in(0) => '0', gtgrefclk1_in(0) => '0', gtgrefclk_in(0) => '0', gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtnorthrefclk00_in(0) => '0', gtnorthrefclk01_in(0) => '0', gtnorthrefclk0_in(0) => '0', gtnorthrefclk10_in(0) => '0', gtnorthrefclk11_in(0) => '0', gtnorthrefclk1_in(0) => '0', gtpowergood_out(0) => gtpowergood_out(0), gtrefclk00_in(0) => '0', gtrefclk01_in(0) => '0', gtrefclk0_in(0) => gtrefclk0_in(0), gtrefclk10_in(0) => '0', gtrefclk11_in(0) => '0', gtrefclk1_in(0) => '0', gtrefclkmonitor_out(0) => NLW_inst_gtrefclkmonitor_out_UNCONNECTED(0), gtresetsel_in(0) => '0', gtrsvd_in(15 downto 0) => B"0000000000000000", gtrxreset_in(0) => '0', gtrxresetsel_in(0) => '0', gtsouthrefclk00_in(0) => '0', gtsouthrefclk01_in(0) => '0', gtsouthrefclk0_in(0) => '0', gtsouthrefclk10_in(0) => '0', gtsouthrefclk11_in(0) => '0', gtsouthrefclk1_in(0) => '0', gttxreset_in(0) => '0', gttxresetsel_in(0) => '0', gtwiz_buffbypass_rx_done_out(0) => NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED(0), gtwiz_buffbypass_rx_error_out(0) => NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED(0), gtwiz_buffbypass_rx_reset_in(0) => '0', gtwiz_buffbypass_rx_start_user_in(0) => '0', gtwiz_buffbypass_tx_done_out(0) => NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED(0), gtwiz_buffbypass_tx_error_out(0) => NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED(0), gtwiz_buffbypass_tx_reset_in(0) => '0', gtwiz_buffbypass_tx_start_user_in(0) => '0', gtwiz_gthe3_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gthe3_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gthe3_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_gthe4_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gthe4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gthe4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_gtye4_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gtye4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gtye4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_reset_all_in(0) => '0', gtwiz_reset_clk_freerun_in(0) => '0', gtwiz_reset_qpll0lock_in(0) => '0', gtwiz_reset_qpll0reset_out(0) => NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED(0), gtwiz_reset_qpll1lock_in(0) => '0', gtwiz_reset_qpll1reset_out(0) => NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED(0), gtwiz_reset_rx_cdr_stable_out(0) => NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_in(0) => '0', gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0), gtwiz_reset_tx_datapath_in(0) => '0', gtwiz_reset_tx_done_in(0) => '0', gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0), gtwiz_userclk_rx_active_out(0) => NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED(0), gtwiz_userclk_rx_reset_in(0) => '0', gtwiz_userclk_rx_srcclk_out(0) => NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED(0), gtwiz_userclk_rx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED(0), gtwiz_userclk_rx_usrclk_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), gtwiz_userclk_tx_active_out(0) => NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED(0), gtwiz_userclk_tx_reset_in(0) => '0', gtwiz_userclk_tx_srcclk_out(0) => NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED(0), gtwiz_userclk_tx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED(0), gtwiz_userclk_tx_usrclk_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED(0), gtwiz_userdata_rx_out(31 downto 0) => gtwiz_userdata_rx_out(31 downto 0), gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0), gtyrxn_in(0) => '0', gtyrxp_in(0) => '0', gtytxn_out(0) => NLW_inst_gtytxn_out_UNCONNECTED(0), gtytxp_out(0) => NLW_inst_gtytxp_out_UNCONNECTED(0), incpctrl_in(0) => '0', loopback_in(2 downto 0) => loopback_in(2 downto 0), looprsvd_in(0) => '0', lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, lopt_4 => lopt_4, lopt_5 => lopt_5, lopt_6 => lopt_6, lopt_7 => lopt_7, lpbkrxtxseren_in(0) => '0', lpbktxrxseren_in(0) => '0', pcieeqrxeqadaptdone_in(0) => '0', pcierategen3_out(0) => NLW_inst_pcierategen3_out_UNCONNECTED(0), pcierateidle_out(0) => NLW_inst_pcierateidle_out_UNCONNECTED(0), pcierateqpll0_in(0) => '0', pcierateqpll1_in(0) => '0', pcierateqpllpd_out(1 downto 0) => NLW_inst_pcierateqpllpd_out_UNCONNECTED(1 downto 0), pcierateqpllreset_out(1 downto 0) => NLW_inst_pcierateqpllreset_out_UNCONNECTED(1 downto 0), pcierstidle_in(0) => '0', pciersttxsyncstart_in(0) => '0', pciesynctxsyncdone_out(0) => NLW_inst_pciesynctxsyncdone_out_UNCONNECTED(0), pcieusergen3rdy_out(0) => NLW_inst_pcieusergen3rdy_out_UNCONNECTED(0), pcieuserphystatusrst_out(0) => NLW_inst_pcieuserphystatusrst_out_UNCONNECTED(0), pcieuserratedone_in(0) => '0', pcieuserratestart_out(0) => NLW_inst_pcieuserratestart_out_UNCONNECTED(0), pcsrsvdin2_in(4 downto 0) => B"00000", pcsrsvdin_in(15 downto 0) => B"0000000000000000", pcsrsvdout_out(11 downto 0) => NLW_inst_pcsrsvdout_out_UNCONNECTED(11 downto 0), phystatus_out(0) => NLW_inst_phystatus_out_UNCONNECTED(0), pinrsrvdas_out(7 downto 0) => NLW_inst_pinrsrvdas_out_UNCONNECTED(7 downto 0), pmarsvd0_in(7 downto 0) => B"00000000", pmarsvd1_in(7 downto 0) => B"00000000", pmarsvdin_in(4 downto 0) => B"00000", pmarsvdout0_out(7 downto 0) => NLW_inst_pmarsvdout0_out_UNCONNECTED(7 downto 0), pmarsvdout1_out(7 downto 0) => NLW_inst_pmarsvdout1_out_UNCONNECTED(7 downto 0), powerpresent_out(0) => NLW_inst_powerpresent_out_UNCONNECTED(0), qpll0clk_in(0) => '0', qpll0clkrsvd0_in(0) => '0', qpll0clkrsvd1_in(0) => '0', qpll0fbclklost_out(0) => NLW_inst_qpll0fbclklost_out_UNCONNECTED(0), qpll0fbdiv_in(0) => '0', qpll0freqlock_in(0) => '0', qpll0lock_out(0) => NLW_inst_qpll0lock_out_UNCONNECTED(0), qpll0lockdetclk_in(0) => '0', qpll0locken_in(0) => '0', qpll0outclk_out(0) => NLW_inst_qpll0outclk_out_UNCONNECTED(0), qpll0outrefclk_out(0) => NLW_inst_qpll0outrefclk_out_UNCONNECTED(0), qpll0pd_in(0) => '1', qpll0refclk_in(0) => '0', qpll0refclklost_out(0) => NLW_inst_qpll0refclklost_out_UNCONNECTED(0), qpll0refclksel_in(2 downto 0) => B"001", qpll0reset_in(0) => '1', qpll1clk_in(0) => '0', qpll1clkrsvd0_in(0) => '0', qpll1clkrsvd1_in(0) => '0', qpll1fbclklost_out(0) => NLW_inst_qpll1fbclklost_out_UNCONNECTED(0), qpll1fbdiv_in(0) => '0', qpll1freqlock_in(0) => '0', qpll1lock_out(0) => NLW_inst_qpll1lock_out_UNCONNECTED(0), qpll1lockdetclk_in(0) => '0', qpll1locken_in(0) => '0', qpll1outclk_out(0) => NLW_inst_qpll1outclk_out_UNCONNECTED(0), qpll1outrefclk_out(0) => NLW_inst_qpll1outrefclk_out_UNCONNECTED(0), qpll1pd_in(0) => '1', qpll1refclk_in(0) => '0', qpll1refclklost_out(0) => NLW_inst_qpll1refclklost_out_UNCONNECTED(0), qpll1refclksel_in(2 downto 0) => B"001", qpll1reset_in(0) => '1', qplldmonitor0_out(7 downto 0) => NLW_inst_qplldmonitor0_out_UNCONNECTED(7 downto 0), qplldmonitor1_out(7 downto 0) => NLW_inst_qplldmonitor1_out_UNCONNECTED(7 downto 0), qpllrsvd1_in(7 downto 0) => B"00000000", qpllrsvd2_in(4 downto 0) => B"00000", qpllrsvd3_in(4 downto 0) => B"00000", qpllrsvd4_in(7 downto 0) => B"00000000", rcalenb_in(0) => '1', refclkoutmonitor0_out(0) => NLW_inst_refclkoutmonitor0_out_UNCONNECTED(0), refclkoutmonitor1_out(0) => NLW_inst_refclkoutmonitor1_out_UNCONNECTED(0), resetexception_out(0) => NLW_inst_resetexception_out_UNCONNECTED(0), resetovrd_in(0) => '0', rstclkentx_in(0) => '0', rx8b10ben_in(0) => '0', rxafecfoken_in(0) => '0', rxbufreset_in(0) => '0', rxbufstatus_out(2) => \^rxbufstatus_out\(2), rxbufstatus_out(1 downto 0) => NLW_inst_rxbufstatus_out_UNCONNECTED(1 downto 0), rxbyteisaligned_out(0) => NLW_inst_rxbyteisaligned_out_UNCONNECTED(0), rxbyterealign_out(0) => NLW_inst_rxbyterealign_out_UNCONNECTED(0), rxcdrfreqreset_in(0) => '0', rxcdrhold_in(0) => '0', rxcdrlock_out(0) => NLW_inst_rxcdrlock_out_UNCONNECTED(0), rxcdrovrden_in(0) => rxcdrovrden_in(0), rxcdrphdone_out(0) => NLW_inst_rxcdrphdone_out_UNCONNECTED(0), rxcdrreset_in(0) => '0', rxcdrresetrsv_in(0) => '0', rxchanbondseq_out(0) => NLW_inst_rxchanbondseq_out_UNCONNECTED(0), rxchanisaligned_out(0) => NLW_inst_rxchanisaligned_out_UNCONNECTED(0), rxchanrealign_out(0) => NLW_inst_rxchanrealign_out_UNCONNECTED(0), rxchbonden_in(0) => '0', rxchbondi_in(4 downto 0) => B"00000", rxchbondlevel_in(2 downto 0) => B"000", rxchbondmaster_in(0) => '0', rxchbondo_out(4 downto 0) => NLW_inst_rxchbondo_out_UNCONNECTED(4 downto 0), rxchbondslave_in(0) => '0', rxckcaldone_out(0) => NLW_inst_rxckcaldone_out_UNCONNECTED(0), rxckcalreset_in(0) => '0', rxckcalstart_in(0) => '0', rxclkcorcnt_out(1 downto 0) => NLW_inst_rxclkcorcnt_out_UNCONNECTED(1 downto 0), rxcominitdet_out(0) => NLW_inst_rxcominitdet_out_UNCONNECTED(0), rxcommadet_out(0) => NLW_inst_rxcommadet_out_UNCONNECTED(0), rxcommadeten_in(0) => '0', rxcomsasdet_out(0) => NLW_inst_rxcomsasdet_out_UNCONNECTED(0), rxcomwakedet_out(0) => NLW_inst_rxcomwakedet_out_UNCONNECTED(0), rxctrl0_out(15 downto 0) => NLW_inst_rxctrl0_out_UNCONNECTED(15 downto 0), rxctrl1_out(15 downto 0) => NLW_inst_rxctrl1_out_UNCONNECTED(15 downto 0), rxctrl2_out(7 downto 0) => NLW_inst_rxctrl2_out_UNCONNECTED(7 downto 0), rxctrl3_out(7 downto 0) => NLW_inst_rxctrl3_out_UNCONNECTED(7 downto 0), rxdata_out(127 downto 0) => NLW_inst_rxdata_out_UNCONNECTED(127 downto 0), rxdataextendrsvd_out(7 downto 0) => NLW_inst_rxdataextendrsvd_out_UNCONNECTED(7 downto 0), rxdatavalid_out(1) => NLW_inst_rxdatavalid_out_UNCONNECTED(1), rxdatavalid_out(0) => \^rxdatavalid_out\(0), rxdccforcestart_in(0) => '0', rxdfeagcctrl_in(1 downto 0) => B"01", rxdfeagchold_in(0) => '0', rxdfeagcovrden_in(0) => '0', rxdfecfokfcnum_in(0) => '0', rxdfecfokfen_in(0) => '0', rxdfecfokfpulse_in(0) => '0', rxdfecfokhold_in(0) => '0', rxdfecfokovren_in(0) => '0', rxdfekhhold_in(0) => '0', rxdfekhovrden_in(0) => '0', rxdfelfhold_in(0) => '0', rxdfelfovrden_in(0) => '0', rxdfelpmreset_in(0) => '0', rxdfetap10hold_in(0) => '0', rxdfetap10ovrden_in(0) => '0', rxdfetap11hold_in(0) => '0', rxdfetap11ovrden_in(0) => '0', rxdfetap12hold_in(0) => '0', rxdfetap12ovrden_in(0) => '0', rxdfetap13hold_in(0) => '0', rxdfetap13ovrden_in(0) => '0', rxdfetap14hold_in(0) => '0', rxdfetap14ovrden_in(0) => '0', rxdfetap15hold_in(0) => '0', rxdfetap15ovrden_in(0) => '0', rxdfetap2hold_in(0) => '0', rxdfetap2ovrden_in(0) => '0', rxdfetap3hold_in(0) => '0', rxdfetap3ovrden_in(0) => '0', rxdfetap4hold_in(0) => '0', rxdfetap4ovrden_in(0) => '0', rxdfetap5hold_in(0) => '0', rxdfetap5ovrden_in(0) => '0', rxdfetap6hold_in(0) => '0', rxdfetap6ovrden_in(0) => '0', rxdfetap7hold_in(0) => '0', rxdfetap7ovrden_in(0) => '0', rxdfetap8hold_in(0) => '0', rxdfetap8ovrden_in(0) => '0', rxdfetap9hold_in(0) => '0', rxdfetap9ovrden_in(0) => '0', rxdfeuthold_in(0) => '0', rxdfeutovrden_in(0) => '0', rxdfevphold_in(0) => '0', rxdfevpovrden_in(0) => '0', rxdfevsen_in(0) => '0', rxdfexyden_in(0) => '1', rxdlybypass_in(0) => '1', rxdlyen_in(0) => '0', rxdlyovrden_in(0) => '0', rxdlysreset_in(0) => '0', rxdlysresetdone_out(0) => NLW_inst_rxdlysresetdone_out_UNCONNECTED(0), rxelecidle_out(0) => NLW_inst_rxelecidle_out_UNCONNECTED(0), rxelecidlemode_in(1 downto 0) => B"11", rxeqtraining_in(0) => '0', rxgearboxslip_in(0) => rxgearboxslip_in(0), rxheader_out(5 downto 2) => NLW_inst_rxheader_out_UNCONNECTED(5 downto 2), rxheader_out(1 downto 0) => \^rxheader_out\(1 downto 0), rxheadervalid_out(1) => NLW_inst_rxheadervalid_out_UNCONNECTED(1), rxheadervalid_out(0) => \^rxheadervalid_out\(0), rxlatclk_in(0) => '0', rxlfpstresetdet_out(0) => NLW_inst_rxlfpstresetdet_out_UNCONNECTED(0), rxlfpsu2lpexitdet_out(0) => NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED(0), rxlfpsu3wakedet_out(0) => NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED(0), rxlpmen_in(0) => '0', rxlpmgchold_in(0) => '0', rxlpmgcovrden_in(0) => '0', rxlpmhfhold_in(0) => '0', rxlpmhfovrden_in(0) => '0', rxlpmlfhold_in(0) => '0', rxlpmlfklovrden_in(0) => '0', rxlpmoshold_in(0) => '0', rxlpmosovrden_in(0) => '0', rxmcommaalignen_in(0) => '0', rxmonitorout_out(6 downto 0) => NLW_inst_rxmonitorout_out_UNCONNECTED(6 downto 0), rxmonitorsel_in(1 downto 0) => B"00", rxoobreset_in(0) => '0', rxoscalreset_in(0) => '0', rxoshold_in(0) => '0', rxosintcfg_in(3 downto 0) => B"1101", rxosintdone_out(0) => NLW_inst_rxosintdone_out_UNCONNECTED(0), rxosinten_in(0) => '1', rxosinthold_in(0) => '0', rxosintovrden_in(0) => '0', rxosintstarted_out(0) => NLW_inst_rxosintstarted_out_UNCONNECTED(0), rxosintstrobe_in(0) => '0', rxosintstrobedone_out(0) => NLW_inst_rxosintstrobedone_out_UNCONNECTED(0), rxosintstrobestarted_out(0) => NLW_inst_rxosintstrobestarted_out_UNCONNECTED(0), rxosinttestovrden_in(0) => '0', rxosovrden_in(0) => '0', rxoutclk_out(0) => rxoutclk_out(0), rxoutclkfabric_out(0) => NLW_inst_rxoutclkfabric_out_UNCONNECTED(0), rxoutclkpcs_out(0) => NLW_inst_rxoutclkpcs_out_UNCONNECTED(0), rxoutclksel_in(2 downto 0) => B"010", rxpcommaalignen_in(0) => '0', rxpcsreset_in(0) => '0', rxpd_in(1 downto 0) => B"00", rxphalign_in(0) => '0', rxphaligndone_out(0) => NLW_inst_rxphaligndone_out_UNCONNECTED(0), rxphalignen_in(0) => '0', rxphalignerr_out(0) => NLW_inst_rxphalignerr_out_UNCONNECTED(0), rxphdlypd_in(0) => '1', rxphdlyreset_in(0) => '0', rxphovrden_in(0) => '0', rxpllclksel_in(1 downto 0) => B"00", rxpmareset_in(0) => '0', rxpmaresetdone_out(0) => rxpmaresetdone_out(0), rxpolarity_in(0) => rxpolarity_in(0), rxprbscntreset_in(0) => '0', rxprbserr_out(0) => NLW_inst_rxprbserr_out_UNCONNECTED(0), rxprbslocked_out(0) => NLW_inst_rxprbslocked_out_UNCONNECTED(0), rxprbssel_in(3 downto 0) => B"0000", rxprgdivresetdone_out(0) => NLW_inst_rxprgdivresetdone_out_UNCONNECTED(0), rxprogdivreset_in(0) => '0', rxqpien_in(0) => '0', rxqpisenn_out(0) => NLW_inst_rxqpisenn_out_UNCONNECTED(0), rxqpisenp_out(0) => NLW_inst_rxqpisenp_out_UNCONNECTED(0), rxrate_in(2 downto 0) => B"000", rxratedone_out(0) => NLW_inst_rxratedone_out_UNCONNECTED(0), rxratemode_in(0) => '0', rxrecclk0_sel_out(1 downto 0) => NLW_inst_rxrecclk0_sel_out_UNCONNECTED(1 downto 0), rxrecclk0sel_out(0) => NLW_inst_rxrecclk0sel_out_UNCONNECTED(0), rxrecclk1_sel_out(1 downto 0) => NLW_inst_rxrecclk1_sel_out_UNCONNECTED(1 downto 0), rxrecclk1sel_out(0) => NLW_inst_rxrecclk1sel_out_UNCONNECTED(0), rxrecclkout_out(0) => NLW_inst_rxrecclkout_out_UNCONNECTED(0), rxresetdone_out(0) => NLW_inst_rxresetdone_out_UNCONNECTED(0), rxslide_in(0) => '0', rxsliderdy_out(0) => NLW_inst_rxsliderdy_out_UNCONNECTED(0), rxslipdone_out(0) => NLW_inst_rxslipdone_out_UNCONNECTED(0), rxslipoutclk_in(0) => '0', rxslipoutclkrdy_out(0) => NLW_inst_rxslipoutclkrdy_out_UNCONNECTED(0), rxslippma_in(0) => '0', rxslippmardy_out(0) => NLW_inst_rxslippmardy_out_UNCONNECTED(0), rxstartofseq_out(1 downto 0) => NLW_inst_rxstartofseq_out_UNCONNECTED(1 downto 0), rxstatus_out(2 downto 0) => NLW_inst_rxstatus_out_UNCONNECTED(2 downto 0), rxsyncallin_in(0) => '0', rxsyncdone_out(0) => NLW_inst_rxsyncdone_out_UNCONNECTED(0), rxsyncin_in(0) => '0', rxsyncmode_in(0) => '0', rxsyncout_out(0) => NLW_inst_rxsyncout_out_UNCONNECTED(0), rxsysclksel_in(1 downto 0) => B"00", rxtermination_in(0) => '0', rxuserrdy_in(0) => '1', rxusrclk2_in(0) => rxusrclk2_in(0), rxusrclk_in(0) => rxusrclk_in(0), rxvalid_out(0) => NLW_inst_rxvalid_out_UNCONNECTED(0), sdm0data_in(0) => '0', sdm0finalout_out(0) => NLW_inst_sdm0finalout_out_UNCONNECTED(0), sdm0reset_in(0) => '0', sdm0testdata_out(0) => NLW_inst_sdm0testdata_out_UNCONNECTED(0), sdm0toggle_in(0) => '0', sdm0width_in(0) => '0', sdm1data_in(0) => '0', sdm1finalout_out(0) => NLW_inst_sdm1finalout_out_UNCONNECTED(0), sdm1reset_in(0) => '0', sdm1testdata_out(0) => NLW_inst_sdm1testdata_out_UNCONNECTED(0), sdm1toggle_in(0) => '0', sdm1width_in(0) => '0', sigvalidclk_in(0) => '0', tcongpi_in(0) => '0', tcongpo_out(0) => NLW_inst_tcongpo_out_UNCONNECTED(0), tconpowerup_in(0) => '0', tconreset_in(0) => '0', tconrsvdin1_in(0) => '0', tconrsvdout0_out(0) => NLW_inst_tconrsvdout0_out_UNCONNECTED(0), tstin_in(19 downto 0) => B"00000000000000000000", tx8b10bbypass_in(7 downto 0) => B"00000000", tx8b10ben_in(0) => '0', txbufdiffctrl_in(2 downto 0) => B"000", txbufstatus_out(1) => \^txbufstatus_out\(1), txbufstatus_out(0) => NLW_inst_txbufstatus_out_UNCONNECTED(0), txcomfinish_out(0) => NLW_inst_txcomfinish_out_UNCONNECTED(0), txcominit_in(0) => '0', txcomsas_in(0) => '0', txcomwake_in(0) => '0', txctrl0_in(15 downto 0) => B"0000000000000000", txctrl1_in(15 downto 0) => B"0000000000000000", txctrl2_in(7 downto 0) => B"00000000", txdata_in(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", txdataextendrsvd_in(7 downto 0) => B"00000000", txdccdone_out(0) => NLW_inst_txdccdone_out_UNCONNECTED(0), txdccforcestart_in(0) => '0', txdccreset_in(0) => '0', txdeemph_in(0) => '0', txdetectrx_in(0) => '0', txdiffctrl_in(3 downto 0) => B"1000", txdiffpd_in(0) => '0', txdlybypass_in(0) => '1', txdlyen_in(0) => '0', txdlyhold_in(0) => '0', txdlyovrden_in(0) => '0', txdlysreset_in(0) => '0', txdlysresetdone_out(0) => NLW_inst_txdlysresetdone_out_UNCONNECTED(0), txdlyupdown_in(0) => '0', txelecidle_in(0) => '0', txelforcestart_in(0) => '0', txheader_in(5 downto 2) => B"0000", txheader_in(1 downto 0) => txheader_in(1 downto 0), txinhibit_in(0) => '0', txlatclk_in(0) => '0', txlfpstreset_in(0) => '0', txlfpsu2lpexit_in(0) => '0', txlfpsu3wake_in(0) => '0', txmaincursor_in(6 downto 0) => B"1000000", txmargin_in(2 downto 0) => B"000", txmuxdcdexhold_in(0) => '0', txmuxdcdorwren_in(0) => '0', txoneszeros_in(0) => '0', txoutclk_out(0) => txoutclk_out(0), txoutclkfabric_out(0) => NLW_inst_txoutclkfabric_out_UNCONNECTED(0), txoutclkpcs_out(0) => NLW_inst_txoutclkpcs_out_UNCONNECTED(0), txoutclksel_in(2 downto 0) => B"010", txpcsreset_in(0) => '0', txpd_in(1 downto 0) => B"00", txpdelecidlemode_in(0) => '0', txphalign_in(0) => '0', txphaligndone_out(0) => NLW_inst_txphaligndone_out_UNCONNECTED(0), txphalignen_in(0) => '0', txphdlypd_in(0) => '1', txphdlyreset_in(0) => '0', txphdlytstclk_in(0) => '0', txphinit_in(0) => '0', txphinitdone_out(0) => NLW_inst_txphinitdone_out_UNCONNECTED(0), txphovrden_in(0) => '0', txpippmen_in(0) => '0', txpippmovrden_in(0) => '0', txpippmpd_in(0) => '0', txpippmsel_in(0) => '0', txpippmstepsize_in(4 downto 0) => B"00000", txpisopd_in(0) => '0', txpllclksel_in(1 downto 0) => B"00", txpmareset_in(0) => '0', txpmaresetdone_out(0) => txpmaresetdone_out(0), txpolarity_in(0) => '0', txpostcursor_in(4 downto 0) => B"00000", txpostcursorinv_in(0) => '0', txprbsforceerr_in(0) => '0', txprbssel_in(3 downto 0) => B"0000", txprecursor_in(4 downto 0) => B"00000", txprecursorinv_in(0) => '0', txprgdivresetdone_out(0) => NLW_inst_txprgdivresetdone_out_UNCONNECTED(0), txprogdivreset_in(0) => '0', txqpibiasen_in(0) => '0', txqpisenn_out(0) => NLW_inst_txqpisenn_out_UNCONNECTED(0), txqpisenp_out(0) => NLW_inst_txqpisenp_out_UNCONNECTED(0), txqpistrongpdown_in(0) => '0', txqpiweakpup_in(0) => '0', txrate_in(2 downto 0) => B"000", txratedone_out(0) => NLW_inst_txratedone_out_UNCONNECTED(0), txratemode_in(0) => '0', txresetdone_out(0) => NLW_inst_txresetdone_out_UNCONNECTED(0), txsequence_in(6 downto 0) => txsequence_in(6 downto 0), txswing_in(0) => '0', txsyncallin_in(0) => '0', txsyncdone_out(0) => NLW_inst_txsyncdone_out_UNCONNECTED(0), txsyncin_in(0) => '0', txsyncmode_in(0) => '0', txsyncout_out(0) => NLW_inst_txsyncout_out_UNCONNECTED(0), txsysclksel_in(1 downto 0) => B"00", txuserrdy_in(0) => '1', txusrclk2_in(0) => txusrclk2_in(0), txusrclk_in(0) => txusrclk_in(0), ubcfgstreamen_in(0) => '0', ubdaddr_out(0) => NLW_inst_ubdaddr_out_UNCONNECTED(0), ubden_out(0) => NLW_inst_ubden_out_UNCONNECTED(0), ubdi_out(0) => NLW_inst_ubdi_out_UNCONNECTED(0), ubdo_in(0) => '0', ubdrdy_in(0) => '0', ubdwe_out(0) => NLW_inst_ubdwe_out_UNCONNECTED(0), ubenable_in(0) => '0', ubgpi_in(0) => '0', ubintr_in(0) => '0', ubiolmbrst_in(0) => '0', ubmbrst_in(0) => '0', ubmdmcapture_in(0) => '0', ubmdmdbgrst_in(0) => '0', ubmdmdbgupdate_in(0) => '0', ubmdmregen_in(0) => '0', ubmdmshift_in(0) => '0', ubmdmsysrst_in(0) => '0', ubmdmtck_in(0) => '0', ubmdmtdi_in(0) => '0', ubmdmtdo_out(0) => NLW_inst_ubmdmtdo_out_UNCONNECTED(0), ubrsvdout_out(0) => NLW_inst_ubrsvdout_out_UNCONNECTED(0), ubtxuart_out(0) => NLW_inst_ubtxuart_out_UNCONNECTED(0) ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block SFoQ2tXDMrL2nCJbfpmHXuteJlKaWDWl3o9OY1miFvmYb8EDywmDpLUHQktJ/VoW+17fK5WHgFVI FZV1B91GDQ== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block mxGWDRjEAsKmBqldxevT1RKZvqK7vn0KlTODVXNGlRcGf9zOAmj0Z7Ppu79POBDb8oNQyCY+2q1q BddzhQfh5WLIVX9BNUMIF6M6IF0elM4GMSLHGeYEwqSaMPC+thuR8FGj1J7z6rH+43gDYhtIeyY+ ZuZUz/Pqg8Lu63Xwe+0= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block HLwPjQzkuqv5FEDBriEJS2DikBeIHB/bWuVWooHY5ChdoHatcmqCHpSvnGxVzLwObZWHFys2nR9y P3zxywjtgtOWq/n3cYVa5li6eyiUmGXv2OE8nw1nLnAY1kzBvGd6VwQ45t6l4Hx5+oqpIfuU2KI2 7/Qpj2atiTN3Y+q5He/BMXLIxF9vWuU6XL/+HsxriGAumcZDuESdidlxOztbW1bFhYr1/qWwou2q wynnRVKYHL41aWycgFdkDoDEFFxv8ft8+F5Ux+J5Hg5XdgRULJc6uUQE/lDG3zOqzPftlODB52zU d0cm8gFOvSZ2nO8ZB8THnxoAGe33iIZJfMcefA== `protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block jlR0iZ4fp9QXiFgaT07DMAK1YFLyBpsOGOOR9j2PWImFEh8oTBt4cvmGo+2z1Umbt9OMQwOhyepO QIsKLFzUXYUba+SFFLBoCiaww24KICecbUfd3VV5sg2bEJjAdtYTT6mJqyc3vQRvBlONeBFdIGy2 AXqdK7QtXGLsLAIF/z4FG8cfG6nSD6e16gccBC6+kl5MoShdnmebKLyoo6UKFdMbDK88sHvTcD9S LNCau6RK7FkTZg23FV0tf6cTP9Rray9YEcowm2AAh51Wldo2lGJ2W5iiDatRKH/W1bu7FGWZG+OT +VZE+Ckiuf4T6cuu+G5IbrtMv6a4U93R0gtxXQ== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block p/kq+JjPPJbOTWT2SRiPJ99/iH6kkVGEiluRRXpuRN+j+cVPgJD1v4QVjw3zMWLlvTGB7OOqC+JG Lc62Wiizd/BFfGj2JYkTZMatcOWok7A87HK+vRTjr4nZMApD2jKaneJdU1279KsIEeRfImCQ2uRl QRNMH3PPdNGYCnOGgNk= `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block kyyI/O29YYc5VBwhz19i7AV7MC75r43hHVKAOTBiGBhRu8zZxCwGGcNFqc2HgHcWC6nq4jCIbIXf S3FDzPdasegnERlWvoob9/SXM88zKsyeTbUf+DRu5lB8SPROBMaIhnj375C5XLowL17MXZdmB6fV X5ukCg7cNhCjssKt/bIJibWkfna7hvj4ye+CLWmi3LdEiix8KTwRoBS3ZJrjM4/N6FfZkXerVxs+ txkhdsmG9ga1g/xErhTRilhqrV2WetlpX86qH/64sRGVxrWeEfNoHhMZsqEK0jWDx4WavKt8XY7W NDzMXLZ2m5Dv5HMiJWgFG+ntPwgiYYtBuwu7Eg== `protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block tv6UL1ZWqo3dAIlhN5UTNGzJyqzdHpCqh217JPvIvHiWJgcFh2tw1n7HWnOPcK3VhCt31AGnCEFe HpTiinXvHna65L2X2HhtNUrsgvZlUuh/oQR273wp5JPFDPD97NQ4ELkGI+w26HTYLgZ70K5rQo87 D4AkQNRuzTRS5G12yb4RU7ZYgmkYLuq1UyqjlxyN62Del4XoqZyivOGw5H+7wlfkNRu98iQwqq12 jthZbH/ue5wxZJUcb7NmEwL+3abpyDNmWs1qORHOFoE3t97/9XMmeSCpM2+KnSKJvsV5VbuoTCOT 964fsEh7ey4IVb4aum095gQjLCqTmDm8DWFmaw== `protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block Oxo3AgNmVWgrXtMKDIThYfXr0YJfyFr7Bsjn2ge/G72mb25MA8Dbkd9ZZPtwqU1poazNnTng5Cx5 s8C1zMNEoo38jNY8zEUBjCCuasJgeMo5xsiha+3ZIBiuHS0KLrjLaPFIQZdsYevb44fg6J5YQLn5 jd1M6YdNMd1VwSezDxtbk9sN8ExPrmtwum/6L1ia9j9UlIzPTEaJ60Xz7tloPsgsbkborO2JLiIk kIAY2q1b8tuhHzJ5DoXlvIo49wSDj75ncLrkwbAd26huob7aOmX1bS34pJLF17JzqYH0MoPJbHxb RPdD+qUawXFsMSs2fOLnZrNxeG8L+TyAT0N8tQ== `protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block CIR/vwxo0IBrPr5+bMp2YuBCQTNBRIIbqgEB18Oewkc8CuHzGCAgPyQUBUKaUG3bBy+KDOPVxBP5 cE/d3QYZAT11fyB1OMMTrjmEIZcr0Vk3nVTAnivoxxxkmdzPjkj0OcGcU9fMArPi3dfTgIsKdtCq 94+mV/70WeprgijzuZFWD7uH+gVioY/+rq/Wc1O6x1n949w8YGgSCTurUvhsobx2bonoC317J0Wm IX17XRkSBIFgzqA8iC+GV5oCfxIGkihKmXxjIJbMamlOdCOycEkjkh3JYmm7TLNxmI65iffsabR0 t5+iI0l8eJxFhElzWeREqE43cnJYLaKZBUA+DA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1200) `protect data_block 9tJC3W5EdGweDFFcSDsO5rtMck5mxUF9yEHGI3yD68PuQ/mDzlVntfzSIcIrbvId6jM81OiEpTc3 VqNfNDbls2EdVNB8L3vmTCsgzwBgEi7S6GY27SGEsTbMJJtIBKn9M4GHzos9NQZL9NjqdD8TyH9E 8x+auwy4fpdMqEMf11hBv2pdz9ThAH10Qx3OhSScvpx7XN8ZD5BLfIXklkHQKznWbl4cVrrLTD2V /cd4i25RO0f6p2qwhvqlXtnE/5l4b0W5S4N907UEmTcqNU1KT6OBxbnzt9xJnL0SmxAaX2A6OJV/ AaLnMXVeooO2FQLq/M3+q/+WHf+niVAAAXr9Z29/cqwGjpKqDkWUaBQcJW4DKNbKjOC/tXuXPiXv Sxvf2ma+aUEfI/34g6VtXKE0J/GYrgB1QCxysviBQMmdMxSQPBG+VSQgxhmcyW3W9Fz+jXZYj6T0 YOFJNA6Tw7JxoKbPvpnrTjBZQ0i/oKDDZ1ornbd4fyvt5wcm0TbbctojJR1zkF9ocZrVKrck57mi mXwzNQgLmrN5FoC/o/mdKaTuV7G95v5ccZnBNLfcdmapvpj5TEiVPJ73n7shW5AnMPSQyLajhLWN kZX5xEGBtVNCMRqgzbaoRXJ18dgSZF41ignE9sVpceNlU12FEEtpkqd4sceOqA5H0pqpwbe9IpYJ y+/YpISu56klHlV3NA12GmqA+Un2LOt1n9KLtXBpXQ+v5n54ku6x+70VgXkCu+0UjRFU/+pe/ELc N4E11OcqikYumsOUXDILMHi1zU2PVNsYJ8kxjPEafcyEY6PgqUbmfCm2SA5el2Z+piwX9t0z8YxH h1rDLmEuIdhC3aZ19CX2BcMkTobIzgRpYC6AFECYO99rmD+YWAlYYUMgISWncSmQyqJM6SgnmKKK rivCWtZnrY8cGZ5KyAMT5EngVlDh0AB76Ygh0eBVfZRObDC9TGt5ekWIpC+W6em/3mAVVRhdULMe sjRjJmE7cfNLo8FLzxGWEt56C1S3LO/ndsBKg7VjW+ana7q1B6FcuKPcNsdTciA3kzXlsbS5lyCh q/o1YDg0I+SGHhx9y0s+f8QP0awnK4hA8ODdCBgV8V8Qy8Wo9l6XLyvq0oTxUf2uj0YkXmPsznRQ mRiEKeLGy0MsRBfChvMJIvkaR2urlE8IhddEz2M3ryg9vCnBcu66JhwaF6WYtz3RSxn8AC382RIA hYTPX87r94h96AfIMQACH6/l02FFAquEtV7VzmUKNgNYvinpTilcmtgFLzMWez6wCQvDm34u3iqa dKuUSQBOwmhoTFsyCmSUPZx78500dw1yhHizeEllhbMw1Eeya8nrizWmFHGxGflYNMVzNW/TIz7c 90WwBs6wfWh4H2dpKTsQeF6Nr1er2vuqXAlCeooEiTNv2+YjSy2fqRtgHTsGb+yO+jjKBRKAyZ0H 6krxIEDBaohJBIKPQ15Ij1r17OzxqS/vDPEm9ldSlxT+JPhcNQ3O17W26Fyp1pGWZqj/goSyCrba 2VR2/vbiNzZzb1PUTu+4dvGN8g7sAziCplLxUI4udBcZNMGHiz54vjXo4IViNy5hbkEzpg9Hq2Y3 sziw `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT is port ( gtwiz_userclk_rx_usrclk_out : out STD_LOGIC; gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 31 downto 0 ); cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gt0_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drprdy : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); init_clk_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); tx_out_clk : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); bufg_gt_clr_out : out STD_LOGIC; rst_in_out_reg : in STD_LOGIC; rst_in_out_reg_0 : in STD_LOGIC; SCRAMBLED_DATA_OUT : in STD_LOGIC_VECTOR ( 63 downto 0 ); gt0_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); init_clk : in STD_LOGIC; gt0_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drpen : in STD_LOGIC; gt0_drpwe : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; refclk1_in : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); gt_rxcdrovrden_in : in STD_LOGIC; i_in_meta_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); i_in_meta_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); i_in_meta_reg_1 : in STD_LOGIC_VECTOR ( 6 downto 0 ); sync_clk_out : in STD_LOGIC; rst_in_out_reg_1 : in STD_LOGIC; mmcm_not_locked_out2 : in STD_LOGIC; lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal aurora_64b66b_0_gt_i_n_87 : STD_LOGIC; signal aurora_64b66b_0_gt_i_n_88 : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[4]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[5]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[7]\ : STD_LOGIC; signal \fabric_pcs_rst_extend_cntr_reg_n_0_[8]\ : STD_LOGIC; signal gtwiz_userclk_rx_active_out : STD_LOGIC; signal gtwiz_userclk_rx_reset_in : STD_LOGIC; signal gtwiz_userclk_rx_reset_in_r : STD_LOGIC; signal \^gtwiz_userclk_rx_usrclk_out\ : STD_LOGIC; signal gtwiz_userclk_tx_active_in : STD_LOGIC; signal gtx_rx_pcsreset_comb : STD_LOGIC; signal \^lopt\ : STD_LOGIC; signal \^lopt_1\ : STD_LOGIC; signal \^lopt_2\ : STD_LOGIC; signal \^lopt_3\ : STD_LOGIC; signal lopt_4 : STD_LOGIC; signal lopt_5 : STD_LOGIC; signal lopt_6 : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \p_0_in__10\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal txpmaresetdone_out : STD_LOGIC; signal ultrascale_rx_userclk_n_1 : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr[7]_i_4_n_0\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[4]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[5]\ : STD_LOGIC; signal \usrclk_rx_active_in_extend_cntr_reg_n_0_[6]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr[7]_i_3_n_0\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[4]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[5]\ : STD_LOGIC; signal \usrclk_tx_active_in_extend_cntr_reg_n_0_[6]\ : STD_LOGIC; signal NLW_aurora_64b66b_0_gt_i_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); signal NLW_aurora_64b66b_0_gt_i_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_aurora_64b66b_0_gt_i_rxdatavalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_aurora_64b66b_0_gt_i_rxheader_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 2 ); signal NLW_aurora_64b66b_0_gt_i_rxheadervalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_aurora_64b66b_0_gt_i_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_rxresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_rxstartofseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_aurora_64b66b_0_gt_i_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aurora_64b66b_0_gt_i_txresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of aurora_64b66b_0_gt_i : label is "aurora_64b66b_0_gt,aurora_64b66b_0_gt_gtwizard_top,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of aurora_64b66b_0_gt_i : label is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of aurora_64b66b_0_gt_i : label is "aurora_64b66b_0_gt_gtwizard_top,Vivado 2020.2"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[1]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[2]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[3]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[4]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[7]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \fabric_pcs_rst_extend_cntr[8]_i_1\ : label is "soft_lutpair28"; attribute inverted : string; attribute inverted of \fabric_pcs_rst_extend_cntr_reg[9]_inv\ : label is "yes"; attribute DowngradeIPIdentifiedWarnings of ultrascale_rx_userclk : label is "yes"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of ultrascale_rx_userclk : label is "soft"; attribute P_CONTENTS : integer; attribute P_CONTENTS of ultrascale_rx_userclk : label is 0; attribute P_FREQ_RATIO_SOURCE_TO_USRCLK : integer; attribute P_FREQ_RATIO_SOURCE_TO_USRCLK of ultrascale_rx_userclk : label is 1; attribute P_FREQ_RATIO_USRCLK_TO_USRCLK2 : integer; attribute P_FREQ_RATIO_USRCLK_TO_USRCLK2 of ultrascale_rx_userclk : label is 1; attribute P_USRCLK2_DIV : string; attribute P_USRCLK2_DIV of ultrascale_rx_userclk : label is "3'b000"; attribute P_USRCLK2_INT_DIV : integer; attribute P_USRCLK2_INT_DIV of ultrascale_rx_userclk : label is 0; attribute P_USRCLK_DIV : string; attribute P_USRCLK_DIV of ultrascale_rx_userclk : label is "3'b000"; attribute P_USRCLK_INT_DIV : integer; attribute P_USRCLK_INT_DIV of ultrascale_rx_userclk : label is 0; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[2]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[3]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[4]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[6]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \usrclk_rx_active_in_extend_cntr[7]_i_2\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[1]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[2]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[3]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[4]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[6]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \usrclk_tx_active_in_extend_cntr[7]_i_2\ : label is "soft_lutpair33"; begin E(0) <= \^e\(0); \^lopt_3\ <= lopt; gtwiz_userclk_rx_usrclk_out <= \^gtwiz_userclk_rx_usrclk_out\; lopt_2 <= lopt_5; lopt_3 <= lopt_6; lopt_4 <= lopt_1; \out\(0) <= \^out\(0); aurora_64b66b_0_gt_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt port map ( cplllock_out(0) => cplllock_out(0), dmonitorout_out(16 downto 0) => NLW_aurora_64b66b_0_gt_i_dmonitorout_out_UNCONNECTED(16 downto 0), drpaddr_in(8 downto 0) => gt0_drpaddr(8 downto 0), drpclk_in(0) => init_clk, drpdi_in(15 downto 0) => gt0_drpdi(15 downto 0), drpdo_out(15 downto 0) => gt0_drpdo(15 downto 0), drpen_in(0) => gt0_drpen, drprdy_out(0) => gt0_drprdy, drpwe_in(0) => gt0_drpwe, eyescandataerror_out(0) => NLW_aurora_64b66b_0_gt_i_eyescandataerror_out_UNCONNECTED(0), eyescanreset_in(0) => '0', eyescantrigger_in(0) => '0', gthrxn_in(0) => rxn, gthrxp_in(0) => rxp, gthtxn_out(0) => txn, gthtxp_out(0) => txp, gtpowergood_out(0) => gt_powergood(0), gtrefclk0_in(0) => refclk1_in, gtwiz_reset_all_in(0) => '0', gtwiz_reset_clk_freerun_in(0) => '0', gtwiz_reset_rx_cdr_stable_out(0) => NLW_aurora_64b66b_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED(0), gtwiz_reset_rx_datapath_in(0) => rst_in_out_reg_0, gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_rx_pll_and_datapath_in(0) => rst_in_out_reg, gtwiz_reset_tx_datapath_in(0) => '0', gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_userclk_rx_active_in(0) => \^out\(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in, gtwiz_userdata_rx_out(31 downto 0) => D(31 downto 0), gtwiz_userdata_tx_in(63 downto 0) => SCRAMBLED_DATA_OUT(63 downto 0), loopback_in(2 downto 0) => loopback(2 downto 0), lopt => \^lopt\, lopt_1 => gtwiz_userclk_rx_reset_in_r, lopt_2 => \^lopt_1\, lopt_3 => \^lopt_2\, lopt_4 => \^lopt_3\, lopt_5 => lopt_4, lopt_6 => lopt_5, lopt_7 => lopt_6, pcsrsvdin_in(15 downto 0) => B"0000000000000000", rxbufreset_in(0) => '0', rxbufstatus_out(2) => rxbufstatus_out(0), rxbufstatus_out(1 downto 0) => NLW_aurora_64b66b_0_gt_i_rxbufstatus_out_UNCONNECTED(1 downto 0), rxcdrhold_in(0) => '0', rxcdrovrden_in(0) => gt_rxcdrovrden_in, rxdatavalid_out(1) => NLW_aurora_64b66b_0_gt_i_rxdatavalid_out_UNCONNECTED(1), rxdatavalid_out(0) => rxdatavalid_out(0), rxdfelpmreset_in(0) => '0', rxgearboxslip_in(0) => i_in_meta_reg(0), rxheader_out(5 downto 2) => NLW_aurora_64b66b_0_gt_i_rxheader_out_UNCONNECTED(5 downto 2), rxheader_out(1 downto 0) => init_clk_0(1 downto 0), rxheadervalid_out(1) => NLW_aurora_64b66b_0_gt_i_rxheadervalid_out_UNCONNECTED(1), rxheadervalid_out(0) => rxheadervalid_out(0), rxlpmen_in(0) => '0', rxoutclk_out(0) => aurora_64b66b_0_gt_i_n_87, rxpcsreset_in(0) => '0', rxpmareset_in(0) => '0', rxpmaresetdone_out(0) => aurora_64b66b_0_gt_i_n_88, rxpolarity_in(0) => i_in_meta_reg_0, rxprbscntreset_in(0) => '0', rxprbserr_out(0) => NLW_aurora_64b66b_0_gt_i_rxprbserr_out_UNCONNECTED(0), rxprbssel_in(3 downto 0) => B"0000", rxresetdone_out(0) => NLW_aurora_64b66b_0_gt_i_rxresetdone_out_UNCONNECTED(0), rxstartofseq_out(1 downto 0) => NLW_aurora_64b66b_0_gt_i_rxstartofseq_out_UNCONNECTED(1 downto 0), rxusrclk2_in(0) => ultrascale_rx_userclk_n_1, rxusrclk_in(0) => \^gtwiz_userclk_rx_usrclk_out\, txbufstatus_out(1) => txbufstatus_out(0), txbufstatus_out(0) => NLW_aurora_64b66b_0_gt_i_txbufstatus_out_UNCONNECTED(0), txdiffctrl_in(3 downto 0) => B"1000", txheader_in(5 downto 2) => B"0000", txheader_in(1 downto 0) => Q(1 downto 0), txinhibit_in(0) => '0', txoutclk_out(0) => tx_out_clk, txoutclkfabric_out(0) => NLW_aurora_64b66b_0_gt_i_txoutclkfabric_out_UNCONNECTED(0), txoutclkpcs_out(0) => NLW_aurora_64b66b_0_gt_i_txoutclkpcs_out_UNCONNECTED(0), txpcsreset_in(0) => '0', txpmareset_in(0) => '0', txpmaresetdone_out(0) => txpmaresetdone_out, txpolarity_in(0) => '0', txpostcursor_in(4 downto 0) => B"00000", txprbsforceerr_in(0) => '0', txprbssel_in(3 downto 0) => B"0000", txprecursor_in(4 downto 0) => B"00000", txresetdone_out(0) => NLW_aurora_64b66b_0_gt_i_txresetdone_out_UNCONNECTED(0), txsequence_in(6 downto 0) => i_in_meta_reg_1(6 downto 0), txusrclk2_in(0) => rst_in_out_reg_1, txusrclk_in(0) => sync_clk_out ); \fabric_pcs_rst_extend_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, O => \p_0_in__1\(0) ); \fabric_pcs_rst_extend_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, O => \p_0_in__1\(1) ); \fabric_pcs_rst_extend_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\, O => \p_0_in__1\(2) ); \fabric_pcs_rst_extend_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\, O => \p_0_in__1\(3) ); \fabric_pcs_rst_extend_cntr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\, I4 => \fabric_pcs_rst_extend_cntr_reg_n_0_[4]\, O => \p_0_in__1\(4) ); \fabric_pcs_rst_extend_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[4]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, I4 => \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\, I5 => \fabric_pcs_rst_extend_cntr_reg_n_0_[5]\, O => \p_0_in__1\(5) ); \fabric_pcs_rst_extend_cntr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\, O => \p_0_in__1\(6) ); \fabric_pcs_rst_extend_cntr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\, I1 => \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[7]\, O => \p_0_in__1\(7) ); \fabric_pcs_rst_extend_cntr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[7]\, I1 => \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[8]\, O => \p_0_in__1\(8) ); \fabric_pcs_rst_extend_cntr[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[4]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\, I2 => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\, I4 => \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\, I5 => \fabric_pcs_rst_extend_cntr_reg_n_0_[5]\, O => \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\ ); \fabric_pcs_rst_extend_cntr[9]_inv_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F7FF" ) port map ( I0 => \fabric_pcs_rst_extend_cntr_reg_n_0_[8]\, I1 => \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\, I2 => \fabric_pcs_rst_extend_cntr[8]_i_2_n_0\, I3 => \fabric_pcs_rst_extend_cntr_reg_n_0_[7]\, O => \p_0_in__1\(9) ); \fabric_pcs_rst_extend_cntr_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(0), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[0]\ ); \fabric_pcs_rst_extend_cntr_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(1), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[1]\ ); \fabric_pcs_rst_extend_cntr_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(2), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[2]\ ); \fabric_pcs_rst_extend_cntr_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(3), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[3]\ ); \fabric_pcs_rst_extend_cntr_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(4), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[4]\ ); \fabric_pcs_rst_extend_cntr_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(5), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[5]\ ); \fabric_pcs_rst_extend_cntr_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(6), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[6]\ ); \fabric_pcs_rst_extend_cntr_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(7), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[7]\ ); \fabric_pcs_rst_extend_cntr_reg[8]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), CLR => mmcm_not_locked_out2, D => \p_0_in__1\(8), Q => \fabric_pcs_rst_extend_cntr_reg_n_0_[8]\ ); \fabric_pcs_rst_extend_cntr_reg[9]_inv\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rst_in_out_reg_1, CE => \^e\(0), D => \p_0_in__1\(9), PRE => mmcm_not_locked_out2, Q => \^e\(0) ); \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => txpmaresetdone_out, O => bufg_gt_clr_out ); gtwiz_userclk_rx_reset_in_r_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aurora_64b66b_0_gt_i_n_88, O => gtwiz_userclk_rx_reset_in ); gtwiz_userclk_rx_reset_in_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => gtwiz_userclk_rx_reset_in, Q => gtwiz_userclk_rx_reset_in_r, R => '0' ); ultrascale_rx_userclk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ultrascale_rx_userclk port map ( gtwiz_reset_clk_freerun_in => '0', gtwiz_userclk_rx_active_out => gtwiz_userclk_rx_active_out, gtwiz_userclk_rx_reset_in => gtwiz_userclk_rx_reset_in_r, gtwiz_userclk_rx_srcclk_in => aurora_64b66b_0_gt_i_n_87, gtwiz_userclk_rx_usrclk2_out => ultrascale_rx_userclk_n_1, gtwiz_userclk_rx_usrclk_out => \^gtwiz_userclk_rx_usrclk_out\, lopt => \^lopt\, lopt_1 => \^lopt_1\, lopt_2 => \^lopt_2\ ); \usrclk_rx_active_in_extend_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, O => \p_0_in__10\(0) ); \usrclk_rx_active_in_extend_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, O => \p_0_in__10\(1) ); \usrclk_rx_active_in_extend_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, I2 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\, O => \p_0_in__10\(2) ); \usrclk_rx_active_in_extend_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I2 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\, I3 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\, O => \p_0_in__10\(3) ); \usrclk_rx_active_in_extend_cntr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I2 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, I3 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\, I4 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[4]\, O => \p_0_in__10\(4) ); \usrclk_rx_active_in_extend_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, I2 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I3 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\, I4 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[4]\, I5 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[5]\, O => \p_0_in__10\(5) ); \usrclk_rx_active_in_extend_cntr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr[7]_i_4_n_0\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[6]\, O => \p_0_in__10\(6) ); \usrclk_rx_active_in_extend_cntr[7]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^out\(0), O => gtx_rx_pcsreset_comb ); \usrclk_rx_active_in_extend_cntr[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr[7]_i_4_n_0\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[6]\, O => \p_0_in__10\(7) ); \usrclk_rx_active_in_extend_cntr[7]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gtwiz_userclk_rx_active_out, O => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\ ); \usrclk_rx_active_in_extend_cntr[7]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[5]\, I1 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\, I2 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\, I3 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\, I4 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\, I5 => \usrclk_rx_active_in_extend_cntr_reg_n_0_[4]\, O => \usrclk_rx_active_in_extend_cntr[7]_i_4_n_0\ ); \usrclk_rx_active_in_extend_cntr_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(0), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[0]\ ); \usrclk_rx_active_in_extend_cntr_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(1), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[1]\ ); \usrclk_rx_active_in_extend_cntr_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(2), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[2]\ ); \usrclk_rx_active_in_extend_cntr_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(3), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[3]\ ); \usrclk_rx_active_in_extend_cntr_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(4), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[4]\ ); \usrclk_rx_active_in_extend_cntr_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(5), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[5]\ ); \usrclk_rx_active_in_extend_cntr_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(6), Q => \usrclk_rx_active_in_extend_cntr_reg_n_0_[6]\ ); \usrclk_rx_active_in_extend_cntr_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => ultrascale_rx_userclk_n_1, CE => gtx_rx_pcsreset_comb, CLR => \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0\, D => \p_0_in__10\(7), Q => \^out\(0) ); \usrclk_tx_active_in_extend_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, O => \p_0_in__2\(0) ); \usrclk_tx_active_in_extend_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, O => \p_0_in__2\(1) ); \usrclk_tx_active_in_extend_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I2 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\, O => \p_0_in__2\(2) ); \usrclk_tx_active_in_extend_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I2 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, I3 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\, O => \p_0_in__2\(3) ); \usrclk_tx_active_in_extend_cntr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, I2 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I3 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\, I4 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[4]\, O => \p_0_in__2\(4) ); \usrclk_tx_active_in_extend_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[4]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\, I2 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I3 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, I4 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\, I5 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[5]\, O => \p_0_in__2\(5) ); \usrclk_tx_active_in_extend_cntr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr[7]_i_3_n_0\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[6]\, O => \p_0_in__2\(6) ); \usrclk_tx_active_in_extend_cntr[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^e\(0), I1 => gtwiz_userclk_tx_active_in, O => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\ ); \usrclk_tx_active_in_extend_cntr[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[6]\, I1 => \usrclk_tx_active_in_extend_cntr[7]_i_3_n_0\, O => \p_0_in__2\(7) ); \usrclk_tx_active_in_extend_cntr[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[4]\, I1 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\, I2 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\, I3 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\, I4 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\, I5 => \usrclk_tx_active_in_extend_cntr_reg_n_0_[5]\, O => \usrclk_tx_active_in_extend_cntr[7]_i_3_n_0\ ); \usrclk_tx_active_in_extend_cntr_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(0), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[0]\ ); \usrclk_tx_active_in_extend_cntr_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(1), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[1]\ ); \usrclk_tx_active_in_extend_cntr_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(2), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[2]\ ); \usrclk_tx_active_in_extend_cntr_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(3), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[3]\ ); \usrclk_tx_active_in_extend_cntr_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(4), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[4]\ ); \usrclk_tx_active_in_extend_cntr_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(5), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[5]\ ); \usrclk_tx_active_in_extend_cntr_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(6), Q => \usrclk_tx_active_in_extend_cntr_reg_n_0_[6]\ ); \usrclk_tx_active_in_extend_cntr_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rst_in_out_reg_1, CE => \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0\, CLR => mmcm_not_locked_out2, D => \p_0_in__2\(7), Q => gtwiz_userclk_tx_active_in ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block SFoQ2tXDMrL2nCJbfpmHXuteJlKaWDWl3o9OY1miFvmYb8EDywmDpLUHQktJ/VoW+17fK5WHgFVI FZV1B91GDQ== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block mxGWDRjEAsKmBqldxevT1RKZvqK7vn0KlTODVXNGlRcGf9zOAmj0Z7Ppu79POBDb8oNQyCY+2q1q BddzhQfh5WLIVX9BNUMIF6M6IF0elM4GMSLHGeYEwqSaMPC+thuR8FGj1J7z6rH+43gDYhtIeyY+ ZuZUz/Pqg8Lu63Xwe+0= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block 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GcrDTLZ0+XgpS5c7z2Jux4QmPXvyoJDb517r3aOZLzbpryWD7qmS79W6mvKWVGjXffZqfuRQ00vc stosj6q/ZKynauqebYsjB5qygCI0W7I9w3kA5OSVll6XJj0WUQeXGaelV3c8gsAkoFc1aX1kmnRg yUf9tBguLX9J4xwZGCDbV77G7leu7iaMhGBmvn+Drl0wwZ0x9nzgats/dD+xw+TbX8KAsdhcEiuZ 1IY9TOFD5jrx5E+yzzbSxtLpX2p8WQX6pnrh2QabSkZjJg/8FE8nUlZZGXlgvtgEGLYcmXyT1r4G jk99fE/klshNw0H52sYge0pRHpvS8w/hRoUIPunnytrlpASFTikcPDolEfvg1wuDjUdcxuJpCD9Z uT1MQ/knG+XsLF5xBWMntwKBPJZU9cx7yZugf+nYPOLCTtssY8BpDMcX7CdmnH572E+aKIDNSI2c wB+Kv4VRuU4tt/VvE2SNMJIWhxX9uWs59dyk5rg3j+Bu4PMbXsmnm7HCyEhGLqIivcfcnC8Aqw0K ezLHzXHRe1nQIWR0lqaRazLZ5eMebnfbPZZiWZEu/gCW5Y7PQ2FVanwpUetEQiRDamzjQOMXJLeN WXiB6yUNWwpCSo6UElK4TSgoQZFLgfPoumMcZbdvviVtHPOn4+de5jug14AcxUhZJwD0YF5sZCo3 2nOyF733k/K/QPUC4rzYLsrUWKj8rEia6/oP0jpBbZf4m5ZCyYcO7uV6ZXqGe9BF897CgSY= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master is port ( srst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 71 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 71 downto 0 ); full : out STD_LOGIC; overflow : out STD_LOGIC; empty : out STD_LOGIC; underflow : out STD_LOGIC; prog_full : out STD_LOGIC; prog_empty : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; rd_rst_busy : out STD_LOGIC ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master : entity is "aurora_64b66b_0_fifo_gen_master,fifo_generator_v13_2_5,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master : entity is "fifo_generator_v13_2_5,Vivado 2020.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master is signal \\ : STD_LOGIC; signal \^dout\ : STD_LOGIC_VECTOR ( 68 downto 0 ); signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_valid_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_U0_dout_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 66 ); signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0; attribute C_APPLICATION_TYPE_AXIS : integer; attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0; attribute C_APPLICATION_TYPE_RACH : integer; attribute C_APPLICATION_TYPE_RACH of U0 : label is 0; attribute C_APPLICATION_TYPE_RDCH : integer; attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WACH : integer; attribute C_APPLICATION_TYPE_WACH of U0 : label is 0; attribute C_APPLICATION_TYPE_WDCH : integer; attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WRCH : integer; attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0; attribute C_AXIS_TDATA_WIDTH : integer; attribute C_AXIS_TDATA_WIDTH of U0 : label is 8; attribute C_AXIS_TDEST_WIDTH : integer; attribute C_AXIS_TDEST_WIDTH of U0 : label is 1; attribute C_AXIS_TID_WIDTH : integer; attribute C_AXIS_TID_WIDTH of U0 : label is 1; attribute C_AXIS_TKEEP_WIDTH : integer; attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1; attribute C_AXIS_TSTRB_WIDTH : integer; attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1; attribute C_AXIS_TUSER_WIDTH : integer; attribute C_AXIS_TUSER_WIDTH of U0 : label is 4; attribute C_AXIS_TYPE : integer; attribute C_AXIS_TYPE of U0 : label is 0; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of U0 : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of U0 : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of U0 : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of U0 : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of U0 : label is 64; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 1; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of U0 : label is 8; attribute C_AXI_LOCK_WIDTH : integer; attribute C_AXI_LOCK_WIDTH of U0 : label is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of U0 : label is 1; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of U0 : label is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of U0 : label is 0; attribute C_COUNT_TYPE : integer; attribute C_COUNT_TYPE of U0 : label is 0; attribute C_DATA_COUNT_WIDTH : integer; attribute C_DATA_COUNT_WIDTH of U0 : label is 9; attribute C_DEFAULT_VALUE : string; attribute C_DEFAULT_VALUE of U0 : label is "BlankString"; attribute C_DIN_WIDTH : integer; attribute C_DIN_WIDTH of U0 : label is 72; attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of U0 : label is 1; attribute C_DIN_WIDTH_RACH : integer; attribute C_DIN_WIDTH_RACH of U0 : label is 32; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of U0 : label is 64; attribute C_DIN_WIDTH_WACH : integer; attribute C_DIN_WIDTH_WACH of U0 : label is 1; attribute C_DIN_WIDTH_WDCH : integer; attribute C_DIN_WIDTH_WDCH of U0 : label is 64; attribute C_DIN_WIDTH_WRCH : integer; attribute C_DIN_WIDTH_WRCH of U0 : label is 2; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of U0 : label is "0"; attribute C_DOUT_WIDTH : integer; attribute C_DOUT_WIDTH of U0 : label is 72; attribute C_ENABLE_RLOCS : integer; attribute C_ENABLE_RLOCS of U0 : label is 0; attribute C_ENABLE_RST_SYNC : integer; attribute C_ENABLE_RST_SYNC of U0 : label is 1; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE : integer; attribute C_ERROR_INJECTION_TYPE of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "kintexu"; attribute C_FULL_FLAGS_RST_VAL : integer; attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0; attribute C_HAS_ALMOST_EMPTY : integer; attribute C_HAS_ALMOST_EMPTY of U0 : label is 0; attribute C_HAS_ALMOST_FULL : integer; attribute C_HAS_ALMOST_FULL of U0 : label is 0; attribute C_HAS_AXIS_TDATA : integer; attribute C_HAS_AXIS_TDATA of U0 : label is 1; attribute C_HAS_AXIS_TDEST : integer; attribute C_HAS_AXIS_TDEST of U0 : label is 0; attribute C_HAS_AXIS_TID : integer; attribute C_HAS_AXIS_TID of U0 : label is 0; attribute C_HAS_AXIS_TKEEP : integer; attribute C_HAS_AXIS_TKEEP of U0 : label is 0; attribute C_HAS_AXIS_TLAST : integer; attribute C_HAS_AXIS_TLAST of U0 : label is 0; attribute C_HAS_AXIS_TREADY : integer; attribute C_HAS_AXIS_TREADY of U0 : label is 1; attribute C_HAS_AXIS_TSTRB : integer; attribute C_HAS_AXIS_TSTRB of U0 : label is 0; attribute C_HAS_AXIS_TUSER : integer; attribute C_HAS_AXIS_TUSER of U0 : label is 1; attribute C_HAS_AXI_ARUSER : integer; attribute C_HAS_AXI_ARUSER of U0 : label is 0; attribute C_HAS_AXI_AWUSER : integer; attribute C_HAS_AXI_AWUSER of U0 : label is 0; attribute C_HAS_AXI_BUSER : integer; attribute C_HAS_AXI_BUSER of U0 : label is 0; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_RUSER : integer; attribute C_HAS_AXI_RUSER of U0 : label is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_WUSER : integer; attribute C_HAS_AXI_WUSER of U0 : label is 0; attribute C_HAS_BACKUP : integer; attribute C_HAS_BACKUP of U0 : label is 0; attribute C_HAS_DATA_COUNT : integer; attribute C_HAS_DATA_COUNT of U0 : label is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0; attribute C_HAS_INT_CLK : integer; attribute C_HAS_INT_CLK of U0 : label is 0; attribute C_HAS_MASTER_CE : integer; attribute C_HAS_MASTER_CE of U0 : label is 0; attribute C_HAS_MEMINIT_FILE : integer; attribute C_HAS_MEMINIT_FILE of U0 : label is 0; attribute C_HAS_OVERFLOW : integer; attribute C_HAS_OVERFLOW of U0 : label is 1; attribute C_HAS_PROG_FLAGS_AXIS : integer; attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0; attribute C_HAS_RD_DATA_COUNT : integer; attribute C_HAS_RD_DATA_COUNT of U0 : label is 0; attribute C_HAS_RD_RST : integer; attribute C_HAS_RD_RST of U0 : label is 0; attribute C_HAS_RST : integer; attribute C_HAS_RST of U0 : label is 0; attribute C_HAS_SLAVE_CE : integer; attribute C_HAS_SLAVE_CE of U0 : label is 0; attribute C_HAS_SRST : integer; attribute C_HAS_SRST of U0 : label is 1; attribute C_HAS_UNDERFLOW : integer; attribute C_HAS_UNDERFLOW of U0 : label is 1; attribute C_HAS_VALID : integer; attribute C_HAS_VALID of U0 : label is 0; attribute C_HAS_WR_ACK : integer; attribute C_HAS_WR_ACK of U0 : label is 0; attribute C_HAS_WR_DATA_COUNT : integer; attribute C_HAS_WR_DATA_COUNT of U0 : label is 0; attribute C_HAS_WR_RST : integer; attribute C_HAS_WR_RST of U0 : label is 0; attribute C_IMPLEMENTATION_TYPE : integer; attribute C_IMPLEMENTATION_TYPE of U0 : label is 6; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1; attribute C_INIT_WR_PNTR_VAL : integer; attribute C_INIT_WR_PNTR_VAL of U0 : label is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_MEMORY_TYPE : integer; attribute C_MEMORY_TYPE of U0 : label is 4; attribute C_MIF_FILE_NAME : string; attribute C_MIF_FILE_NAME of U0 : label is "BlankString"; attribute C_MSGON_VAL : integer; attribute C_MSGON_VAL of U0 : label is 1; attribute C_OPTIMIZATION_MODE : integer; attribute C_OPTIMIZATION_MODE of U0 : label is 0; attribute C_OVERFLOW_LOW : integer; attribute C_OVERFLOW_LOW of U0 : label is 0; attribute C_POWER_SAVING_MODE : integer; attribute C_POWER_SAVING_MODE of U0 : label is 0; attribute C_PRELOAD_LATENCY : integer; attribute C_PRELOAD_LATENCY of U0 : label is 2; attribute C_PRELOAD_REGS : integer; attribute C_PRELOAD_REGS of U0 : label is 1; attribute C_PRIM_FIFO_TYPE : string; attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72"; attribute C_PRIM_FIFO_TYPE_AXIS : string; attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18"; attribute C_PRIM_FIFO_TYPE_RACH : string; attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "512x72"; attribute C_PRIM_FIFO_TYPE_WACH : string; attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "512x72"; attribute C_PRIM_FIFO_TYPE_WRCH : string; attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 8; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 9; attribute C_PROG_EMPTY_TYPE : integer; attribute C_PROG_EMPTY_TYPE of U0 : label is 1; attribute C_PROG_EMPTY_TYPE_AXIS : integer; attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 450; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 449; attribute C_PROG_FULL_TYPE : integer; attribute C_PROG_FULL_TYPE of U0 : label is 1; attribute C_PROG_FULL_TYPE_AXIS : integer; attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0; attribute C_PROG_FULL_TYPE_RACH : integer; attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WACH : integer; attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0; attribute C_RACH_TYPE : integer; attribute C_RACH_TYPE of U0 : label is 0; attribute C_RDCH_TYPE : integer; attribute C_RDCH_TYPE of U0 : label is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9; attribute C_RD_DEPTH : integer; attribute C_RD_DEPTH of U0 : label is 512; attribute C_RD_FREQ : integer; attribute C_RD_FREQ of U0 : label is 1; attribute C_RD_PNTR_WIDTH : integer; attribute C_RD_PNTR_WIDTH of U0 : label is 9; attribute C_REG_SLICE_MODE_AXIS : integer; attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0; attribute C_REG_SLICE_MODE_RACH : integer; attribute C_REG_SLICE_MODE_RACH of U0 : label is 0; attribute C_REG_SLICE_MODE_RDCH : integer; attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WACH : integer; attribute C_REG_SLICE_MODE_WACH of U0 : label is 0; attribute C_REG_SLICE_MODE_WDCH : integer; attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WRCH : integer; attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_SYNCHRONIZER_STAGE : integer; attribute C_SYNCHRONIZER_STAGE of U0 : label is 2; attribute C_UNDERFLOW_LOW : integer; attribute C_UNDERFLOW_LOW of U0 : label is 0; attribute C_USE_COMMON_OVERFLOW : integer; attribute C_USE_COMMON_OVERFLOW of U0 : label is 0; attribute C_USE_COMMON_UNDERFLOW : integer; attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0; attribute C_USE_DEFAULT_SETTINGS : integer; attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0; attribute C_USE_DOUT_RST : integer; attribute C_USE_DOUT_RST of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_ECC_AXIS : integer; attribute C_USE_ECC_AXIS of U0 : label is 0; attribute C_USE_ECC_RACH : integer; attribute C_USE_ECC_RACH of U0 : label is 0; attribute C_USE_ECC_RDCH : integer; attribute C_USE_ECC_RDCH of U0 : label is 0; attribute C_USE_ECC_WACH : integer; attribute C_USE_ECC_WACH of U0 : label is 0; attribute C_USE_ECC_WDCH : integer; attribute C_USE_ECC_WDCH of U0 : label is 0; attribute C_USE_ECC_WRCH : integer; attribute C_USE_ECC_WRCH of U0 : label is 0; attribute C_USE_EMBEDDED_REG : integer; attribute C_USE_EMBEDDED_REG of U0 : label is 1; attribute C_USE_FIFO16_FLAGS : integer; attribute C_USE_FIFO16_FLAGS of U0 : label is 0; attribute C_USE_FWFT_DATA_COUNT : integer; attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0; attribute C_USE_PIPELINE_REG : integer; attribute C_USE_PIPELINE_REG of U0 : label is 0; attribute C_VALID_LOW : integer; attribute C_VALID_LOW of U0 : label is 0; attribute C_WACH_TYPE : integer; attribute C_WACH_TYPE of U0 : label is 0; attribute C_WDCH_TYPE : integer; attribute C_WDCH_TYPE of U0 : label is 0; attribute C_WRCH_TYPE : integer; attribute C_WRCH_TYPE of U0 : label is 0; attribute C_WR_ACK_LOW : integer; attribute C_WR_ACK_LOW of U0 : label is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9; attribute C_WR_DEPTH : integer; attribute C_WR_DEPTH of U0 : label is 512; attribute C_WR_DEPTH_AXIS : integer; attribute C_WR_DEPTH_AXIS of U0 : label is 1024; attribute C_WR_DEPTH_RACH : integer; attribute C_WR_DEPTH_RACH of U0 : label is 16; attribute C_WR_DEPTH_RDCH : integer; attribute C_WR_DEPTH_RDCH of U0 : label is 1024; attribute C_WR_DEPTH_WACH : integer; attribute C_WR_DEPTH_WACH of U0 : label is 16; attribute C_WR_DEPTH_WDCH : integer; attribute C_WR_DEPTH_WDCH of U0 : label is 1024; attribute C_WR_DEPTH_WRCH : integer; attribute C_WR_DEPTH_WRCH of U0 : label is 16; attribute C_WR_FREQ : integer; attribute C_WR_FREQ of U0 : label is 1; attribute C_WR_PNTR_WIDTH : integer; attribute C_WR_PNTR_WIDTH of U0 : label is 9; attribute C_WR_PNTR_WIDTH_AXIS : integer; attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of U0 : label is 1; attribute is_du_within_envelope : string; attribute is_du_within_envelope of U0 : label is "true"; attribute x_interface_info : string; attribute x_interface_info of empty : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; attribute x_interface_info of full : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; attribute x_interface_info of rd_clk : signal is "xilinx.com:signal:clock:1.0 read_clk CLK"; attribute x_interface_parameter : string; attribute x_interface_parameter of rd_clk : signal is "XIL_INTERFACENAME read_clk, FREQ_HZ 1000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; attribute x_interface_info of rd_en : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; attribute x_interface_info of wr_clk : signal is "xilinx.com:signal:clock:1.0 write_clk CLK"; attribute x_interface_parameter of wr_clk : signal is "XIL_INTERFACENAME write_clk, FREQ_HZ 1000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; attribute x_interface_info of wr_en : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; attribute x_interface_info of din : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; attribute x_interface_info of dout : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; begin dout(71) <= \\; dout(70) <= \\; dout(69) <= \\; dout(68) <= \^dout\(68); dout(67) <= \\; dout(66) <= \\; dout(65 downto 0) <= \^dout\(65 downto 0); prog_full <= \\; rd_rst_busy <= \\; wr_rst_busy <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_2_5 port map ( almost_empty => NLW_U0_almost_empty_UNCONNECTED, almost_full => NLW_U0_almost_full_UNCONNECTED, axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0), axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED, axi_ar_injectdbiterr => '0', axi_ar_injectsbiterr => '0', axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED, axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED, axi_ar_prog_empty_thresh(3 downto 0) => B"0000", axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED, axi_ar_prog_full_thresh(3 downto 0) => B"0000", axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED, axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED, axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0), axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED, axi_aw_injectdbiterr => '0', axi_aw_injectsbiterr => '0', axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED, axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED, axi_aw_prog_empty_thresh(3 downto 0) => B"0000", axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED, axi_aw_prog_full_thresh(3 downto 0) => B"0000", axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED, axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED, axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0), axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED, axi_b_injectdbiterr => '0', axi_b_injectsbiterr => '0', axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED, axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED, axi_b_prog_empty_thresh(3 downto 0) => B"0000", axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED, axi_b_prog_full_thresh(3 downto 0) => B"0000", axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0), axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED, axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED, axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0), axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0), axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED, axi_r_injectdbiterr => '0', axi_r_injectsbiterr => '0', axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED, axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED, axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED, axi_r_prog_full_thresh(9 downto 0) => B"0000000000", axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0), axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED, axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED, axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0), axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0), axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED, axi_w_injectdbiterr => '0', axi_w_injectsbiterr => '0', axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED, axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED, axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED, axi_w_prog_full_thresh(9 downto 0) => B"0000000000", axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0), axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED, axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED, axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0), axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0), axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED, axis_injectdbiterr => '0', axis_injectsbiterr => '0', axis_overflow => NLW_U0_axis_overflow_UNCONNECTED, axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED, axis_prog_empty_thresh(9 downto 0) => B"0000000000", axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED, axis_prog_full_thresh(9 downto 0) => B"0000000000", axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0), axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED, axis_underflow => NLW_U0_axis_underflow_UNCONNECTED, axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0), backup => '0', backup_marker => '0', clk => '0', data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0), dbiterr => NLW_U0_dbiterr_UNCONNECTED, din(71 downto 0) => din(71 downto 0), dout(71 downto 69) => NLW_U0_dout_UNCONNECTED(71 downto 69), dout(68) => \^dout\(68), dout(67 downto 66) => NLW_U0_dout_UNCONNECTED(67 downto 66), dout(65 downto 0) => \^dout\(65 downto 0), empty => empty, full => full, injectdbiterr => '0', injectsbiterr => '0', int_clk => '0', m_aclk => '0', m_aclk_en => '0', m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0), m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0), m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => '0', m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED, m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0), m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0), m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => '0', m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED, m_axi_bid(0) => '0', m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED, m_axi_bresp(1 downto 0) => B"00", m_axi_buser(0) => '0', m_axi_bvalid => '0', m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", m_axi_rid(0) => '0', m_axi_rlast => '0', m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED, m_axi_rresp(1 downto 0) => B"00", m_axi_ruser(0) => '0', m_axi_rvalid => '0', m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0), m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0), m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED, m_axi_wready => '0', m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0), m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED, m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0), m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0), m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0), m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0), m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED, m_axis_tready => '0', m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0), m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0), m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED, overflow => overflow, prog_empty => prog_empty, prog_empty_thresh(8 downto 0) => B"000000000", prog_empty_thresh_assert(8 downto 0) => B"000000000", prog_empty_thresh_negate(8 downto 0) => B"000000000", prog_full => NLW_U0_prog_full_UNCONNECTED, prog_full_thresh(8 downto 0) => B"000000000", prog_full_thresh_assert(8 downto 0) => B"000000000", prog_full_thresh_negate(8 downto 0) => B"000000000", rd_clk => rd_clk, rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0), rd_en => rd_en, rd_rst => '0', rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED, rst => '0', s_aclk => '0', s_aclk_en => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arcache(3 downto 0) => B"0000", s_axi_arid(0) => '0', s_axi_arlen(7 downto 0) => B"00000000", s_axi_arlock(0) => '0', s_axi_arprot(2 downto 0) => B"000", s_axi_arqos(3 downto 0) => B"0000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => B"000", s_axi_aruser(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(0) => '0', s_axi_awlen(7 downto 0) => B"00000000", s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => B"000", s_axi_awuser(0) => '0', s_axi_awvalid => '0', s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0), s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", s_axi_wid(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(7 downto 0) => B"00000000", s_axi_wuser(0) => '0', s_axi_wvalid => '0', s_axis_tdata(7 downto 0) => B"00000000", s_axis_tdest(0) => '0', s_axis_tid(0) => '0', s_axis_tkeep(0) => '0', s_axis_tlast => '0', s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED, s_axis_tstrb(0) => '0', s_axis_tuser(3 downto 0) => B"0000", s_axis_tvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', srst => srst, underflow => underflow, valid => NLW_U0_valid_UNCONNECTED, wr_ack => NLW_U0_wr_ack_UNCONNECTED, wr_clk => wr_clk, wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0), wr_en => wr_en, wr_rst => '0', wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING is port ( dout : out STD_LOGIC_VECTOR ( 65 downto 0 ); do_rd_en_i : out STD_LOGIC; rx_lossofsync_i : out STD_LOGIC; CC_detect_dlyd1 : out STD_LOGIC; CB_detect_dlyd0p5 : out STD_LOGIC; bit_err_chan_bond_i : out STD_LOGIC; valid_btf_detect_dlyd1 : out STD_LOGIC; ILLEGAL_BTF_reg : out STD_LOGIC; rxdatavalid_i : out STD_LOGIC; wr_err_rd_clk_sync_reg_0 : out STD_LOGIC; hard_err_usr0 : out STD_LOGIC; hold_reg_reg_0 : out STD_LOGIC; rxfsm_reset_i : out STD_LOGIC; \LINK_RESET_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); LINK_RESET_OUT0 : out STD_LOGIC; final_gater_for_fifo_din_i : out STD_LOGIC; START_CB_WRITES_OUT : out STD_LOGIC; ANY_VLD_BTF_FLAG : out STD_LOGIC; srst : in STD_LOGIC; gtwiz_userclk_rx_usrclk_out : in STD_LOGIC; s_level_out_d5_reg : in STD_LOGIC; \out\ : in STD_LOGIC; in0 : in STD_LOGIC; UNSCRAMBLED_DATA_OUT : in STD_LOGIC_VECTOR ( 31 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxdatavalid_to_fifo_i : in STD_LOGIC; cbcc_fifo_reset_rd_clk : in STD_LOGIC; init_clk : in STD_LOGIC; cbcc_reset_cbstg2_rd_clk : in STD_LOGIC; CC_RXLOSSOFSYNC_OUT_reg_0 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); valid_btf_detect_c : in STD_LOGIC; CB_detect0 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \count_for_reset_r_reg[23]_0\ : in STD_LOGIC; illegal_btf_i : in STD_LOGIC; enable_err_detect_i : in STD_LOGIC; HARD_ERR_reg : in STD_LOGIC; txbufstatus_out : in STD_LOGIC_VECTOR ( 0 to 0 ); hard_err_usr_reg : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; allow_block_sync_propagation_reg : in STD_LOGIC; LINK_RESET_OUT_reg : in STD_LOGIC; hard_err_rst_int : in STD_LOGIC; FINAL_GATER_FOR_FIFO_DIN_reg_0 : in STD_LOGIC; \wr_monitor_flag_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \valid_btf_detect_extend_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); START_CB_WRITES_OUT_reg_0 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING is signal \^any_vld_btf_flag\ : STD_LOGIC; signal ANY_VLD_BTF_FLAG_i_1_n_0 : STD_LOGIC; signal \^cb_detect_dlyd0p5\ : STD_LOGIC; signal CB_detect_dlyd1 : STD_LOGIC; signal CB_detect_dlyd10 : STD_LOGIC; signal CB_detect_dlyd1p0 : STD_LOGIC; signal CC_detect_pulse_r : STD_LOGIC; signal FINAL_GATER_FOR_FIFO_DIN0 : STD_LOGIC; signal FINAL_GATER_FOR_FIFO_DIN_i_1_n_0 : STD_LOGIC; signal \FIRST_CB_BITERR_CB_RESET_OUT1__15\ : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 : STD_LOGIC; signal \LINK_RESET[0]_i_2_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_3_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_4_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_5_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_6_n_0\ : STD_LOGIC; signal SOFT_ERR_i_2_n_0 : STD_LOGIC; signal \^start_cb_writes_out\ : STD_LOGIC; signal START_CB_WRITES_OUT_i_1_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_3_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_4_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_6_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 : STD_LOGIC; signal bit80_prsnt : STD_LOGIC; signal \^bit_err_chan_bond_i\ : STD_LOGIC; signal buffer_too_empty_c : STD_LOGIC; signal cb_fifo_din_detect_q : STD_LOGIC; signal \count_for_reset_r[0]_i_3_n_0\ : STD_LOGIC; signal count_for_reset_r_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); signal \count_for_reset_r_reg[0]_i_2_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_10\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_11\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_12\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_13\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_14\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_15\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_8\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_9\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_10\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_11\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_12\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_13\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_14\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_15\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_8\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_9\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_10\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_11\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_12\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_13\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_14\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_15\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_8\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_9\ : STD_LOGIC; signal do_rd_en : STD_LOGIC; signal \^do_rd_en_i\ : STD_LOGIC; signal do_wr_en : STD_LOGIC; signal do_wr_en_i_1_n_0 : STD_LOGIC; signal \^dout\ : STD_LOGIC_VECTOR ( 65 downto 0 ); signal en32_fifo_din_i : STD_LOGIC_VECTOR ( 79 downto 0 ); signal \^final_gater_for_fifo_din_i\ : STD_LOGIC; signal first_cb_to_write_to_fifo : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_2_n_0 : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_3_n_0 : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_4_n_0 : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_5_n_0 : STD_LOGIC; signal hold_reg : STD_LOGIC; signal hold_reg_i_1_n_0 : STD_LOGIC; signal link_reset_0 : STD_LOGIC; signal link_reset_0_c : STD_LOGIC; signal master_do_rd_en_q : STD_LOGIC; signal mod_do_wr_en : STD_LOGIC; signal new_do_wr_en : STD_LOGIC; signal new_do_wr_en_i_1_n_0 : STD_LOGIC; signal new_underflow_flag_c : STD_LOGIC; signal new_underflow_flag_c0 : STD_LOGIC; signal overflow_flag_c : STD_LOGIC; signal p_0_in0_in : STD_LOGIC; signal p_0_in4_in : STD_LOGIC; signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \raw_data_r_r_reg_n_0_[0]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[10]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[11]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[12]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[13]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[14]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[15]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[16]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[17]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[18]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[19]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[1]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[20]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[21]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[22]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[23]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[24]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[25]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[26]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[27]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[28]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[29]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[2]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[30]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[31]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[32]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[33]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[3]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[4]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[5]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[6]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[7]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[8]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[9]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[0]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[10]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[11]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[12]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[13]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[14]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[15]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[16]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[17]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[18]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[19]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[1]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[20]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[21]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[22]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[23]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[24]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[25]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[26]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[27]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[28]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[29]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[2]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[30]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[31]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[32]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[33]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[3]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[4]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[5]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[6]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[7]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[8]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[9]\ : STD_LOGIC; signal raw_data_srl_out : STD_LOGIC_VECTOR ( 34 downto 0 ); signal rd_err_c : STD_LOGIC; signal rd_err_pre : STD_LOGIC; signal rxbuferr_out_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdatavalid_lookahead_i : STD_LOGIC; signal u_cdc_rxlossofsync_in_n_0 : STD_LOGIC; signal u_rst_sync_btf_sync_n_0 : STD_LOGIC; signal underflow_flag_c : STD_LOGIC; signal underflow_flag_r1 : STD_LOGIC; signal underflow_flag_r10 : STD_LOGIC; signal underflow_flag_r2 : STD_LOGIC; signal underflow_flag_r3 : STD_LOGIC; signal valid_btf_detect : STD_LOGIC; signal valid_btf_detect_extend_r : STD_LOGIC_VECTOR ( 4 downto 0 ); signal valid_btf_detect_extend_r2 : STD_LOGIC; signal valid_btf_detect_extend_r20_n_0 : STD_LOGIC; signal wait_for_rd_en : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \wait_for_rd_en[0]_i_1_n_0\ : STD_LOGIC; signal \wait_for_rd_en[1]_i_1_n_0\ : STD_LOGIC; signal \wait_for_rd_en[2]_i_1_n_0\ : STD_LOGIC; signal \wait_for_rd_en[2]_i_2_n_0\ : STD_LOGIC; signal \wait_for_wr_en[5]_i_1_n_0\ : STD_LOGIC; signal wait_for_wr_en_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); signal \wait_for_wr_en_wr3_reg[0]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[1]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[2]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[3]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[4]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[5]_srl3_n_0\ : STD_LOGIC; signal wait_for_wr_en_wr4 : STD_LOGIC_VECTOR ( 5 downto 0 ); signal wdth_conv_1stage : STD_LOGIC_VECTOR ( 39 downto 0 ); signal wdth_conv_2stage : STD_LOGIC_VECTOR ( 39 downto 32 ); signal \wdth_conv_count[1]_i_1_n_0\ : STD_LOGIC; signal \wdth_conv_count_reg_n_0_[0]\ : STD_LOGIC; signal wr_err_c : STD_LOGIC; signal wr_err_rd_clk_pre : STD_LOGIC; signal wr_monitor_flag : STD_LOGIC; signal wr_monitor_flag_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_SRLC32E_inst_4_Q31_UNCONNECTED : STD_LOGIC; signal \NLW_count_for_reset_r_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); signal \NLW_master_fifo.data_fifo_prog_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_master_fifo.data_fifo_rd_rst_busy_UNCONNECTED\ : STD_LOGIC; signal \NLW_master_fifo.data_fifo_wr_rst_busy_UNCONNECTED\ : STD_LOGIC; signal \NLW_master_fifo.data_fifo_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 71 downto 66 ); signal \NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of FINAL_GATER_FOR_FIFO_DIN_i_1 : label is "soft_lutpair46"; attribute SOFT_HLUTNM of FIRST_CB_BITERR_CB_RESET_OUT_i_3 : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \FSM_onehot_cdr_reset_fsm_r[2]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of RXDATAVALID_IN_REG_i_1 : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \RX_DATA_REG[63]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of SOFT_ERR_i_1 : label is "soft_lutpair43"; attribute SOFT_HLUTNM of SOFT_ERR_i_2 : label is "soft_lutpair49"; attribute BOX_TYPE : string; attribute BOX_TYPE of SRLC32E_inst_4 : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of SRLC32E_inst_4 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/SRLC32E_inst_4 "; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \count_for_reset_r_reg[0]_i_2\ : label is 16; attribute ADDER_THRESHOLD of \count_for_reset_r_reg[16]_i_1\ : label is 16; attribute ADDER_THRESHOLD of \count_for_reset_r_reg[8]_i_1\ : label is 16; attribute SOFT_HLUTNM of do_wr_en_i_2 : label is "soft_lutpair46"; attribute shift_extract : string; attribute shift_extract of master_do_rd_en_q_reg : label is "{no}"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of \master_fifo.data_fifo\ : label is "aurora_64b66b_0_fifo_gen_master,fifo_generator_v13_2_5,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of \master_fifo.data_fifo\ : label is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of \master_fifo.data_fifo\ : label is "fifo_generator_v13_2_5,Vivado 2020.2"; attribute inverted : string; attribute inverted of new_underflow_flag_c_reg_inv : label is "yes"; attribute shift_extract of \raw_data_r_r_reg[0]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[10]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[11]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[12]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[13]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[14]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[15]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[16]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[17]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[18]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[19]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[1]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[20]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[21]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[22]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[23]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[24]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[25]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[26]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[27]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[28]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[29]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[2]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[30]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[31]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[32]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[33]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[34]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[3]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[4]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[5]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[6]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[7]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[8]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[9]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[0]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[10]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[11]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[12]\ : label is "{no}"; attribute shift_extract of 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srl_bus_name of \srlc32e[11].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[11].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[12].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[12].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[12].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[13].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[13].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[13].SRLC32E_inst_1\ : label is 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attribute BOX_TYPE of \srlc32e[19].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[19].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[19].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[19].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[1].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[1].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[1].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[1].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[20].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[20].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of 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attribute BOX_TYPE of \srlc32e[30].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[30].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[30].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[30].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[31].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[31].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[31].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[31].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[32].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[32].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[32].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[32].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[33].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[33].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[33].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[34].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[34].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[34].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[34].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[3].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[3].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[3].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[3].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[4].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[4].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[4].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[4].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[5].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[5].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[5].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[5].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[6].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[6].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[6].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[6].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[7].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[7].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[7].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[7].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[8].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[8].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[8].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[8].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[9].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[9].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[9].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[9].SRLC32E_inst_1 "; attribute shift_extract of valid_btf_detect_reg : label is "{no}"; attribute SOFT_HLUTNM of \wait_for_rd_en[1]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \wait_for_rd_en[2]_i_2\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \wait_for_wr_en[0]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \wait_for_wr_en[1]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \wait_for_wr_en[2]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wait_for_wr_en[3]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wait_for_wr_en[4]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \wait_for_wr_en[5]_i_2\ : label is "soft_lutpair42"; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[0]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[1]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[2]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[2]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[2]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[3]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[3]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[3]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[4]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[4]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[4]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[5]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[5]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[5]_srl3 "; attribute shift_extract of \wdth_conv_1stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[9]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[9]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[9]\ : label is "{no}"; attribute SOFT_HLUTNM of \wdth_conv_count[0]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \wdth_conv_count[1]_i_2\ : label is "soft_lutpair48"; attribute shift_extract of wr_err_rd_clk_sync_reg : label is "{no}"; attribute SOFT_HLUTNM of \wr_monitor_flag[0]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \wr_monitor_flag[1]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \wr_monitor_flag[2]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wr_monitor_flag[3]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \wr_monitor_flag[4]_i_2\ : label is "soft_lutpair44"; begin ANY_VLD_BTF_FLAG <= \^any_vld_btf_flag\; CB_detect_dlyd0p5 <= \^cb_detect_dlyd0p5\; START_CB_WRITES_OUT <= \^start_cb_writes_out\; bit_err_chan_bond_i <= \^bit_err_chan_bond_i\; do_rd_en_i <= \^do_rd_en_i\; dout(65 downto 0) <= \^dout\(65 downto 0); final_gater_for_fifo_din_i <= \^final_gater_for_fifo_din_i\; ANY_VLD_BTF_FLAG_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => p_0_in0_in, I1 => any_vld_btf_fifo_din_detect_dlyd, I2 => \^any_vld_btf_flag\, O => ANY_VLD_BTF_FLAG_i_1_n_0 ); ANY_VLD_BTF_FLAG_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => ANY_VLD_BTF_FLAG_i_1_n_0, Q => \^any_vld_btf_flag\, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); CB_detect_dlyd0p5_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => CB_detect0, Q => \^cb_detect_dlyd0p5\, R => SR(0) ); CB_detect_dlyd1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => CB_detect_dlyd1p0, I1 => \^cb_detect_dlyd0p5\, O => CB_detect_dlyd10 ); CB_detect_dlyd1_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => CB_detect_dlyd10, Q => CB_detect_dlyd1, R => SR(0) ); CB_detect_dlyd1p0_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \^cb_detect_dlyd0p5\, Q => CB_detect_dlyd1p0, R => SR(0) ); CC_RXLOSSOFSYNC_OUT_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d5_reg, CE => '1', D => u_cdc_rxlossofsync_in_n_0, Q => rx_lossofsync_i, S => CC_RXLOSSOFSYNC_OUT_reg_0 ); CC_detect_dlyd1_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_c, Q => CC_detect_dlyd1, R => SR(0) ); CC_detect_pulse_r_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => D(1), Q => CC_detect_pulse_r, R => '0' ); FINAL_GATER_FOR_FIFO_DIN_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF80" ) port map ( I0 => FINAL_GATER_FOR_FIFO_DIN_reg_0, I1 => cb_fifo_din_detect_q, I2 => p_0_in0_in, I3 => \^final_gater_for_fifo_din_i\, O => FINAL_GATER_FOR_FIFO_DIN_i_1_n_0 ); FINAL_GATER_FOR_FIFO_DIN_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => FINAL_GATER_FOR_FIFO_DIN_i_1_n_0, Q => \^final_gater_for_fifo_din_i\, R => SR(0) ); FIRST_CB_BITERR_CB_RESET_OUT_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000E22E" ) port map ( I0 => \^bit_err_chan_bond_i\, I1 => new_do_wr_en, I2 => \FIRST_CB_BITERR_CB_RESET_OUT1__15\, I3 => FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0, I4 => FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0, O => FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0100000000000000" ) port map ( I0 => en32_fifo_din_i(58), I1 => en32_fifo_din_i(57), I2 => en32_fifo_din_i(56), I3 => FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0, I4 => FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0, I5 => FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0, O => \FIRST_CB_BITERR_CB_RESET_OUT1__15\ ); FIRST_CB_BITERR_CB_RESET_OUT_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FFFDFFFF" ) port map ( I0 => wr_monitor_flag_reg(3), I1 => wr_monitor_flag_reg(4), I2 => wr_monitor_flag_reg(0), I3 => wr_monitor_flag_reg(2), I4 => wr_monitor_flag_reg(1), O => FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FEFEFEFAFEFAFEFB" ) port map ( I0 => \wr_monitor_flag_reg[4]_0\(0), I1 => wr_monitor_flag_reg(3), I2 => wr_monitor_flag_reg(4), I3 => wr_monitor_flag_reg(2), I4 => wr_monitor_flag_reg(1), I5 => wr_monitor_flag_reg(0), O => FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => en32_fifo_din_i(61), I1 => en32_fifo_din_i(62), I2 => en32_fifo_din_i(60), I3 => en32_fifo_din_i(59), O => FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => en32_fifo_din_i(66), I1 => en32_fifo_din_i(65), I2 => en32_fifo_din_i(64), I3 => en32_fifo_din_i(63), O => FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"0000800000000000" ) port map ( I0 => en32_fifo_din_i(67), I1 => en32_fifo_din_i(68), I2 => en32_fifo_din_i(69), I3 => en32_fifo_din_i(70), I4 => en32_fifo_din_i(71), I5 => en32_fifo_din_i(76), O => FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0, Q => \^bit_err_chan_bond_i\, R => '0' ); \FSM_onehot_cdr_reset_fsm_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => link_reset_0_c, I1 => allow_block_sync_propagation_reg, I2 => hard_err_rst_int, O => \LINK_RESET_reg[0]_0\(0) ); HARD_ERR_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => rxbuferr_out_i(1), I1 => rxbuferr_out_i(0), I2 => HARD_ERR_reg, I3 => txbufstatus_out(0), I4 => enable_err_detect_i, O => wr_err_rd_clk_sync_reg_0 ); \LINK_RESET[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"ABA8000000000000" ) port map ( I0 => \LINK_RESET[0]_i_2_n_0\, I1 => count_for_reset_r_reg(1), I2 => count_for_reset_r_reg(2), I3 => \LINK_RESET[0]_i_3_n_0\, I4 => \LINK_RESET[0]_i_4_n_0\, I5 => \LINK_RESET[0]_i_5_n_0\, O => link_reset_0 ); \LINK_RESET[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => count_for_reset_r_reg(3), I1 => count_for_reset_r_reg(6), I2 => count_for_reset_r_reg(7), I3 => count_for_reset_r_reg(5), I4 => count_for_reset_r_reg(4), O => \LINK_RESET[0]_i_2_n_0\ ); \LINK_RESET[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => count_for_reset_r_reg(6), I1 => count_for_reset_r_reg(7), I2 => count_for_reset_r_reg(4), I3 => count_for_reset_r_reg(5), I4 => count_for_reset_r_reg(3), I5 => count_for_reset_r_reg(0), O => \LINK_RESET[0]_i_3_n_0\ ); \LINK_RESET[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => count_for_reset_r_reg(10), I1 => count_for_reset_r_reg(11), I2 => count_for_reset_r_reg(8), I3 => count_for_reset_r_reg(9), I4 => \LINK_RESET[0]_i_6_n_0\, O => \LINK_RESET[0]_i_4_n_0\ ); \LINK_RESET[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => count_for_reset_r_reg(20), I1 => count_for_reset_r_reg(21), I2 => count_for_reset_r_reg(18), I3 => count_for_reset_r_reg(19), I4 => count_for_reset_r_reg(23), I5 => count_for_reset_r_reg(22), O => \LINK_RESET[0]_i_5_n_0\ ); \LINK_RESET[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => count_for_reset_r_reg(14), I1 => count_for_reset_r_reg(15), I2 => count_for_reset_r_reg(12), I3 => count_for_reset_r_reg(13), I4 => count_for_reset_r_reg(17), I5 => count_for_reset_r_reg(16), O => \LINK_RESET[0]_i_6_n_0\ ); LINK_RESET_OUT_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => LINK_RESET_OUT_reg, I1 => link_reset_0_c, O => LINK_RESET_OUT0 ); \LINK_RESET_reg[0]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => link_reset_0, Q => link_reset_0_c, R => '0' ); RXDATAVALID_IN_REG_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => master_do_rd_en_q, I1 => p_0_in4_in, O => rxdatavalid_i ); \RX_DATA_REG[63]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => hold_reg, O => hold_reg_reg_0 ); SOFT_ERR_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FBBF0000" ) port map ( I0 => illegal_btf_i, I1 => hold_reg, I2 => \^dout\(65), I3 => \^dout\(64), I4 => SOFT_ERR_i_2_n_0, O => ILLEGAL_BTF_reg ); SOFT_ERR_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => p_0_in4_in, I1 => master_do_rd_en_q, I2 => enable_err_detect_i, O => SOFT_ERR_i_2_n_0 ); SRLC32E_inst_4: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00010", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => rxdatavalid_to_fifo_i, Q => rxdatavalid_lookahead_i, Q31 => NLW_SRLC32E_inst_4_Q31_UNCONNECTED ); START_CB_WRITES_OUT_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF80" ) port map ( I0 => START_CB_WRITES_OUT_reg_0, I1 => cb_fifo_din_detect_q, I2 => p_0_in0_in, I3 => \^start_cb_writes_out\, O => START_CB_WRITES_OUT_i_1_n_0 ); START_CB_WRITES_OUT_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => START_CB_WRITES_OUT_i_1_n_0, Q => \^start_cb_writes_out\, R => SR(0) ); any_vld_btf_fifo_din_detect_dlyd_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => any_vld_btf_fifo_din_detect_dlyd_i_3_n_0, I1 => SR(0), I2 => wait_for_wr_en_wr4(3), I3 => wait_for_wr_en_wr4(1), O => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"01000000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[18]\, I1 => \raw_data_r_r_reg_n_0_[17]\, I2 => \raw_data_r_r_reg_n_0_[16]\, I3 => any_vld_btf_fifo_din_detect_dlyd_i_4_n_0, I4 => any_vld_btf_fifo_din_detect_dlyd_i_5_n_0, O => any_vld_btf_fifo_din_detect ); any_vld_btf_fifo_din_detect_dlyd_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => wait_for_wr_en_wr4(2), I1 => wait_for_wr_en_wr4(4), I2 => wait_for_wr_en_wr4(5), I3 => wait_for_wr_en_wr4(0), O => any_vld_btf_fifo_din_detect_dlyd_i_3_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"00100000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[19]\, I1 => \raw_data_r_r_reg_n_0_[20]\, I2 => \raw_data_r_r_reg_n_0_[22]\, I3 => \raw_data_r_r_reg_n_0_[21]\, I4 => any_vld_btf_fifo_din_detect_dlyd_i_6_n_0, O => any_vld_btf_fifo_din_detect_dlyd_i_4_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"10000000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[31]\, I1 => \raw_data_r_r_reg_n_0_[32]\, I2 => \raw_data_r_r_reg_n_0_[33]\, I3 => p_0_in0_in, I4 => any_vld_btf_fifo_din_detect_dlyd_i_7_n_0, O => any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \raw_data_r_r_reg_n_0_[26]\, I1 => \raw_data_r_r_reg_n_0_[25]\, I2 => \raw_data_r_r_reg_n_0_[24]\, I3 => \raw_data_r_r_reg_n_0_[23]\, O => any_vld_btf_fifo_din_detect_dlyd_i_6_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[30]\, I1 => \raw_data_r_r_reg_n_0_[29]\, I2 => \raw_data_r_r_reg_n_0_[28]\, I3 => \raw_data_r_r_reg_n_0_[27]\, O => any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 ); any_vld_btf_fifo_din_detect_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => any_vld_btf_fifo_din_detect, Q => any_vld_btf_fifo_din_detect_dlyd, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); cb_fifo_din_detect_q_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => any_vld_btf_fifo_din_detect, Q => cb_fifo_din_detect_q, R => SR(0) ); \count_for_reset_r[0]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => count_for_reset_r_reg(0), O => \count_for_reset_r[0]_i_3_n_0\ ); \count_for_reset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_15\, Q => count_for_reset_r_reg(0), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[0]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \count_for_reset_r_reg[0]_i_2_n_0\, CO(6) => \count_for_reset_r_reg[0]_i_2_n_1\, CO(5) => \count_for_reset_r_reg[0]_i_2_n_2\, CO(4) => \count_for_reset_r_reg[0]_i_2_n_3\, CO(3) => \count_for_reset_r_reg[0]_i_2_n_4\, CO(2) => \count_for_reset_r_reg[0]_i_2_n_5\, CO(1) => \count_for_reset_r_reg[0]_i_2_n_6\, CO(0) => \count_for_reset_r_reg[0]_i_2_n_7\, DI(7 downto 0) => B"00000001", O(7) => \count_for_reset_r_reg[0]_i_2_n_8\, O(6) => \count_for_reset_r_reg[0]_i_2_n_9\, O(5) => \count_for_reset_r_reg[0]_i_2_n_10\, O(4) => \count_for_reset_r_reg[0]_i_2_n_11\, O(3) => \count_for_reset_r_reg[0]_i_2_n_12\, O(2) => \count_for_reset_r_reg[0]_i_2_n_13\, O(1) => \count_for_reset_r_reg[0]_i_2_n_14\, O(0) => \count_for_reset_r_reg[0]_i_2_n_15\, S(7 downto 1) => count_for_reset_r_reg(7 downto 1), S(0) => \count_for_reset_r[0]_i_3_n_0\ ); \count_for_reset_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_13\, Q => count_for_reset_r_reg(10), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_12\, Q => count_for_reset_r_reg(11), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_11\, Q => count_for_reset_r_reg(12), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_10\, Q => count_for_reset_r_reg(13), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_9\, Q => count_for_reset_r_reg(14), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_8\, Q => count_for_reset_r_reg(15), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_15\, Q => count_for_reset_r_reg(16), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[16]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \count_for_reset_r_reg[8]_i_1_n_0\, CI_TOP => '0', CO(7) => \NLW_count_for_reset_r_reg[16]_i_1_CO_UNCONNECTED\(7), CO(6) => \count_for_reset_r_reg[16]_i_1_n_1\, CO(5) => \count_for_reset_r_reg[16]_i_1_n_2\, CO(4) => \count_for_reset_r_reg[16]_i_1_n_3\, CO(3) => \count_for_reset_r_reg[16]_i_1_n_4\, CO(2) => \count_for_reset_r_reg[16]_i_1_n_5\, CO(1) => \count_for_reset_r_reg[16]_i_1_n_6\, CO(0) => \count_for_reset_r_reg[16]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \count_for_reset_r_reg[16]_i_1_n_8\, O(6) => \count_for_reset_r_reg[16]_i_1_n_9\, O(5) => \count_for_reset_r_reg[16]_i_1_n_10\, O(4) => \count_for_reset_r_reg[16]_i_1_n_11\, O(3) => \count_for_reset_r_reg[16]_i_1_n_12\, O(2) => \count_for_reset_r_reg[16]_i_1_n_13\, O(1) => \count_for_reset_r_reg[16]_i_1_n_14\, O(0) => \count_for_reset_r_reg[16]_i_1_n_15\, S(7 downto 0) => count_for_reset_r_reg(23 downto 16) ); \count_for_reset_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_14\, Q => count_for_reset_r_reg(17), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_13\, Q => count_for_reset_r_reg(18), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_12\, Q => count_for_reset_r_reg(19), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_14\, Q => count_for_reset_r_reg(1), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_11\, Q => count_for_reset_r_reg(20), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_10\, Q => count_for_reset_r_reg(21), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_9\, Q => count_for_reset_r_reg(22), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_8\, Q => count_for_reset_r_reg(23), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_13\, Q => count_for_reset_r_reg(2), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_12\, Q => count_for_reset_r_reg(3), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_11\, Q => count_for_reset_r_reg(4), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_10\, Q => count_for_reset_r_reg(5), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_9\, Q => count_for_reset_r_reg(6), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_8\, Q => count_for_reset_r_reg(7), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_15\, Q => count_for_reset_r_reg(8), R => \count_for_reset_r_reg[23]_0\ ); \count_for_reset_r_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \count_for_reset_r_reg[0]_i_2_n_0\, CI_TOP => '0', CO(7) => \count_for_reset_r_reg[8]_i_1_n_0\, CO(6) => \count_for_reset_r_reg[8]_i_1_n_1\, CO(5) => \count_for_reset_r_reg[8]_i_1_n_2\, CO(4) => \count_for_reset_r_reg[8]_i_1_n_3\, CO(3) => \count_for_reset_r_reg[8]_i_1_n_4\, CO(2) => \count_for_reset_r_reg[8]_i_1_n_5\, CO(1) => \count_for_reset_r_reg[8]_i_1_n_6\, CO(0) => \count_for_reset_r_reg[8]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \count_for_reset_r_reg[8]_i_1_n_8\, O(6) => \count_for_reset_r_reg[8]_i_1_n_9\, O(5) => \count_for_reset_r_reg[8]_i_1_n_10\, O(4) => \count_for_reset_r_reg[8]_i_1_n_11\, O(3) => \count_for_reset_r_reg[8]_i_1_n_12\, O(2) => \count_for_reset_r_reg[8]_i_1_n_13\, O(1) => \count_for_reset_r_reg[8]_i_1_n_14\, O(0) => \count_for_reset_r_reg[8]_i_1_n_15\, S(7 downto 0) => count_for_reset_r_reg(15 downto 8) ); \count_for_reset_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_14\, Q => count_for_reset_r_reg(9), R => \count_for_reset_r_reg[23]_0\ ); do_rd_en_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => cbcc_fifo_reset_rd_clk, I1 => wait_for_rd_en(2), I2 => wait_for_rd_en(1), O => do_rd_en ); do_rd_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => '1', D => new_underflow_flag_c, Q => \^do_rd_en_i\, R => do_rd_en ); do_wr_en_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => FINAL_GATER_FOR_FIFO_DIN0, I1 => p_1_in, I2 => overflow_flag_c, I3 => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0, I4 => \^final_gater_for_fifo_din_i\, O => do_wr_en_i_1_n_0 ); do_wr_en_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => p_0_in0_in, I1 => cb_fifo_din_detect_q, I2 => FINAL_GATER_FOR_FIFO_DIN_reg_0, O => FINAL_GATER_FOR_FIFO_DIN0 ); do_wr_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => do_wr_en_i_1_n_0, Q => do_wr_en, R => '0' ); first_cb_to_write_to_fifo_dlyd_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"01000000" ) port map ( I0 => \raw_data_r_reg_n_0_[18]\, I1 => \raw_data_r_reg_n_0_[17]\, I2 => \raw_data_r_reg_n_0_[16]\, I3 => first_cb_to_write_to_fifo_dlyd_i_2_n_0, I4 => first_cb_to_write_to_fifo_dlyd_i_3_n_0, O => first_cb_to_write_to_fifo ); first_cb_to_write_to_fifo_dlyd_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00100000" ) port map ( I0 => \raw_data_r_reg_n_0_[19]\, I1 => \raw_data_r_reg_n_0_[20]\, I2 => \raw_data_r_reg_n_0_[22]\, I3 => \raw_data_r_reg_n_0_[21]\, I4 => first_cb_to_write_to_fifo_dlyd_i_4_n_0, O => first_cb_to_write_to_fifo_dlyd_i_2_n_0 ); first_cb_to_write_to_fifo_dlyd_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"10000000" ) port map ( I0 => \raw_data_r_reg_n_0_[31]\, I1 => \raw_data_r_reg_n_0_[32]\, I2 => \raw_data_r_reg_n_0_[33]\, I3 => p_1_in, I4 => first_cb_to_write_to_fifo_dlyd_i_5_n_0, O => first_cb_to_write_to_fifo_dlyd_i_3_n_0 ); first_cb_to_write_to_fifo_dlyd_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \raw_data_r_reg_n_0_[26]\, I1 => \raw_data_r_reg_n_0_[25]\, I2 => \raw_data_r_reg_n_0_[24]\, I3 => \raw_data_r_reg_n_0_[23]\, O => first_cb_to_write_to_fifo_dlyd_i_4_n_0 ); first_cb_to_write_to_fifo_dlyd_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \raw_data_r_reg_n_0_[30]\, I1 => \raw_data_r_reg_n_0_[29]\, I2 => \raw_data_r_reg_n_0_[28]\, I3 => \raw_data_r_reg_n_0_[27]\, O => first_cb_to_write_to_fifo_dlyd_i_5_n_0 ); first_cb_to_write_to_fifo_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => first_cb_to_write_to_fifo, Q => first_cb_to_write_to_fifo_dlyd, R => SR(0) ); hard_err_usr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFAAA8AAA8AAA8" ) port map ( I0 => hard_err_usr_reg, I1 => rxbuferr_out_i(1), I2 => rxbuferr_out_i(0), I3 => HARD_ERR_reg, I4 => channel_up_tx_if, I5 => txbufstatus_out(0), O => hard_err_usr0 ); hold_reg_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^do_rd_en_i\, I1 => hold_reg, O => hold_reg_i_1_n_0 ); hold_reg_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => hold_reg_i_1_n_0, Q => hold_reg, R => CC_RXLOSSOFSYNC_OUT_reg_0 ); master_do_rd_en_q_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => \out\, Q => master_do_rd_en_q, R => cbcc_fifo_reset_rd_clk ); \master_fifo.data_fifo\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_fifo_gen_master port map ( din(71 downto 32) => en32_fifo_din_i(79 downto 40), din(31 downto 0) => en32_fifo_din_i(31 downto 0), dout(71 downto 69) => \NLW_master_fifo.data_fifo_dout_UNCONNECTED\(71 downto 69), dout(68) => p_0_in4_in, dout(67 downto 66) => \NLW_master_fifo.data_fifo_dout_UNCONNECTED\(67 downto 66), dout(65 downto 0) => \^dout\(65 downto 0), empty => underflow_flag_c, full => overflow_flag_c, overflow => wr_err_c, prog_empty => buffer_too_empty_c, prog_full => \NLW_master_fifo.data_fifo_prog_full_UNCONNECTED\, rd_clk => s_level_out_d5_reg, rd_en => \out\, rd_rst_busy => \NLW_master_fifo.data_fifo_rd_rst_busy_UNCONNECTED\, srst => srst, underflow => rd_err_c, wr_clk => gtwiz_userclk_rx_usrclk_out, wr_en => new_do_wr_en, wr_rst_busy => \NLW_master_fifo.data_fifo_wr_rst_busy_UNCONNECTED\ ); new_do_wr_en_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => bit80_prsnt, I1 => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0, O => new_do_wr_en_i_1_n_0 ); new_do_wr_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => new_do_wr_en_i_1_n_0, Q => new_do_wr_en, R => '0' ); new_underflow_flag_c_inv_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"57" ) port map ( I0 => underflow_flag_r3, I1 => buffer_too_empty_c, I2 => underflow_flag_c, O => new_underflow_flag_c0 ); new_underflow_flag_c_reg_inv: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => new_underflow_flag_c0, Q => new_underflow_flag_c, R => cbcc_fifo_reset_rd_clk ); \raw_data_r_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[0]\, Q => \raw_data_r_r_reg_n_0_[0]\, R => '0' ); \raw_data_r_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[10]\, Q => \raw_data_r_r_reg_n_0_[10]\, R => '0' ); \raw_data_r_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[11]\, Q => \raw_data_r_r_reg_n_0_[11]\, R => '0' ); \raw_data_r_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[12]\, Q => \raw_data_r_r_reg_n_0_[12]\, R => '0' ); \raw_data_r_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[13]\, Q => \raw_data_r_r_reg_n_0_[13]\, R => '0' ); \raw_data_r_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[14]\, Q => \raw_data_r_r_reg_n_0_[14]\, R => '0' ); \raw_data_r_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[15]\, Q => \raw_data_r_r_reg_n_0_[15]\, R => '0' ); \raw_data_r_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[16]\, Q => \raw_data_r_r_reg_n_0_[16]\, R => '0' ); \raw_data_r_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[17]\, Q => \raw_data_r_r_reg_n_0_[17]\, R => '0' ); \raw_data_r_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[18]\, Q => \raw_data_r_r_reg_n_0_[18]\, R => '0' ); \raw_data_r_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[19]\, Q => \raw_data_r_r_reg_n_0_[19]\, R => '0' ); \raw_data_r_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[1]\, Q => \raw_data_r_r_reg_n_0_[1]\, R => '0' ); \raw_data_r_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[20]\, Q => \raw_data_r_r_reg_n_0_[20]\, R => '0' ); \raw_data_r_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[21]\, Q => \raw_data_r_r_reg_n_0_[21]\, R => '0' ); \raw_data_r_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[22]\, Q => \raw_data_r_r_reg_n_0_[22]\, R => '0' ); \raw_data_r_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[23]\, Q => \raw_data_r_r_reg_n_0_[23]\, R => '0' ); \raw_data_r_r_reg[24]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[24]\, Q => \raw_data_r_r_reg_n_0_[24]\, R => '0' ); \raw_data_r_r_reg[25]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[25]\, Q => \raw_data_r_r_reg_n_0_[25]\, R => '0' ); \raw_data_r_r_reg[26]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[26]\, Q => \raw_data_r_r_reg_n_0_[26]\, R => '0' ); \raw_data_r_r_reg[27]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[27]\, Q => \raw_data_r_r_reg_n_0_[27]\, R => '0' ); \raw_data_r_r_reg[28]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[28]\, Q => \raw_data_r_r_reg_n_0_[28]\, R => '0' ); \raw_data_r_r_reg[29]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[29]\, Q => \raw_data_r_r_reg_n_0_[29]\, R => '0' ); \raw_data_r_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[2]\, Q => \raw_data_r_r_reg_n_0_[2]\, R => '0' ); \raw_data_r_r_reg[30]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[30]\, Q => \raw_data_r_r_reg_n_0_[30]\, R => '0' ); \raw_data_r_r_reg[31]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[31]\, Q => \raw_data_r_r_reg_n_0_[31]\, R => '0' ); \raw_data_r_r_reg[32]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[32]\, Q => \raw_data_r_r_reg_n_0_[32]\, R => '0' ); \raw_data_r_r_reg[33]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[33]\, Q => \raw_data_r_r_reg_n_0_[33]\, R => '0' ); \raw_data_r_r_reg[34]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => p_1_in, Q => p_0_in0_in, R => '0' ); \raw_data_r_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[3]\, Q => \raw_data_r_r_reg_n_0_[3]\, R => '0' ); \raw_data_r_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[4]\, Q => \raw_data_r_r_reg_n_0_[4]\, R => '0' ); \raw_data_r_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[5]\, Q => \raw_data_r_r_reg_n_0_[5]\, R => '0' ); \raw_data_r_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[6]\, Q => \raw_data_r_r_reg_n_0_[6]\, R => '0' ); \raw_data_r_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[7]\, Q => \raw_data_r_r_reg_n_0_[7]\, R => '0' ); \raw_data_r_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[8]\, Q => \raw_data_r_r_reg_n_0_[8]\, R => '0' ); \raw_data_r_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \raw_data_r_reg_n_0_[9]\, Q => \raw_data_r_r_reg_n_0_[9]\, R => '0' ); \raw_data_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(0), Q => \raw_data_r_reg_n_0_[0]\, R => '0' ); \raw_data_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(10), Q => \raw_data_r_reg_n_0_[10]\, R => '0' ); \raw_data_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(11), Q => \raw_data_r_reg_n_0_[11]\, R => '0' ); \raw_data_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(12), Q => \raw_data_r_reg_n_0_[12]\, R => '0' ); \raw_data_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(13), Q => \raw_data_r_reg_n_0_[13]\, R => '0' ); \raw_data_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(14), Q => \raw_data_r_reg_n_0_[14]\, R => '0' ); \raw_data_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(15), Q => \raw_data_r_reg_n_0_[15]\, R => '0' ); \raw_data_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(16), Q => \raw_data_r_reg_n_0_[16]\, R => '0' ); \raw_data_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(17), Q => \raw_data_r_reg_n_0_[17]\, R => '0' ); \raw_data_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(18), Q => \raw_data_r_reg_n_0_[18]\, R => '0' ); \raw_data_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(19), Q => \raw_data_r_reg_n_0_[19]\, R => '0' ); \raw_data_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(1), Q => \raw_data_r_reg_n_0_[1]\, R => '0' ); \raw_data_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(20), Q => \raw_data_r_reg_n_0_[20]\, R => '0' ); \raw_data_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(21), Q => \raw_data_r_reg_n_0_[21]\, R => '0' ); \raw_data_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(22), Q => \raw_data_r_reg_n_0_[22]\, R => '0' ); \raw_data_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(23), Q => \raw_data_r_reg_n_0_[23]\, R => '0' ); \raw_data_r_reg[24]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(24), Q => \raw_data_r_reg_n_0_[24]\, R => '0' ); \raw_data_r_reg[25]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(25), Q => \raw_data_r_reg_n_0_[25]\, R => '0' ); \raw_data_r_reg[26]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(26), Q => \raw_data_r_reg_n_0_[26]\, R => '0' ); \raw_data_r_reg[27]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(27), Q => \raw_data_r_reg_n_0_[27]\, R => '0' ); \raw_data_r_reg[28]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(28), Q => \raw_data_r_reg_n_0_[28]\, R => '0' ); \raw_data_r_reg[29]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(29), Q => \raw_data_r_reg_n_0_[29]\, R => '0' ); \raw_data_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(2), Q => \raw_data_r_reg_n_0_[2]\, R => '0' ); \raw_data_r_reg[30]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(30), Q => \raw_data_r_reg_n_0_[30]\, R => '0' ); \raw_data_r_reg[31]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(31), Q => \raw_data_r_reg_n_0_[31]\, R => '0' ); \raw_data_r_reg[32]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(32), Q => \raw_data_r_reg_n_0_[32]\, R => '0' ); \raw_data_r_reg[33]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(33), Q => \raw_data_r_reg_n_0_[33]\, R => '0' ); \raw_data_r_reg[34]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(34), Q => p_1_in, R => '0' ); \raw_data_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(3), Q => \raw_data_r_reg_n_0_[3]\, R => '0' ); \raw_data_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(4), Q => \raw_data_r_reg_n_0_[4]\, R => '0' ); \raw_data_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(5), Q => \raw_data_r_reg_n_0_[5]\, R => '0' ); \raw_data_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(6), Q => \raw_data_r_reg_n_0_[6]\, R => '0' ); \raw_data_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(7), Q => \raw_data_r_reg_n_0_[7]\, R => '0' ); \raw_data_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(8), Q => \raw_data_r_reg_n_0_[8]\, R => '0' ); \raw_data_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => raw_data_srl_out(9), Q => \raw_data_r_reg_n_0_[9]\, R => '0' ); rd_err_pre_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => rd_err_c, Q => rd_err_pre, R => do_rd_en ); rd_err_q_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => rd_err_pre, Q => rxbuferr_out_i(0), R => do_rd_en ); rxfsm_reset_i_inferred_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => allow_block_sync_propagation_reg, I1 => LINK_RESET_OUT_reg, I2 => link_reset_0_c, I3 => hard_err_rst_int, O => rxfsm_reset_i ); \srlc32e[0].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(0), Q => raw_data_srl_out(0), Q31 => \NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[10].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(10), Q => raw_data_srl_out(10), Q31 => \NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[11].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(11), Q => raw_data_srl_out(11), Q31 => \NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[12].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(12), Q => raw_data_srl_out(12), Q31 => \NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[13].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(13), Q => raw_data_srl_out(13), Q31 => \NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[14].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(14), Q => raw_data_srl_out(14), Q31 => \NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[15].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(15), Q => raw_data_srl_out(15), Q31 => \NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[16].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(16), Q => raw_data_srl_out(16), Q31 => \NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[17].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(17), Q => raw_data_srl_out(17), Q31 => \NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[18].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(18), Q => raw_data_srl_out(18), Q31 => \NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[19].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(19), Q => raw_data_srl_out(19), Q31 => \NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[1].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(1), Q => raw_data_srl_out(1), Q31 => \NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[20].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(20), Q => raw_data_srl_out(20), Q31 => \NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[21].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(21), Q => raw_data_srl_out(21), Q31 => \NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[22].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(22), Q => raw_data_srl_out(22), Q31 => \NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[23].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(23), Q => raw_data_srl_out(23), Q31 => \NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[24].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(24), Q => raw_data_srl_out(24), Q31 => \NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[25].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(25), Q => raw_data_srl_out(25), Q31 => \NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[26].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(26), Q => raw_data_srl_out(26), Q31 => \NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[27].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(27), Q => raw_data_srl_out(27), Q31 => \NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[28].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(28), Q => raw_data_srl_out(28), Q31 => \NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[29].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(29), Q => raw_data_srl_out(29), Q31 => \NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[2].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(2), Q => raw_data_srl_out(2), Q31 => \NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[30].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(30), Q => raw_data_srl_out(30), Q31 => \NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[31].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(31), Q => raw_data_srl_out(31), Q31 => \NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[32].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => Q(0), Q => raw_data_srl_out(32), Q31 => \NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[33].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => Q(1), Q => raw_data_srl_out(33), Q31 => \NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[34].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => rxdatavalid_to_fifo_i, Q => raw_data_srl_out(34), Q31 => \NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[3].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(3), Q => raw_data_srl_out(3), Q31 => \NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[4].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(4), Q => raw_data_srl_out(4), Q31 => \NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[5].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(5), Q => raw_data_srl_out(5), Q31 => \NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[6].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(6), Q => raw_data_srl_out(6), Q31 => \NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[7].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(7), Q => raw_data_srl_out(7), Q31 => \NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[8].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(8), Q => raw_data_srl_out(8), Q31 => \NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[9].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => UNSCRAMBLED_DATA_OUT(9), Q => raw_data_srl_out(9), Q31 => \NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED\ ); u_cdc_overflow_flag_c: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ port map ( cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, full => overflow_flag_c, s_level_out_d5_reg_0 => s_level_out_d5_reg ); u_cdc_rxlossofsync_in: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_27\ port map ( in0 => in0, s_level_out_d5_reg_0 => u_cdc_rxlossofsync_in_n_0, s_level_out_d5_reg_1 => s_level_out_d5_reg ); u_cdc_wr_err_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_28\ port map ( cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, \out\ => wr_err_rd_clk_pre, overflow => wr_err_c, s_level_out_d5_reg_0 => s_level_out_d5_reg ); u_rst_sync_btf_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_29\ port map ( in0 => valid_btf_detect_extend_r2, init_clk => init_clk, stg3_reg_0 => u_rst_sync_btf_sync_n_0 ); underflow_flag_r1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => underflow_flag_c, I1 => buffer_too_empty_c, O => underflow_flag_r10 ); underflow_flag_r1_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d5_reg, CE => '1', D => underflow_flag_r10, Q => underflow_flag_r1, S => cbcc_fifo_reset_rd_clk ); underflow_flag_r2_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d5_reg, CE => '1', D => underflow_flag_r1, Q => underflow_flag_r2, S => cbcc_fifo_reset_rd_clk ); underflow_flag_r3_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d5_reg, CE => '1', D => underflow_flag_r2, Q => underflow_flag_r3, S => cbcc_fifo_reset_rd_clk ); valid_btf_detect_dlyd1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => '1', D => u_rst_sync_btf_sync_n_0, Q => valid_btf_detect_dlyd1, R => '0' ); valid_btf_detect_extend_r20: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => valid_btf_detect_extend_r(0), I1 => valid_btf_detect_extend_r(3), I2 => valid_btf_detect_extend_r(4), I3 => valid_btf_detect_extend_r(1), I4 => valid_btf_detect_extend_r(2), O => valid_btf_detect_extend_r20_n_0 ); valid_btf_detect_extend_r2_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_extend_r20_n_0, Q => valid_btf_detect_extend_r2, R => '0' ); \valid_btf_detect_extend_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_extend_r(1), Q => valid_btf_detect_extend_r(0), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_extend_r(2), Q => valid_btf_detect_extend_r(1), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_extend_r(3), Q => valid_btf_detect_extend_r(2), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_extend_r(4), Q => valid_btf_detect_extend_r(3), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect, Q => valid_btf_detect_extend_r(4), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); valid_btf_detect_reg: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => valid_btf_detect_c, Q => valid_btf_detect, R => '0' ); \wait_for_rd_en[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_for_rd_en(0), O => \wait_for_rd_en[0]_i_1_n_0\ ); \wait_for_rd_en[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => wait_for_rd_en(0), I1 => wait_for_rd_en(1), O => \wait_for_rd_en[1]_i_1_n_0\ ); \wait_for_rd_en[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => wait_for_rd_en(1), I1 => wait_for_rd_en(2), O => \wait_for_rd_en[2]_i_1_n_0\ ); \wait_for_rd_en[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => wait_for_rd_en(0), I1 => wait_for_rd_en(1), I2 => wait_for_rd_en(2), O => \wait_for_rd_en[2]_i_2_n_0\ ); \wait_for_rd_en_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => \wait_for_rd_en[2]_i_1_n_0\, D => \wait_for_rd_en[0]_i_1_n_0\, Q => wait_for_rd_en(0), R => cbcc_fifo_reset_rd_clk ); \wait_for_rd_en_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => \wait_for_rd_en[2]_i_1_n_0\, D => \wait_for_rd_en[1]_i_1_n_0\, Q => wait_for_rd_en(1), R => cbcc_fifo_reset_rd_clk ); \wait_for_rd_en_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d5_reg, CE => \wait_for_rd_en[2]_i_1_n_0\, D => \wait_for_rd_en[2]_i_2_n_0\, Q => wait_for_rd_en(2), R => cbcc_fifo_reset_rd_clk ); \wait_for_wr_en[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_for_wr_en_reg(0), O => \p_0_in__8\(0) ); \wait_for_wr_en[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => wait_for_wr_en_reg(0), I1 => wait_for_wr_en_reg(1), O => \p_0_in__8\(1) ); \wait_for_wr_en[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => wait_for_wr_en_reg(0), I1 => wait_for_wr_en_reg(1), I2 => wait_for_wr_en_reg(2), O => \p_0_in__8\(2) ); \wait_for_wr_en[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => wait_for_wr_en_reg(1), I1 => wait_for_wr_en_reg(0), I2 => wait_for_wr_en_reg(2), I3 => wait_for_wr_en_reg(3), O => \p_0_in__8\(3) ); \wait_for_wr_en[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => wait_for_wr_en_reg(2), I1 => wait_for_wr_en_reg(0), I2 => wait_for_wr_en_reg(1), I3 => wait_for_wr_en_reg(3), I4 => wait_for_wr_en_reg(4), O => \p_0_in__8\(4) ); \wait_for_wr_en[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_for_wr_en_reg(5), O => \wait_for_wr_en[5]_i_1_n_0\ ); \wait_for_wr_en[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => wait_for_wr_en_reg(3), I1 => wait_for_wr_en_reg(1), I2 => wait_for_wr_en_reg(0), I3 => wait_for_wr_en_reg(2), I4 => wait_for_wr_en_reg(4), O => \p_0_in__8\(5) ); \wait_for_wr_en_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(0), Q => wait_for_wr_en_reg(0), R => SR(0) ); \wait_for_wr_en_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(1), Q => wait_for_wr_en_reg(1), R => SR(0) ); \wait_for_wr_en_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(2), Q => wait_for_wr_en_reg(2), R => SR(0) ); \wait_for_wr_en_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(3), Q => wait_for_wr_en_reg(3), R => SR(0) ); \wait_for_wr_en_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(4), Q => wait_for_wr_en_reg(4), R => SR(0) ); \wait_for_wr_en_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wait_for_wr_en[5]_i_1_n_0\, D => \p_0_in__8\(5), Q => wait_for_wr_en_reg(5), R => SR(0) ); \wait_for_wr_en_wr3_reg[0]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(0), Q => \wait_for_wr_en_wr3_reg[0]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[1]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(1), Q => \wait_for_wr_en_wr3_reg[1]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[2]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(2), Q => \wait_for_wr_en_wr3_reg[2]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[3]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(3), Q => \wait_for_wr_en_wr3_reg[3]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[4]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(4), Q => \wait_for_wr_en_wr3_reg[4]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[5]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => gtwiz_userclk_rx_usrclk_out, D => wait_for_wr_en_reg(5), Q => \wait_for_wr_en_wr3_reg[5]_srl3_n_0\ ); \wait_for_wr_en_wr4_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[0]_srl3_n_0\, Q => wait_for_wr_en_wr4(0), R => '0' ); \wait_for_wr_en_wr4_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[1]_srl3_n_0\, Q => wait_for_wr_en_wr4(1), R => '0' ); \wait_for_wr_en_wr4_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[2]_srl3_n_0\, Q => wait_for_wr_en_wr4(2), R => '0' ); \wait_for_wr_en_wr4_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[3]_srl3_n_0\, Q => wait_for_wr_en_wr4(3), R => '0' ); \wait_for_wr_en_wr4_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[4]_srl3_n_0\, Q => wait_for_wr_en_wr4(4), R => '0' ); \wait_for_wr_en_wr4_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => \wait_for_wr_en_wr3_reg[5]_srl3_n_0\, Q => wait_for_wr_en_wr4(5), R => '0' ); \wdth_conv_1stage[39]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF8F8F8F0F0F0F0" ) port map ( I0 => p_0_in0_in, I1 => cb_fifo_din_detect_q, I2 => do_wr_en, I3 => first_cb_to_write_to_fifo_dlyd, I4 => p_1_in, I5 => FINAL_GATER_FOR_FIFO_DIN_reg_0, O => mod_do_wr_en ); \wdth_conv_1stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[0]\, Q => wdth_conv_1stage(0), R => SR(0) ); \wdth_conv_1stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[10]\, Q => wdth_conv_1stage(10), R => SR(0) ); \wdth_conv_1stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[11]\, Q => wdth_conv_1stage(11), R => SR(0) ); \wdth_conv_1stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[12]\, Q => wdth_conv_1stage(12), R => SR(0) ); \wdth_conv_1stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[13]\, Q => wdth_conv_1stage(13), R => SR(0) ); \wdth_conv_1stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[14]\, Q => wdth_conv_1stage(14), R => SR(0) ); \wdth_conv_1stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[15]\, Q => wdth_conv_1stage(15), R => SR(0) ); \wdth_conv_1stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[16]\, Q => wdth_conv_1stage(16), R => SR(0) ); \wdth_conv_1stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[17]\, Q => wdth_conv_1stage(17), R => SR(0) ); \wdth_conv_1stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[18]\, Q => wdth_conv_1stage(18), R => SR(0) ); \wdth_conv_1stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[19]\, Q => wdth_conv_1stage(19), R => SR(0) ); \wdth_conv_1stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[1]\, Q => wdth_conv_1stage(1), R => SR(0) ); \wdth_conv_1stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[20]\, Q => wdth_conv_1stage(20), R => SR(0) ); \wdth_conv_1stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[21]\, Q => wdth_conv_1stage(21), R => SR(0) ); \wdth_conv_1stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[22]\, Q => wdth_conv_1stage(22), R => SR(0) ); \wdth_conv_1stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[23]\, Q => wdth_conv_1stage(23), R => SR(0) ); \wdth_conv_1stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[24]\, Q => wdth_conv_1stage(24), R => SR(0) ); \wdth_conv_1stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[25]\, Q => wdth_conv_1stage(25), R => SR(0) ); \wdth_conv_1stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[26]\, Q => wdth_conv_1stage(26), R => SR(0) ); \wdth_conv_1stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[27]\, Q => wdth_conv_1stage(27), R => SR(0) ); \wdth_conv_1stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[28]\, Q => wdth_conv_1stage(28), R => SR(0) ); \wdth_conv_1stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[29]\, Q => wdth_conv_1stage(29), R => SR(0) ); \wdth_conv_1stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[2]\, Q => wdth_conv_1stage(2), R => SR(0) ); \wdth_conv_1stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[30]\, Q => wdth_conv_1stage(30), R => SR(0) ); \wdth_conv_1stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[31]\, Q => wdth_conv_1stage(31), R => SR(0) ); \wdth_conv_1stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[32]\, Q => wdth_conv_1stage(32), R => SR(0) ); \wdth_conv_1stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[33]\, Q => wdth_conv_1stage(33), R => SR(0) ); \wdth_conv_1stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => rxdatavalid_lookahead_i, Q => wdth_conv_1stage(34), R => SR(0) ); \wdth_conv_1stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => CC_detect_pulse_r, Q => wdth_conv_1stage(35), R => SR(0) ); \wdth_conv_1stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => p_0_in0_in, Q => wdth_conv_1stage(36), R => SR(0) ); \wdth_conv_1stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => CB_detect_dlyd1, Q => wdth_conv_1stage(37), R => SR(0) ); \wdth_conv_1stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => D(0), Q => wdth_conv_1stage(38), R => SR(0) ); \wdth_conv_1stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => D(1), Q => wdth_conv_1stage(39), R => SR(0) ); \wdth_conv_1stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[3]\, Q => wdth_conv_1stage(3), R => SR(0) ); \wdth_conv_1stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[4]\, Q => wdth_conv_1stage(4), R => SR(0) ); \wdth_conv_1stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[5]\, Q => wdth_conv_1stage(5), R => SR(0) ); \wdth_conv_1stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[6]\, Q => wdth_conv_1stage(6), R => SR(0) ); \wdth_conv_1stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[7]\, Q => wdth_conv_1stage(7), R => SR(0) ); \wdth_conv_1stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[8]\, Q => wdth_conv_1stage(8), R => SR(0) ); \wdth_conv_1stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[9]\, Q => wdth_conv_1stage(9), R => SR(0) ); \wdth_conv_2stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(0), Q => en32_fifo_din_i(0), R => SR(0) ); \wdth_conv_2stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(10), Q => en32_fifo_din_i(10), R => SR(0) ); \wdth_conv_2stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(11), Q => en32_fifo_din_i(11), R => SR(0) ); \wdth_conv_2stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(12), Q => en32_fifo_din_i(12), R => SR(0) ); \wdth_conv_2stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(13), Q => en32_fifo_din_i(13), R => SR(0) ); \wdth_conv_2stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(14), Q => en32_fifo_din_i(14), R => SR(0) ); \wdth_conv_2stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(15), Q => en32_fifo_din_i(15), R => SR(0) ); \wdth_conv_2stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(16), Q => en32_fifo_din_i(16), R => SR(0) ); \wdth_conv_2stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(17), Q => en32_fifo_din_i(17), R => SR(0) ); \wdth_conv_2stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(18), Q => en32_fifo_din_i(18), R => SR(0) ); \wdth_conv_2stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(19), Q => en32_fifo_din_i(19), R => SR(0) ); \wdth_conv_2stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(1), Q => en32_fifo_din_i(1), R => SR(0) ); \wdth_conv_2stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(20), Q => en32_fifo_din_i(20), R => SR(0) ); \wdth_conv_2stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(21), Q => en32_fifo_din_i(21), R => SR(0) ); \wdth_conv_2stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(22), Q => en32_fifo_din_i(22), R => SR(0) ); \wdth_conv_2stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(23), Q => en32_fifo_din_i(23), R => SR(0) ); \wdth_conv_2stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(24), Q => en32_fifo_din_i(24), R => SR(0) ); \wdth_conv_2stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(25), Q => en32_fifo_din_i(25), R => SR(0) ); \wdth_conv_2stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(26), Q => en32_fifo_din_i(26), R => SR(0) ); \wdth_conv_2stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(27), Q => en32_fifo_din_i(27), R => SR(0) ); \wdth_conv_2stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(28), Q => en32_fifo_din_i(28), R => SR(0) ); \wdth_conv_2stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(29), Q => en32_fifo_din_i(29), R => SR(0) ); \wdth_conv_2stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(2), Q => en32_fifo_din_i(2), R => SR(0) ); \wdth_conv_2stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(30), Q => en32_fifo_din_i(30), R => SR(0) ); \wdth_conv_2stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(31), Q => en32_fifo_din_i(31), R => SR(0) ); \wdth_conv_2stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(32), Q => wdth_conv_2stage(32), R => SR(0) ); \wdth_conv_2stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(33), Q => wdth_conv_2stage(33), R => SR(0) ); \wdth_conv_2stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(34), Q => wdth_conv_2stage(34), R => SR(0) ); \wdth_conv_2stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(35), Q => wdth_conv_2stage(35), R => SR(0) ); \wdth_conv_2stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(36), Q => wdth_conv_2stage(36), R => SR(0) ); \wdth_conv_2stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(37), Q => wdth_conv_2stage(37), R => SR(0) ); \wdth_conv_2stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(38), Q => wdth_conv_2stage(38), R => SR(0) ); \wdth_conv_2stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(39), Q => wdth_conv_2stage(39), R => SR(0) ); \wdth_conv_2stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(3), Q => en32_fifo_din_i(3), R => SR(0) ); \wdth_conv_2stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(4), Q => en32_fifo_din_i(4), R => SR(0) ); \wdth_conv_2stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(5), Q => en32_fifo_din_i(5), R => SR(0) ); \wdth_conv_2stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(6), Q => en32_fifo_din_i(6), R => SR(0) ); \wdth_conv_2stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(7), Q => en32_fifo_din_i(7), R => SR(0) ); \wdth_conv_2stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(8), Q => en32_fifo_din_i(8), R => SR(0) ); \wdth_conv_2stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_1stage(9), Q => en32_fifo_din_i(9), R => SR(0) ); \wdth_conv_3stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(0), Q => en32_fifo_din_i(40), R => SR(0) ); \wdth_conv_3stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(10), Q => en32_fifo_din_i(50), R => SR(0) ); \wdth_conv_3stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(11), Q => en32_fifo_din_i(51), R => SR(0) ); \wdth_conv_3stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(12), Q => en32_fifo_din_i(52), R => SR(0) ); \wdth_conv_3stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(13), Q => en32_fifo_din_i(53), R => SR(0) ); \wdth_conv_3stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(14), Q => en32_fifo_din_i(54), R => SR(0) ); \wdth_conv_3stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(15), Q => en32_fifo_din_i(55), R => SR(0) ); \wdth_conv_3stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(16), Q => en32_fifo_din_i(56), R => SR(0) ); \wdth_conv_3stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(17), Q => en32_fifo_din_i(57), R => SR(0) ); \wdth_conv_3stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(18), Q => en32_fifo_din_i(58), R => SR(0) ); \wdth_conv_3stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(19), Q => en32_fifo_din_i(59), R => SR(0) ); \wdth_conv_3stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(1), Q => en32_fifo_din_i(41), R => SR(0) ); \wdth_conv_3stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(20), Q => en32_fifo_din_i(60), R => SR(0) ); \wdth_conv_3stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(21), Q => en32_fifo_din_i(61), R => SR(0) ); \wdth_conv_3stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(22), Q => en32_fifo_din_i(62), R => SR(0) ); \wdth_conv_3stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(23), Q => en32_fifo_din_i(63), R => SR(0) ); \wdth_conv_3stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(24), Q => en32_fifo_din_i(64), R => SR(0) ); \wdth_conv_3stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(25), Q => en32_fifo_din_i(65), R => SR(0) ); \wdth_conv_3stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(26), Q => en32_fifo_din_i(66), R => SR(0) ); \wdth_conv_3stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(27), Q => en32_fifo_din_i(67), R => SR(0) ); \wdth_conv_3stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(28), Q => en32_fifo_din_i(68), R => SR(0) ); \wdth_conv_3stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(29), Q => en32_fifo_din_i(69), R => SR(0) ); \wdth_conv_3stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(2), Q => en32_fifo_din_i(42), R => SR(0) ); \wdth_conv_3stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(30), Q => en32_fifo_din_i(70), R => SR(0) ); \wdth_conv_3stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(31), Q => en32_fifo_din_i(71), R => SR(0) ); \wdth_conv_3stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(32), Q => en32_fifo_din_i(72), R => SR(0) ); \wdth_conv_3stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(33), Q => en32_fifo_din_i(73), R => SR(0) ); \wdth_conv_3stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(34), Q => en32_fifo_din_i(74), R => SR(0) ); \wdth_conv_3stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(35), Q => en32_fifo_din_i(75), R => SR(0) ); \wdth_conv_3stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(36), Q => en32_fifo_din_i(76), R => SR(0) ); \wdth_conv_3stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(37), Q => en32_fifo_din_i(77), R => SR(0) ); \wdth_conv_3stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(38), Q => en32_fifo_din_i(78), R => SR(0) ); \wdth_conv_3stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => wdth_conv_2stage(39), Q => en32_fifo_din_i(79), R => SR(0) ); \wdth_conv_3stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(3), Q => en32_fifo_din_i(43), R => SR(0) ); \wdth_conv_3stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(4), Q => en32_fifo_din_i(44), R => SR(0) ); \wdth_conv_3stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(5), Q => en32_fifo_din_i(45), R => SR(0) ); \wdth_conv_3stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(6), Q => en32_fifo_din_i(46), R => SR(0) ); \wdth_conv_3stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(7), Q => en32_fifo_din_i(47), R => SR(0) ); \wdth_conv_3stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(8), Q => en32_fifo_din_i(48), R => SR(0) ); \wdth_conv_3stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => '1', D => en32_fifo_din_i(9), Q => en32_fifo_din_i(49), R => SR(0) ); \wdth_conv_count[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"2D" ) port map ( I0 => bit80_prsnt, I1 => mod_do_wr_en, I2 => \wdth_conv_count_reg_n_0_[0]\, O => p_2_in(0) ); \wdth_conv_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => bit80_prsnt, I1 => mod_do_wr_en, O => \wdth_conv_count[1]_i_1_n_0\ ); \wdth_conv_count[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B0" ) port map ( I0 => mod_do_wr_en, I1 => bit80_prsnt, I2 => \wdth_conv_count_reg_n_0_[0]\, O => p_2_in(1) ); \wdth_conv_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wdth_conv_count[1]_i_1_n_0\, D => p_2_in(0), Q => \wdth_conv_count_reg_n_0_[0]\, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); \wdth_conv_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtwiz_userclk_rx_usrclk_out, CE => \wdth_conv_count[1]_i_1_n_0\, D => p_2_in(1), Q => bit80_prsnt, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); wr_err_rd_clk_sync_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg, CE => '1', D => wr_err_rd_clk_pre, Q => rxbuferr_out_i(1), R => do_rd_en ); \wr_monitor_flag[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wr_monitor_flag_reg(0), O => \p_0_in__9\(0) ); \wr_monitor_flag[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => wr_monitor_flag_reg(0), I1 => wr_monitor_flag_reg(1), O => \p_0_in__9\(1) ); \wr_monitor_flag[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => wr_monitor_flag_reg(0), I1 => wr_monitor_flag_reg(1), I2 => wr_monitor_flag_reg(2), O => \p_0_in__9\(2) ); \wr_monitor_flag[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => wr_monitor_flag_reg(1), I1 => wr_monitor_flag_reg(0), I2 => wr_monitor_flag_reg(2), I3 => wr_monitor_flag_reg(3), O => \p_0_in__9\(3) ); \wr_monitor_flag[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000AA2AAA" ) port map ( I0 => new_do_wr_en, I1 => wr_monitor_flag_reg(0), I2 => wr_monitor_flag_reg(1), I3 => wr_monitor_flag_reg(3), I4 => wr_monitor_flag_reg(2), I5 => wr_monitor_flag_reg(4), O => wr_monitor_flag ); \wr_monitor_flag[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => wr_monitor_flag_reg(2), I1 => wr_monitor_flag_reg(0), I2 => wr_monitor_flag_reg(1), I3 => wr_monitor_flag_reg(3), O => \p_0_in__9\(4) ); \wr_monitor_flag_reg[0]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => wr_monitor_flag, D => \p_0_in__9\(0), Q => wr_monitor_flag_reg(0), R => \wr_monitor_flag_reg[4]_0\(0) ); \wr_monitor_flag_reg[1]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => wr_monitor_flag, D => \p_0_in__9\(1), Q => wr_monitor_flag_reg(1), R => \wr_monitor_flag_reg[4]_0\(0) ); \wr_monitor_flag_reg[2]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => wr_monitor_flag, D => \p_0_in__9\(2), Q => wr_monitor_flag_reg(2), R => \wr_monitor_flag_reg[4]_0\(0) ); \wr_monitor_flag_reg[3]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => wr_monitor_flag, D => \p_0_in__9\(3), Q => wr_monitor_flag_reg(3), R => \wr_monitor_flag_reg[4]_0\(0) ); \wr_monitor_flag_reg[4]\: unisim.vcomponents.FDRE port map ( C => gtwiz_userclk_rx_usrclk_out, CE => wr_monitor_flag, D => \p_0_in__9\(4), Q => wr_monitor_flag_reg(4), R => \wr_monitor_flag_reg[4]_0\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER is port ( gt0_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drprdy : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 ); tx_out_clk : out STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 65 downto 0 ); gt_pll_lock : out STD_LOGIC; rx_lossofsync_i : out STD_LOGIC; link_reset_out : out STD_LOGIC; stg3_reg : out STD_LOGIC; RX_NEG_OUT_reg_0 : out STD_LOGIC; \txseq_counter_i_reg[0]_0\ : out STD_LOGIC; TXDATAVALID_IN : out STD_LOGIC; \txseq_counter_i_reg[1]_0\ : out STD_LOGIC; txdatavalid_symgen_i : out STD_LOGIC; ILLEGAL_BTF_reg : out STD_LOGIC; rxdatavalid_i : out STD_LOGIC; wr_err_rd_clk_sync_reg : out STD_LOGIC; bufg_gt_clr_out : out STD_LOGIC; hold_reg_reg : out STD_LOGIC; tx_dst_rdy_n_r0 : out STD_LOGIC; scrambler : out STD_LOGIC_VECTOR ( 11 downto 0 ); rst_in_out_reg : in STD_LOGIC; gt0_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); init_clk : in STD_LOGIC; gt0_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drpen : in STD_LOGIC; gt0_drpwe : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; refclk1_in : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); gt_rxcdrovrden_in : in STD_LOGIC; sync_clk_out : in STD_LOGIC; stg3_reg_0 : in STD_LOGIC; in0 : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); tx_reset_i : in STD_LOGIC; extend_cc_r : in STD_LOGIC; Q : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; illegal_btf_i : in STD_LOGIC; enable_err_detect_i : in STD_LOGIC; hard_err_usr_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; do_cc_r : in STD_LOGIC; tx_data_i : in STD_LOGIC_VECTOR ( 57 downto 0 ); D : in STD_LOGIC_VECTOR ( 1 downto 0 ); mmcm_not_locked_out2 : in STD_LOGIC; tempData : in STD_LOGIC_VECTOR ( 5 downto 0 ); lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER is signal ANY_VLD_BTF_FLAG : STD_LOGIC; signal CB_detect : STD_LOGIC; signal CB_detect0 : STD_LOGIC; signal CB_detect_dlyd0p5 : STD_LOGIC; signal CC_detect_dlyd1 : STD_LOGIC; signal CC_detect_pulse_i : STD_LOGIC; signal FSM_RESETDONE_j : STD_LOGIC; signal \FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0\ : STD_LOGIC; signal \FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0\ : STD_LOGIC; signal \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\ : STD_LOGIC; signal HPCNT_RESET_IN : STD_LOGIC; signal LINK_RESET_OUT0 : STD_LOGIC; signal \^rx_neg_out_reg_0\ : STD_LOGIC; signal START_CB_WRITES_OUT : STD_LOGIC; signal \TX_DATA[55]_i_3_n_0\ : STD_LOGIC; signal all_start_cb_writes_i : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of all_start_cb_writes_i : signal is "true"; signal all_vld_btf_flag_i : STD_LOGIC; attribute RTL_KEEP of all_vld_btf_flag_i : signal is "true"; signal allow_block_sync_propagation : STD_LOGIC; signal allow_block_sync_propagation_reg_n_0 : STD_LOGIC; signal bit_err_chan_bond_i : STD_LOGIC; attribute RTL_KEEP of bit_err_chan_bond_i : signal is "true"; signal blocksync_all_lanes_inrxclk_q : STD_LOGIC; signal blocksync_out_i : STD_LOGIC; signal cb_bit_err_out : STD_LOGIC; signal cbcc_data_srst : STD_LOGIC; signal cbcc_fifo_reset_rd_clk : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_wr_clk : STD_LOGIC; signal cbcc_fifo_reset_wr_clk : STD_LOGIC; signal cbcc_reset_cbstg2_rd_clk : STD_LOGIC; signal cdr_reset_fsm_cntr_r : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cdr_reset_fsm_cntr_r[0]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[1]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[2]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[3]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[4]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[5]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[6]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_2_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_3_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_4_n_0\ : STD_LOGIC; signal cdr_reset_fsm_lnkreset : STD_LOGIC; signal cdr_reset_fsm_lnkreset_i_1_n_0 : STD_LOGIC; signal cdr_reset_fsm_lnkreset_reg_n_0 : STD_LOGIC; signal common_reset_cbcc_i_n_0 : STD_LOGIC; signal descrambler_64b66b_gtx0_i_n_36 : STD_LOGIC; signal do_rd_en_i : STD_LOGIC; attribute RTL_KEEP of do_rd_en_i : signal is "true"; signal final_gater_for_fifo_din_i : STD_LOGIC; attribute RTL_KEEP of final_gater_for_fifo_din_i : signal is "true"; signal fsm_resetdone_initclk : STD_LOGIC; signal fsm_resetdone_to_rxreset_in : STD_LOGIC; signal gt_cplllock_i : STD_LOGIC; signal gt_cplllock_j : STD_LOGIC; signal gtwiz_userclk_rx_active_in : STD_LOGIC; signal gtx_reset_comb : STD_LOGIC; signal hard_err_cntr_r : STD_LOGIC; signal \hard_err_cntr_r[7]_i_4_n_0\ : STD_LOGIC; signal \hard_err_cntr_r[7]_i_5_n_0\ : STD_LOGIC; signal \hard_err_cntr_r[7]_i_6_n_0\ : STD_LOGIC; signal hard_err_cntr_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); signal hard_err_rst_int : STD_LOGIC; signal hard_err_rst_int0 : STD_LOGIC; signal hard_err_rst_int_i_4_n_0 : STD_LOGIC; signal hard_err_usr : STD_LOGIC; signal hard_err_usr0 : STD_LOGIC; signal int_gt_rxbufstatus : STD_LOGIC_VECTOR ( 2 to 2 ); signal master_do_rd_en_i : STD_LOGIC; attribute RTL_KEEP of master_do_rd_en_i : signal is "true"; signal new_gtx_rx_pcsreset_comb : STD_LOGIC; signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_2_in_1 : STD_LOGIC; signal poly : STD_LOGIC_VECTOR ( 52 to 52 ); signal pos_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pos_rxdatavalid_i : STD_LOGIC; signal pos_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pos_rxheadervalid_i : STD_LOGIC; signal pre_r1_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pre_r1_rxdatavalid_i : STD_LOGIC; signal pre_r1_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pre_r1_rxheadervalid_i : STD_LOGIC; signal pre_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pre_rxdatavalid_i : STD_LOGIC; signal pre_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pre_rxheadervalid_i : STD_LOGIC; signal reset_initclk : STD_LOGIC; signal rx_elastic_buf_err : STD_LOGIC; signal rx_fsm_resetdone_i : STD_LOGIC; attribute RTL_KEEP of rx_fsm_resetdone_i : signal is "true"; signal rx_fsm_resetdone_i_i : STD_LOGIC; signal rx_fsm_resetdone_ii : STD_LOGIC; attribute RTL_KEEP of rx_fsm_resetdone_ii : signal is "true"; signal rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rxdata_to_fifo_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rxdatavalid_i_0 : STD_LOGIC; signal rxdatavalid_to_fifo_i : STD_LOGIC; signal rxfsm_reset_i : STD_LOGIC; attribute RTL_KEEP of rxfsm_reset_i : signal is "true"; signal rxgearboxslip_i : STD_LOGIC; signal rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxheader_to_fifo_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxheadervalid_i : STD_LOGIC; signal rxlossofsync_out_i : STD_LOGIC; signal rxlossofsync_out_q : STD_LOGIC; signal rxreset_for_lanes_q : STD_LOGIC; signal rxusrclk_out : STD_LOGIC; signal scrambled_data_i : STD_LOGIC_VECTOR ( 63 downto 0 ); signal scrambler_64b66b_gtx0_i_n_0 : STD_LOGIC; signal sel : STD_LOGIC; signal stableclk_gtx_reset_comb : STD_LOGIC; signal \^stg3_reg\ : STD_LOGIC; signal sync_rx_polarity_r : STD_LOGIC; signal tx_buf_err_i : STD_LOGIC; signal tx_fsm_resetdone_i : STD_LOGIC; attribute RTL_KEEP of tx_fsm_resetdone_i : signal is "true"; signal tx_fsm_resetdone_ii : STD_LOGIC; attribute RTL_KEEP of tx_fsm_resetdone_ii : signal is "true"; signal tx_hdr_r : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txseq_counter_i : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \txseq_counter_i[0]_i_2_n_0\ : STD_LOGIC; signal \txseq_counter_i[5]_i_2_n_0\ : STD_LOGIC; signal \txseq_counter_i[5]_i_3_n_0\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[0]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[1]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[2]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[3]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[4]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[5]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[6]\ : STD_LOGIC; signal \u_cdc__check_polarity_n_0\ : STD_LOGIC; signal u_cdc_hard_err_init_n_0 : STD_LOGIC; signal u_rst_sync_blocksyncall_initclk_sync_n_0 : STD_LOGIC; signal u_rst_sync_fsm_resetdone_initclk_n_1 : STD_LOGIC; signal u_rst_sync_fsm_resetdone_n_0 : STD_LOGIC; signal unscrambled_data_i052_out : STD_LOGIC; signal valid_btf_detect_c : STD_LOGIC; signal valid_btf_detect_dlyd1 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_onehot_cdr_reset_fsm_r[2]_i_3\ : label is "soft_lutpair104"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[0]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[1]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[2]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute SOFT_HLUTNM of \TX_DATA[55]_i_1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \TX_DATA[55]_i_3\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of TX_HEADER_0_i_2 : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[0]_i_1\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[1]_i_1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[2]_i_1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[3]_i_1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[5]_i_1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[6]_i_1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[7]_i_4\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of data_v_r_i_1 : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \hard_err_cntr_r[1]_i_1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \hard_err_cntr_r[2]_i_1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \hard_err_cntr_r[3]_i_1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \hard_err_cntr_r[4]_i_1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_4\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_5\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_6\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of hard_err_rst_int_i_3 : label is "soft_lutpair101"; attribute shift_extract : string; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[10]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[11]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[12]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[13]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[14]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[15]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[16]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[17]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[18]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[19]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[20]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[21]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[22]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[23]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[24]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[25]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[26]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[27]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[28]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[29]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[2]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[30]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[31]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[3]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[4]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[5]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[6]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[7]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[8]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[9]\ : label is "{no}"; attribute shift_extract of pos_rxdatavalid_i_reg : label is "{no}"; attribute shift_extract of \pos_rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pos_rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of pos_rxheadervalid_i_reg : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[10]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[11]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[12]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[13]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[14]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[15]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[16]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[17]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[18]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[19]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[20]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[21]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[22]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[23]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[24]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[25]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[26]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[27]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[28]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[29]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[2]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[30]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[31]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[3]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[4]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[5]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[6]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[7]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[8]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxdata_from_gtx_i_reg[9]\ : label is "{no}"; attribute shift_extract of pre_r1_rxdatavalid_i_reg : label is "{no}"; attribute shift_extract of \pre_r1_rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pre_r1_rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of pre_r1_rxheadervalid_i_reg : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[10]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[11]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[12]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[13]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[14]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[15]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[16]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[17]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[18]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[19]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[20]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[21]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[22]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[23]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[24]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[25]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[26]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[27]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[28]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[29]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[2]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[30]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[31]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[3]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[4]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[5]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[6]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[7]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[8]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[9]\ : label is "{no}"; attribute shift_extract of rxdatavalid_i_reg : label is "{no}"; attribute shift_extract of \rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of rxheadervalid_i_reg : label is "{no}"; attribute SOFT_HLUTNM of \txseq_counter_i[0]_i_2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \txseq_counter_i[1]_i_1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \txseq_counter_i[2]_i_1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \txseq_counter_i[3]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \txseq_counter_i[4]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \txseq_counter_i[5]_i_2\ : label is "soft_lutpair98"; begin RX_NEG_OUT_reg_0 <= \^rx_neg_out_reg_0\; stg3_reg <= \^stg3_reg\; FSM_RESETDONE_j_reg: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => \^stg3_reg\, Q => FSM_RESETDONE_j, R => '0' ); \FSM_onehot_cdr_reset_fsm_r[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => allow_block_sync_propagation, I1 => cdr_reset_fsm_lnkreset, O => \FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0\ ); \FSM_onehot_cdr_reset_fsm_r[2]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, I1 => cdr_reset_fsm_cntr_r(7), I2 => cdr_reset_fsm_cntr_r(6), I3 => cdr_reset_fsm_cntr_r(4), I4 => cdr_reset_fsm_cntr_r(5), O => \FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0\ ); \FSM_onehot_cdr_reset_fsm_r_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => init_clk, CE => u_rst_sync_blocksyncall_initclk_sync_n_0, D => '0', Q => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, S => p_2_in_1 ); \FSM_onehot_cdr_reset_fsm_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => u_rst_sync_blocksyncall_initclk_sync_n_0, D => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, Q => cdr_reset_fsm_lnkreset, R => p_2_in_1 ); \FSM_onehot_cdr_reset_fsm_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => u_rst_sync_blocksyncall_initclk_sync_n_0, D => \FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0\, Q => allow_block_sync_propagation, R => p_2_in_1 ); LINK_RESET_OUT_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => LINK_RESET_OUT0, Q => link_reset_out, R => '0' ); PLLLKDET_OUT: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => gt_cplllock_i, I1 => rx_fsm_resetdone_ii, I2 => tx_fsm_resetdone_ii, O => gt_pll_lock ); RX_NEG_OUT_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => \u_cdc__check_polarity_n_0\, Q => \^rx_neg_out_reg_0\, R => '0' ); \TX_DATA[55]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFD" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \TX_DATA[55]_i_3_n_0\, I2 => \txseq_counter_i_reg_n_0_[6]\, I3 => \txseq_counter_i_reg_n_0_[0]\, I4 => rst_pma_init_usrclk, O => \txseq_counter_i_reg[1]_0\ ); \TX_DATA[55]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => \txseq_counter_i_reg_n_0_[4]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[3]\, I3 => \txseq_counter_i_reg_n_0_[5]\, O => \TX_DATA[55]_i_3_n_0\ ); TX_HEADER_0_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FEFF" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, O => txdatavalid_symgen_i ); allow_block_sync_propagation_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => cdr_reset_fsm_lnkreset_i_1_n_0, D => allow_block_sync_propagation, Q => allow_block_sync_propagation_reg_n_0, R => p_2_in_1 ); aurora_64b66b_0_multi_gt_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT port map ( D(31 downto 0) => pre_rxdata_from_gtx_i(31 downto 0), E(0) => sel, Q(1 downto 0) => tx_hdr_r(1 downto 0), SCRAMBLED_DATA_OUT(63 downto 0) => scrambled_data_i(63 downto 0), bufg_gt_clr_out => bufg_gt_clr_out, cplllock_out(0) => gt_cplllock_j, gt0_drpaddr(8 downto 0) => gt0_drpaddr(8 downto 0), gt0_drpdi(15 downto 0) => gt0_drpdi(15 downto 0), gt0_drpdo(15 downto 0) => gt0_drpdo(15 downto 0), gt0_drpen => gt0_drpen, gt0_drprdy => gt0_drprdy, gt0_drpwe => gt0_drpwe, gt_powergood(0) => gt_powergood(0), gt_rxcdrovrden_in => gt_rxcdrovrden_in, gtwiz_reset_rx_done_out(0) => rx_fsm_resetdone_i, gtwiz_reset_tx_done_out(0) => tx_fsm_resetdone_i, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, i_in_meta_reg(0) => rxgearboxslip_i, i_in_meta_reg_0 => sync_rx_polarity_r, i_in_meta_reg_1(6) => \txseq_counter_i_reg_n_0_[6]\, i_in_meta_reg_1(5) => \txseq_counter_i_reg_n_0_[5]\, i_in_meta_reg_1(4) => \txseq_counter_i_reg_n_0_[4]\, i_in_meta_reg_1(3) => \txseq_counter_i_reg_n_0_[3]\, i_in_meta_reg_1(2) => \txseq_counter_i_reg_n_0_[2]\, i_in_meta_reg_1(1) => \txseq_counter_i_reg_n_0_[1]\, i_in_meta_reg_1(0) => \txseq_counter_i_reg_n_0_[0]\, init_clk => init_clk, init_clk_0(1 downto 0) => pre_rxheader_from_gtx_i(1 downto 0), loopback(2 downto 0) => loopback(2 downto 0), lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, mmcm_not_locked_out2 => mmcm_not_locked_out2, \out\(0) => gtwiz_userclk_rx_active_in, refclk1_in => refclk1_in, rst_in_out_reg => rst_in_out_reg, rst_in_out_reg_0 => rxfsm_reset_i, rst_in_out_reg_1 => stg3_reg_0, rxbufstatus_out(0) => int_gt_rxbufstatus(2), rxdatavalid_out(0) => pre_rxdatavalid_i, rxheadervalid_out(0) => pre_rxheadervalid_i, rxn => rxn, rxp => rxp, sync_clk_out => sync_clk_out, tx_out_clk => tx_out_clk, txbufstatus_out(0) => tx_buf_err_i, txn => txn, txp => txp ); block_sync_sm_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM port map ( D(0) => rxgearboxslip_i, Q(1 downto 0) => rxheader_from_gtx_i(1 downto 0), SR(0) => new_gtx_rx_pcsreset_comb, blocksync_out_i => blocksync_out_i, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, rxheadervalid_i => rxheadervalid_i ); blocksync_all_lanes_inrxclk_q_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rxusrclk_out, CE => '1', D => blocksync_out_i, Q => blocksync_all_lanes_inrxclk_q, R => '0' ); cbcc_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING port map ( ANY_VLD_BTF_FLAG => ANY_VLD_BTF_FLAG, CB_detect0 => CB_detect0, CB_detect_dlyd0p5 => CB_detect_dlyd0p5, CC_RXLOSSOFSYNC_OUT_reg_0 => common_reset_cbcc_i_n_0, CC_detect_dlyd1 => CC_detect_dlyd1, D(1) => CC_detect_pulse_i, D(0) => CB_detect, FINAL_GATER_FOR_FIFO_DIN_reg_0 => all_start_cb_writes_i, HARD_ERR_reg => rx_elastic_buf_err, ILLEGAL_BTF_reg => ILLEGAL_BTF_reg, LINK_RESET_OUT0 => LINK_RESET_OUT0, LINK_RESET_OUT_reg => cdr_reset_fsm_lnkreset_reg_n_0, \LINK_RESET_reg[0]_0\(0) => p_2_in_1, Q(1 downto 0) => rxheader_to_fifo_i(1 downto 0), SR(0) => cbcc_fifo_reset_wr_clk, START_CB_WRITES_OUT => START_CB_WRITES_OUT, START_CB_WRITES_OUT_reg_0 => all_vld_btf_flag_i, UNSCRAMBLED_DATA_OUT(31 downto 0) => rxdata_to_fifo_i(31 downto 0), allow_block_sync_propagation_reg => rst_in_out_reg, bit_err_chan_bond_i => bit_err_chan_bond_i, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, channel_up_tx_if => channel_up_tx_if, \count_for_reset_r_reg[23]_0\ => u_rst_sync_fsm_resetdone_initclk_n_1, do_rd_en_i => do_rd_en_i, dout(65 downto 0) => dout(65 downto 0), enable_err_detect_i => enable_err_detect_i, final_gater_for_fifo_din_i => final_gater_for_fifo_din_i, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, hard_err_rst_int => hard_err_rst_int, hard_err_usr0 => hard_err_usr0, hard_err_usr_reg => hard_err_usr_reg_0, hold_reg_reg_0 => hold_reg_reg, illegal_btf_i => illegal_btf_i, in0 => rxlossofsync_out_q, init_clk => init_clk, \out\ => master_do_rd_en_i, rx_lossofsync_i => rx_lossofsync_i, rxdatavalid_i => rxdatavalid_i, rxdatavalid_to_fifo_i => rxdatavalid_to_fifo_i, rxfsm_reset_i => rxfsm_reset_i, s_level_out_d5_reg => stg3_reg_0, srst => cbcc_data_srst, txbufstatus_out(0) => tx_buf_err_i, valid_btf_detect_c => valid_btf_detect_c, valid_btf_detect_dlyd1 => valid_btf_detect_dlyd1, \valid_btf_detect_extend_r_reg[4]_0\(0) => new_gtx_rx_pcsreset_comb, wr_err_rd_clk_sync_reg_0 => wr_err_rd_clk_sync_reg, \wr_monitor_flag_reg[4]_0\(0) => cbcc_fifo_reset_to_fifo_wr_clk ); \cdr_reset_fsm_cntr_r[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(0), O => \cdr_reset_fsm_cntr_r[0]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"60" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[1]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7800" ) port map ( I0 => cdr_reset_fsm_cntr_r(0), I1 => cdr_reset_fsm_cntr_r(1), I2 => cdr_reset_fsm_cntr_r(2), I3 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[2]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(2), I2 => cdr_reset_fsm_cntr_r(1), I3 => cdr_reset_fsm_cntr_r(0), I4 => cdr_reset_fsm_cntr_r(3), O => \cdr_reset_fsm_cntr_r[3]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF800000000000" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_cntr_r(3), I3 => cdr_reset_fsm_cntr_r(2), I4 => cdr_reset_fsm_cntr_r(4), I5 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[4]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2A80" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(4), I2 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, I3 => cdr_reset_fsm_cntr_r(5), O => \cdr_reset_fsm_cntr_r[5]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(5), I2 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, I3 => cdr_reset_fsm_cntr_r(4), I4 => cdr_reset_fsm_cntr_r(6), O => \cdr_reset_fsm_cntr_r[6]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, I1 => allow_block_sync_propagation, I2 => \cdr_reset_fsm_cntr_r[7]_i_3_n_0\, O => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA80000000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(4), I2 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, I3 => cdr_reset_fsm_cntr_r(5), I4 => cdr_reset_fsm_cntr_r(6), I5 => cdr_reset_fsm_cntr_r(7), O => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAAAAAAAAAA" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(5), I2 => cdr_reset_fsm_cntr_r(4), I3 => cdr_reset_fsm_cntr_r(6), I4 => cdr_reset_fsm_cntr_r(7), I5 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, O => \cdr_reset_fsm_cntr_r[7]_i_3_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_cntr_r(3), I3 => cdr_reset_fsm_cntr_r(2), O => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\ ); \cdr_reset_fsm_cntr_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[0]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(0), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[1]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(1), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[2]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(2), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[3]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(3), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[4]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(4), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[5]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(5), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[6]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(6), R => p_2_in_1 ); \cdr_reset_fsm_cntr_r_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => \cdr_reset_fsm_cntr_r[7]_i_1_n_0\, D => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, Q => cdr_reset_fsm_cntr_r(7), R => p_2_in_1 ); cdr_reset_fsm_lnkreset_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, I2 => allow_block_sync_propagation, O => cdr_reset_fsm_lnkreset_i_1_n_0 ); cdr_reset_fsm_lnkreset_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => cdr_reset_fsm_lnkreset_i_1_n_0, D => cdr_reset_fsm_lnkreset, Q => cdr_reset_fsm_lnkreset_reg_n_0, R => p_2_in_1 ); common_logic_cbcc_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc port map ( ANY_VLD_BTF_FLAG => ANY_VLD_BTF_FLAG, SR(0) => cbcc_fifo_reset_wr_clk, START_CB_WRITES_OUT => START_CB_WRITES_OUT, all_vld_btf_flag_i => all_vld_btf_flag_i, cb_bit_err_out => cb_bit_err_out, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => all_start_cb_writes_i, master_do_rd_en_i => master_do_rd_en_i, master_do_rd_en_out_reg_0 => do_rd_en_i, master_do_rd_en_out_reg_1 => stg3_reg_0, \out\ => bit_err_chan_bond_i ); common_reset_cbcc_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc port map ( SR(0) => cbcc_fifo_reset_wr_clk, cb_bit_err_out => cb_bit_err_out, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, srst => cbcc_data_srst, stg1_aurora_64b66b_0_cdc_to_reg(0) => new_gtx_rx_pcsreset_comb, stg5_reg => common_reset_cbcc_i_n_0, stg5_reg_0 => stg3_reg_0, stg9_reg(0) => cbcc_fifo_reset_to_fifo_wr_clk ); data_v_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, O => TXDATAVALID_IN ); descrambler_64b66b_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B port map ( CB_detect0 => CB_detect0, CB_detect_dlyd0p5 => CB_detect_dlyd0p5, CB_detect_dlyd0p5_reg(1 downto 0) => rxheader_to_fifo_i(1 downto 0), CC_detect_dlyd1 => CC_detect_dlyd1, D(1) => CC_detect_pulse_i, D(0) => CB_detect, E(0) => rxdatavalid_i_0, Q(31 downto 0) => rxdata_to_fifo_i(31 downto 0), \descrambler_reg[31]_0\(31 downto 0) => rxdata_from_gtx_i(31 downto 0), \descrambler_reg[39]_0\(1) => descrambler_64b66b_gtx0_i_n_36, \descrambler_reg[39]_0\(0) => poly(52), gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => rxlossofsync_out_q, rxdatavalid_to_fifo_i => rxdatavalid_to_fifo_i, \unscrambled_data_i_reg[13]_0\(0) => unscrambled_data_i052_out, valid_btf_detect_c => valid_btf_detect_c ); extend_cc_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF000100000000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, I4 => extend_cc_r, I5 => Q, O => \txseq_counter_i_reg[0]_0\ ); \hard_err_cntr_r[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => hard_err_cntr_r_reg(0), O => \p_0_in__4\(0) ); \hard_err_cntr_r[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => hard_err_cntr_r_reg(0), I1 => hard_err_cntr_r_reg(1), O => \p_0_in__4\(1) ); \hard_err_cntr_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => hard_err_cntr_r_reg(1), I1 => hard_err_cntr_r_reg(0), I2 => hard_err_cntr_r_reg(2), O => \p_0_in__4\(2) ); \hard_err_cntr_r[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => hard_err_cntr_r_reg(2), I1 => hard_err_cntr_r_reg(0), I2 => hard_err_cntr_r_reg(1), I3 => hard_err_cntr_r_reg(3), O => \p_0_in__4\(3) ); \hard_err_cntr_r[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => hard_err_cntr_r_reg(3), I1 => hard_err_cntr_r_reg(1), I2 => hard_err_cntr_r_reg(0), I3 => hard_err_cntr_r_reg(2), I4 => hard_err_cntr_r_reg(4), O => \p_0_in__4\(4) ); \hard_err_cntr_r[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => hard_err_cntr_r_reg(1), I1 => hard_err_cntr_r_reg(0), I2 => hard_err_cntr_r_reg(2), I3 => hard_err_cntr_r_reg(3), I4 => hard_err_cntr_r_reg(4), I5 => hard_err_cntr_r_reg(5), O => \p_0_in__4\(5) ); \hard_err_cntr_r[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"BFFF4000" ) port map ( I0 => \hard_err_cntr_r[7]_i_6_n_0\, I1 => hard_err_cntr_r_reg(4), I2 => hard_err_cntr_r_reg(3), I3 => hard_err_cntr_r_reg(5), I4 => hard_err_cntr_r_reg(6), O => \p_0_in__4\(6) ); \hard_err_cntr_r[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFFFFF40000000" ) port map ( I0 => \hard_err_cntr_r[7]_i_6_n_0\, I1 => hard_err_cntr_r_reg(5), I2 => hard_err_cntr_r_reg(3), I3 => hard_err_cntr_r_reg(4), I4 => hard_err_cntr_r_reg(6), I5 => hard_err_cntr_r_reg(7), O => \p_0_in__4\(7) ); \hard_err_cntr_r[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => hard_err_cntr_r_reg(6), I1 => hard_err_cntr_r_reg(4), I2 => hard_err_cntr_r_reg(3), I3 => hard_err_cntr_r_reg(5), I4 => hard_err_cntr_r_reg(7), O => \hard_err_cntr_r[7]_i_4_n_0\ ); \hard_err_cntr_r[7]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => hard_err_cntr_r_reg(3), I1 => hard_err_cntr_r_reg(6), I2 => hard_err_cntr_r_reg(7), I3 => hard_err_cntr_r_reg(5), I4 => hard_err_cntr_r_reg(4), O => \hard_err_cntr_r[7]_i_5_n_0\ ); \hard_err_cntr_r[7]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => hard_err_cntr_r_reg(1), I1 => hard_err_cntr_r_reg(0), I2 => hard_err_cntr_r_reg(2), O => \hard_err_cntr_r[7]_i_6_n_0\ ); \hard_err_cntr_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(0), Q => hard_err_cntr_r_reg(0), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(1), Q => hard_err_cntr_r_reg(1), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(2), Q => hard_err_cntr_r_reg(2), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(3), Q => hard_err_cntr_r_reg(3), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(4), Q => hard_err_cntr_r_reg(4), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(5), Q => hard_err_cntr_r_reg(5), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(6), Q => hard_err_cntr_r_reg(6), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => init_clk, CE => hard_err_cntr_r, D => \p_0_in__4\(7), Q => hard_err_cntr_r_reg(7), R => HPCNT_RESET_IN ); hard_err_rst_int_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"AAAE" ) port map ( I0 => hard_err_rst_int_i_4_n_0, I1 => hard_err_cntr_r_reg(2), I2 => hard_err_cntr_r_reg(0), I3 => hard_err_cntr_r_reg(1), O => hard_err_rst_int0 ); hard_err_rst_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFE" ) port map ( I0 => hard_err_cntr_r_reg(2), I1 => hard_err_cntr_r_reg(6), I2 => hard_err_cntr_r_reg(4), I3 => hard_err_cntr_r_reg(3), I4 => hard_err_cntr_r_reg(5), I5 => hard_err_cntr_r_reg(7), O => hard_err_rst_int_i_4_n_0 ); hard_err_rst_int_reg: unisim.vcomponents.FDRE port map ( C => init_clk, CE => '1', D => u_cdc_hard_err_init_n_0, Q => hard_err_rst_int, R => '0' ); hard_err_usr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg3_reg_0, CE => '1', D => hard_err_usr0, Q => hard_err_usr, R => '0' ); new_gtx_rx_pcsreset_comb_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => rxusrclk_out, CE => '1', D => u_rst_sync_fsm_resetdone_n_0, Q => new_gtx_rx_pcsreset_comb, R => '0' ); \pos_rxdata_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(0), Q => pos_rxdata_from_gtx_i(0), R => '0' ); \pos_rxdata_from_gtx_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(10), Q => pos_rxdata_from_gtx_i(10), R => '0' ); \pos_rxdata_from_gtx_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(11), Q => pos_rxdata_from_gtx_i(11), R => '0' ); \pos_rxdata_from_gtx_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(12), Q => pos_rxdata_from_gtx_i(12), R => '0' ); \pos_rxdata_from_gtx_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(13), Q => pos_rxdata_from_gtx_i(13), R => '0' ); \pos_rxdata_from_gtx_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(14), Q => pos_rxdata_from_gtx_i(14), R => '0' ); \pos_rxdata_from_gtx_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(15), Q => pos_rxdata_from_gtx_i(15), R => '0' ); \pos_rxdata_from_gtx_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(16), Q => pos_rxdata_from_gtx_i(16), R => '0' ); \pos_rxdata_from_gtx_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(17), Q => pos_rxdata_from_gtx_i(17), R => '0' ); \pos_rxdata_from_gtx_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(18), Q => pos_rxdata_from_gtx_i(18), R => '0' ); \pos_rxdata_from_gtx_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(19), Q => pos_rxdata_from_gtx_i(19), R => '0' ); \pos_rxdata_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(1), Q => pos_rxdata_from_gtx_i(1), R => '0' ); \pos_rxdata_from_gtx_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(20), Q => pos_rxdata_from_gtx_i(20), R => '0' ); \pos_rxdata_from_gtx_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(21), Q => pos_rxdata_from_gtx_i(21), R => '0' ); \pos_rxdata_from_gtx_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(22), Q => pos_rxdata_from_gtx_i(22), R => '0' ); \pos_rxdata_from_gtx_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(23), Q => pos_rxdata_from_gtx_i(23), R => '0' ); \pos_rxdata_from_gtx_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(24), Q => pos_rxdata_from_gtx_i(24), R => '0' ); \pos_rxdata_from_gtx_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(25), Q => pos_rxdata_from_gtx_i(25), R => '0' ); \pos_rxdata_from_gtx_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(26), Q => pos_rxdata_from_gtx_i(26), R => '0' ); \pos_rxdata_from_gtx_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(27), Q => pos_rxdata_from_gtx_i(27), R => '0' ); \pos_rxdata_from_gtx_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(28), Q => pos_rxdata_from_gtx_i(28), R => '0' ); \pos_rxdata_from_gtx_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(29), Q => pos_rxdata_from_gtx_i(29), R => '0' ); \pos_rxdata_from_gtx_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(2), Q => pos_rxdata_from_gtx_i(2), R => '0' ); \pos_rxdata_from_gtx_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(30), Q => pos_rxdata_from_gtx_i(30), R => '0' ); \pos_rxdata_from_gtx_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(31), Q => pos_rxdata_from_gtx_i(31), R => '0' ); \pos_rxdata_from_gtx_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(3), Q => pos_rxdata_from_gtx_i(3), R => '0' ); \pos_rxdata_from_gtx_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(4), Q => pos_rxdata_from_gtx_i(4), R => '0' ); \pos_rxdata_from_gtx_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(5), Q => pos_rxdata_from_gtx_i(5), R => '0' ); \pos_rxdata_from_gtx_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(6), Q => pos_rxdata_from_gtx_i(6), R => '0' ); \pos_rxdata_from_gtx_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(7), Q => pos_rxdata_from_gtx_i(7), R => '0' ); \pos_rxdata_from_gtx_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(8), Q => pos_rxdata_from_gtx_i(8), R => '0' ); \pos_rxdata_from_gtx_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxdatavalid_i, D => pre_r1_rxdata_from_gtx_i(9), Q => pos_rxdata_from_gtx_i(9), R => '0' ); pos_rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_r1_rxdatavalid_i, Q => pos_rxdatavalid_i, R => '0' ); \pos_rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxheadervalid_i, D => pre_r1_rxheader_from_gtx_i(0), Q => pos_rxheader_from_gtx_i(0), R => '0' ); \pos_rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => pre_r1_rxheadervalid_i, D => pre_r1_rxheader_from_gtx_i(1), Q => pos_rxheader_from_gtx_i(1), R => '0' ); pos_rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_r1_rxheadervalid_i, Q => pos_rxheadervalid_i, R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(0), Q => pre_r1_rxdata_from_gtx_i(0), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(10), Q => pre_r1_rxdata_from_gtx_i(10), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(11), Q => pre_r1_rxdata_from_gtx_i(11), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(12), Q => pre_r1_rxdata_from_gtx_i(12), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(13), Q => pre_r1_rxdata_from_gtx_i(13), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(14), Q => pre_r1_rxdata_from_gtx_i(14), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(15), Q => pre_r1_rxdata_from_gtx_i(15), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(16), Q => pre_r1_rxdata_from_gtx_i(16), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(17), Q => pre_r1_rxdata_from_gtx_i(17), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(18), Q => pre_r1_rxdata_from_gtx_i(18), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(19), Q => pre_r1_rxdata_from_gtx_i(19), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(1), Q => pre_r1_rxdata_from_gtx_i(1), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(20), Q => pre_r1_rxdata_from_gtx_i(20), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(21), Q => pre_r1_rxdata_from_gtx_i(21), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(22), Q => pre_r1_rxdata_from_gtx_i(22), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(23), Q => pre_r1_rxdata_from_gtx_i(23), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(24), Q => pre_r1_rxdata_from_gtx_i(24), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(25), Q => pre_r1_rxdata_from_gtx_i(25), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(26), Q => pre_r1_rxdata_from_gtx_i(26), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(27), Q => pre_r1_rxdata_from_gtx_i(27), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(28), Q => pre_r1_rxdata_from_gtx_i(28), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(29), Q => pre_r1_rxdata_from_gtx_i(29), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(2), Q => pre_r1_rxdata_from_gtx_i(2), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(30), Q => pre_r1_rxdata_from_gtx_i(30), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(31), Q => pre_r1_rxdata_from_gtx_i(31), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(3), Q => pre_r1_rxdata_from_gtx_i(3), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(4), Q => pre_r1_rxdata_from_gtx_i(4), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(5), Q => pre_r1_rxdata_from_gtx_i(5), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(6), Q => pre_r1_rxdata_from_gtx_i(6), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(7), Q => pre_r1_rxdata_from_gtx_i(7), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(8), Q => pre_r1_rxdata_from_gtx_i(8), R => '0' ); \pre_r1_rxdata_from_gtx_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdata_from_gtx_i(9), Q => pre_r1_rxdata_from_gtx_i(9), R => '0' ); pre_r1_rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxdatavalid_i, Q => pre_r1_rxdatavalid_i, R => '0' ); \pre_r1_rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxheader_from_gtx_i(0), Q => pre_r1_rxheader_from_gtx_i(0), R => '0' ); \pre_r1_rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxheader_from_gtx_i(1), Q => pre_r1_rxheader_from_gtx_i(1), R => '0' ); pre_r1_rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pre_rxheadervalid_i, Q => pre_r1_rxheadervalid_i, R => '0' ); \rxdata_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(0), Q => rxdata_from_gtx_i(0), R => '0' ); \rxdata_from_gtx_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(10), Q => rxdata_from_gtx_i(10), R => '0' ); \rxdata_from_gtx_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(11), Q => rxdata_from_gtx_i(11), R => '0' ); \rxdata_from_gtx_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(12), Q => rxdata_from_gtx_i(12), R => '0' ); \rxdata_from_gtx_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(13), Q => rxdata_from_gtx_i(13), R => '0' ); \rxdata_from_gtx_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(14), Q => rxdata_from_gtx_i(14), R => '0' ); \rxdata_from_gtx_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(15), Q => rxdata_from_gtx_i(15), R => '0' ); \rxdata_from_gtx_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(16), Q => rxdata_from_gtx_i(16), R => '0' ); \rxdata_from_gtx_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(17), Q => rxdata_from_gtx_i(17), R => '0' ); \rxdata_from_gtx_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(18), Q => rxdata_from_gtx_i(18), R => '0' ); \rxdata_from_gtx_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(19), Q => rxdata_from_gtx_i(19), R => '0' ); \rxdata_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(1), Q => rxdata_from_gtx_i(1), R => '0' ); \rxdata_from_gtx_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(20), Q => rxdata_from_gtx_i(20), R => '0' ); \rxdata_from_gtx_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(21), Q => rxdata_from_gtx_i(21), R => '0' ); \rxdata_from_gtx_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(22), Q => rxdata_from_gtx_i(22), R => '0' ); \rxdata_from_gtx_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(23), Q => rxdata_from_gtx_i(23), R => '0' ); \rxdata_from_gtx_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(24), Q => rxdata_from_gtx_i(24), R => '0' ); \rxdata_from_gtx_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(25), Q => rxdata_from_gtx_i(25), R => '0' ); \rxdata_from_gtx_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(26), Q => rxdata_from_gtx_i(26), R => '0' ); \rxdata_from_gtx_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(27), Q => rxdata_from_gtx_i(27), R => '0' ); \rxdata_from_gtx_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(28), Q => rxdata_from_gtx_i(28), R => '0' ); \rxdata_from_gtx_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(29), Q => rxdata_from_gtx_i(29), R => '0' ); \rxdata_from_gtx_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(2), Q => rxdata_from_gtx_i(2), R => '0' ); \rxdata_from_gtx_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(30), Q => rxdata_from_gtx_i(30), R => '0' ); \rxdata_from_gtx_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(31), Q => rxdata_from_gtx_i(31), R => '0' ); \rxdata_from_gtx_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(3), Q => rxdata_from_gtx_i(3), R => '0' ); \rxdata_from_gtx_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(4), Q => rxdata_from_gtx_i(4), R => '0' ); \rxdata_from_gtx_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(5), Q => rxdata_from_gtx_i(5), R => '0' ); \rxdata_from_gtx_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(6), Q => rxdata_from_gtx_i(6), R => '0' ); \rxdata_from_gtx_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(7), Q => rxdata_from_gtx_i(7), R => '0' ); \rxdata_from_gtx_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(8), Q => rxdata_from_gtx_i(8), R => '0' ); \rxdata_from_gtx_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdata_from_gtx_i(9), Q => rxdata_from_gtx_i(9), R => '0' ); rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxdatavalid_i, Q => rxdatavalid_i_0, R => '0' ); rxdatavalid_to_fifo_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => rxdatavalid_i_0, Q => rxdatavalid_to_fifo_i, R => '0' ); \rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxheader_from_gtx_i(0), Q => rxheader_from_gtx_i(0), R => '0' ); \rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxheader_from_gtx_i(1), Q => rxheader_from_gtx_i(1), R => '0' ); \rxheader_to_fifo_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => rxheader_from_gtx_i(0), Q => rxheader_to_fifo_i(0), R => '0' ); \rxheader_to_fifo_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => rxheader_from_gtx_i(1), Q => rxheader_to_fifo_i(1), R => '0' ); rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => pos_rxheadervalid_i, Q => rxheadervalid_i, R => '0' ); rxlossofsync_out_q_reg: unisim.vcomponents.FDRE port map ( C => rxusrclk_out, CE => '1', D => rxlossofsync_out_i, Q => rxlossofsync_out_q, R => '0' ); rxreset_for_lanes_q_reg: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => tx_reset_i, Q => rxreset_for_lanes_q, R => '0' ); scrambler_64b66b_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B port map ( Q(6) => \txseq_counter_i_reg_n_0_[6]\, Q(5) => \txseq_counter_i_reg_n_0_[5]\, Q(4) => \txseq_counter_i_reg_n_0_[4]\, Q(3) => \txseq_counter_i_reg_n_0_[3]\, Q(2) => \txseq_counter_i_reg_n_0_[2]\, Q(1) => \txseq_counter_i_reg_n_0_[1]\, Q(0) => \txseq_counter_i_reg_n_0_[0]\, \SCRAMBLED_DATA_OUT_reg[63]_0\(63 downto 0) => scrambled_data_i(63 downto 0), \SCRAMBLED_DATA_OUT_reg[63]_1\ => stg3_reg_0, scrambler(11 downto 0) => scrambler(11 downto 0), tempData(5 downto 0) => tempData(5 downto 0), tx_data_i(57 downto 0) => tx_data_i(57 downto 0), \txseq_counter_i_reg[0]\ => scrambler_64b66b_gtx0_i_n_0 ); tx_dst_rdy_n_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF0001" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, I4 => do_cc_r, I5 => Q, O => tx_dst_rdy_n_r0 ); \tx_hdr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => D(0), Q => tx_hdr_r(0), R => '0' ); \tx_hdr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => D(1), Q => tx_hdr_r(1), R => '0' ); \txseq_counter_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0F0F0F0F0F0F0F0E" ) port map ( I0 => \txseq_counter_i_reg_n_0_[6]\, I1 => \txseq_counter_i[0]_i_2_n_0\, I2 => \txseq_counter_i_reg_n_0_[0]\, I3 => \txseq_counter_i_reg_n_0_[4]\, I4 => \txseq_counter_i_reg_n_0_[3]\, I5 => \txseq_counter_i_reg_n_0_[2]\, O => txseq_counter_i(0) ); \txseq_counter_i[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \txseq_counter_i_reg_n_0_[5]\, O => \txseq_counter_i[0]_i_2_n_0\ ); \txseq_counter_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[1]\, O => txseq_counter_i(1) ); \txseq_counter_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \txseq_counter_i_reg_n_0_[0]\, I2 => \txseq_counter_i_reg_n_0_[2]\, O => txseq_counter_i(2) ); \txseq_counter_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \txseq_counter_i_reg_n_0_[2]\, I1 => \txseq_counter_i_reg_n_0_[0]\, I2 => \txseq_counter_i_reg_n_0_[1]\, I3 => \txseq_counter_i_reg_n_0_[3]\, O => txseq_counter_i(3) ); \txseq_counter_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[2]\, I1 => \txseq_counter_i_reg_n_0_[3]\, I2 => \txseq_counter_i_reg_n_0_[0]\, I3 => \txseq_counter_i_reg_n_0_[1]\, I4 => \txseq_counter_i_reg_n_0_[4]\, O => txseq_counter_i(4) ); \txseq_counter_i[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCC3C3CCCC8CCC8" ) port map ( I0 => \txseq_counter_i[5]_i_2_n_0\, I1 => \txseq_counter_i_reg_n_0_[5]\, I2 => \txseq_counter_i_reg_n_0_[1]\, I3 => \txseq_counter_i_reg_n_0_[6]\, I4 => \txseq_counter_i[5]_i_3_n_0\, I5 => \txseq_counter_i_reg_n_0_[0]\, O => txseq_counter_i(5) ); \txseq_counter_i[5]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \txseq_counter_i_reg_n_0_[4]\, I1 => \txseq_counter_i_reg_n_0_[3]\, I2 => \txseq_counter_i_reg_n_0_[2]\, O => \txseq_counter_i[5]_i_2_n_0\ ); \txseq_counter_i[5]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \txseq_counter_i_reg_n_0_[3]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[4]\, O => \txseq_counter_i[5]_i_3_n_0\ ); \txseq_counter_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7FFFFF00800000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[3]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[4]\, I3 => scrambler_64b66b_gtx0_i_n_0, I4 => \txseq_counter_i_reg_n_0_[5]\, I5 => \txseq_counter_i_reg_n_0_[6]\, O => txseq_counter_i(6) ); \txseq_counter_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(0), Q => \txseq_counter_i_reg_n_0_[0]\, R => gtx_reset_comb ); \txseq_counter_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(1), Q => \txseq_counter_i_reg_n_0_[1]\, R => gtx_reset_comb ); \txseq_counter_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(2), Q => \txseq_counter_i_reg_n_0_[2]\, R => gtx_reset_comb ); \txseq_counter_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(3), Q => \txseq_counter_i_reg_n_0_[3]\, R => gtx_reset_comb ); \txseq_counter_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(4), Q => \txseq_counter_i_reg_n_0_[4]\, R => gtx_reset_comb ); \txseq_counter_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(5), Q => \txseq_counter_i_reg_n_0_[5]\, R => gtx_reset_comb ); \txseq_counter_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => stg3_reg_0, CE => '1', D => txseq_counter_i(6), Q => \txseq_counter_i_reg_n_0_[6]\, R => gtx_reset_comb ); \u_cdc__check_polarity\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 port map ( Q(1 downto 0) => rxheader_from_gtx_i(1 downto 0), RX_NEG_OUT_reg => \^rx_neg_out_reg_0\, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => in0, \rxheader_from_gtx_i_reg[0]\ => \u_cdc__check_polarity_n_0\, rxheadervalid_i => rxheadervalid_i ); u_cdc_gt_cplllock_i: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ port map ( cplllock_out(0) => gt_cplllock_j, init_clk => init_clk, \out\ => gt_cplllock_i ); u_cdc_hard_err_init: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_7\ port map ( E(0) => hard_err_cntr_r, Q(2 downto 0) => hard_err_cntr_r_reg(2 downto 0), SR(0) => HPCNT_RESET_IN, \hard_err_cntr_r_reg[0]\ => \hard_err_cntr_r[7]_i_4_n_0\, \hard_err_cntr_r_reg[0]_0\ => \hard_err_cntr_r[7]_i_5_n_0\, hard_err_rst_int => hard_err_rst_int, hard_err_rst_int0 => hard_err_rst_int0, hard_err_rst_int_reg => u_cdc_hard_err_init_n_0, in0 => hard_err_usr, init_clk => init_clk ); u_cdc_rx_elastic_buferr: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ port map ( gtwiz_userclk_rx_usrclk_out => rxusrclk_out, \out\ => rx_elastic_buf_err, rxbufstatus_out(0) => int_gt_rxbufstatus(2), s_level_out_d5_reg_0 => stg3_reg_0 ); u_cdc_rx_fsm_resetdone_i: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_8\ port map ( init_clk => init_clk, \out\ => rx_fsm_resetdone_i, rx_fsm_resetdone_ii => rx_fsm_resetdone_ii ); \u_cdc_rxpolarity_\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ port map ( gtwiz_userclk_rx_usrclk_out => rxusrclk_out, \out\ => sync_rx_polarity_r, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg ); u_cdc_tx_fsm_resetdone_i: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0_9\ port map ( init_clk => init_clk, \out\ => tx_fsm_resetdone_i, tx_fsm_resetdone_ii => tx_fsm_resetdone_ii ); u_rst_done_sync_rx: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ port map ( \out\ => rx_fsm_resetdone_i, stg3_reg_0 => rx_fsm_resetdone_i_i, stg3_reg_1 => stg3_reg_0 ); u_rst_done_sync_rx1: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ port map ( gtwiz_userclk_rx_usrclk_out => rxusrclk_out, \out\ => rx_fsm_resetdone_i ); u_rst_done_sync_tx: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ port map ( FSM_RESETDONE_j_reg => rx_fsm_resetdone_i_i, \out\ => tx_fsm_resetdone_i, stg2_reg_0 => stg3_reg_0, stg3_reg_0 => \^stg3_reg\ ); u_rst_done_sync_tx1: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ port map ( gtwiz_userclk_rx_usrclk_out => rxusrclk_out, \out\ => tx_fsm_resetdone_i ); u_rst_sync_blocksyncall_initclk_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ port map ( E(0) => u_rst_sync_blocksyncall_initclk_sync_n_0, \FSM_onehot_cdr_reset_fsm_r_reg[0]\ => \FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0\, Q(2) => allow_block_sync_propagation, Q(1) => cdr_reset_fsm_lnkreset, Q(0) => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, in0 => blocksync_all_lanes_inrxclk_q, init_clk => init_clk ); u_rst_sync_blocksyncprop_inrxclk_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ port map ( blocksync_out_i => blocksync_out_i, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => allow_block_sync_propagation_reg_n_0, rxlossofsync_out_i => rxlossofsync_out_i ); u_rst_sync_fsm_resetdone: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ port map ( fsm_resetdone_to_rxreset_in => fsm_resetdone_to_rxreset_in, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => FSM_RESETDONE_j, \out\(0) => gtwiz_userclk_rx_active_in, stg5_reg_0 => u_rst_sync_fsm_resetdone_n_0 ); u_rst_sync_fsm_resetdone_initclk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ port map ( \count_for_reset_r_reg[23]\ => rst_in_out_reg, \count_for_reset_r_reg[23]_0\ => cdr_reset_fsm_lnkreset_reg_n_0, \dly_gt_rst_r_reg[18]\ => u_rst_sync_fsm_resetdone_initclk_n_1, fsm_resetdone_initclk => fsm_resetdone_initclk, in0 => FSM_RESETDONE_j, init_clk => init_clk, \out\ => rxfsm_reset_i, reset_initclk => reset_initclk, valid_btf_detect_dlyd1 => valid_btf_detect_dlyd1 ); u_rst_sync_gtx_reset_comb: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ port map ( SR(0) => gtx_reset_comb, in0 => stableclk_gtx_reset_comb, stg3_reg_0 => stg3_reg_0 ); u_rst_sync_reset_initclk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ port map ( SR(0) => SR(0), fsm_resetdone_initclk => fsm_resetdone_initclk, \hard_err_cntr_r_reg[7]\ => cdr_reset_fsm_lnkreset_reg_n_0, \hard_err_cntr_r_reg[7]_0\ => rst_in_out_reg, init_clk => init_clk, \out\ => rxfsm_reset_i, reset_initclk => reset_initclk, stg5_reg_0(0) => HPCNT_RESET_IN ); u_rst_sync_rxreset_in: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ port map ( fsm_resetdone_to_rxreset_in => fsm_resetdone_to_rxreset_in, gtwiz_userclk_rx_usrclk_out => rxusrclk_out, in0 => rxreset_for_lanes_q ); u_rst_sync_txusrclk_gtx_reset_comb: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ port map ( E(0) => sel, in0 => stableclk_gtx_reset_comb, init_clk => init_clk ); \unscrambled_data_i[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(52), I1 => rxdata_from_gtx_i(13), I2 => descrambler_64b66b_gtx0_i_n_36, O => unscrambled_data_i052_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core is port ( link_reset_out : out STD_LOGIC; lane_up_flop_i : out STD_LOGIC; SYSTEM_RESET_reg : out STD_LOGIC; gt0_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drprdy : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 ); tx_out_clk : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; CHANNEL_UP_RX_IF_reg : out STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; m_axi_rx_tvalid : out STD_LOGIC; bufg_gt_clr_out : out STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); power_down : in STD_LOGIC; sysreset_from_support : in STD_LOGIC; TX_PE_DATA_V_reg : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; gt0_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); init_clk : in STD_LOGIC; gt0_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drpen : in STD_LOGIC; gt0_drpwe : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; refclk1_in : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); gt_rxcdrovrden_in : in STD_LOGIC; sync_clk_out : in STD_LOGIC; s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ); mmcm_not_locked_out2 : in STD_LOGIC; lopt : in STD_LOGIC; lopt_1 : in STD_LOGIC; lopt_2 : out STD_LOGIC; lopt_3 : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core is signal \^channel_up_rx_if_reg\ : STD_LOGIC; signal RX_IDLE : STD_LOGIC; signal RX_PE_DATA : STD_LOGIC_VECTOR ( 0 to 63 ); signal \^system_reset_reg\ : STD_LOGIC; signal TXDATAVALID_IN : STD_LOGIC; signal TXHEADER_IN : STD_LOGIC_VECTOR ( 1 downto 0 ); signal TX_PE_DATA : STD_LOGIC_VECTOR ( 0 to 63 ); signal aurora_64b66b_0_wrapper_i_n_100 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_102 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_103 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_104 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_105 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_106 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_107 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_21 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_22 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_23 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_24 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_25 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_26 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_27 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_28 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_29 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_30 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_31 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_32 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_33 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_34 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_35 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_36 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_37 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_38 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_39 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_40 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_41 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_42 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_43 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_44 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_45 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_46 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_47 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_48 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_49 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_50 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_51 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_52 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_53 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_54 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_55 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_56 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_57 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_58 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_59 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_60 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_61 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_62 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_63 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_64 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_65 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_66 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_67 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_68 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_69 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_70 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_71 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_72 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_73 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_74 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_75 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_76 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_77 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_78 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_79 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_80 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_81 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_82 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_83 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_84 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_85 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_86 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_92 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_94 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_96 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_98 : STD_LOGIC; signal aurora_lane_0_i_n_13 : STD_LOGIC; signal \channel_init_sm_i/reset_lanes_c\ : STD_LOGIC; signal channel_up_tx_if : STD_LOGIC; signal check_polarity_i : STD_LOGIC; signal core_reset_logic_i_n_3 : STD_LOGIC; signal do_cc_i : STD_LOGIC; signal enable_err_detect_i : STD_LOGIC; signal fsm_resetdone : STD_LOGIC; signal gen_cc_i : STD_LOGIC; signal gen_ch_bond_i : STD_LOGIC; signal gen_na_idles_i : STD_LOGIC; signal global_logic_i_n_11 : STD_LOGIC; signal global_logic_i_n_12 : STD_LOGIC; signal global_logic_i_n_6 : STD_LOGIC; signal global_logic_i_n_7 : STD_LOGIC; signal global_logic_i_n_9 : STD_LOGIC; signal hard_err_i : STD_LOGIC; signal illegal_btf_i : STD_LOGIC; signal \lane_init_sm_i/ready_r_reg0\ : STD_LOGIC; signal \lane_init_sm_i/reset_count_r0\ : STD_LOGIC; signal \^lane_up_flop_i\ : STD_LOGIC; signal \^link_reset_out\ : STD_LOGIC; signal remote_ready_i : STD_LOGIC; signal reset_lanes_i : STD_LOGIC; signal rx_lossofsync_i : STD_LOGIC; signal rx_neg_i : STD_LOGIC; signal rx_pe_data_v_i : STD_LOGIC; signal rx_polarity_i : STD_LOGIC; signal \rx_stream_datapath_i/RX_D0\ : STD_LOGIC; signal rxdatavalid_i : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_153_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_157_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_161_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_165_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_169_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_173_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData0\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData012_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData016_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData020_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData04_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData08_out\ : STD_LOGIC; signal \sym_gen_i/rst_pma_init_usrclk\ : STD_LOGIC; signal tx_data_i : STD_LOGIC_VECTOR ( 0 to 57 ); signal tx_pe_data_v_i : STD_LOGIC; signal tx_reset_i : STD_LOGIC; signal \tx_stream_control_sm_i/R0\ : STD_LOGIC; signal \tx_stream_control_sm_i/do_cc_r\ : STD_LOGIC; signal \tx_stream_control_sm_i/do_cc_r_reg0\ : STD_LOGIC; signal \tx_stream_control_sm_i/extend_cc_r\ : STD_LOGIC; signal \tx_stream_control_sm_i/tx_dst_rdy_n_r0\ : STD_LOGIC; signal tx_stream_i_n_4 : STD_LOGIC; signal tx_stream_i_n_5 : STD_LOGIC; signal tx_stream_i_n_6 : STD_LOGIC; signal txdatavalid_symgen_i : STD_LOGIC; begin CHANNEL_UP_RX_IF_reg <= \^channel_up_rx_if_reg\; SYSTEM_RESET_reg <= \^system_reset_reg\; lane_up_flop_i <= \^lane_up_flop_i\; link_reset_out <= \^link_reset_out\; aurora_64b66b_0_wrapper_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER port map ( D(1 downto 0) => TXHEADER_IN(1 downto 0), ILLEGAL_BTF_reg => aurora_64b66b_0_wrapper_i_n_96, Q => do_cc_i, RX_NEG_OUT_reg_0 => rx_neg_i, SR(0) => \^system_reset_reg\, TXDATAVALID_IN => TXDATAVALID_IN, bufg_gt_clr_out => bufg_gt_clr_out, channel_up_tx_if => channel_up_tx_if, do_cc_r => \tx_stream_control_sm_i/do_cc_r\, dout(65) => aurora_64b66b_0_wrapper_i_n_21, dout(64) => aurora_64b66b_0_wrapper_i_n_22, dout(63) => aurora_64b66b_0_wrapper_i_n_23, dout(62) => aurora_64b66b_0_wrapper_i_n_24, dout(61) => aurora_64b66b_0_wrapper_i_n_25, dout(60) => aurora_64b66b_0_wrapper_i_n_26, dout(59) => aurora_64b66b_0_wrapper_i_n_27, dout(58) => aurora_64b66b_0_wrapper_i_n_28, dout(57) => aurora_64b66b_0_wrapper_i_n_29, dout(56) => aurora_64b66b_0_wrapper_i_n_30, dout(55) => aurora_64b66b_0_wrapper_i_n_31, dout(54) => aurora_64b66b_0_wrapper_i_n_32, dout(53) => aurora_64b66b_0_wrapper_i_n_33, dout(52) => aurora_64b66b_0_wrapper_i_n_34, dout(51) => aurora_64b66b_0_wrapper_i_n_35, dout(50) => aurora_64b66b_0_wrapper_i_n_36, dout(49) => aurora_64b66b_0_wrapper_i_n_37, dout(48) => aurora_64b66b_0_wrapper_i_n_38, dout(47) => aurora_64b66b_0_wrapper_i_n_39, dout(46) => aurora_64b66b_0_wrapper_i_n_40, dout(45) => aurora_64b66b_0_wrapper_i_n_41, dout(44) => aurora_64b66b_0_wrapper_i_n_42, dout(43) => aurora_64b66b_0_wrapper_i_n_43, dout(42) => aurora_64b66b_0_wrapper_i_n_44, dout(41) => aurora_64b66b_0_wrapper_i_n_45, dout(40) => aurora_64b66b_0_wrapper_i_n_46, dout(39) => aurora_64b66b_0_wrapper_i_n_47, dout(38) => aurora_64b66b_0_wrapper_i_n_48, dout(37) => aurora_64b66b_0_wrapper_i_n_49, dout(36) => aurora_64b66b_0_wrapper_i_n_50, dout(35) => aurora_64b66b_0_wrapper_i_n_51, dout(34) => aurora_64b66b_0_wrapper_i_n_52, dout(33) => aurora_64b66b_0_wrapper_i_n_53, dout(32) => aurora_64b66b_0_wrapper_i_n_54, dout(31) => aurora_64b66b_0_wrapper_i_n_55, dout(30) => aurora_64b66b_0_wrapper_i_n_56, dout(29) => aurora_64b66b_0_wrapper_i_n_57, dout(28) => aurora_64b66b_0_wrapper_i_n_58, dout(27) => aurora_64b66b_0_wrapper_i_n_59, dout(26) => aurora_64b66b_0_wrapper_i_n_60, dout(25) => aurora_64b66b_0_wrapper_i_n_61, dout(24) => aurora_64b66b_0_wrapper_i_n_62, dout(23) => aurora_64b66b_0_wrapper_i_n_63, dout(22) => aurora_64b66b_0_wrapper_i_n_64, dout(21) => aurora_64b66b_0_wrapper_i_n_65, dout(20) => aurora_64b66b_0_wrapper_i_n_66, dout(19) => aurora_64b66b_0_wrapper_i_n_67, dout(18) => aurora_64b66b_0_wrapper_i_n_68, dout(17) => aurora_64b66b_0_wrapper_i_n_69, dout(16) => aurora_64b66b_0_wrapper_i_n_70, dout(15) => aurora_64b66b_0_wrapper_i_n_71, dout(14) => aurora_64b66b_0_wrapper_i_n_72, dout(13) => aurora_64b66b_0_wrapper_i_n_73, dout(12) => aurora_64b66b_0_wrapper_i_n_74, dout(11) => aurora_64b66b_0_wrapper_i_n_75, dout(10) => aurora_64b66b_0_wrapper_i_n_76, dout(9) => aurora_64b66b_0_wrapper_i_n_77, dout(8) => aurora_64b66b_0_wrapper_i_n_78, dout(7) => aurora_64b66b_0_wrapper_i_n_79, dout(6) => aurora_64b66b_0_wrapper_i_n_80, dout(5) => aurora_64b66b_0_wrapper_i_n_81, dout(4) => aurora_64b66b_0_wrapper_i_n_82, dout(3) => aurora_64b66b_0_wrapper_i_n_83, dout(2) => aurora_64b66b_0_wrapper_i_n_84, dout(1) => aurora_64b66b_0_wrapper_i_n_85, dout(0) => aurora_64b66b_0_wrapper_i_n_86, enable_err_detect_i => enable_err_detect_i, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\, gt0_drpaddr(8 downto 0) => gt0_drpaddr(8 downto 0), gt0_drpdi(15 downto 0) => gt0_drpdi(15 downto 0), gt0_drpdo(15 downto 0) => gt0_drpdo(15 downto 0), gt0_drpen => gt0_drpen, gt0_drprdy => gt0_drprdy, gt0_drpwe => gt0_drpwe, gt_pll_lock => gt_pll_lock, gt_powergood(0) => gt_powergood(0), gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err_usr_reg_0 => \^channel_up_rx_if_reg\, hold_reg_reg => aurora_64b66b_0_wrapper_i_n_100, illegal_btf_i => illegal_btf_i, in0 => check_polarity_i, init_clk => init_clk, link_reset_out => \^link_reset_out\, loopback(2 downto 0) => loopback(2 downto 0), lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, lopt_3 => lopt_3, mmcm_not_locked_out2 => mmcm_not_locked_out2, refclk1_in => refclk1_in, rst_in_out_reg => stg1_aurora_64b66b_0_cdc_to_reg, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_lossofsync_i => rx_lossofsync_i, rxdatavalid_i => rxdatavalid_i, rxn => rxn, rxp => rxp, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => rx_polarity_i, scrambler(11) => aurora_64b66b_0_wrapper_i_n_102, scrambler(10) => aurora_64b66b_0_wrapper_i_n_103, scrambler(9) => aurora_64b66b_0_wrapper_i_n_104, scrambler(8) => aurora_64b66b_0_wrapper_i_n_105, scrambler(7) => aurora_64b66b_0_wrapper_i_n_106, scrambler(6) => aurora_64b66b_0_wrapper_i_n_107, scrambler(5) => \scrambler_64b66b_gtx0_i/p_173_in\, scrambler(4) => \scrambler_64b66b_gtx0_i/p_169_in\, scrambler(3) => \scrambler_64b66b_gtx0_i/p_165_in\, scrambler(2) => \scrambler_64b66b_gtx0_i/p_161_in\, scrambler(1) => \scrambler_64b66b_gtx0_i/p_157_in\, scrambler(0) => \scrambler_64b66b_gtx0_i/p_153_in\, stg3_reg => fsm_resetdone, stg3_reg_0 => TX_PE_DATA_V_reg, sync_clk_out => sync_clk_out, tempData(5) => \scrambler_64b66b_gtx0_i/tempData020_out\, tempData(4) => \scrambler_64b66b_gtx0_i/tempData016_out\, tempData(3) => \scrambler_64b66b_gtx0_i/tempData012_out\, tempData(2) => \scrambler_64b66b_gtx0_i/tempData08_out\, tempData(1) => \scrambler_64b66b_gtx0_i/tempData04_out\, tempData(0) => \scrambler_64b66b_gtx0_i/tempData0\, tx_data_i(57) => tx_data_i(0), tx_data_i(56) => tx_data_i(1), tx_data_i(55) => tx_data_i(2), tx_data_i(54) => tx_data_i(3), tx_data_i(53) => tx_data_i(4), tx_data_i(52) => tx_data_i(5), tx_data_i(51) => tx_data_i(6), tx_data_i(50) => tx_data_i(7), tx_data_i(49) => tx_data_i(8), tx_data_i(48) => tx_data_i(9), tx_data_i(47) => tx_data_i(10), tx_data_i(46) => tx_data_i(11), tx_data_i(45) => tx_data_i(12), tx_data_i(44) => tx_data_i(13), tx_data_i(43) => tx_data_i(14), tx_data_i(42) => tx_data_i(15), tx_data_i(41) => tx_data_i(16), tx_data_i(40) => tx_data_i(17), tx_data_i(39) => tx_data_i(18), tx_data_i(38) => tx_data_i(19), tx_data_i(37) => tx_data_i(20), tx_data_i(36) => tx_data_i(21), tx_data_i(35) => tx_data_i(22), tx_data_i(34) => tx_data_i(23), tx_data_i(33) => tx_data_i(24), tx_data_i(32) => tx_data_i(25), tx_data_i(31) => tx_data_i(26), tx_data_i(30) => tx_data_i(27), tx_data_i(29) => tx_data_i(28), tx_data_i(28) => tx_data_i(29), tx_data_i(27) => tx_data_i(30), tx_data_i(26) => tx_data_i(31), tx_data_i(25) => tx_data_i(32), tx_data_i(24) => tx_data_i(33), tx_data_i(23) => tx_data_i(34), tx_data_i(22) => tx_data_i(35), tx_data_i(21) => tx_data_i(36), tx_data_i(20) => tx_data_i(37), tx_data_i(19) => tx_data_i(38), tx_data_i(18) => tx_data_i(39), tx_data_i(17) => tx_data_i(40), tx_data_i(16) => tx_data_i(41), tx_data_i(15) => tx_data_i(42), tx_data_i(14) => tx_data_i(43), tx_data_i(13) => tx_data_i(44), tx_data_i(12) => tx_data_i(45), tx_data_i(11) => tx_data_i(46), tx_data_i(10) => tx_data_i(47), tx_data_i(9) => tx_data_i(48), tx_data_i(8) => tx_data_i(49), tx_data_i(7) => tx_data_i(50), tx_data_i(6) => tx_data_i(51), tx_data_i(5) => tx_data_i(52), tx_data_i(4) => tx_data_i(53), tx_data_i(3) => tx_data_i(54), tx_data_i(2) => tx_data_i(55), tx_data_i(1) => tx_data_i(56), tx_data_i(0) => tx_data_i(57), tx_dst_rdy_n_r0 => \tx_stream_control_sm_i/tx_dst_rdy_n_r0\, tx_out_clk => tx_out_clk, tx_reset_i => tx_reset_i, txdatavalid_symgen_i => txdatavalid_symgen_i, txn => txn, txp => txp, \txseq_counter_i_reg[0]_0\ => aurora_64b66b_0_wrapper_i_n_92, \txseq_counter_i_reg[1]_0\ => aurora_64b66b_0_wrapper_i_n_94, wr_err_rd_clk_sync_reg => aurora_64b66b_0_wrapper_i_n_98 ); aurora_lane_0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE port map ( D(1 downto 0) => TXHEADER_IN(1 downto 0), HARD_ERR_reg => aurora_64b66b_0_wrapper_i_n_98, Q(59) => TX_PE_DATA(0), Q(58) => TX_PE_DATA(1), Q(57) => TX_PE_DATA(2), Q(56) => TX_PE_DATA(3), Q(55) => TX_PE_DATA(4), Q(54) => TX_PE_DATA(5), Q(53) => TX_PE_DATA(6), Q(52) => TX_PE_DATA(7), Q(51) => TX_PE_DATA(8), Q(50) => TX_PE_DATA(9), Q(49) => TX_PE_DATA(10), Q(48) => TX_PE_DATA(11), Q(47) => TX_PE_DATA(12), Q(46) => TX_PE_DATA(13), Q(45) => TX_PE_DATA(14), Q(44) => TX_PE_DATA(15), Q(43) => TX_PE_DATA(16), Q(42) => TX_PE_DATA(17), Q(41) => TX_PE_DATA(18), Q(40) => TX_PE_DATA(19), Q(39) => TX_PE_DATA(20), Q(38) => TX_PE_DATA(21), Q(37) => TX_PE_DATA(22), Q(36) => TX_PE_DATA(23), Q(35) => TX_PE_DATA(24), Q(34) => TX_PE_DATA(25), Q(33) => TX_PE_DATA(26), Q(32) => TX_PE_DATA(27), Q(31) => TX_PE_DATA(28), Q(30) => TX_PE_DATA(29), Q(29) => TX_PE_DATA(30), Q(28) => TX_PE_DATA(31), Q(27) => TX_PE_DATA(32), Q(26) => TX_PE_DATA(33), Q(25) => TX_PE_DATA(34), Q(24) => TX_PE_DATA(35), Q(23) => TX_PE_DATA(36), Q(22) => TX_PE_DATA(37), Q(21) => TX_PE_DATA(38), Q(20) => TX_PE_DATA(39), Q(19) => TX_PE_DATA(40), Q(18) => TX_PE_DATA(41), Q(17) => TX_PE_DATA(42), Q(16) => TX_PE_DATA(43), Q(15) => TX_PE_DATA(44), Q(14) => TX_PE_DATA(45), Q(13) => TX_PE_DATA(46), Q(12) => TX_PE_DATA(47), Q(11) => TX_PE_DATA(52), Q(10) => TX_PE_DATA(53), Q(9) => TX_PE_DATA(54), Q(8) => TX_PE_DATA(55), Q(7) => TX_PE_DATA(56), Q(6) => TX_PE_DATA(57), Q(5) => TX_PE_DATA(58), Q(4) => TX_PE_DATA(59), Q(3) => TX_PE_DATA(60), Q(2) => TX_PE_DATA(61), Q(1) => TX_PE_DATA(62), Q(0) => TX_PE_DATA(63), \RX_DATA_REG_reg[0]\ => aurora_64b66b_0_wrapper_i_n_100, RX_IDLE => RX_IDLE, \RX_PE_DATA_reg[0]\(63) => RX_PE_DATA(0), \RX_PE_DATA_reg[0]\(62) => RX_PE_DATA(1), \RX_PE_DATA_reg[0]\(61) => RX_PE_DATA(2), \RX_PE_DATA_reg[0]\(60) => RX_PE_DATA(3), \RX_PE_DATA_reg[0]\(59) => RX_PE_DATA(4), \RX_PE_DATA_reg[0]\(58) => RX_PE_DATA(5), \RX_PE_DATA_reg[0]\(57) => RX_PE_DATA(6), \RX_PE_DATA_reg[0]\(56) => RX_PE_DATA(7), \RX_PE_DATA_reg[0]\(55) => RX_PE_DATA(8), \RX_PE_DATA_reg[0]\(54) => RX_PE_DATA(9), \RX_PE_DATA_reg[0]\(53) => RX_PE_DATA(10), \RX_PE_DATA_reg[0]\(52) => RX_PE_DATA(11), \RX_PE_DATA_reg[0]\(51) => RX_PE_DATA(12), \RX_PE_DATA_reg[0]\(50) => RX_PE_DATA(13), \RX_PE_DATA_reg[0]\(49) => RX_PE_DATA(14), \RX_PE_DATA_reg[0]\(48) => RX_PE_DATA(15), \RX_PE_DATA_reg[0]\(47) => RX_PE_DATA(16), \RX_PE_DATA_reg[0]\(46) => RX_PE_DATA(17), \RX_PE_DATA_reg[0]\(45) => RX_PE_DATA(18), \RX_PE_DATA_reg[0]\(44) => RX_PE_DATA(19), \RX_PE_DATA_reg[0]\(43) => RX_PE_DATA(20), \RX_PE_DATA_reg[0]\(42) => RX_PE_DATA(21), \RX_PE_DATA_reg[0]\(41) => RX_PE_DATA(22), \RX_PE_DATA_reg[0]\(40) => RX_PE_DATA(23), \RX_PE_DATA_reg[0]\(39) => RX_PE_DATA(24), \RX_PE_DATA_reg[0]\(38) => RX_PE_DATA(25), \RX_PE_DATA_reg[0]\(37) => RX_PE_DATA(26), \RX_PE_DATA_reg[0]\(36) => RX_PE_DATA(27), \RX_PE_DATA_reg[0]\(35) => RX_PE_DATA(28), \RX_PE_DATA_reg[0]\(34) => RX_PE_DATA(29), \RX_PE_DATA_reg[0]\(33) => RX_PE_DATA(30), \RX_PE_DATA_reg[0]\(32) => RX_PE_DATA(31), \RX_PE_DATA_reg[0]\(31) => RX_PE_DATA(32), \RX_PE_DATA_reg[0]\(30) => RX_PE_DATA(33), \RX_PE_DATA_reg[0]\(29) => RX_PE_DATA(34), \RX_PE_DATA_reg[0]\(28) => RX_PE_DATA(35), \RX_PE_DATA_reg[0]\(27) => RX_PE_DATA(36), \RX_PE_DATA_reg[0]\(26) => RX_PE_DATA(37), \RX_PE_DATA_reg[0]\(25) => RX_PE_DATA(38), \RX_PE_DATA_reg[0]\(24) => RX_PE_DATA(39), \RX_PE_DATA_reg[0]\(23) => RX_PE_DATA(40), \RX_PE_DATA_reg[0]\(22) => RX_PE_DATA(41), \RX_PE_DATA_reg[0]\(21) => RX_PE_DATA(42), \RX_PE_DATA_reg[0]\(20) => RX_PE_DATA(43), \RX_PE_DATA_reg[0]\(19) => RX_PE_DATA(44), \RX_PE_DATA_reg[0]\(18) => RX_PE_DATA(45), \RX_PE_DATA_reg[0]\(17) => RX_PE_DATA(46), \RX_PE_DATA_reg[0]\(16) => RX_PE_DATA(47), \RX_PE_DATA_reg[0]\(15) => RX_PE_DATA(48), \RX_PE_DATA_reg[0]\(14) => RX_PE_DATA(49), \RX_PE_DATA_reg[0]\(13) => RX_PE_DATA(50), \RX_PE_DATA_reg[0]\(12) => RX_PE_DATA(51), \RX_PE_DATA_reg[0]\(11) => RX_PE_DATA(52), \RX_PE_DATA_reg[0]\(10) => RX_PE_DATA(53), \RX_PE_DATA_reg[0]\(9) => RX_PE_DATA(54), \RX_PE_DATA_reg[0]\(8) => RX_PE_DATA(55), \RX_PE_DATA_reg[0]\(7) => RX_PE_DATA(56), \RX_PE_DATA_reg[0]\(6) => RX_PE_DATA(57), \RX_PE_DATA_reg[0]\(5) => RX_PE_DATA(58), \RX_PE_DATA_reg[0]\(4) => RX_PE_DATA(59), \RX_PE_DATA_reg[0]\(3) => RX_PE_DATA(60), \RX_PE_DATA_reg[0]\(2) => RX_PE_DATA(61), \RX_PE_DATA_reg[0]\(1) => RX_PE_DATA(62), \RX_PE_DATA_reg[0]\(0) => RX_PE_DATA(63), SOFT_ERR_reg => aurora_lane_0_i_n_13, SOFT_ERR_reg_0 => aurora_64b66b_0_wrapper_i_n_96, SR(0) => \^system_reset_reg\, \TX_DATA_reg[55]\(3) => global_logic_i_n_6, \TX_DATA_reg[55]\(2) => global_logic_i_n_7, \TX_DATA_reg[55]\(1) => tx_stream_i_n_4, \TX_DATA_reg[55]\(0) => tx_stream_i_n_5, \TX_DATA_reg[59]\ => aurora_64b66b_0_wrapper_i_n_94, \TX_DATA_reg[63]\(57) => tx_data_i(0), \TX_DATA_reg[63]\(56) => tx_data_i(1), \TX_DATA_reg[63]\(55) => tx_data_i(2), \TX_DATA_reg[63]\(54) => tx_data_i(3), \TX_DATA_reg[63]\(53) => tx_data_i(4), \TX_DATA_reg[63]\(52) => tx_data_i(5), \TX_DATA_reg[63]\(51) => tx_data_i(6), \TX_DATA_reg[63]\(50) => tx_data_i(7), \TX_DATA_reg[63]\(49) => tx_data_i(8), \TX_DATA_reg[63]\(48) => tx_data_i(9), \TX_DATA_reg[63]\(47) => tx_data_i(10), \TX_DATA_reg[63]\(46) => tx_data_i(11), \TX_DATA_reg[63]\(45) => tx_data_i(12), \TX_DATA_reg[63]\(44) => tx_data_i(13), \TX_DATA_reg[63]\(43) => tx_data_i(14), \TX_DATA_reg[63]\(42) => tx_data_i(15), \TX_DATA_reg[63]\(41) => tx_data_i(16), \TX_DATA_reg[63]\(40) => tx_data_i(17), \TX_DATA_reg[63]\(39) => tx_data_i(18), \TX_DATA_reg[63]\(38) => tx_data_i(19), \TX_DATA_reg[63]\(37) => tx_data_i(20), \TX_DATA_reg[63]\(36) => tx_data_i(21), \TX_DATA_reg[63]\(35) => tx_data_i(22), \TX_DATA_reg[63]\(34) => tx_data_i(23), \TX_DATA_reg[63]\(33) => tx_data_i(24), \TX_DATA_reg[63]\(32) => tx_data_i(25), \TX_DATA_reg[63]\(31) => tx_data_i(26), \TX_DATA_reg[63]\(30) => tx_data_i(27), \TX_DATA_reg[63]\(29) => tx_data_i(28), \TX_DATA_reg[63]\(28) => tx_data_i(29), \TX_DATA_reg[63]\(27) => tx_data_i(30), \TX_DATA_reg[63]\(26) => tx_data_i(31), \TX_DATA_reg[63]\(25) => tx_data_i(32), \TX_DATA_reg[63]\(24) => tx_data_i(33), \TX_DATA_reg[63]\(23) => tx_data_i(34), \TX_DATA_reg[63]\(22) => tx_data_i(35), \TX_DATA_reg[63]\(21) => tx_data_i(36), \TX_DATA_reg[63]\(20) => tx_data_i(37), \TX_DATA_reg[63]\(19) => tx_data_i(38), \TX_DATA_reg[63]\(18) => tx_data_i(39), \TX_DATA_reg[63]\(17) => tx_data_i(40), \TX_DATA_reg[63]\(16) => tx_data_i(41), \TX_DATA_reg[63]\(15) => tx_data_i(42), \TX_DATA_reg[63]\(14) => tx_data_i(43), \TX_DATA_reg[63]\(13) => tx_data_i(44), \TX_DATA_reg[63]\(12) => tx_data_i(45), \TX_DATA_reg[63]\(11) => tx_data_i(46), \TX_DATA_reg[63]\(10) => tx_data_i(47), \TX_DATA_reg[63]\(9) => tx_data_i(48), \TX_DATA_reg[63]\(8) => tx_data_i(49), \TX_DATA_reg[63]\(7) => tx_data_i(50), \TX_DATA_reg[63]\(6) => tx_data_i(51), \TX_DATA_reg[63]\(5) => tx_data_i(52), \TX_DATA_reg[63]\(4) => tx_data_i(53), \TX_DATA_reg[63]\(3) => tx_data_i(54), \TX_DATA_reg[63]\(2) => tx_data_i(55), \TX_DATA_reg[63]\(1) => tx_data_i(56), \TX_DATA_reg[63]\(0) => tx_data_i(57), \TX_DATA_reg[63]_0\ => global_logic_i_n_11, TX_HEADER_1_reg => tx_stream_i_n_6, channel_up_tx_if => channel_up_tx_if, dout(65) => aurora_64b66b_0_wrapper_i_n_21, dout(64) => aurora_64b66b_0_wrapper_i_n_22, dout(63) => aurora_64b66b_0_wrapper_i_n_23, dout(62) => aurora_64b66b_0_wrapper_i_n_24, dout(61) => aurora_64b66b_0_wrapper_i_n_25, dout(60) => aurora_64b66b_0_wrapper_i_n_26, dout(59) => aurora_64b66b_0_wrapper_i_n_27, dout(58) => aurora_64b66b_0_wrapper_i_n_28, dout(57) => aurora_64b66b_0_wrapper_i_n_29, dout(56) => aurora_64b66b_0_wrapper_i_n_30, dout(55) => aurora_64b66b_0_wrapper_i_n_31, dout(54) => aurora_64b66b_0_wrapper_i_n_32, dout(53) => aurora_64b66b_0_wrapper_i_n_33, dout(52) => aurora_64b66b_0_wrapper_i_n_34, dout(51) => aurora_64b66b_0_wrapper_i_n_35, dout(50) => aurora_64b66b_0_wrapper_i_n_36, dout(49) => aurora_64b66b_0_wrapper_i_n_37, dout(48) => aurora_64b66b_0_wrapper_i_n_38, dout(47) => aurora_64b66b_0_wrapper_i_n_39, dout(46) => aurora_64b66b_0_wrapper_i_n_40, dout(45) => aurora_64b66b_0_wrapper_i_n_41, dout(44) => aurora_64b66b_0_wrapper_i_n_42, dout(43) => aurora_64b66b_0_wrapper_i_n_43, dout(42) => aurora_64b66b_0_wrapper_i_n_44, dout(41) => aurora_64b66b_0_wrapper_i_n_45, dout(40) => aurora_64b66b_0_wrapper_i_n_46, dout(39) => aurora_64b66b_0_wrapper_i_n_47, dout(38) => aurora_64b66b_0_wrapper_i_n_48, dout(37) => aurora_64b66b_0_wrapper_i_n_49, dout(36) => aurora_64b66b_0_wrapper_i_n_50, dout(35) => aurora_64b66b_0_wrapper_i_n_51, dout(34) => aurora_64b66b_0_wrapper_i_n_52, dout(33) => aurora_64b66b_0_wrapper_i_n_53, dout(32) => aurora_64b66b_0_wrapper_i_n_54, dout(31) => aurora_64b66b_0_wrapper_i_n_55, dout(30) => aurora_64b66b_0_wrapper_i_n_56, dout(29) => aurora_64b66b_0_wrapper_i_n_57, dout(28) => aurora_64b66b_0_wrapper_i_n_58, dout(27) => aurora_64b66b_0_wrapper_i_n_59, dout(26) => aurora_64b66b_0_wrapper_i_n_60, dout(25) => aurora_64b66b_0_wrapper_i_n_61, dout(24) => aurora_64b66b_0_wrapper_i_n_62, dout(23) => aurora_64b66b_0_wrapper_i_n_63, dout(22) => aurora_64b66b_0_wrapper_i_n_64, dout(21) => aurora_64b66b_0_wrapper_i_n_65, dout(20) => aurora_64b66b_0_wrapper_i_n_66, dout(19) => aurora_64b66b_0_wrapper_i_n_67, dout(18) => aurora_64b66b_0_wrapper_i_n_68, dout(17) => aurora_64b66b_0_wrapper_i_n_69, dout(16) => aurora_64b66b_0_wrapper_i_n_70, dout(15) => aurora_64b66b_0_wrapper_i_n_71, dout(14) => aurora_64b66b_0_wrapper_i_n_72, dout(13) => aurora_64b66b_0_wrapper_i_n_73, dout(12) => aurora_64b66b_0_wrapper_i_n_74, dout(11) => aurora_64b66b_0_wrapper_i_n_75, dout(10) => aurora_64b66b_0_wrapper_i_n_76, dout(9) => aurora_64b66b_0_wrapper_i_n_77, dout(8) => aurora_64b66b_0_wrapper_i_n_78, dout(7) => aurora_64b66b_0_wrapper_i_n_79, dout(6) => aurora_64b66b_0_wrapper_i_n_80, dout(5) => aurora_64b66b_0_wrapper_i_n_81, dout(4) => aurora_64b66b_0_wrapper_i_n_82, dout(3) => aurora_64b66b_0_wrapper_i_n_83, dout(2) => aurora_64b66b_0_wrapper_i_n_84, dout(1) => aurora_64b66b_0_wrapper_i_n_85, dout(0) => aurora_64b66b_0_wrapper_i_n_86, enable_err_detect_i => enable_err_detect_i, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, hard_err_i => hard_err_i, illegal_btf_i => illegal_btf_i, in0 => check_polarity_i, lane_up_flop_i => \^lane_up_flop_i\, ready_r_reg0 => \lane_init_sm_i/ready_r_reg0\, remote_ready_i => remote_ready_i, reset_count_r0 => \lane_init_sm_i/reset_count_r0\, reset_lanes_c => \channel_init_sm_i/reset_lanes_c\, reset_lanes_i => reset_lanes_i, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_lossofsync_i => rx_lossofsync_i, rx_pe_data_v_i => rx_pe_data_v_i, rx_polarity_r_reg => rx_polarity_i, rxdatavalid_i => rxdatavalid_i, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => rx_neg_i, scrambler(11) => aurora_64b66b_0_wrapper_i_n_102, scrambler(10) => aurora_64b66b_0_wrapper_i_n_103, scrambler(9) => aurora_64b66b_0_wrapper_i_n_104, scrambler(8) => aurora_64b66b_0_wrapper_i_n_105, scrambler(7) => aurora_64b66b_0_wrapper_i_n_106, scrambler(6) => aurora_64b66b_0_wrapper_i_n_107, scrambler(5) => \scrambler_64b66b_gtx0_i/p_173_in\, scrambler(4) => \scrambler_64b66b_gtx0_i/p_169_in\, scrambler(3) => \scrambler_64b66b_gtx0_i/p_165_in\, scrambler(2) => \scrambler_64b66b_gtx0_i/p_161_in\, scrambler(1) => \scrambler_64b66b_gtx0_i/p_157_in\, scrambler(0) => \scrambler_64b66b_gtx0_i/p_153_in\, stg1_aurora_64b66b_0_cdc_to_reg => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg => TX_PE_DATA_V_reg, tempData(5) => \scrambler_64b66b_gtx0_i/tempData020_out\, tempData(4) => \scrambler_64b66b_gtx0_i/tempData016_out\, tempData(3) => \scrambler_64b66b_gtx0_i/tempData012_out\, tempData(2) => \scrambler_64b66b_gtx0_i/tempData08_out\, tempData(1) => \scrambler_64b66b_gtx0_i/tempData04_out\, tempData(0) => \scrambler_64b66b_gtx0_i/tempData0\, tx_pe_data_v_i => tx_pe_data_v_i, tx_reset_i => tx_reset_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); core_reset_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC port map ( SR(0) => \^system_reset_reg\, SYSTEM_RESET_reg_0 => core_reset_logic_i_n_3, hard_err_i => hard_err_i, link_reset_out => \^link_reset_out\, power_down => power_down, ready_r_reg0 => \lane_init_sm_i/ready_r_reg0\, reset_count_r0 => \lane_init_sm_i/reset_count_r0\, stg1_aurora_64b66b_0_cdc_to_reg => fsm_resetdone, stg4_reg => TX_PE_DATA_V_reg, sysreset_from_support => sysreset_from_support, tx_reset_i => tx_reset_i, wait_for_lane_up_r_reg => \^lane_up_flop_i\ ); global_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC port map ( CHANNEL_UP_RX_IF_reg => \^channel_up_rx_if_reg\, CHANNEL_UP_RX_IF_reg_0 => global_logic_i_n_9, CHANNEL_UP_RX_IF_reg_1 => global_logic_i_n_12, CHANNEL_UP_RX_IF_reg_2 => TX_PE_DATA_V_reg, CHANNEL_UP_RX_IF_reg_3(0) => \^system_reset_reg\, E(0) => \rx_stream_datapath_i/RX_D0\, Q(1) => TX_PE_DATA(48), Q(0) => TX_PE_DATA(49), R0 => \tx_stream_control_sm_i/R0\, RX_IDLE => RX_IDLE, SR(0) => reset_lanes_i, TXDATAVALID_IN => TXDATAVALID_IN, \TX_DATA_reg[63]\ => aurora_64b66b_0_wrapper_i_n_94, channel_up_tx_if => channel_up_tx_if, gen_cc_flop_0_i(1) => global_logic_i_n_6, gen_cc_flop_0_i(0) => global_logic_i_n_7, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_ch_bond_int_reg => global_logic_i_n_11, gen_na_idles_i => gen_na_idles_i, hard_err => hard_err, hard_err_i => hard_err_i, remote_ready_i => remote_ready_i, reset_lanes_c => \channel_init_sm_i/reset_lanes_c\, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_pe_data_v_i => rx_pe_data_v_i, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg => core_reset_logic_i_n_3 ); rx_stream_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM port map ( D(63) => RX_PE_DATA(0), D(62) => RX_PE_DATA(1), D(61) => RX_PE_DATA(2), D(60) => RX_PE_DATA(3), D(59) => RX_PE_DATA(4), D(58) => RX_PE_DATA(5), D(57) => RX_PE_DATA(6), D(56) => RX_PE_DATA(7), D(55) => RX_PE_DATA(8), D(54) => RX_PE_DATA(9), D(53) => RX_PE_DATA(10), D(52) => RX_PE_DATA(11), D(51) => RX_PE_DATA(12), D(50) => RX_PE_DATA(13), D(49) => RX_PE_DATA(14), D(48) => RX_PE_DATA(15), D(47) => RX_PE_DATA(16), D(46) => RX_PE_DATA(17), D(45) => RX_PE_DATA(18), D(44) => RX_PE_DATA(19), D(43) => RX_PE_DATA(20), D(42) => RX_PE_DATA(21), D(41) => RX_PE_DATA(22), D(40) => RX_PE_DATA(23), D(39) => RX_PE_DATA(24), D(38) => RX_PE_DATA(25), D(37) => RX_PE_DATA(26), D(36) => RX_PE_DATA(27), D(35) => RX_PE_DATA(28), D(34) => RX_PE_DATA(29), D(33) => RX_PE_DATA(30), D(32) => RX_PE_DATA(31), D(31) => RX_PE_DATA(32), D(30) => RX_PE_DATA(33), D(29) => RX_PE_DATA(34), D(28) => RX_PE_DATA(35), D(27) => RX_PE_DATA(36), D(26) => RX_PE_DATA(37), D(25) => RX_PE_DATA(38), D(24) => RX_PE_DATA(39), D(23) => RX_PE_DATA(40), D(22) => RX_PE_DATA(41), D(21) => RX_PE_DATA(42), D(20) => RX_PE_DATA(43), D(19) => RX_PE_DATA(44), D(18) => RX_PE_DATA(45), D(17) => RX_PE_DATA(46), D(16) => RX_PE_DATA(47), D(15) => RX_PE_DATA(48), D(14) => RX_PE_DATA(49), D(13) => RX_PE_DATA(50), D(12) => RX_PE_DATA(51), D(11) => RX_PE_DATA(52), D(10) => RX_PE_DATA(53), D(9) => RX_PE_DATA(54), D(8) => RX_PE_DATA(55), D(7) => RX_PE_DATA(56), D(6) => RX_PE_DATA(57), D(5) => RX_PE_DATA(58), D(4) => RX_PE_DATA(59), D(3) => RX_PE_DATA(60), D(2) => RX_PE_DATA(61), D(1) => RX_PE_DATA(62), D(0) => RX_PE_DATA(63), E(0) => \rx_stream_datapath_i/RX_D0\, RX_SRC_RDY_N_reg_inv => global_logic_i_n_12, RX_SRC_RDY_N_reg_inv_0 => TX_PE_DATA_V_reg, SR(0) => reset_lanes_i, m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid ); soft_err_reg: unisim.vcomponents.FDRE port map ( C => TX_PE_DATA_V_reg, CE => '1', D => aurora_lane_0_i_n_13, Q => soft_err, R => \^system_reset_reg\ ); standard_cc_module_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE port map ( Q => do_cc_i, SR => global_logic_i_n_9, \count_16d_srl_r_reg[0]_0\ => \^channel_up_rx_if_reg\, \count_24d_srl_r_reg[0]_0\ => TX_PE_DATA_V_reg, do_cc_r_reg0 => \tx_stream_control_sm_i/do_cc_r_reg0\, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\ ); tx_stream_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM port map ( Q(61) => TX_PE_DATA(0), Q(60) => TX_PE_DATA(1), Q(59) => TX_PE_DATA(2), Q(58) => TX_PE_DATA(3), Q(57) => TX_PE_DATA(4), Q(56) => TX_PE_DATA(5), Q(55) => TX_PE_DATA(6), Q(54) => TX_PE_DATA(7), Q(53) => TX_PE_DATA(8), Q(52) => TX_PE_DATA(9), Q(51) => TX_PE_DATA(10), Q(50) => TX_PE_DATA(11), Q(49) => TX_PE_DATA(12), Q(48) => TX_PE_DATA(13), Q(47) => TX_PE_DATA(14), Q(46) => TX_PE_DATA(15), Q(45) => TX_PE_DATA(16), Q(44) => TX_PE_DATA(17), Q(43) => TX_PE_DATA(18), Q(42) => TX_PE_DATA(19), Q(41) => TX_PE_DATA(20), Q(40) => TX_PE_DATA(21), Q(39) => TX_PE_DATA(22), Q(38) => TX_PE_DATA(23), Q(37) => TX_PE_DATA(24), Q(36) => TX_PE_DATA(25), Q(35) => TX_PE_DATA(26), Q(34) => TX_PE_DATA(27), Q(33) => TX_PE_DATA(28), Q(32) => TX_PE_DATA(29), Q(31) => TX_PE_DATA(30), Q(30) => TX_PE_DATA(31), Q(29) => TX_PE_DATA(32), Q(28) => TX_PE_DATA(33), Q(27) => TX_PE_DATA(34), Q(26) => TX_PE_DATA(35), Q(25) => TX_PE_DATA(36), Q(24) => TX_PE_DATA(37), Q(23) => TX_PE_DATA(38), Q(22) => TX_PE_DATA(39), Q(21) => TX_PE_DATA(40), Q(20) => TX_PE_DATA(41), Q(19) => TX_PE_DATA(42), Q(18) => TX_PE_DATA(43), Q(17) => TX_PE_DATA(44), Q(16) => TX_PE_DATA(45), Q(15) => TX_PE_DATA(46), Q(14) => TX_PE_DATA(47), Q(13) => TX_PE_DATA(48), Q(12) => TX_PE_DATA(49), Q(11) => TX_PE_DATA(52), Q(10) => TX_PE_DATA(53), Q(9) => TX_PE_DATA(54), Q(8) => TX_PE_DATA(55), Q(7) => TX_PE_DATA(56), Q(6) => TX_PE_DATA(57), Q(5) => TX_PE_DATA(58), Q(4) => TX_PE_DATA(59), Q(3) => TX_PE_DATA(60), Q(2) => TX_PE_DATA(61), Q(1) => TX_PE_DATA(62), Q(0) => TX_PE_DATA(63), R0 => \tx_stream_control_sm_i/R0\, TX_PE_DATA_V_reg => TX_PE_DATA_V_reg, channel_up_tx_if => channel_up_tx_if, do_cc_r => \tx_stream_control_sm_i/do_cc_r\, do_cc_r_reg0 => \tx_stream_control_sm_i/do_cc_r_reg0\, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\, extend_cc_r_reg => aurora_64b66b_0_wrapper_i_n_92, gen_cc_flop_0_i => tx_stream_i_n_6, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, tx_dst_rdy_n_r0 => \tx_stream_control_sm_i/tx_dst_rdy_n_r0\, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg(1) => tx_stream_i_n_4, wait_for_lane_up_r_reg(0) => tx_stream_i_n_5 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support is port ( s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ); s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); m_axi_rx_tvalid : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; channel_up : out STD_LOGIC; lane_up : out STD_LOGIC; user_clk_out : out STD_LOGIC; sync_clk_out : out STD_LOGIC; reset_pb : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; power_down : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); pma_init : in STD_LOGIC; gt0_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drprdy : out STD_LOGIC; gt0_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); gt0_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drpen : in STD_LOGIC; gt0_drpwe : in STD_LOGIC; init_clk : in STD_LOGIC; link_reset_out : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; sys_reset_out : out STD_LOGIC; gt_reset_out : out STD_LOGIC; refclk1_in : in STD_LOGIC; gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 ); mmcm_not_locked_out : out STD_LOGIC; mmcm_not_locked_out2 : out STD_LOGIC; tx_out_clk : out STD_LOGIC ); attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support is signal bufg_gt_clr_out : STD_LOGIC; signal \^gt_reset_out\ : STD_LOGIC; signal gt_reset_sync_n_0 : STD_LOGIC; signal lopt : STD_LOGIC; signal lopt_1 : STD_LOGIC; signal lopt_2 : STD_LOGIC; signal \^mmcm_not_locked_out2\ : STD_LOGIC; signal stg5 : STD_LOGIC; signal \^sync_clk_out\ : STD_LOGIC; signal sysreset_from_support : STD_LOGIC; signal \^tx_out_clk\ : STD_LOGIC; signal \^user_clk_out\ : STD_LOGIC; begin gt_reset_out <= \^gt_reset_out\; mmcm_not_locked_out2 <= \^mmcm_not_locked_out2\; sync_clk_out <= \^sync_clk_out\; tx_out_clk <= \^tx_out_clk\; user_clk_out <= \^user_clk_out\; aurora_64b66b_0_core_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core port map ( CHANNEL_UP_RX_IF_reg => channel_up, SYSTEM_RESET_reg => sys_reset_out, TX_PE_DATA_V_reg => \^user_clk_out\, bufg_gt_clr_out => bufg_gt_clr_out, gt0_drpaddr(8 downto 0) => gt0_drpaddr(8 downto 0), gt0_drpdi(15 downto 0) => gt0_drpdi(15 downto 0), gt0_drpdo(15 downto 0) => gt0_drpdo(15 downto 0), gt0_drpen => gt0_drpen, gt0_drprdy => gt0_drprdy, gt0_drpwe => gt0_drpwe, gt_pll_lock => gt_pll_lock, gt_powergood(0) => gt_powergood(0), gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err => hard_err, init_clk => init_clk, lane_up_flop_i => lane_up, link_reset_out => link_reset_out, loopback(2 downto 0) => loopback(2 downto 0), lopt => lopt, lopt_1 => bufg_gt_clr_out, lopt_2 => lopt_1, lopt_3 => lopt_2, m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, mmcm_not_locked_out2 => \^mmcm_not_locked_out2\, power_down => power_down, refclk1_in => refclk1_in, rxn => rxn, rxp => rxp, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, soft_err => soft_err, stg1_aurora_64b66b_0_cdc_to_reg => \^gt_reset_out\, sync_clk_out => \^sync_clk_out\, sysreset_from_support => sysreset_from_support, tx_out_clk => \^tx_out_clk\, txn => txn, txp => txp ); clock_module_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE port map ( CLK => \^user_clk_out\, bufg_gt_clr_out => bufg_gt_clr_out, lopt => lopt, lopt_1 => lopt_1, lopt_2 => lopt_2, mmcm_not_locked_out => mmcm_not_locked_out, mmcm_not_locked_out2 => \^mmcm_not_locked_out2\, sync_clk_out => \^sync_clk_out\, tx_out_clk => \^tx_out_clk\ ); gt_reset_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync port map ( D(0) => gt_reset_sync_n_0, init_clk => init_clk, pma_init => pma_init ); reset_pb_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 port map ( CLK => \^user_clk_out\, D(0) => stg5, reset_pb => reset_pb ); support_reset_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC port map ( CLK => \^user_clk_out\, D(0) => stg5, \debounce_gt_rst_r_reg[0]_0\(0) => gt_reset_sync_n_0, gt_reset_out => \^gt_reset_out\, init_clk => init_clk, sysreset_from_support => sysreset_from_support ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ); s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); m_axi_rx_tvalid : out STD_LOGIC; rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); txp : out STD_LOGIC_VECTOR ( 0 to 0 ); txn : out STD_LOGIC_VECTOR ( 0 to 0 ); refclk1_in : in STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; channel_up : out STD_LOGIC; lane_up : out STD_LOGIC_VECTOR ( 0 to 0 ); user_clk_out : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; sync_clk_out : out STD_LOGIC; reset_pb : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; power_down : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); pma_init : in STD_LOGIC; gt_pll_lock : out STD_LOGIC; gt0_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); gt0_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 ); gt0_drprdy : out STD_LOGIC; gt0_drpen : in STD_LOGIC; gt0_drpwe : in STD_LOGIC; init_clk : in STD_LOGIC; link_reset_out : out STD_LOGIC; gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 ); sys_reset_out : out STD_LOGIC; gt_reset_out : out STD_LOGIC; tx_out_clk : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "aurora_64b66b_v12_0_3, Coregen v14.3_ip3, Number of lanes = 1, Line rate is double5.0Gbps, Reference Clock is double125.0MHz, Interface is Streaming, Flow Control is None and is operating in DUPLEX configuration"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_mmcm_not_locked_out_UNCONNECTED : STD_LOGIC; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support port map ( channel_up => channel_up, gt0_drpaddr(8 downto 0) => gt0_drpaddr(8 downto 0), gt0_drpdi(15 downto 0) => gt0_drpdi(15 downto 0), gt0_drpdo(15 downto 0) => gt0_drpdo(15 downto 0), gt0_drpen => gt0_drpen, gt0_drprdy => gt0_drprdy, gt0_drpwe => gt0_drpwe, gt_pll_lock => gt_pll_lock, gt_powergood(0) => gt_powergood(0), gt_reset_out => gt_reset_out, gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err => hard_err, init_clk => init_clk, lane_up => lane_up(0), link_reset_out => link_reset_out, loopback(2 downto 0) => loopback(2 downto 0), m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, mmcm_not_locked_out => NLW_inst_mmcm_not_locked_out_UNCONNECTED, mmcm_not_locked_out2 => mmcm_not_locked_out, pma_init => pma_init, power_down => power_down, refclk1_in => refclk1_in, reset_pb => reset_pb, rxn => rxn(0), rxp => rxp(0), s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, soft_err => soft_err, sync_clk_out => sync_clk_out, sys_reset_out => sys_reset_out, tx_out_clk => tx_out_clk, txn => txn(0), txp => txp(0), user_clk_out => user_clk_out ); end STRUCTURE;