-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -- Date : Fri Mar 12 21:30:35 2021 -- Host : baby running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ axi_chip2chip_64B66B_sim_netlist.vhdl -- Design : axi_chip2chip_64B66B -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku115-flva2104-1-c -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0; attribute VERSION : integer; attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0; attribute WIDTH : integer; attribute WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "GRAY"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair135"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair135"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair136"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair136"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair137"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair137"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair131"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair131"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair129"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair129"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair97"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair104"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair63"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ is signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair70"; begin dest_out_bin(7) <= \dest_graysync_ff[2]\(7); dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \^dest_out_bin\(2), I2 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \dest_graysync_ff[2]\(4), I2 => \dest_graysync_ff[2]\(6), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), I5 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(6), I4 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(7), Q => async_path(7), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 5; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[3]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY"; signal \dest_graysync_ff[4]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[4]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[4]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[4]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair133"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair133"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair134"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair134"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair132"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair132"; begin dest_out_bin(8) <= \dest_graysync_ff[4]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(0), Q => \dest_graysync_ff[3]\(0), R => '0' ); \dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(1), Q => \dest_graysync_ff[3]\(1), R => '0' ); \dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(2), Q => \dest_graysync_ff[3]\(2), R => '0' ); \dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(3), Q => \dest_graysync_ff[3]\(3), R => '0' ); \dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(4), Q => \dest_graysync_ff[3]\(4), R => '0' ); \dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(5), Q => \dest_graysync_ff[3]\(5), R => '0' ); \dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(6), Q => \dest_graysync_ff[3]\(6), R => '0' ); \dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(7), Q => \dest_graysync_ff[3]\(7), R => '0' ); \dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(8), Q => \dest_graysync_ff[3]\(8), R => '0' ); \dest_graysync_ff_reg[4][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(0), Q => \dest_graysync_ff[4]\(0), R => '0' ); \dest_graysync_ff_reg[4][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(1), Q => \dest_graysync_ff[4]\(1), R => '0' ); \dest_graysync_ff_reg[4][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(2), Q => \dest_graysync_ff[4]\(2), R => '0' ); \dest_graysync_ff_reg[4][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(3), Q => \dest_graysync_ff[4]\(3), R => '0' ); \dest_graysync_ff_reg[4][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(4), Q => \dest_graysync_ff[4]\(4), R => '0' ); \dest_graysync_ff_reg[4][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(5), Q => \dest_graysync_ff[4]\(5), R => '0' ); \dest_graysync_ff_reg[4][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(6), Q => \dest_graysync_ff[4]\(6), R => '0' ); \dest_graysync_ff_reg[4][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(7), Q => \dest_graysync_ff[4]\(7), R => '0' ); \dest_graysync_ff_reg[4][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(8), Q => \dest_graysync_ff[4]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(0), I1 => \dest_graysync_ff[4]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[4]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[4]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[4]\(3), I1 => \dest_graysync_ff[4]\(5), I2 => \dest_graysync_ff[4]\(7), I3 => \dest_graysync_ff[4]\(8), I4 => \dest_graysync_ff[4]\(6), I5 => \dest_graysync_ff[4]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(4), I1 => \dest_graysync_ff[4]\(6), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(7), I4 => \dest_graysync_ff[4]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(5), I1 => \dest_graysync_ff[4]\(7), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(6), I1 => \dest_graysync_ff[4]\(8), I2 => \dest_graysync_ff[4]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(7), I1 => \dest_graysync_ff[4]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 5; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[3]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY"; signal \dest_graysync_ff[4]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[4]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[4]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[4]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair101"; begin dest_out_bin(8) <= \dest_graysync_ff[4]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(0), Q => \dest_graysync_ff[3]\(0), R => '0' ); \dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(1), Q => \dest_graysync_ff[3]\(1), R => '0' ); \dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(2), Q => \dest_graysync_ff[3]\(2), R => '0' ); \dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(3), Q => \dest_graysync_ff[3]\(3), R => '0' ); \dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(4), Q => \dest_graysync_ff[3]\(4), R => '0' ); \dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(5), Q => \dest_graysync_ff[3]\(5), R => '0' ); \dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(6), Q => \dest_graysync_ff[3]\(6), R => '0' ); \dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(7), Q => \dest_graysync_ff[3]\(7), R => '0' ); \dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(8), Q => \dest_graysync_ff[3]\(8), R => '0' ); \dest_graysync_ff_reg[4][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(0), Q => \dest_graysync_ff[4]\(0), R => '0' ); \dest_graysync_ff_reg[4][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(1), Q => \dest_graysync_ff[4]\(1), R => '0' ); \dest_graysync_ff_reg[4][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(2), Q => \dest_graysync_ff[4]\(2), R => '0' ); \dest_graysync_ff_reg[4][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(3), Q => \dest_graysync_ff[4]\(3), R => '0' ); \dest_graysync_ff_reg[4][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(4), Q => \dest_graysync_ff[4]\(4), R => '0' ); \dest_graysync_ff_reg[4][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(5), Q => \dest_graysync_ff[4]\(5), R => '0' ); \dest_graysync_ff_reg[4][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(6), Q => \dest_graysync_ff[4]\(6), R => '0' ); \dest_graysync_ff_reg[4][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(7), Q => \dest_graysync_ff[4]\(7), R => '0' ); \dest_graysync_ff_reg[4][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(8), Q => \dest_graysync_ff[4]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(0), I1 => \dest_graysync_ff[4]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[4]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[4]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[4]\(3), I1 => \dest_graysync_ff[4]\(5), I2 => \dest_graysync_ff[4]\(7), I3 => \dest_graysync_ff[4]\(8), I4 => \dest_graysync_ff[4]\(6), I5 => \dest_graysync_ff[4]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(4), I1 => \dest_graysync_ff[4]\(6), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(7), I4 => \dest_graysync_ff[4]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(5), I1 => \dest_graysync_ff[4]\(7), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(6), I1 => \dest_graysync_ff[4]\(8), I2 => \dest_graysync_ff[4]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(7), I1 => \dest_graysync_ff[4]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 5; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[3]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY"; signal \dest_graysync_ff[4]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[4]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[4]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[4]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair67"; begin dest_out_bin(8) <= \dest_graysync_ff[4]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(0), Q => \dest_graysync_ff[3]\(0), R => '0' ); \dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(1), Q => \dest_graysync_ff[3]\(1), R => '0' ); \dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(2), Q => \dest_graysync_ff[3]\(2), R => '0' ); \dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(3), Q => \dest_graysync_ff[3]\(3), R => '0' ); \dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(4), Q => \dest_graysync_ff[3]\(4), R => '0' ); \dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(5), Q => \dest_graysync_ff[3]\(5), R => '0' ); \dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(6), Q => \dest_graysync_ff[3]\(6), R => '0' ); \dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(7), Q => \dest_graysync_ff[3]\(7), R => '0' ); \dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(8), Q => \dest_graysync_ff[3]\(8), R => '0' ); \dest_graysync_ff_reg[4][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(0), Q => \dest_graysync_ff[4]\(0), R => '0' ); \dest_graysync_ff_reg[4][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(1), Q => \dest_graysync_ff[4]\(1), R => '0' ); \dest_graysync_ff_reg[4][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(2), Q => \dest_graysync_ff[4]\(2), R => '0' ); \dest_graysync_ff_reg[4][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(3), Q => \dest_graysync_ff[4]\(3), R => '0' ); \dest_graysync_ff_reg[4][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(4), Q => \dest_graysync_ff[4]\(4), R => '0' ); \dest_graysync_ff_reg[4][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(5), Q => \dest_graysync_ff[4]\(5), R => '0' ); \dest_graysync_ff_reg[4][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(6), Q => \dest_graysync_ff[4]\(6), R => '0' ); \dest_graysync_ff_reg[4][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(7), Q => \dest_graysync_ff[4]\(7), R => '0' ); \dest_graysync_ff_reg[4][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(8), Q => \dest_graysync_ff[4]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(0), I1 => \dest_graysync_ff[4]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[4]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[4]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[4]\(3), I1 => \dest_graysync_ff[4]\(5), I2 => \dest_graysync_ff[4]\(7), I3 => \dest_graysync_ff[4]\(8), I4 => \dest_graysync_ff[4]\(6), I5 => \dest_graysync_ff[4]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(4), I1 => \dest_graysync_ff[4]\(6), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(7), I4 => \dest_graysync_ff[4]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(5), I1 => \dest_graysync_ff[4]\(7), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(6), I1 => \dest_graysync_ff[4]\(8), I2 => \dest_graysync_ff[4]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(7), I1 => \dest_graysync_ff[4]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair141"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair141"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair140"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair140"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair139"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair139"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair138"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair138"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair234"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair234"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair233"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair233"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair235"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair235"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair236"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair236"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair165"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair165"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair166"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair166"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair167"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair167"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair168"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair168"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair174"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair174"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair173"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair173"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair175"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair175"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair176"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair176"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair105"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair71"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ is signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair225"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair225"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair226"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair226"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair227"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair227"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair228"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair228"; begin dest_out_bin(8) <= \dest_graysync_ff[2]\(8); dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(3), I3 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \^dest_out_bin\(3), I2 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \dest_graysync_ff[2]\(5), I2 => \dest_graysync_ff[2]\(7), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), I5 => \dest_graysync_ff[2]\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(7), I4 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(8), Q => async_path(8), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 5; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is 10; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ is signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[3]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY"; signal \dest_graysync_ff[4]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[4]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[4]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[4]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][9]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair169"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair169"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair170"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair170"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair171"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair171"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair172"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair172"; begin dest_out_bin(9) <= \dest_graysync_ff[4]\(9); dest_out_bin(8 downto 0) <= \^dest_out_bin\(8 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(9), Q => \dest_graysync_ff[0]\(9), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(9), Q => \dest_graysync_ff[1]\(9), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[2][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(9), Q => \dest_graysync_ff[2]\(9), R => '0' ); \dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(0), Q => \dest_graysync_ff[3]\(0), R => '0' ); \dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(1), Q => \dest_graysync_ff[3]\(1), R => '0' ); \dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(2), Q => \dest_graysync_ff[3]\(2), R => '0' ); \dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(3), Q => \dest_graysync_ff[3]\(3), R => '0' ); \dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(4), Q => \dest_graysync_ff[3]\(4), R => '0' ); \dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(5), Q => \dest_graysync_ff[3]\(5), R => '0' ); \dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(6), Q => \dest_graysync_ff[3]\(6), R => '0' ); \dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(7), Q => \dest_graysync_ff[3]\(7), R => '0' ); \dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(8), Q => \dest_graysync_ff[3]\(8), R => '0' ); \dest_graysync_ff_reg[3][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(9), Q => \dest_graysync_ff[3]\(9), R => '0' ); \dest_graysync_ff_reg[4][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(0), Q => \dest_graysync_ff[4]\(0), R => '0' ); \dest_graysync_ff_reg[4][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(1), Q => \dest_graysync_ff[4]\(1), R => '0' ); \dest_graysync_ff_reg[4][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(2), Q => \dest_graysync_ff[4]\(2), R => '0' ); \dest_graysync_ff_reg[4][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(3), Q => \dest_graysync_ff[4]\(3), R => '0' ); \dest_graysync_ff_reg[4][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(4), Q => \dest_graysync_ff[4]\(4), R => '0' ); \dest_graysync_ff_reg[4][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(5), Q => \dest_graysync_ff[4]\(5), R => '0' ); \dest_graysync_ff_reg[4][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(6), Q => \dest_graysync_ff[4]\(6), R => '0' ); \dest_graysync_ff_reg[4][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(7), Q => \dest_graysync_ff[4]\(7), R => '0' ); \dest_graysync_ff_reg[4][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(8), Q => \dest_graysync_ff[4]\(8), R => '0' ); \dest_graysync_ff_reg[4][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(9), Q => \dest_graysync_ff[4]\(9), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(0), I1 => \dest_graysync_ff[4]\(2), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[4]\(3), I4 => \dest_graysync_ff[4]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(1), I1 => \dest_graysync_ff[4]\(3), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[4]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(2), I1 => \^dest_out_bin\(4), I2 => \dest_graysync_ff[4]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(3), I1 => \^dest_out_bin\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[4]\(4), I1 => \dest_graysync_ff[4]\(6), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(9), I4 => \dest_graysync_ff[4]\(7), I5 => \dest_graysync_ff[4]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(5), I1 => \dest_graysync_ff[4]\(7), I2 => \dest_graysync_ff[4]\(9), I3 => \dest_graysync_ff[4]\(8), I4 => \dest_graysync_ff[4]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(6), I1 => \dest_graysync_ff[4]\(8), I2 => \dest_graysync_ff[4]\(9), I3 => \dest_graysync_ff[4]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(7), I1 => \dest_graysync_ff[4]\(9), I2 => \dest_graysync_ff[4]\(8), O => \^dest_out_bin\(7) ); \dest_out_bin[8]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(8), I1 => \dest_graysync_ff[4]\(9), O => \^dest_out_bin\(8) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(9), I1 => src_in_bin(8), O => gray_enc(8) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(8), Q => async_path(8), R => '0' ); \src_gray_ff_reg[9]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(9), Q => async_path(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 5; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is 10; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ is signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[3]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY"; signal \dest_graysync_ff[4]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[4]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[4]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[4]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[3][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[3][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[4][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[4][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[4][9]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair229"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair229"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair230"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair230"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair231"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair231"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair232"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair232"; begin dest_out_bin(9) <= \dest_graysync_ff[4]\(9); dest_out_bin(8 downto 0) <= \^dest_out_bin\(8 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(9), Q => \dest_graysync_ff[0]\(9), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(9), Q => \dest_graysync_ff[1]\(9), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[2][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(9), Q => \dest_graysync_ff[2]\(9), R => '0' ); \dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(0), Q => \dest_graysync_ff[3]\(0), R => '0' ); \dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(1), Q => \dest_graysync_ff[3]\(1), R => '0' ); \dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(2), Q => \dest_graysync_ff[3]\(2), R => '0' ); \dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(3), Q => \dest_graysync_ff[3]\(3), R => '0' ); \dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(4), Q => \dest_graysync_ff[3]\(4), R => '0' ); \dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(5), Q => \dest_graysync_ff[3]\(5), R => '0' ); \dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(6), Q => \dest_graysync_ff[3]\(6), R => '0' ); \dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(7), Q => \dest_graysync_ff[3]\(7), R => '0' ); \dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(8), Q => \dest_graysync_ff[3]\(8), R => '0' ); \dest_graysync_ff_reg[3][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[2]\(9), Q => \dest_graysync_ff[3]\(9), R => '0' ); \dest_graysync_ff_reg[4][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(0), Q => \dest_graysync_ff[4]\(0), R => '0' ); \dest_graysync_ff_reg[4][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(1), Q => \dest_graysync_ff[4]\(1), R => '0' ); \dest_graysync_ff_reg[4][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(2), Q => \dest_graysync_ff[4]\(2), R => '0' ); \dest_graysync_ff_reg[4][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(3), Q => \dest_graysync_ff[4]\(3), R => '0' ); \dest_graysync_ff_reg[4][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(4), Q => \dest_graysync_ff[4]\(4), R => '0' ); \dest_graysync_ff_reg[4][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(5), Q => \dest_graysync_ff[4]\(5), R => '0' ); \dest_graysync_ff_reg[4][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(6), Q => \dest_graysync_ff[4]\(6), R => '0' ); \dest_graysync_ff_reg[4][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(7), Q => \dest_graysync_ff[4]\(7), R => '0' ); \dest_graysync_ff_reg[4][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(8), Q => \dest_graysync_ff[4]\(8), R => '0' ); \dest_graysync_ff_reg[4][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[3]\(9), Q => \dest_graysync_ff[4]\(9), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(0), I1 => \dest_graysync_ff[4]\(2), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[4]\(3), I4 => \dest_graysync_ff[4]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(1), I1 => \dest_graysync_ff[4]\(3), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[4]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(2), I1 => \^dest_out_bin\(4), I2 => \dest_graysync_ff[4]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(3), I1 => \^dest_out_bin\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[4]\(4), I1 => \dest_graysync_ff[4]\(6), I2 => \dest_graysync_ff[4]\(8), I3 => \dest_graysync_ff[4]\(9), I4 => \dest_graysync_ff[4]\(7), I5 => \dest_graysync_ff[4]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[4]\(5), I1 => \dest_graysync_ff[4]\(7), I2 => \dest_graysync_ff[4]\(9), I3 => \dest_graysync_ff[4]\(8), I4 => \dest_graysync_ff[4]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[4]\(6), I1 => \dest_graysync_ff[4]\(8), I2 => \dest_graysync_ff[4]\(9), I3 => \dest_graysync_ff[4]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[4]\(7), I1 => \dest_graysync_ff[4]\(9), I2 => \dest_graysync_ff[4]\(8), O => \^dest_out_bin\(7) ); \dest_out_bin[8]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[4]\(8), I1 => \dest_graysync_ff[4]\(9), O => \^dest_out_bin\(8) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(9), I1 => src_in_bin(8), O => gray_enc(8) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(8), Q => async_path(8), R => '0' ); \src_gray_ff_reg[9]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(9), Q => async_path(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is 10; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ is signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][9]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair180"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair180"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair179"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair179"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair178"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair178"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair177"; attribute SOFT_HLUTNM of \src_gray_ff[8]_i_1\ : label is "soft_lutpair177"; begin dest_out_bin(9) <= \dest_graysync_ff[2]\(9); dest_out_bin(8 downto 0) <= \^dest_out_bin\(8 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(9), Q => \dest_graysync_ff[0]\(9), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(9), Q => \dest_graysync_ff[1]\(9), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[2][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(9), Q => \dest_graysync_ff[2]\(9), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[2]\(3), I4 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \dest_graysync_ff[2]\(3), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(4), I2 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \^dest_out_bin\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(9), I4 => \dest_graysync_ff[2]\(7), I5 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(9), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(9), I3 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(9), I2 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \dest_out_bin[8]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(8), I1 => \dest_graysync_ff[2]\(9), O => \^dest_out_bin\(8) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(9), I1 => src_in_bin(8), O => gray_enc(8) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(8), Q => async_path(8), R => '0' ); \src_gray_ff_reg[9]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(9), Q => async_path(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is 10; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ : entity is "GRAY"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ is signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[2]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY"; signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][9]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[2][9]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[2][9]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair240"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair240"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair239"; attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair239"; attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair238"; attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair238"; attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair237"; attribute SOFT_HLUTNM of \src_gray_ff[8]_i_1\ : label is "soft_lutpair237"; begin dest_out_bin(9) <= \dest_graysync_ff[2]\(9); dest_out_bin(8 downto 0) <= \^dest_out_bin\(8 downto 0); \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(5), Q => \dest_graysync_ff[0]\(5), R => '0' ); \dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(6), Q => \dest_graysync_ff[0]\(6), R => '0' ); \dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(7), Q => \dest_graysync_ff[0]\(7), R => '0' ); \dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(8), Q => \dest_graysync_ff[0]\(8), R => '0' ); \dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(9), Q => \dest_graysync_ff[0]\(9), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(5), Q => \dest_graysync_ff[1]\(5), R => '0' ); \dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(6), Q => \dest_graysync_ff[1]\(6), R => '0' ); \dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(7), Q => \dest_graysync_ff[1]\(7), R => '0' ); \dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(8), Q => \dest_graysync_ff[1]\(8), R => '0' ); \dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(9), Q => \dest_graysync_ff[1]\(9), R => '0' ); \dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(0), Q => \dest_graysync_ff[2]\(0), R => '0' ); \dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(1), Q => \dest_graysync_ff[2]\(1), R => '0' ); \dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(2), Q => \dest_graysync_ff[2]\(2), R => '0' ); \dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(3), Q => \dest_graysync_ff[2]\(3), R => '0' ); \dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => \dest_graysync_ff[2]\(4), R => '0' ); \dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(5), Q => \dest_graysync_ff[2]\(5), R => '0' ); \dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(6), Q => \dest_graysync_ff[2]\(6), R => '0' ); \dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(7), Q => \dest_graysync_ff[2]\(7), R => '0' ); \dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(8), Q => \dest_graysync_ff[2]\(8), R => '0' ); \dest_graysync_ff_reg[2][9]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(9), Q => \dest_graysync_ff[2]\(9), R => '0' ); \dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(0), I1 => \dest_graysync_ff[2]\(2), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[2]\(3), I4 => \dest_graysync_ff[2]\(1), O => \^dest_out_bin\(0) ); \dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(1), I1 => \dest_graysync_ff[2]\(3), I2 => \^dest_out_bin\(4), I3 => \dest_graysync_ff[2]\(2), O => \^dest_out_bin\(1) ); \dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(2), I1 => \^dest_out_bin\(4), I2 => \dest_graysync_ff[2]\(3), O => \^dest_out_bin\(2) ); \dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(3), I1 => \^dest_out_bin\(4), O => \^dest_out_bin\(3) ); \dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996696996" ) port map ( I0 => \dest_graysync_ff[2]\(4), I1 => \dest_graysync_ff[2]\(6), I2 => \dest_graysync_ff[2]\(8), I3 => \dest_graysync_ff[2]\(9), I4 => \dest_graysync_ff[2]\(7), I5 => \dest_graysync_ff[2]\(5), O => \^dest_out_bin\(4) ); \dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[2]\(5), I1 => \dest_graysync_ff[2]\(7), I2 => \dest_graysync_ff[2]\(9), I3 => \dest_graysync_ff[2]\(8), I4 => \dest_graysync_ff[2]\(6), O => \^dest_out_bin\(5) ); \dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[2]\(6), I1 => \dest_graysync_ff[2]\(8), I2 => \dest_graysync_ff[2]\(9), I3 => \dest_graysync_ff[2]\(7), O => \^dest_out_bin\(6) ); \dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[2]\(7), I1 => \dest_graysync_ff[2]\(9), I2 => \dest_graysync_ff[2]\(8), O => \^dest_out_bin\(7) ); \dest_out_bin[8]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[2]\(8), I1 => \dest_graysync_ff[2]\(9), O => \^dest_out_bin\(8) ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(5), I1 => src_in_bin(4), O => gray_enc(4) ); \src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(6), I1 => src_in_bin(5), O => gray_enc(5) ); \src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(7), I1 => src_in_bin(6), O => gray_enc(6) ); \src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(8), I1 => src_in_bin(7), O => gray_enc(7) ); \src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(9), I1 => src_in_bin(8), O => gray_enc(8) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(4), Q => async_path(4), R => '0' ); \src_gray_ff_reg[5]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(5), Q => async_path(5), R => '0' ); \src_gray_ff_reg[6]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(6), Q => async_path(6), R => '0' ); \src_gray_ff_reg[7]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(7), Q => async_path(7), R => '0' ); \src_gray_ff_reg[8]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(8), Q => async_path(8), R => '0' ); \src_gray_ff_reg[9]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(9), Q => async_path(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 3; attribute INIT : string; attribute INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0; attribute VERSION : integer; attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "SYNC_RST"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ is port ( src_rst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_rst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is 3; attribute INIT : string; attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "xpm_cdc_sync_rst"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "true"; attribute xpm_cdc : string; attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ : entity is "SYNC_RST"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST"; begin dest_rst <= syncstages_ff(2); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => src_rst, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 ); DI : out STD_LOGIC_VECTOR ( 1 downto 0 ); ram_empty_i : in STD_LOGIC; rd_en : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \src_gray_ff_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; begin Q(1 downto 0) <= \^q\(1 downto 0); \count_value_i[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"696A9999" ) port map ( I0 => \^q\(0), I1 => ram_empty_i, I2 => rd_en, I3 => \count_value_i_reg[0]_0\(0), I4 => \count_value_i_reg[0]_0\(1), O => \count_value_i[0]_i_1__2_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"9855" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9A9AAAAAA6A666A6" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => rd_en, I5 => ram_empty_i, O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[0]_i_1__2_n_0\, Q => \^q\(0), R => SR(0) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[1]_i_3_n_0\, Q => \^q\(1), R => SR(0) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => src_in_bin(0) ); \grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => DI(1) ); \grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => DI(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 1 downto 0 ); DI : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 : entity is "xpm_counter_updn"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 is signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; attribute HLUTNM : string; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_16\ : label is "lutpair2"; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_8\ : label is "lutpair2"; begin DI(0) <= \^di\(0); Q(1 downto 0) <= \^q\(1 downto 0); \count_value_i[0]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"5AAAA655" ) port map ( I0 => \^q\(0), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \count_value_i_reg[0]_0\(1), I4 => ram_empty_i, O => \count_value_i[0]_i_1__3_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"C02F" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => ram_empty_i, O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"A999A9A96AAA6AAA" ) port map ( I0 => \^q\(1), I1 => ram_empty_i, I2 => \count_value_i_reg[0]_0\(1), I3 => rd_en, I4 => \count_value_i_reg[0]_0\(0), I5 => \^q\(0), O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[0]_i_1__3_n_0\, Q => \^q\(0), R => SR(0) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[1]_i_3_n_0\, Q => \^q\(1), R => SR(0) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"2DD2" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), O => src_in_bin(0) ); \grdc.rd_data_count_i[7]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"9669" ) port map ( I0 => \^di\(0), I1 => \^q\(1), I2 => \grdc.rd_data_count_i_reg[7]\(1), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), O => S(1) ); \grdc.rd_data_count_i[7]_i_16\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), O => S(0) ); \grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \^di\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 1 downto 0 ); DI : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 : entity is "xpm_counter_updn"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 is signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; attribute HLUTNM : string; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_16\ : label is "lutpair0"; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_8\ : label is "lutpair0"; begin DI(0) <= \^di\(0); Q(1 downto 0) <= \^q\(1 downto 0); \count_value_i[0]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"5AAAA655" ) port map ( I0 => \^q\(0), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \count_value_i_reg[0]_0\(1), I4 => ram_empty_i, O => \count_value_i[0]_i_1__3_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"C02F" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => ram_empty_i, O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"A999A9A96AAA6AAA" ) port map ( I0 => \^q\(1), I1 => ram_empty_i, I2 => \count_value_i_reg[0]_0\(1), I3 => rd_en, I4 => \count_value_i_reg[0]_0\(0), I5 => \^q\(0), O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[0]_i_1__3_n_0\, Q => \^q\(0), R => SR(0) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[1]_i_3_n_0\, Q => \^q\(1), R => SR(0) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"2DD2" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), O => src_in_bin(0) ); \grdc.rd_data_count_i[7]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"9669" ) port map ( I0 => \^di\(0), I1 => \^q\(1), I2 => \grdc.rd_data_count_i_reg[7]\(1), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), O => S(1) ); \grdc.rd_data_count_i[7]_i_16\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), O => S(0) ); \grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \^di\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 1 downto 0 ); DI : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 : entity is "xpm_counter_updn"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 is signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; attribute HLUTNM : string; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_16\ : label is "lutpair1"; attribute HLUTNM of \grdc.rd_data_count_i[7]_i_8\ : label is "lutpair1"; begin DI(0) <= \^di\(0); Q(1 downto 0) <= \^q\(1 downto 0); \count_value_i[0]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"5AAAA655" ) port map ( I0 => \^q\(0), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \count_value_i_reg[0]_0\(1), I4 => ram_empty_i, O => \count_value_i[0]_i_1__3_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"C02F" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => ram_empty_i, O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"A999A9A96AAA6AAA" ) port map ( I0 => \^q\(1), I1 => ram_empty_i, I2 => \count_value_i_reg[0]_0\(1), I3 => rd_en, I4 => \count_value_i_reg[0]_0\(0), I5 => \^q\(0), O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[0]_i_1__3_n_0\, Q => \^q\(0), R => SR(0) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[1]_i_3_n_0\, Q => \^q\(1), R => SR(0) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"2DD2" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), O => src_in_bin(0) ); \grdc.rd_data_count_i[7]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"9669" ) port map ( I0 => \^di\(0), I1 => \^q\(1), I2 => \grdc.rd_data_count_i_reg[7]\(1), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), O => S(1) ); \grdc.rd_data_count_i[7]_i_16\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), O => S(0) ); \grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \^di\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 ); DI : out STD_LOGIC_VECTOR ( 1 downto 0 ); ram_empty_i : in STD_LOGIC; rd_en : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \src_gray_ff_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 : entity is "xpm_counter_updn"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_3_n_0\ : STD_LOGIC; signal \gen_fwft.count_en\ : STD_LOGIC; begin Q(1 downto 0) <= \^q\(1 downto 0); \count_value_i[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"696A9999" ) port map ( I0 => \^q\(0), I1 => ram_empty_i, I2 => rd_en, I3 => \count_value_i_reg[0]_0\(0), I4 => \count_value_i_reg[0]_0\(1), O => \count_value_i[0]_i_1__2_n_0\ ); \count_value_i[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"9855" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), O => \gen_fwft.count_en\ ); \count_value_i[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9A9AAAAAA6A666A6" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => rd_en, I5 => ram_empty_i, O => \count_value_i[1]_i_3_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[0]_i_1__2_n_0\, Q => \^q\(0), R => SR(0) ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \gen_fwft.count_en\, D => \count_value_i[1]_i_3_n_0\, Q => \^q\(1), R => SR(0) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => src_in_bin(0) ); \grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => DI(1) ); \grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \src_gray_ff_reg[0]\(0), O => DI(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); enb : out STD_LOGIC; DI : out STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); S : out STD_LOGIC_VECTOR ( 4 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[8]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; signal \^enb\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair144"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair145"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair145"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair142"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair142"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair146"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair143"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\ : label is "soft_lutpair143"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\ : label is "soft_lutpair144"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair146"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(7 downto 0) <= \^q\(7 downto 0); enb <= \^enb\; \count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \count_value_i[0]_i_1__4_n_0\ ); \count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__3_n_0\ ); \count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__3_n_0\ ); \count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__3_n_0\ ); \count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__3_n_0\ ); \count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__2_n_0\ ); \count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__2_n_0\ ); \count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[0]_0\(1), I2 => \count_value_i_reg[0]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__2_n_0\ ); \count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__2_n_0\ ); \count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \count_value_i_reg_n_0_[8]\, O => \count_value_i[8]_i_1__0_n_0\ ); \count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => \^enb\, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[0]_i_1__4_n_0\, Q => \^q\(0), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[1]_i_1__3_n_0\, Q => \^q\(1), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[2]_i_1__3_n_0\, Q => \^q\(2), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[3]_i_1__3_n_0\, Q => \^q\(3), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[4]_i_1__3_n_0\, Q => \^q\(4), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[5]_i_1__2_n_0\, Q => \^q\(5), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[6]_i_1__2_n_0\, Q => \^q\(6), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[7]_i_1__2_n_0\, Q => \^q\(7), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[8]_i_1__0_n_0\, Q => \count_value_i_reg_n_0_[8]\, R => \count_value_i_reg[8]_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \^q\(7), I1 => \^q\(5), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(4), I4 => \^q\(6), I5 => \count_value_i_reg_n_0_[8]\, O => src_in_bin(7) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFBFBBAFB" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(5), I4 => \^q\(7), O => src_in_bin(6) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(5), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(4), I3 => \^q\(6), O => src_in_bin(5) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(5), O => src_in_bin(4) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFEAFE00001501" ) port map ( I0 => \^q\(3), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), I5 => \^q\(4), O => src_in_bin(3) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBBAFB04044504" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => src_in_bin(2) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT5 generic map( INIT => X"B0FB4F04" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), O => src_in_bin(1) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => src_in_bin(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0), CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\, DI(7) => '0', DI(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\, DI(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\, DI(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\, DI(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\, DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\, DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\, DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\, O(7 downto 0) => D(7 downto 0), S(7) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\, S(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\, S(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\, S(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\, S(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\, S(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\, S(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\, S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"00FD" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => ram_empty_i, O => \^enb\ ); \grdc.rd_data_count_i[7]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[8]\(4), I2 => \^q\(6), I3 => \grdc.rd_data_count_i_reg[8]\(5), O => S(3) ); \grdc.rd_data_count_i[7]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[8]\(3), I2 => \^q\(5), I3 => \grdc.rd_data_count_i_reg[8]\(4), O => S(2) ); \grdc.rd_data_count_i[7]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[8]\(2), I2 => \^q\(4), I3 => \grdc.rd_data_count_i_reg[8]\(3), O => S(1) ); \grdc.rd_data_count_i[7]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[8]\(1), I2 => \^q\(3), I3 => \grdc.rd_data_count_i_reg[8]\(2), O => S(0) ); \grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[8]\(0), O => DI(0) ); \grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[8]\(5), I2 => \^q\(7), I3 => \grdc.rd_data_count_i_reg[8]\(6), O => S(4) ); \grdc.rd_data_count_i[8]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[8]\(6), I2 => \count_value_i_reg_n_0_[8]\, I3 => \grdc.rd_data_count_i_reg[8]\(7), O => \count_value_i_reg[7]_0\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gwdc.wr_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair151"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair151"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair150"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair150"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair149"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair149"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[8]_i_1\ : label is 35; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__1_n_0\ ); \count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__1_n_0\ ); \count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__1_n_0\ ); \count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__1_n_0\ ); \count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__1_n_0\ ); \count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__1_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__1_n_0\ ); \count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__1_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__1_n_0\ ); \count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__1_n_0\ ); \count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__1_n_0\ ); \count_value_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1_n_0\ ); \count_value_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__1_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1_n_0\, Q => \^q\(8), R => wrst_busy ); \gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gwdc.wr_data_count_i_reg[8]\(7), O => \gwdc.wr_data_count_i[7]_i_2_n_0\ ); \gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gwdc.wr_data_count_i_reg[8]\(6), O => \gwdc.wr_data_count_i[7]_i_3_n_0\ ); \gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gwdc.wr_data_count_i_reg[8]\(5), O => \gwdc.wr_data_count_i[7]_i_4_n_0\ ); \gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gwdc.wr_data_count_i_reg[8]\(4), O => \gwdc.wr_data_count_i[7]_i_5_n_0\ ); \gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gwdc.wr_data_count_i_reg[8]\(3), O => \gwdc.wr_data_count_i[7]_i_6_n_0\ ); \gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gwdc.wr_data_count_i_reg[8]\(2), O => \gwdc.wr_data_count_i[7]_i_7_n_0\ ); \gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gwdc.wr_data_count_i_reg[8]\(1), O => \gwdc.wr_data_count_i[7]_i_8_n_0\ ); \gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gwdc.wr_data_count_i_reg[8]\(0), O => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gwdc.wr_data_count_i_reg[8]\(8), O => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '1', CI_TOP => '0', CO(7) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CO(6) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\, CO(5) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\, CO(4) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\, CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_4\, CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_5\, CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_6\, CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \gwdc.wr_data_count_i[7]_i_2_n_0\, S(6) => \gwdc.wr_data_count_i[7]_i_3_n_0\, S(5) => \gwdc.wr_data_count_i[7]_i_4_n_0\, S(4) => \gwdc.wr_data_count_i[7]_i_5_n_0\, S(3) => \gwdc.wr_data_count_i[7]_i_6_n_0\, S(2) => \gwdc.wr_data_count_i[7]_i_7_n_0\, S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); enb : out STD_LOGIC; DI : out STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); S : out STD_LOGIC_VECTOR ( 4 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[8]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; signal \^enb\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair113"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(7 downto 0) <= \^q\(7 downto 0); enb <= \^enb\; \count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \count_value_i[0]_i_1__4_n_0\ ); \count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__3_n_0\ ); \count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__3_n_0\ ); \count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__3_n_0\ ); \count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__3_n_0\ ); \count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__2_n_0\ ); \count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__2_n_0\ ); \count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[0]_0\(1), I2 => \count_value_i_reg[0]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__2_n_0\ ); \count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__2_n_0\ ); \count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \count_value_i_reg_n_0_[8]\, O => \count_value_i[8]_i_1__0_n_0\ ); \count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => \^enb\, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[0]_i_1__4_n_0\, Q => \^q\(0), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[1]_i_1__3_n_0\, Q => \^q\(1), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[2]_i_1__3_n_0\, Q => \^q\(2), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[3]_i_1__3_n_0\, Q => \^q\(3), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[4]_i_1__3_n_0\, Q => \^q\(4), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[5]_i_1__2_n_0\, Q => \^q\(5), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[6]_i_1__2_n_0\, Q => \^q\(6), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[7]_i_1__2_n_0\, Q => \^q\(7), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[8]_i_1__0_n_0\, Q => \count_value_i_reg_n_0_[8]\, R => \count_value_i_reg[8]_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \^q\(7), I1 => \^q\(5), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(4), I4 => \^q\(6), I5 => \count_value_i_reg_n_0_[8]\, O => src_in_bin(7) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFBFBBAFB" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(5), I4 => \^q\(7), O => src_in_bin(6) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(5), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(4), I3 => \^q\(6), O => src_in_bin(5) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(5), O => src_in_bin(4) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFEAFE00001501" ) port map ( I0 => \^q\(3), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), I5 => \^q\(4), O => src_in_bin(3) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBBAFB04044504" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => src_in_bin(2) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT5 generic map( INIT => X"B0FB4F04" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), O => src_in_bin(1) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => src_in_bin(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0), CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\, DI(7) => '0', DI(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\, DI(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\, DI(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\, DI(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\, DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\, DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\, DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\, O(7 downto 0) => D(7 downto 0), S(7) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\, S(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\, S(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\, S(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\, S(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\, S(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\, S(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\, S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"00FD" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => ram_empty_i, O => \^enb\ ); \grdc.rd_data_count_i[7]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[8]\(4), I2 => \^q\(6), I3 => \grdc.rd_data_count_i_reg[8]\(5), O => S(3) ); \grdc.rd_data_count_i[7]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[8]\(3), I2 => \^q\(5), I3 => \grdc.rd_data_count_i_reg[8]\(4), O => S(2) ); \grdc.rd_data_count_i[7]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[8]\(2), I2 => \^q\(4), I3 => \grdc.rd_data_count_i_reg[8]\(3), O => S(1) ); \grdc.rd_data_count_i[7]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[8]\(1), I2 => \^q\(3), I3 => \grdc.rd_data_count_i_reg[8]\(2), O => S(0) ); \grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[8]\(0), O => DI(0) ); \grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[8]\(5), I2 => \^q\(7), I3 => \grdc.rd_data_count_i_reg[8]\(6), O => S(4) ); \grdc.rd_data_count_i[8]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[8]\(6), I2 => \count_value_i_reg_n_0_[8]\, I3 => \grdc.rd_data_count_i_reg[8]\(7), O => \count_value_i_reg[7]_0\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gwdc.wr_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair116"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[8]_i_1\ : label is 35; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__1_n_0\ ); \count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__1_n_0\ ); \count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__1_n_0\ ); \count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__1_n_0\ ); \count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__1_n_0\ ); \count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__1_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__1_n_0\ ); \count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__1_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__1_n_0\ ); \count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__1_n_0\ ); \count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__1_n_0\ ); \count_value_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1_n_0\ ); \count_value_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__1_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1_n_0\, Q => \^q\(8), R => wrst_busy ); \gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gwdc.wr_data_count_i_reg[8]\(7), O => \gwdc.wr_data_count_i[7]_i_2_n_0\ ); \gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gwdc.wr_data_count_i_reg[8]\(6), O => \gwdc.wr_data_count_i[7]_i_3_n_0\ ); \gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gwdc.wr_data_count_i_reg[8]\(5), O => \gwdc.wr_data_count_i[7]_i_4_n_0\ ); \gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gwdc.wr_data_count_i_reg[8]\(4), O => \gwdc.wr_data_count_i[7]_i_5_n_0\ ); \gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gwdc.wr_data_count_i_reg[8]\(3), O => \gwdc.wr_data_count_i[7]_i_6_n_0\ ); \gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gwdc.wr_data_count_i_reg[8]\(2), O => \gwdc.wr_data_count_i[7]_i_7_n_0\ ); \gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gwdc.wr_data_count_i_reg[8]\(1), O => \gwdc.wr_data_count_i[7]_i_8_n_0\ ); \gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gwdc.wr_data_count_i_reg[8]\(0), O => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gwdc.wr_data_count_i_reg[8]\(8), O => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '1', CI_TOP => '0', CO(7) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CO(6) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\, CO(5) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\, CO(4) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\, CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_4\, CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_5\, CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_6\, CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \gwdc.wr_data_count_i[7]_i_2_n_0\, S(6) => \gwdc.wr_data_count_i[7]_i_3_n_0\, S(5) => \gwdc.wr_data_count_i[7]_i_4_n_0\, S(4) => \gwdc.wr_data_count_i[7]_i_5_n_0\, S(3) => \gwdc.wr_data_count_i[7]_i_6_n_0\, S(2) => \gwdc.wr_data_count_i[7]_i_7_n_0\, S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); enb : out STD_LOGIC; DI : out STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); S : out STD_LOGIC_VECTOR ( 4 downto 0 ); src_in_bin : out STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[8]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; signal \^enb\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair79"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(7 downto 0) <= \^q\(7 downto 0); enb <= \^enb\; \count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \count_value_i[0]_i_1__4_n_0\ ); \count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__3_n_0\ ); \count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__3_n_0\ ); \count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__3_n_0\ ); \count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__3_n_0\ ); \count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__2_n_0\ ); \count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__2_n_0\ ); \count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[0]_0\(1), I2 => \count_value_i_reg[0]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__2_n_0\ ); \count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__2_n_0\ ); \count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \count_value_i_reg_n_0_[8]\, O => \count_value_i[8]_i_1__0_n_0\ ); \count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => \^enb\, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[0]_i_1__4_n_0\, Q => \^q\(0), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[1]_i_1__3_n_0\, Q => \^q\(1), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[2]_i_1__3_n_0\, Q => \^q\(2), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[3]_i_1__3_n_0\, Q => \^q\(3), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[4]_i_1__3_n_0\, Q => \^q\(4), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[5]_i_1__2_n_0\, Q => \^q\(5), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[6]_i_1__2_n_0\, Q => \^q\(6), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[7]_i_1__2_n_0\, Q => \^q\(7), R => \count_value_i_reg[8]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^enb\, D => \count_value_i[8]_i_1__0_n_0\, Q => \count_value_i_reg_n_0_[8]\, R => \count_value_i_reg[8]_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \^q\(7), I1 => \^q\(5), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(4), I4 => \^q\(6), I5 => \count_value_i_reg_n_0_[8]\, O => src_in_bin(7) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFBFBBAFB" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I3 => \^q\(5), I4 => \^q\(7), O => src_in_bin(6) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(5), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(4), I3 => \^q\(6), O => src_in_bin(5) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\, I2 => \^q\(5), O => src_in_bin(4) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFEAFE00001501" ) port map ( I0 => \^q\(3), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), I5 => \^q\(4), O => src_in_bin(3) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBBAFB04044504" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(0), I4 => \^q\(0), I5 => \^q\(3), O => src_in_bin(2) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT5 generic map( INIT => X"B0FB4F04" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \^q\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(2), O => src_in_bin(1) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), O => src_in_bin(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"ABAA5455" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(0), I3 => \count_value_i_reg[0]_0\(1), I4 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(6), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(5), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(4), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(3), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(2), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(1), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0), CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\, DI(7) => '0', DI(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\, DI(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\, DI(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\, DI(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\, DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\, DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\, DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\, O(7 downto 0) => D(7 downto 0), S(7) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0\, S(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0\, S(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0\, S(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0\, S(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0\, S(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0\, S(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0\, S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0\ ); \gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"00FD" ) port map ( I0 => \count_value_i_reg[0]_0\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => rd_en, I3 => ram_empty_i, O => \^enb\ ); \grdc.rd_data_count_i[7]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[8]\(4), I2 => \^q\(6), I3 => \grdc.rd_data_count_i_reg[8]\(5), O => S(3) ); \grdc.rd_data_count_i[7]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[8]\(3), I2 => \^q\(5), I3 => \grdc.rd_data_count_i_reg[8]\(4), O => S(2) ); \grdc.rd_data_count_i[7]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[8]\(2), I2 => \^q\(4), I3 => \grdc.rd_data_count_i_reg[8]\(3), O => S(1) ); \grdc.rd_data_count_i[7]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[8]\(1), I2 => \^q\(3), I3 => \grdc.rd_data_count_i_reg[8]\(2), O => S(0) ); \grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[8]\(0), O => DI(0) ); \grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[8]\(5), I2 => \^q\(7), I3 => \grdc.rd_data_count_i_reg[8]\(6), O => S(4) ); \grdc.rd_data_count_i[8]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[8]\(6), I2 => \count_value_i_reg_n_0_[8]\, I3 => \grdc.rd_data_count_i_reg[8]\(7), O => \count_value_i_reg[7]_0\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gwdc.wr_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[8]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair82"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[8]_i_1\ : label is 35; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__1_n_0\ ); \count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__1_n_0\ ); \count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__1_n_0\ ); \count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__1_n_0\ ); \count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__1_n_0\ ); \count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__1_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__1_n_0\ ); \count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__1_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__1_n_0\ ); \count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__1_n_0\ ); \count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__1_n_0\ ); \count_value_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1_n_0\ ); \count_value_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__1_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1_n_0\, Q => \^q\(8), R => wrst_busy ); \gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gwdc.wr_data_count_i_reg[8]\(7), O => \gwdc.wr_data_count_i[7]_i_2_n_0\ ); \gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gwdc.wr_data_count_i_reg[8]\(6), O => \gwdc.wr_data_count_i[7]_i_3_n_0\ ); \gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gwdc.wr_data_count_i_reg[8]\(5), O => \gwdc.wr_data_count_i[7]_i_4_n_0\ ); \gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gwdc.wr_data_count_i_reg[8]\(4), O => \gwdc.wr_data_count_i[7]_i_5_n_0\ ); \gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gwdc.wr_data_count_i_reg[8]\(3), O => \gwdc.wr_data_count_i[7]_i_6_n_0\ ); \gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gwdc.wr_data_count_i_reg[8]\(2), O => \gwdc.wr_data_count_i[7]_i_7_n_0\ ); \gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gwdc.wr_data_count_i_reg[8]\(1), O => \gwdc.wr_data_count_i[7]_i_8_n_0\ ); \gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gwdc.wr_data_count_i_reg[8]\(0), O => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gwdc.wr_data_count_i_reg[8]\(8), O => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '1', CI_TOP => '0', CO(7) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CO(6) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\, CO(5) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\, CO(4) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\, CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_4\, CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_5\, CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_6\, CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \gwdc.wr_data_count_i[7]_i_2_n_0\, S(6) => \gwdc.wr_data_count_i[7]_i_3_n_0\, S(5) => \gwdc.wr_data_count_i[7]_i_4_n_0\, S(4) => \gwdc.wr_data_count_i[7]_i_5_n_0\, S(3) => \gwdc.wr_data_count_i[7]_i_6_n_0\, S(2) => \gwdc.wr_data_count_i[7]_i_7_n_0\, S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \gwdc.wr_data_count_i[8]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__1_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair147"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair147"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"10EF" ) port map ( I0 => rd_en, I1 => \count_value_i_reg[1]_0\(0), I2 => \count_value_i_reg[1]_0\(1), I3 => \^q\(0), O => \count_value_i[0]_i_1__2_n_0\ ); \count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[1]_0\(1), I1 => \count_value_i_reg[1]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__2_n_0\ ); \count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__2_n_0\ ); \count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__2_n_0\ ); \count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__2_n_0\ ); \count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__3_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__3_n_0\ ); \count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__3_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__3_n_0\ ); \count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[1]_0\(1), I2 => \count_value_i_reg[1]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__3_n_0\ ); \count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__1_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__3_n_0\ ); \count_value_i[7]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => E(0), I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[0]_i_1__2_n_0\, Q => \^q\(0), S => \count_value_i_reg[0]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[1]_i_1__2_n_0\, Q => \^q\(1), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[2]_i_1__2_n_0\, Q => \^q\(2), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[3]_i_1__2_n_0\, Q => \^q\(3), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[4]_i_1__2_n_0\, Q => \^q\(4), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[5]_i_1__3_n_0\, Q => \^q\(5), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[6]_i_1__3_n_0\, Q => \^q\(6), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[7]_i_1__3_n_0\, Q => \^q\(7), R => \count_value_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); D : out STD_LOGIC_VECTOR ( 6 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__0_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair153"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair153"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair152"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair152"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__0_n_0\ ); \count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__0_n_0\ ); \count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__0_n_0\ ); \count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__0_n_0\ ); \count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__0_n_0\ ); \count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__0_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__0_n_0\ ); \count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__0_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__0_n_0\ ); \count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__0_n_0\ ); \count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__0_n_0\ ); \count_value_i[7]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__0_n_0\, Q => \^q\(0), S => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__0_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__0_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__0_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__0_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__0_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__0_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__0_n_0\, Q => \^q\(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(6), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(5), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(4), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(3), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(2), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(1), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(0), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => wr_pntr_plus1_pf_carry, CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\, DI(7) => '0', DI(6 downto 0) => \^q\(6 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\(0), S(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\, S(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\, S(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\, S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\, S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\, S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\, S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\, S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__1_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair114"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"10EF" ) port map ( I0 => rd_en, I1 => \count_value_i_reg[1]_0\(0), I2 => \count_value_i_reg[1]_0\(1), I3 => \^q\(0), O => \count_value_i[0]_i_1__2_n_0\ ); \count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[1]_0\(1), I1 => \count_value_i_reg[1]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__2_n_0\ ); \count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__2_n_0\ ); \count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__2_n_0\ ); \count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__2_n_0\ ); \count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__3_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__3_n_0\ ); \count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__3_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__3_n_0\ ); \count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[1]_0\(1), I2 => \count_value_i_reg[1]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__3_n_0\ ); \count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__1_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__3_n_0\ ); \count_value_i[7]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => E(0), I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[0]_i_1__2_n_0\, Q => \^q\(0), S => \count_value_i_reg[0]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[1]_i_1__2_n_0\, Q => \^q\(1), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[2]_i_1__2_n_0\, Q => \^q\(2), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[3]_i_1__2_n_0\, Q => \^q\(3), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[4]_i_1__2_n_0\, Q => \^q\(4), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[5]_i_1__3_n_0\, Q => \^q\(5), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[6]_i_1__3_n_0\, Q => \^q\(6), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[7]_i_1__3_n_0\, Q => \^q\(7), R => \count_value_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); D : out STD_LOGIC_VECTOR ( 6 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__0_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair119"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__0_n_0\ ); \count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__0_n_0\ ); \count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__0_n_0\ ); \count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__0_n_0\ ); \count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__0_n_0\ ); \count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__0_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__0_n_0\ ); \count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__0_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__0_n_0\ ); \count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__0_n_0\ ); \count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__0_n_0\ ); \count_value_i[7]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__0_n_0\, Q => \^q\(0), S => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__0_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__0_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__0_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__0_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__0_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__0_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__0_n_0\, Q => \^q\(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(6), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(5), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(4), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(3), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(2), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(1), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(0), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => wr_pntr_plus1_pf_carry, CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\, DI(7) => '0', DI(6 downto 0) => \^q\(6 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\(0), S(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\, S(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\, S(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\, S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\, S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\, S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\, S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\, S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \count_value_i_reg[0]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__1_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair80"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"10EF" ) port map ( I0 => rd_en, I1 => \count_value_i_reg[1]_0\(0), I2 => \count_value_i_reg[1]_0\(1), I3 => \^q\(0), O => \count_value_i[0]_i_1__2_n_0\ ); \count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"02FFFD00" ) port map ( I0 => \count_value_i_reg[1]_0\(1), I1 => \count_value_i_reg[1]_0\(0), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__2_n_0\ ); \count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__2_n_0\ ); \count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__2_n_0\ ); \count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__2_n_0\ ); \count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__3_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__3_n_0\ ); \count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__3_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__3_n_0\ ); \count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AAA200000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[1]_0\(1), I2 => \count_value_i_reg[1]_0\(0), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__3_n_0\ ); \count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__1_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__3_n_0\ ); \count_value_i[7]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => E(0), I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[0]_i_1__2_n_0\, Q => \^q\(0), S => \count_value_i_reg[0]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[1]_i_1__2_n_0\, Q => \^q\(1), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[2]_i_1__2_n_0\, Q => \^q\(2), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[3]_i_1__2_n_0\, Q => \^q\(3), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[4]_i_1__2_n_0\, Q => \^q\(4), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[5]_i_1__3_n_0\, Q => \^q\(5), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[6]_i_1__3_n_0\, Q => \^q\(6), R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[7]_i_1__3_n_0\, Q => \^q\(7), R => \count_value_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); D : out STD_LOGIC_VECTOR ( 6 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2__0_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair85"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__0_n_0\ ); \count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__0_n_0\ ); \count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__0_n_0\ ); \count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__0_n_0\ ); \count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__0_n_0\ ); \count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__0_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__0_n_0\ ); \count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__0_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__0_n_0\ ); \count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__0_n_0\ ); \count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__0_n_0\ ); \count_value_i[7]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__0_n_0\, Q => \^q\(0), S => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__0_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__0_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__0_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__0_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__0_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__0_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__0_n_0\, Q => \^q\(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(6), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(5), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(4), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(3), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(2), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(1), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(0), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => wr_pntr_plus1_pf_carry, CI_TOP => '0', CO(7) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\(7), CO(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\, DI(7) => '0', DI(6 downto 0) => \^q\(6 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\(0), S(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\, S(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\, S(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\, S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\, S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\, S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\, S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\, S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair155"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair155"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair154"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair154"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1_n_0\ ); \count_value_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1_n_0\ ); \count_value_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1_n_0\ ); \count_value_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1_n_0\ ); \count_value_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1_n_0\ ); \count_value_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1_n_0\ ); \count_value_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2_n_0\ ); \count_value_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1_n_0\ ); \count_value_i[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1_n_0\, Q => \^q\(1), S => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1_n_0\, Q => \^q\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair121"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1_n_0\ ); \count_value_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1_n_0\ ); \count_value_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1_n_0\ ); \count_value_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1_n_0\ ); \count_value_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1_n_0\ ); \count_value_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1_n_0\ ); \count_value_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2_n_0\ ); \count_value_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1_n_0\ ); \count_value_i[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1_n_0\, Q => \^q\(1), S => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1_n_0\, Q => \^q\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44\ is port ( Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[6]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44\ is signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_2_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair87"; begin Q(7 downto 0) <= \^q\(7 downto 0); \count_value_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1_n_0\ ); \count_value_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1_n_0\ ); \count_value_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1_n_0\ ); \count_value_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1_n_0\ ); \count_value_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1_n_0\ ); \count_value_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1_n_0\ ); \count_value_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[6]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2_n_0\ ); \count_value_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[7]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1_n_0\ ); \count_value_i[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[7]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1_n_0\, Q => \^q\(1), S => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1_n_0\, Q => \^q\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); ram_rd_en_i : out STD_LOGIC; \reg_out_i_reg[7]\ : out STD_LOGIC; src_in_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[1]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); DI : in STD_LOGIC_VECTOR ( 7 downto 0 ); \grdc.rd_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[9]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_2__0_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_8_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_10_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_11_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_12_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_13_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_14_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_15_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_16_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_17_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[9]_i_5_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[9]_i_2_n_7\ : STD_LOGIC; signal \^ram_rd_en_i\ : STD_LOGIC; signal \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair247"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair244"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair244"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair241"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__3\ : label is "soft_lutpair241"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\ : label is "soft_lutpair245"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair242"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12\ : label is "soft_lutpair243"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair245"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\ : label is "soft_lutpair242"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\ : label is "soft_lutpair246"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\ : label is "soft_lutpair246"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\ : label is "soft_lutpair243"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair247"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[9]_i_2\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[9]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(9 downto 0) <= \^q\(9 downto 0); ram_rd_en_i <= \^ram_rd_en_i\; \count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"AABA5545" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => \^q\(0), O => \count_value_i[0]_i_1__4_n_0\ ); \count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"04FFFB00" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => \count_value_i_reg[0]_0\(1), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__3_n_0\ ); \count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__3_n_0\ ); \count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(2), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(3), O => \count_value_i[3]_i_1__3_n_0\ ); \count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__3_n_0\ ); \count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(2), I3 => \count_value_i[6]_i_2__3_n_0\, I4 => \^q\(5), O => \count_value_i[5]_i_1__3_n_0\ ); \count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \count_value_i[6]_i_2__3_n_0\, I1 => \^q\(2), I2 => \^q\(3), I3 => \^q\(4), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__3_n_0\ ); \count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AA8A00000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => \count_value_i_reg[0]_0\(1), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__3_n_0\ ); \count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"F708" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \count_value_i[9]_i_2__0_n_0\, I3 => \^q\(7), O => \count_value_i[7]_i_1__3_n_0\ ); \count_value_i[8]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"BFFF4000" ) port map ( I0 => \count_value_i[9]_i_2__0_n_0\, I1 => \^q\(5), I2 => \^q\(6), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__3_n_0\ ); \count_value_i[9]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF7FFF00008000" ) port map ( I0 => \^q\(8), I1 => \^q\(7), I2 => \^q\(6), I3 => \^q\(5), I4 => \count_value_i[9]_i_2__0_n_0\, I5 => \^q\(9), O => \count_value_i[9]_i_1__0_n_0\ ); \count_value_i[9]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^q\(0), I1 => \^ram_rd_en_i\, I2 => \^q\(1), I3 => \^q\(2), I4 => \^q\(3), I5 => \^q\(4), O => \count_value_i[9]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[0]_i_1__4_n_0\, Q => \^q\(0), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[1]_i_1__3_n_0\, Q => \^q\(1), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[2]_i_1__3_n_0\, Q => \^q\(2), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[3]_i_1__3_n_0\, Q => \^q\(3), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[4]_i_1__3_n_0\, Q => \^q\(4), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[5]_i_1__3_n_0\, Q => \^q\(5), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[6]_i_1__3_n_0\, Q => \^q\(6), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[7]_i_1__3_n_0\, Q => \^q\(7), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[8]_i_1__3_n_0\, Q => \^q\(8), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[9]_i_1__0_n_0\, Q => \^q\(9), R => \count_value_i_reg[9]_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(8), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(7), I3 => \^q\(9), O => src_in_bin(8) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \^q\(5), I1 => \^q\(3), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(4), I4 => \^q\(6), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFDD4D" ) port map ( I0 => \grdc.rd_data_count_i_reg[7]\(1), I1 => \^q\(1), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(0), I4 => \^q\(2), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^q\(8), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(7), O => src_in_bin(7) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(7), O => src_in_bin(6) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(3), I4 => \^q\(5), O => src_in_bin(5) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I2 => \^q\(3), I3 => \^q\(5), O => src_in_bin(4) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I2 => \^q\(3), O => src_in_bin(3) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"EFAAFFEF10550010" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(1), I4 => \grdc.rd_data_count_i_reg[7]\(1), I5 => \^q\(3), O => src_in_bin(2) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"9A55AA9A" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(1), I4 => \grdc.rd_data_count_i_reg[7]\(1), O => src_in_bin(1) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6696" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(0), O => src_in_bin(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"AABA5545" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => \^q\(0), O => \count_value_i_reg[7]_0\(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(7), O => \count_value_i_reg[7]_0\(7) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(6), O => \count_value_i_reg[7]_0\(6) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(5), O => \count_value_i_reg[7]_0\(5) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(4), O => \count_value_i_reg[7]_0\(4) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3), O => \count_value_i_reg[7]_0\(3) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2), O => \count_value_i_reg[7]_0\(2) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(1), O => \count_value_i_reg[7]_0\(1) ); \gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(1), I2 => \^q\(0), I3 => \gen_pf_ic_rc.ram_empty_i_reg\(0), I4 => \^q\(2), I5 => \gen_pf_ic_rc.ram_empty_i_reg\(2), O => \count_value_i_reg[1]_0\ ); \gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8200008200000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\, I1 => \gen_pf_ic_rc.ram_empty_i_reg\(7), I2 => \^q\(7), I3 => \^q\(8), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(8), I5 => \gen_pf_ic_rc.ram_empty_i_i_8_n_0\, O => \reg_out_i_reg[7]\ ); \gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(6), O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(4), I2 => \^q\(3), I3 => \gen_pf_ic_rc.ram_empty_i_reg\(3), I4 => \^q\(5), I5 => \gen_pf_ic_rc.ram_empty_i_reg\(5), O => \gen_pf_ic_rc.ram_empty_i_i_8_n_0\ ); \gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"00FB" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => \count_value_i_reg[0]_0\(1), I2 => rd_en, I3 => ram_empty_i, O => \^ram_rd_en_i\ ); \grdc.rd_data_count_i[7]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[9]_0\(6), I2 => \^q\(7), I3 => \grdc.rd_data_count_i_reg[9]_0\(7), O => \grdc.rd_data_count_i[7]_i_10_n_0\ ); \grdc.rd_data_count_i[7]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[9]_0\(5), I2 => \^q\(6), I3 => \grdc.rd_data_count_i_reg[9]_0\(6), O => \grdc.rd_data_count_i[7]_i_11_n_0\ ); \grdc.rd_data_count_i[7]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[9]_0\(4), I2 => \^q\(5), I3 => \grdc.rd_data_count_i_reg[9]_0\(5), O => \grdc.rd_data_count_i[7]_i_12_n_0\ ); \grdc.rd_data_count_i[7]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[9]_0\(3), I2 => \^q\(4), I3 => \grdc.rd_data_count_i_reg[9]_0\(4), O => \grdc.rd_data_count_i[7]_i_13_n_0\ ); \grdc.rd_data_count_i[7]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[9]_0\(2), I2 => \^q\(3), I3 => \grdc.rd_data_count_i_reg[9]_0\(3), O => \grdc.rd_data_count_i[7]_i_14_n_0\ ); \grdc.rd_data_count_i[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"2BD4D42B" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[9]_0\(1), I3 => \^q\(2), I4 => \grdc.rd_data_count_i_reg[9]_0\(2), O => \grdc.rd_data_count_i[7]_i_15_n_0\ ); \grdc.rd_data_count_i[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"D22D2DD2" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]_0\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(1), O => \grdc.rd_data_count_i[7]_i_16_n_0\ ); \grdc.rd_data_count_i[7]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]_0\(0), O => \grdc.rd_data_count_i[7]_i_17_n_0\ ); \grdc.rd_data_count_i[9]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[9]_0\(7), I2 => \^q\(8), I3 => \grdc.rd_data_count_i_reg[9]_0\(8), O => \grdc.rd_data_count_i[9]_i_5_n_0\ ); \grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CO(6) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\, CO(5) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\, CO(4) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\, CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_4\, CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_5\, CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_6\, CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => DI(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \grdc.rd_data_count_i[7]_i_10_n_0\, S(6) => \grdc.rd_data_count_i[7]_i_11_n_0\, S(5) => \grdc.rd_data_count_i[7]_i_12_n_0\, S(4) => \grdc.rd_data_count_i[7]_i_13_n_0\, S(3) => \grdc.rd_data_count_i[7]_i_14_n_0\, S(2) => \grdc.rd_data_count_i[7]_i_15_n_0\, S(1) => \grdc.rd_data_count_i[7]_i_16_n_0\, S(0) => \grdc.rd_data_count_i[7]_i_17_n_0\ ); \grdc.rd_data_count_i_reg[9]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED\(7 downto 1), CO(0) => \grdc.rd_data_count_i_reg[9]_i_2_n_7\, DI(7 downto 1) => B"0000000", DI(0) => \grdc.rd_data_count_i_reg[9]\(0), O(7 downto 2) => \NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED\(7 downto 2), O(1 downto 0) => D(8 downto 7), S(7 downto 2) => B"000000", S(1) => S(0), S(0) => \grdc.rd_data_count_i[9]_i_5_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); D : out STD_LOGIC_VECTOR ( 8 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gwdc.wr_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[9]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[9]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[9]_i_1_n_7\ : STD_LOGIC; signal \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair193"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair193"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair192"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair192"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1\ : label is "soft_lutpair191"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair191"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[9]_i_1\ : label is 35; begin Q(9 downto 0) <= \^q\(9 downto 0); \count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__1_n_0\ ); \count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__1_n_0\ ); \count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__1_n_0\ ); \count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__1_n_0\ ); \count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__1_n_0\ ); \count_value_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1_n_0\ ); \count_value_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1_n_0\ ); \count_value_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2_n_0\ ); \count_value_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[9]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1_n_0\ ); \count_value_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[9]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1_n_0\ ); \count_value_i[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(7), I1 => \^q\(5), I2 => \count_value_i[9]_i_2_n_0\, I3 => \^q\(6), I4 => \^q\(8), I5 => \^q\(9), O => \count_value_i[9]_i_1_n_0\ ); \count_value_i[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[9]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__1_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1_n_0\, Q => \^q\(8), R => wrst_busy ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[9]_i_1_n_0\, Q => \^q\(9), R => wrst_busy ); \gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gwdc.wr_data_count_i_reg[9]\(7), O => \gwdc.wr_data_count_i[7]_i_2_n_0\ ); \gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gwdc.wr_data_count_i_reg[9]\(6), O => \gwdc.wr_data_count_i[7]_i_3_n_0\ ); \gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gwdc.wr_data_count_i_reg[9]\(5), O => \gwdc.wr_data_count_i[7]_i_4_n_0\ ); \gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gwdc.wr_data_count_i_reg[9]\(4), O => \gwdc.wr_data_count_i[7]_i_5_n_0\ ); \gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gwdc.wr_data_count_i_reg[9]\(3), O => \gwdc.wr_data_count_i[7]_i_6_n_0\ ); \gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gwdc.wr_data_count_i_reg[9]\(2), O => \gwdc.wr_data_count_i[7]_i_7_n_0\ ); \gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gwdc.wr_data_count_i_reg[9]\(1), O => \gwdc.wr_data_count_i[7]_i_8_n_0\ ); \gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gwdc.wr_data_count_i_reg[9]\(0), O => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i[9]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(9), I1 => \gwdc.wr_data_count_i_reg[9]\(9), O => \gwdc.wr_data_count_i[9]_i_2_n_0\ ); \gwdc.wr_data_count_i[9]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gwdc.wr_data_count_i_reg[9]\(8), O => \gwdc.wr_data_count_i[9]_i_3_n_0\ ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '1', CI_TOP => '0', CO(7) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CO(6) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\, CO(5) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\, CO(4) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\, CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_4\, CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_5\, CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_6\, CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \gwdc.wr_data_count_i[7]_i_2_n_0\, S(6) => \gwdc.wr_data_count_i[7]_i_3_n_0\, S(5) => \gwdc.wr_data_count_i[7]_i_4_n_0\, S(4) => \gwdc.wr_data_count_i[7]_i_5_n_0\, S(3) => \gwdc.wr_data_count_i[7]_i_6_n_0\, S(2) => \gwdc.wr_data_count_i[7]_i_7_n_0\, S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i_reg[9]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\(7 downto 1), CO(0) => \gwdc.wr_data_count_i_reg[9]_i_1_n_7\, DI(7 downto 1) => B"0000000", DI(0) => \^q\(8), O(7 downto 2) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\(7 downto 2), O(1 downto 0) => D(8 downto 7), S(7 downto 2) => B"000000", S(1) => \gwdc.wr_data_count_i[9]_i_2_n_0\, S(0) => \gwdc.wr_data_count_i[9]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); D : out STD_LOGIC_VECTOR ( 8 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gwdc.wr_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2\ is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_7_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_8_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[7]_i_9_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[9]_i_2_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i[9]_i_3_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \gwdc.wr_data_count_i_reg[9]_i_1_n_7\ : STD_LOGIC; signal \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair253"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair253"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair252"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair252"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1\ : label is "soft_lutpair251"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair251"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[9]_i_1\ : label is 35; begin Q(9 downto 0) <= \^q\(9 downto 0); \count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__1_n_0\ ); \count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__1_n_0\ ); \count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__1_n_0\ ); \count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__1_n_0\ ); \count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__1_n_0\ ); \count_value_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1_n_0\ ); \count_value_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1_n_0\ ); \count_value_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2_n_0\ ); \count_value_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[9]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1_n_0\ ); \count_value_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[9]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1_n_0\ ); \count_value_i[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(7), I1 => \^q\(5), I2 => \count_value_i[9]_i_2_n_0\, I3 => \^q\(6), I4 => \^q\(8), I5 => \^q\(9), O => \count_value_i[9]_i_1_n_0\ ); \count_value_i[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[9]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__1_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1_n_0\, Q => \^q\(8), R => wrst_busy ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[9]_i_1_n_0\, Q => \^q\(9), R => wrst_busy ); \gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gwdc.wr_data_count_i_reg[9]\(7), O => \gwdc.wr_data_count_i[7]_i_2_n_0\ ); \gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gwdc.wr_data_count_i_reg[9]\(6), O => \gwdc.wr_data_count_i[7]_i_3_n_0\ ); \gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gwdc.wr_data_count_i_reg[9]\(5), O => \gwdc.wr_data_count_i[7]_i_4_n_0\ ); \gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gwdc.wr_data_count_i_reg[9]\(4), O => \gwdc.wr_data_count_i[7]_i_5_n_0\ ); \gwdc.wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gwdc.wr_data_count_i_reg[9]\(3), O => \gwdc.wr_data_count_i[7]_i_6_n_0\ ); \gwdc.wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gwdc.wr_data_count_i_reg[9]\(2), O => \gwdc.wr_data_count_i[7]_i_7_n_0\ ); \gwdc.wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gwdc.wr_data_count_i_reg[9]\(1), O => \gwdc.wr_data_count_i[7]_i_8_n_0\ ); \gwdc.wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gwdc.wr_data_count_i_reg[9]\(0), O => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i[9]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(9), I1 => \gwdc.wr_data_count_i_reg[9]\(9), O => \gwdc.wr_data_count_i[9]_i_2_n_0\ ); \gwdc.wr_data_count_i[9]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gwdc.wr_data_count_i_reg[9]\(8), O => \gwdc.wr_data_count_i[9]_i_3_n_0\ ); \gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '1', CI_TOP => '0', CO(7) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CO(6) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\, CO(5) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\, CO(4) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\, CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_4\, CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_5\, CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_6\, CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \gwdc.wr_data_count_i[7]_i_2_n_0\, S(6) => \gwdc.wr_data_count_i[7]_i_3_n_0\, S(5) => \gwdc.wr_data_count_i[7]_i_4_n_0\, S(4) => \gwdc.wr_data_count_i[7]_i_5_n_0\, S(3) => \gwdc.wr_data_count_i[7]_i_6_n_0\, S(2) => \gwdc.wr_data_count_i[7]_i_7_n_0\, S(1) => \gwdc.wr_data_count_i[7]_i_8_n_0\, S(0) => \gwdc.wr_data_count_i[7]_i_9_n_0\ ); \gwdc.wr_data_count_i_reg[9]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED\(7 downto 1), CO(0) => \gwdc.wr_data_count_i_reg[9]_i_1_n_7\, DI(7 downto 1) => B"0000000", DI(0) => \^q\(8), O(7 downto 2) => \NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED\(7 downto 2), O(1 downto 0) => D(8 downto 7), S(7 downto 2) => B"000000", S(1) => \gwdc.wr_data_count_i[9]_i_2_n_0\, S(0) => \gwdc.wr_data_count_i[9]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); ram_rd_en_i : out STD_LOGIC; \reg_out_i_reg[7]\ : out STD_LOGIC; src_in_bin : out STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[1]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); DI : in STD_LOGIC_VECTOR ( 7 downto 0 ); \grdc.rd_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[9]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9\ is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[9]_i_2__0_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_8_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_10_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_11_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_12_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_13_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_14_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_15_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_16_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_17_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[9]_i_5_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[9]_i_2_n_7\ : STD_LOGIC; signal \^ram_rd_en_i\ : STD_LOGIC; signal \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair187"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair184"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair184"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair181"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__3\ : label is "soft_lutpair181"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\ : label is "soft_lutpair185"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair182"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12\ : label is "soft_lutpair183"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair185"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\ : label is "soft_lutpair182"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\ : label is "soft_lutpair186"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\ : label is "soft_lutpair186"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\ : label is "soft_lutpair183"; attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair187"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[9]_i_2\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[9]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(9 downto 0) <= \^q\(9 downto 0); ram_rd_en_i <= \^ram_rd_en_i\; \count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"AABA5545" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => \^q\(0), O => \count_value_i[0]_i_1__4_n_0\ ); \count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"04FFFB00" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => \count_value_i_reg[0]_0\(1), I2 => rd_en, I3 => \^q\(0), I4 => \^q\(1), O => \count_value_i[1]_i_1__3_n_0\ ); \count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__3_n_0\ ); \count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(2), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(3), O => \count_value_i[3]_i_1__3_n_0\ ); \count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__3_n_0\ ); \count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(2), I3 => \count_value_i[6]_i_2__3_n_0\, I4 => \^q\(5), O => \count_value_i[5]_i_1__3_n_0\ ); \count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \count_value_i[6]_i_2__3_n_0\, I1 => \^q\(2), I2 => \^q\(3), I3 => \^q\(4), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__3_n_0\ ); \count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AA8A00000000" ) port map ( I0 => \^q\(1), I1 => \count_value_i_reg[0]_0\(0), I2 => \count_value_i_reg[0]_0\(1), I3 => rd_en, I4 => ram_empty_i, I5 => \^q\(0), O => \count_value_i[6]_i_2__3_n_0\ ); \count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"F708" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \count_value_i[9]_i_2__0_n_0\, I3 => \^q\(7), O => \count_value_i[7]_i_1__3_n_0\ ); \count_value_i[8]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"BFFF4000" ) port map ( I0 => \count_value_i[9]_i_2__0_n_0\, I1 => \^q\(5), I2 => \^q\(6), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__3_n_0\ ); \count_value_i[9]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF7FFF00008000" ) port map ( I0 => \^q\(8), I1 => \^q\(7), I2 => \^q\(6), I3 => \^q\(5), I4 => \count_value_i[9]_i_2__0_n_0\, I5 => \^q\(9), O => \count_value_i[9]_i_1__0_n_0\ ); \count_value_i[9]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^q\(0), I1 => \^ram_rd_en_i\, I2 => \^q\(1), I3 => \^q\(2), I4 => \^q\(3), I5 => \^q\(4), O => \count_value_i[9]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[0]_i_1__4_n_0\, Q => \^q\(0), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[1]_i_1__3_n_0\, Q => \^q\(1), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[2]_i_1__3_n_0\, Q => \^q\(2), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[3]_i_1__3_n_0\, Q => \^q\(3), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[4]_i_1__3_n_0\, Q => \^q\(4), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[5]_i_1__3_n_0\, Q => \^q\(5), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[6]_i_1__3_n_0\, Q => \^q\(6), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[7]_i_1__3_n_0\, Q => \^q\(7), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[8]_i_1__3_n_0\, Q => \^q\(8), R => \count_value_i_reg[9]_0\ ); \count_value_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => \^ram_rd_en_i\, D => \count_value_i[9]_i_1__0_n_0\, Q => \^q\(9), R => \count_value_i_reg[9]_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(8), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(7), I3 => \^q\(9), O => src_in_bin(8) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \^q\(5), I1 => \^q\(3), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(4), I4 => \^q\(6), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFDD4D" ) port map ( I0 => \grdc.rd_data_count_i_reg[7]\(1), I1 => \^q\(1), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(0), I4 => \^q\(2), O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^q\(8), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\, I2 => \^q\(7), O => src_in_bin(7) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(7), O => src_in_bin(6) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I3 => \^q\(3), I4 => \^q\(5), O => src_in_bin(5) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I2 => \^q\(3), I3 => \^q\(5), O => src_in_bin(4) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^q\(4), I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0\, I2 => \^q\(3), O => src_in_bin(3) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"EFAAFFEF10550010" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(1), I4 => \grdc.rd_data_count_i_reg[7]\(1), I5 => \^q\(3), O => src_in_bin(2) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"9A55AA9A" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(1), I4 => \grdc.rd_data_count_i_reg[7]\(1), O => src_in_bin(1) ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6696" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[7]\(0), I3 => \^q\(0), O => src_in_bin(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"AABA5545" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => \count_value_i_reg[0]_0\(1), I3 => \count_value_i_reg[0]_0\(0), I4 => \^q\(0), O => \count_value_i_reg[7]_0\(0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(7), O => \count_value_i_reg[7]_0\(7) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(6), O => \count_value_i_reg[7]_0\(6) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(5), O => \count_value_i_reg[7]_0\(5) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(4), O => \count_value_i_reg[7]_0\(4) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3), O => \count_value_i_reg[7]_0\(3) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2), O => \count_value_i_reg[7]_0\(2) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(1), O => \count_value_i_reg[7]_0\(1) ); \gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(1), I2 => \^q\(0), I3 => \gen_pf_ic_rc.ram_empty_i_reg\(0), I4 => \^q\(2), I5 => \gen_pf_ic_rc.ram_empty_i_reg\(2), O => \count_value_i_reg[1]_0\ ); \gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8200008200000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\, I1 => \gen_pf_ic_rc.ram_empty_i_reg\(7), I2 => \^q\(7), I3 => \^q\(8), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(8), I5 => \gen_pf_ic_rc.ram_empty_i_i_8_n_0\, O => \reg_out_i_reg[7]\ ); \gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(6), O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(4), I2 => \^q\(3), I3 => \gen_pf_ic_rc.ram_empty_i_reg\(3), I4 => \^q\(5), I5 => \gen_pf_ic_rc.ram_empty_i_reg\(5), O => \gen_pf_ic_rc.ram_empty_i_i_8_n_0\ ); \gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"00FB" ) port map ( I0 => \count_value_i_reg[0]_0\(0), I1 => \count_value_i_reg[0]_0\(1), I2 => rd_en, I3 => ram_empty_i, O => \^ram_rd_en_i\ ); \grdc.rd_data_count_i[7]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[9]_0\(6), I2 => \^q\(7), I3 => \grdc.rd_data_count_i_reg[9]_0\(7), O => \grdc.rd_data_count_i[7]_i_10_n_0\ ); \grdc.rd_data_count_i[7]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[9]_0\(5), I2 => \^q\(6), I3 => \grdc.rd_data_count_i_reg[9]_0\(6), O => \grdc.rd_data_count_i[7]_i_11_n_0\ ); \grdc.rd_data_count_i[7]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[9]_0\(4), I2 => \^q\(5), I3 => \grdc.rd_data_count_i_reg[9]_0\(5), O => \grdc.rd_data_count_i[7]_i_12_n_0\ ); \grdc.rd_data_count_i[7]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[9]_0\(3), I2 => \^q\(4), I3 => \grdc.rd_data_count_i_reg[9]_0\(4), O => \grdc.rd_data_count_i[7]_i_13_n_0\ ); \grdc.rd_data_count_i[7]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[9]_0\(2), I2 => \^q\(3), I3 => \grdc.rd_data_count_i_reg[9]_0\(3), O => \grdc.rd_data_count_i[7]_i_14_n_0\ ); \grdc.rd_data_count_i[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"2BD4D42B" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(1), I2 => \grdc.rd_data_count_i_reg[9]_0\(1), I3 => \^q\(2), I4 => \grdc.rd_data_count_i_reg[9]_0\(2), O => \grdc.rd_data_count_i[7]_i_15_n_0\ ); \grdc.rd_data_count_i[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"D22D2DD2" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]_0\(1), I3 => \grdc.rd_data_count_i_reg[7]\(1), I4 => \^q\(1), O => \grdc.rd_data_count_i[7]_i_16_n_0\ ); \grdc.rd_data_count_i[7]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^q\(0), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]_0\(0), O => \grdc.rd_data_count_i[7]_i_17_n_0\ ); \grdc.rd_data_count_i[9]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[9]_0\(7), I2 => \^q\(8), I3 => \grdc.rd_data_count_i_reg[9]_0\(8), O => \grdc.rd_data_count_i[9]_i_5_n_0\ ); \grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CO(6) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\, CO(5) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\, CO(4) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\, CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_4\, CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_5\, CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_6\, CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_7\, DI(7 downto 0) => DI(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7) => \grdc.rd_data_count_i[7]_i_10_n_0\, S(6) => \grdc.rd_data_count_i[7]_i_11_n_0\, S(5) => \grdc.rd_data_count_i[7]_i_12_n_0\, S(4) => \grdc.rd_data_count_i[7]_i_13_n_0\, S(3) => \grdc.rd_data_count_i[7]_i_14_n_0\, S(2) => \grdc.rd_data_count_i[7]_i_15_n_0\, S(1) => \grdc.rd_data_count_i[7]_i_16_n_0\, S(0) => \grdc.rd_data_count_i[7]_i_17_n_0\ ); \grdc.rd_data_count_i_reg[9]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED\(7 downto 1), CO(0) => \grdc.rd_data_count_i_reg[9]_i_2_n_7\, DI(7 downto 1) => B"0000000", DI(0) => \grdc.rd_data_count_i_reg[9]\(0), O(7 downto 2) => \NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED\(7 downto 2), O(1 downto 0) => D(8 downto 7), S(7 downto 2) => B"000000", S(1) => S(0), S(0) => \grdc.rd_data_count_i[9]_i_5_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4\ is port ( ram_empty_i0 : out STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4\ is signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[6]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[7]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair249"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair249"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair248"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__2\ : label is "soft_lutpair248"; begin \count_value_i[0]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"04FB" ) port map ( I0 => rd_en, I1 => Q(1), I2 => Q(0), I3 => \count_value_i_reg_n_0_[0]\, O => \count_value_i[0]_i_1__3_n_0\ ); \count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"04FFFB00" ) port map ( I0 => Q(0), I1 => Q(1), I2 => rd_en, I3 => \count_value_i_reg_n_0_[0]\, I4 => \count_value_i_reg_n_0_[1]\, O => \count_value_i[1]_i_1__2_n_0\ ); \count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[2]\, O => \count_value_i[2]_i_1__2_n_0\ ); \count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \count_value_i_reg_n_0_[2]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[0]\, I3 => \count_value_i_reg_n_0_[3]\, O => \count_value_i[3]_i_1__2_n_0\ ); \count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[2]\, I3 => \count_value_i_reg_n_0_[3]\, I4 => \count_value_i_reg_n_0_[4]\, O => \count_value_i[4]_i_1__2_n_0\ ); \count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \count_value_i_reg_n_0_[4]\, I1 => \count_value_i_reg_n_0_[3]\, I2 => \count_value_i_reg_n_0_[2]\, I3 => \count_value_i[6]_i_2__2_n_0\, I4 => \count_value_i_reg_n_0_[5]\, O => \count_value_i[5]_i_1__2_n_0\ ); \count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \count_value_i[6]_i_2__2_n_0\, I1 => \count_value_i_reg_n_0_[2]\, I2 => \count_value_i_reg_n_0_[3]\, I3 => \count_value_i_reg_n_0_[4]\, I4 => \count_value_i_reg_n_0_[5]\, I5 => \count_value_i_reg_n_0_[6]\, O => \count_value_i[6]_i_1__2_n_0\ ); \count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AA8A00000000" ) port map ( I0 => \count_value_i_reg_n_0_[1]\, I1 => Q(0), I2 => Q(1), I3 => rd_en, I4 => ram_empty_i, I5 => \count_value_i_reg_n_0_[0]\, O => \count_value_i[6]_i_2__2_n_0\ ); \count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F708" ) port map ( I0 => \count_value_i_reg_n_0_[6]\, I1 => \count_value_i_reg_n_0_[5]\, I2 => \count_value_i[8]_i_2__1_n_0\, I3 => \count_value_i_reg_n_0_[7]\, O => \count_value_i[7]_i_1__2_n_0\ ); \count_value_i[8]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"DFFF2000" ) port map ( I0 => \count_value_i_reg_n_0_[7]\, I1 => \count_value_i[8]_i_2__1_n_0\, I2 => \count_value_i_reg_n_0_[5]\, I3 => \count_value_i_reg_n_0_[6]\, I4 => \count_value_i_reg_n_0_[8]\, O => \count_value_i[8]_i_1__2_n_0\ ); \count_value_i[8]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => E(0), I2 => \count_value_i_reg_n_0_[1]\, I3 => \count_value_i_reg_n_0_[2]\, I4 => \count_value_i_reg_n_0_[3]\, I5 => \count_value_i_reg_n_0_[4]\, O => \count_value_i[8]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[0]_i_1__3_n_0\, Q => \count_value_i_reg_n_0_[0]\, S => \count_value_i_reg[0]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[1]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[1]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[2]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[2]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[3]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[3]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[4]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[4]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[5]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[5]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[6]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[6]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[7]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[7]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[8]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[8]\, R => \count_value_i_reg[0]_0\ ); \gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF800080008000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\, I1 => E(0), I2 => \gen_pf_ic_rc.ram_empty_i_i_3_n_0\, I3 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\, I4 => \gen_pf_ic_rc.ram_empty_i_reg\, I5 => \gen_pf_ic_rc.ram_empty_i_reg_0\, O => ram_empty_i0 ); \gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[7]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(7), I2 => \count_value_i_reg_n_0_[6]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(6), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(8), I5 => \count_value_i_reg_n_0_[8]\, O => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[1]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(1), I2 => \count_value_i_reg_n_0_[0]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(0), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(2), I5 => \count_value_i_reg_n_0_[2]\, O => \gen_pf_ic_rc.ram_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[4]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(4), I2 => \count_value_i_reg_n_0_[3]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(3), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(5), I5 => \count_value_i_reg_n_0_[5]\, O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10\ is port ( ram_empty_i0 : out STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \count_value_i_reg[0]_0\ : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10\ is signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[6]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[7]\ : STD_LOGIC; signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair189"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair189"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair188"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__2\ : label is "soft_lutpair188"; begin \count_value_i[0]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"04FB" ) port map ( I0 => rd_en, I1 => Q(1), I2 => Q(0), I3 => \count_value_i_reg_n_0_[0]\, O => \count_value_i[0]_i_1__3_n_0\ ); \count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"04FFFB00" ) port map ( I0 => Q(0), I1 => Q(1), I2 => rd_en, I3 => \count_value_i_reg_n_0_[0]\, I4 => \count_value_i_reg_n_0_[1]\, O => \count_value_i[1]_i_1__2_n_0\ ); \count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[2]\, O => \count_value_i[2]_i_1__2_n_0\ ); \count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \count_value_i_reg_n_0_[2]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[0]\, I3 => \count_value_i_reg_n_0_[3]\, O => \count_value_i[3]_i_1__2_n_0\ ); \count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => \count_value_i_reg_n_0_[1]\, I2 => \count_value_i_reg_n_0_[2]\, I3 => \count_value_i_reg_n_0_[3]\, I4 => \count_value_i_reg_n_0_[4]\, O => \count_value_i[4]_i_1__2_n_0\ ); \count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \count_value_i_reg_n_0_[4]\, I1 => \count_value_i_reg_n_0_[3]\, I2 => \count_value_i_reg_n_0_[2]\, I3 => \count_value_i[6]_i_2__2_n_0\, I4 => \count_value_i_reg_n_0_[5]\, O => \count_value_i[5]_i_1__2_n_0\ ); \count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \count_value_i[6]_i_2__2_n_0\, I1 => \count_value_i_reg_n_0_[2]\, I2 => \count_value_i_reg_n_0_[3]\, I3 => \count_value_i_reg_n_0_[4]\, I4 => \count_value_i_reg_n_0_[5]\, I5 => \count_value_i_reg_n_0_[6]\, O => \count_value_i[6]_i_1__2_n_0\ ); \count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AA8A00000000" ) port map ( I0 => \count_value_i_reg_n_0_[1]\, I1 => Q(0), I2 => Q(1), I3 => rd_en, I4 => ram_empty_i, I5 => \count_value_i_reg_n_0_[0]\, O => \count_value_i[6]_i_2__2_n_0\ ); \count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F708" ) port map ( I0 => \count_value_i_reg_n_0_[6]\, I1 => \count_value_i_reg_n_0_[5]\, I2 => \count_value_i[8]_i_2__1_n_0\, I3 => \count_value_i_reg_n_0_[7]\, O => \count_value_i[7]_i_1__2_n_0\ ); \count_value_i[8]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"DFFF2000" ) port map ( I0 => \count_value_i_reg_n_0_[7]\, I1 => \count_value_i[8]_i_2__1_n_0\, I2 => \count_value_i_reg_n_0_[5]\, I3 => \count_value_i_reg_n_0_[6]\, I4 => \count_value_i_reg_n_0_[8]\, O => \count_value_i[8]_i_1__2_n_0\ ); \count_value_i[8]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \count_value_i_reg_n_0_[0]\, I1 => E(0), I2 => \count_value_i_reg_n_0_[1]\, I3 => \count_value_i_reg_n_0_[2]\, I4 => \count_value_i_reg_n_0_[3]\, I5 => \count_value_i_reg_n_0_[4]\, O => \count_value_i[8]_i_2__1_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[0]_i_1__3_n_0\, Q => \count_value_i_reg_n_0_[0]\, S => \count_value_i_reg[0]_0\ ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[1]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[1]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[2]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[2]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[3]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[3]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[4]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[4]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[5]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[5]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[6]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[6]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[7]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[7]\, R => \count_value_i_reg[0]_0\ ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), D => \count_value_i[8]_i_1__2_n_0\, Q => \count_value_i_reg_n_0_[8]\, R => \count_value_i_reg[0]_0\ ); \gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF800080008000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\, I1 => E(0), I2 => \gen_pf_ic_rc.ram_empty_i_i_3_n_0\, I3 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\, I4 => \gen_pf_ic_rc.ram_empty_i_reg\, I5 => \gen_pf_ic_rc.ram_empty_i_reg_0\, O => ram_empty_i0 ); \gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[7]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(7), I2 => \count_value_i_reg_n_0_[6]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(6), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(8), I5 => \count_value_i_reg_n_0_[8]\, O => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[1]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(1), I2 => \count_value_i_reg_n_0_[0]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(0), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(2), I5 => \count_value_i_reg_n_0_[2]\, O => \gen_pf_ic_rc.ram_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \count_value_i_reg_n_0_[4]\, I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(4), I2 => \count_value_i_reg_n_0_[3]\, I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\(3), I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(5), I5 => \count_value_i_reg_n_0_[5]\, O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair196"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair196"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair195"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair195"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__0\ : label is "soft_lutpair194"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair194"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1\ : label is 35; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__0_n_0\ ); \count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__0_n_0\ ); \count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__0_n_0\ ); \count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__0_n_0\ ); \count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__0_n_0\ ); \count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__0_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__0_n_0\ ); \count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__0_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__0_n_0\ ); \count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__0_n_0\ ); \count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__0_n_0\ ); \count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__0_n_0\ ); \count_value_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__0_n_0\, Q => \^q\(0), S => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__0_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__0_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__0_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__0_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__0_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__0_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__0_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1__0_n_0\, Q => \^q\(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(7), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(6), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(5), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(4), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(3), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(2), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(1), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(0), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(8), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => wr_pntr_plus1_pf_carry, CI_TOP => '0', CO(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\, CO(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\(0), S(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\, S(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\, S(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\, S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\, S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\, S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\, S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\, S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair256"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair256"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair255"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair255"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__0\ : label is "soft_lutpair254"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair254"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1\ : label is 35; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1__0_n_0\ ); \count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1__0_n_0\ ); \count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1__0_n_0\ ); \count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1__0_n_0\ ); \count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1__0_n_0\ ); \count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__0_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__0_n_0\ ); \count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__0_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__0_n_0\ ); \count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__0_n_0\ ); \count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__0_n_0\ ); \count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__0_n_0\ ); \count_value_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1__0_n_0\, Q => \^q\(0), S => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1__0_n_0\, Q => \^q\(1), R => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1__0_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1__0_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1__0_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__0_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__0_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__0_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1__0_n_0\, Q => \^q\(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(7), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(6), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(5), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(4), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(3), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(2), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(1), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(0), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(8), O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => wr_pntr_plus1_pf_carry, CI_TOP => '0', CO(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\, CO(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7\, DI(7 downto 0) => \^q\(7 downto 0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED\(0), S(7) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\, S(6) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\, S(5) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\, S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\, S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0\, S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0\, S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0\, S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair259"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair259"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair258"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair258"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair257"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__1\ : label is "soft_lutpair257"; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1_n_0\ ); \count_value_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1_n_0\ ); \count_value_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1_n_0\ ); \count_value_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1_n_0\ ); \count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__1_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__1_n_0\ ); \count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__1_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__1_n_0\ ); \count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__1_n_0\ ); \count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__1_n_0\ ); \count_value_i[8]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__1_n_0\ ); \count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1_n_0\, Q => \^q\(1), S => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1__1_n_0\, Q => \^q\(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[5]_0\ : in STD_LOGIC; wrst_busy : in STD_LOGIC; rst_d1 : in STD_LOGIC; wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14\ : entity is "xpm_counter_updn"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC; signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC; signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair199"; attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair199"; attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair198"; attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair198"; attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair197"; attribute SOFT_HLUTNM of \count_value_i[8]_i_1__1\ : label is "soft_lutpair197"; begin Q(8 downto 0) <= \^q\(8 downto 0); \count_value_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => \count_value_i[0]_i_1_n_0\ ); \count_value_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => \count_value_i[1]_i_1_n_0\ ); \count_value_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => \count_value_i[2]_i_1_n_0\ ); \count_value_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => \count_value_i[3]_i_1_n_0\ ); \count_value_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => \count_value_i[4]_i_1_n_0\ ); \count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(3), I1 => \count_value_i[6]_i_2__1_n_0\, I2 => \^q\(2), I3 => \^q\(4), I4 => \^q\(5), O => \count_value_i[5]_i_1__1_n_0\ ); \count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \count_value_i[6]_i_2__1_n_0\, I3 => \^q\(3), I4 => \^q\(5), I5 => \^q\(6), O => \count_value_i[6]_i_1__1_n_0\ ); \count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000800000000" ) port map ( I0 => \^q\(1), I1 => wr_en, I2 => \count_value_i_reg[5]_0\, I3 => wrst_busy, I4 => rst_d1, I5 => \^q\(0), O => \count_value_i[6]_i_2__1_n_0\ ); \count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(5), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(6), I3 => \^q\(7), O => \count_value_i[7]_i_1__1_n_0\ ); \count_value_i[8]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(6), I1 => \count_value_i[8]_i_2__0_n_0\, I2 => \^q\(5), I3 => \^q\(7), I4 => \^q\(8), O => \count_value_i[8]_i_1__1_n_0\ ); \count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(0), I3 => wr_pntr_plus1_pf_carry, I4 => \^q\(1), I5 => \^q\(3), O => \count_value_i[8]_i_2__0_n_0\ ); \count_value_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[0]_i_1_n_0\, Q => \^q\(0), R => wrst_busy ); \count_value_i_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[1]_i_1_n_0\, Q => \^q\(1), S => wrst_busy ); \count_value_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[2]_i_1_n_0\, Q => \^q\(2), R => wrst_busy ); \count_value_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[3]_i_1_n_0\, Q => \^q\(3), R => wrst_busy ); \count_value_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[4]_i_1_n_0\, Q => \^q\(4), R => wrst_busy ); \count_value_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[5]_i_1__1_n_0\, Q => \^q\(5), R => wrst_busy ); \count_value_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[6]_i_1__1_n_0\, Q => \^q\(6), R => wrst_busy ); \count_value_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[7]_i_1__1_n_0\, Q => \^q\(7), R => wrst_busy ); \count_value_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => wr_pntr_plus1_pf_carry, D => \count_value_i[8]_i_1__1_n_0\, Q => \^q\(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is port ( rst_d1 : out STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : out STD_LOGIC; clr_full : out STD_LOGIC; overflow_i0 : out STD_LOGIC; wrst_busy : in STD_LOGIC; wr_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ : in STD_LOGIC; prog_full : in STD_LOGIC; wr_en : in STD_LOGIC; rst : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is signal \^clr_full\ : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\ : label is "soft_lutpair250"; attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair250"; begin clr_full <= \^clr_full\; rst_d1 <= \^rst_d1\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => wrst_busy, Q => \^rst_d1\, R => '0' ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rst, I1 => \^rst_d1\, I2 => wrst_busy, O => \^clr_full\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00FF00E0000000E0" ) port map ( I0 => Q(0), I1 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\, I2 => Q(1), I3 => \^clr_full\, I4 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I5 => prog_full, O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ ); \gof.overflow_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE00" ) port map ( I0 => \^rst_d1\, I1 => wrst_busy, I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I3 => wr_en, O => overflow_i0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 is port ( rst_d1 : out STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : out STD_LOGIC; clr_full : out STD_LOGIC; overflow_i0 : out STD_LOGIC; wrst_busy : in STD_LOGIC; wr_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ : in STD_LOGIC; prog_full : in STD_LOGIC; wr_en : in STD_LOGIC; rst : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 : entity is "xpm_fifo_reg_bit"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 is signal \^clr_full\ : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\ : label is "soft_lutpair190"; attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair190"; begin clr_full <= \^clr_full\; rst_d1 <= \^rst_d1\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => wrst_busy, Q => \^rst_d1\, R => '0' ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rst, I1 => \^rst_d1\, I2 => wrst_busy, O => \^clr_full\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00FF00E0000000E0" ) port map ( I0 => Q(0), I1 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\, I2 => Q(1), I3 => \^clr_full\, I4 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I5 => prog_full, O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ ); \gof.overflow_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE00" ) port map ( I0 => \^rst_d1\, I1 => wrst_busy, I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I3 => wr_en, O => overflow_i0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 is port ( rst_d1 : out STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : out STD_LOGIC; overflow_i0 : out STD_LOGIC; wrst_busy : in STD_LOGIC; wr_clk : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ : in STD_LOGIC; prog_full : in STD_LOGIC; wr_en : in STD_LOGIC; rst : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 : entity is "xpm_fifo_reg_bit"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 is signal clr_full : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\ : label is "soft_lutpair148"; attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair148"; begin rst_d1 <= \^rst_d1\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => wrst_busy, Q => \^rst_d1\, R => '0' ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0F0E000E" ) port map ( I0 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\, I1 => Q(0), I2 => clr_full, I3 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I4 => prog_full, O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rst, I1 => \^rst_d1\, I2 => wrst_busy, O => clr_full ); \gof.overflow_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE00" ) port map ( I0 => \^rst_d1\, I1 => wrst_busy, I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I3 => wr_en, O => overflow_i0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 is port ( rst_d1 : out STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : out STD_LOGIC; overflow_i0 : out STD_LOGIC; wrst_busy : in STD_LOGIC; wr_clk : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ : in STD_LOGIC; prog_full : in STD_LOGIC; wr_en : in STD_LOGIC; rst : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 : entity is "xpm_fifo_reg_bit"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 is signal clr_full : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair115"; begin rst_d1 <= \^rst_d1\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => wrst_busy, Q => \^rst_d1\, R => '0' ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0F0E000E" ) port map ( I0 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\, I1 => Q(0), I2 => clr_full, I3 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I4 => prog_full, O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rst, I1 => \^rst_d1\, I2 => wrst_busy, O => clr_full ); \gof.overflow_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE00" ) port map ( I0 => \^rst_d1\, I1 => wrst_busy, I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I3 => wr_en, O => overflow_i0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 is port ( rst_d1 : out STD_LOGIC; \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : out STD_LOGIC; overflow_i0 : out STD_LOGIC; wrst_busy : in STD_LOGIC; wr_clk : in STD_LOGIC; \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ : in STD_LOGIC; prog_full : in STD_LOGIC; wr_en : in STD_LOGIC; rst : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 : entity is "xpm_fifo_reg_bit"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 is signal clr_full : STD_LOGIC; signal \^rst_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair81"; begin rst_d1 <= \^rst_d1\; d_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => wrst_busy, Q => \^rst_d1\, R => '0' ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0F0E000E" ) port map ( I0 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\, I1 => Q(0), I2 => clr_full, I3 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I4 => prog_full, O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rst, I1 => \^rst_d1\, I2 => wrst_busy, O => clr_full ); \gof.overflow_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE00" ) port map ( I0 => \^rst_d1\, I1 => wrst_busy, I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\, I3 => wr_en, O => overflow_i0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec is port ( \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); d_out_reg : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; rst_d1 : in STD_LOGIC; rst : in STD_LOGIC; wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec is signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC; signal going_full0 : STD_LOGIC; signal leaving_full : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EAEA00EA" ) port map ( I0 => leaving_full, I1 => going_full0, I2 => wr_pntr_plus1_pf_carry, I3 => rst_d1, I4 => rst, O => d_out_reg ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => Q(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => Q(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\, O => leaving_full ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\, O => going_full0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => Q(3), I2 => Q(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => Q(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => Q(0), I2 => Q(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => Q(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 is port ( ram_empty_i0 : out STD_LOGIC; \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \reg_out_i_reg[0]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 : entity is "xpm_fifo_reg_vec"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 is signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC; signal going_empty0 : STD_LOGIC; signal leaving_empty : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00FD0000" ) port map ( I0 => Q(1), I1 => Q(0), I2 => rd_en, I3 => ram_empty_i, I4 => going_empty0, I5 => leaving_empty, O => ram_empty_i0 ); \gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg_0\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\, O => going_empty0 ); \gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\, O => leaving_empty ); \gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => \reg_out_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 is port ( \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); d_out_reg : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; rst_d1 : in STD_LOGIC; rst : in STD_LOGIC; wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 : entity is "xpm_fifo_reg_vec"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 is signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC; signal going_full0 : STD_LOGIC; signal leaving_full : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EAEA00EA" ) port map ( I0 => leaving_full, I1 => going_full0, I2 => wr_pntr_plus1_pf_carry, I3 => rst_d1, I4 => rst, O => d_out_reg ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => Q(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => Q(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\, O => leaving_full ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\, O => going_full0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => Q(3), I2 => Q(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => Q(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => Q(0), I2 => Q(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => Q(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 is port ( ram_empty_i0 : out STD_LOGIC; \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \reg_out_i_reg[0]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 : entity is "xpm_fifo_reg_vec"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 is signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC; signal going_empty0 : STD_LOGIC; signal leaving_empty : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00FD0000" ) port map ( I0 => Q(1), I1 => Q(0), I2 => rd_en, I3 => ram_empty_i, I4 => going_empty0, I5 => leaving_empty, O => ram_empty_i0 ); \gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg_0\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\, O => going_empty0 ); \gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\, O => leaving_empty ); \gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => \reg_out_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 is port ( \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); d_out_reg : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_pntr_plus1_pf_carry : in STD_LOGIC; rst_d1 : in STD_LOGIC; rst : in STD_LOGIC; wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 : entity is "xpm_fifo_reg_vec"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 is signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC; signal going_full0 : STD_LOGIC; signal leaving_full : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EAEA00EA" ) port map ( I0 => leaving_full, I1 => going_full0, I2 => wr_pntr_plus1_pf_carry, I3 => rst_d1, I4 => rst, O => d_out_reg ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => Q(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => Q(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\, O => leaving_full ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\, I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\, O => going_full0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => Q(3), I2 => Q(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => Q(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => Q(0), I2 => Q(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => Q(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 is port ( ram_empty_i0 : out STD_LOGIC; \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \reg_out_i_reg[0]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 : entity is "xpm_fifo_reg_vec"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 is signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC; signal going_empty0 : STD_LOGIC; signal leaving_empty : STD_LOGIC; signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0); \gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00FD0000" ) port map ( I0 => Q(1), I1 => Q(0), I2 => rd_en, I3 => ram_empty_i, I4 => going_empty0, I5 => leaving_empty, O => ram_empty_i0 ); \gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg_0\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\, O => going_empty0 ); \gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000000000" ) port map ( I0 => \gen_pf_ic_rc.ram_empty_i_reg\(7), I1 => \^reg_out_i_reg[7]_0\(7), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(6), I3 => \^reg_out_i_reg[7]_0\(6), I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\, I5 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\, O => leaving_empty ); \gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(3), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(5), I3 => \^reg_out_i_reg[7]_0\(5), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(4), I5 => \^reg_out_i_reg[7]_0\(4), O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ ); \gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^reg_out_i_reg[7]_0\(0), I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0), I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2), I3 => \^reg_out_i_reg[7]_0\(2), I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1), I5 => \^reg_out_i_reg[7]_0\(1), O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(0), Q => \^reg_out_i_reg[7]_0\(0), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(1), Q => \^reg_out_i_reg[7]_0\(1), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(2), Q => \^reg_out_i_reg[7]_0\(2), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(3), Q => \^reg_out_i_reg[7]_0\(3), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(4), Q => \^reg_out_i_reg[7]_0\(4), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(5), Q => \^reg_out_i_reg[7]_0\(5), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(6), Q => \^reg_out_i_reg[7]_0\(6), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(7), Q => \^reg_out_i_reg[7]_0\(7), R => \reg_out_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[0]_0\ : out STD_LOGIC; wr_pntr_plus1_pf_carry : in STD_LOGIC; \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); clr_full : in STD_LOGIC; wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\ : STD_LOGIC; signal going_full : STD_LOGIC; begin Q(8 downto 0) <= \^q\(8 downto 0); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\, I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\, I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\, I3 => going_full, I4 => clr_full, O => \reg_out_i_reg[0]_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2), I3 => \^q\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1), I5 => \^q\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(8), I3 => \^q\(8), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7), I5 => \^q\(7), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5), I3 => \^q\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4), I5 => \^q\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\, I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\, I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\, I3 => wr_pntr_plus1_pf_carry, O => going_full ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(5), I3 => \^q\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(4), I5 => \^q\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(6), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(8), I3 => \^q\(8), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(7), I5 => \^q\(7), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(2), I3 => \^q\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(1), I5 => \^q\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => \^q\(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => \^q\(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => \^q\(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => \^q\(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => \^q\(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => \^q\(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => \^q\(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => \^q\(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => \^q\(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 8 downto 0 ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); DI : in STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 7 downto 0 ); \reg_out_i_reg[0]_0\ : in STD_LOGIC; \reg_out_i_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(8 downto 0) <= \^q\(8 downto 0); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \^q\(0), CI_TOP => '0', CO(7) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\, CO(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\, DI(7 downto 1) => \^q\(7 downto 1), DI(0) => DI(0), O(7 downto 0) => D(7 downto 0), S(7 downto 0) => S(7 downto 0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(8), S(7 downto 1) => B"0000000", S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(0), Q => \^q\(0), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(1), Q => \^q\(1), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(2), Q => \^q\(2), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(3), Q => \^q\(3), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(4), Q => \^q\(4), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(5), Q => \^q\(5), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(6), Q => \^q\(6), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(7), Q => \^q\(7), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(8), Q => \^q\(8), R => \reg_out_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16\ is begin \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => Q(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => Q(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => Q(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => Q(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => Q(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => Q(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => Q(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => Q(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => Q(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18\ is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); DI : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 6 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); \reg_out_i_reg[8]_0\ : in STD_LOGIC; \reg_out_i_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \grdc.rd_data_count_i[7]_i_14_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[8]_i_2\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[8]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(8 downto 0) <= \^q\(8 downto 0); \grdc.rd_data_count_i[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"718E8E71" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), I4 => \^q\(2), O => \grdc.rd_data_count_i[7]_i_14_n_0\ ); \grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[7]_0\(5), O => \grdc.rd_data_count_i[7]_i_2_n_0\ ); \grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[7]_0\(4), O => \grdc.rd_data_count_i[7]_i_3_n_0\ ); \grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[7]_0\(3), O => \grdc.rd_data_count_i[7]_i_4_n_0\ ); \grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[7]_0\(2), O => \grdc.rd_data_count_i[7]_i_5_n_0\ ); \grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]_0\(1), O => \grdc.rd_data_count_i[7]_i_6_n_0\ ); \grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CO(6) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\, CO(5) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\, CO(4) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\, CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_4\, CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_5\, CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_6\, CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_7\, DI(7) => \grdc.rd_data_count_i[7]_i_2_n_0\, DI(6) => \grdc.rd_data_count_i[7]_i_3_n_0\, DI(5) => \grdc.rd_data_count_i[7]_i_4_n_0\, DI(4) => \grdc.rd_data_count_i[7]_i_5_n_0\, DI(3) => \grdc.rd_data_count_i[7]_i_6_n_0\, DI(2 downto 1) => DI(1 downto 0), DI(0) => \^q\(0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7 downto 3) => S(6 downto 2), S(2) => \grdc.rd_data_count_i[7]_i_14_n_0\, S(1 downto 0) => S(1 downto 0) ); \grdc.rd_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \grdc.rd_data_count_i_reg[8]\(0) ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(0), Q => \^q\(0), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(1), Q => \^q\(1), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(2), Q => \^q\(2), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(3), Q => \^q\(3), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(4), Q => \^q\(4), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(5), Q => \^q\(5), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(6), Q => \^q\(6), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(7), Q => \^q\(7), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(8), Q => \^q\(8), R => \reg_out_i_reg[8]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24\ is begin \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => Q(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => Q(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => Q(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => Q(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => Q(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => Q(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => Q(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => Q(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => Q(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26\ is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); DI : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 6 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); \reg_out_i_reg[8]_0\ : in STD_LOGIC; \reg_out_i_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \grdc.rd_data_count_i[7]_i_14_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[8]_i_2\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[8]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(8 downto 0) <= \^q\(8 downto 0); \grdc.rd_data_count_i[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"718E8E71" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), I4 => \^q\(2), O => \grdc.rd_data_count_i[7]_i_14_n_0\ ); \grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[7]_0\(5), O => \grdc.rd_data_count_i[7]_i_2_n_0\ ); \grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[7]_0\(4), O => \grdc.rd_data_count_i[7]_i_3_n_0\ ); \grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[7]_0\(3), O => \grdc.rd_data_count_i[7]_i_4_n_0\ ); \grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[7]_0\(2), O => \grdc.rd_data_count_i[7]_i_5_n_0\ ); \grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]_0\(1), O => \grdc.rd_data_count_i[7]_i_6_n_0\ ); \grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CO(6) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\, CO(5) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\, CO(4) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\, CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_4\, CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_5\, CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_6\, CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_7\, DI(7) => \grdc.rd_data_count_i[7]_i_2_n_0\, DI(6) => \grdc.rd_data_count_i[7]_i_3_n_0\, DI(5) => \grdc.rd_data_count_i[7]_i_4_n_0\, DI(4) => \grdc.rd_data_count_i[7]_i_5_n_0\, DI(3) => \grdc.rd_data_count_i[7]_i_6_n_0\, DI(2 downto 1) => DI(1 downto 0), DI(0) => \^q\(0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7 downto 3) => S(6 downto 2), S(2) => \grdc.rd_data_count_i[7]_i_14_n_0\, S(1 downto 0) => S(1 downto 0) ); \grdc.rd_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \grdc.rd_data_count_i_reg[8]\(0) ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(0), Q => \^q\(0), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(1), Q => \^q\(1), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(2), Q => \^q\(2), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(3), Q => \^q\(3), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(4), Q => \^q\(4), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(5), Q => \^q\(5), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(6), Q => \^q\(6), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(7), Q => \^q\(7), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(8), Q => \^q\(8), R => \reg_out_i_reg[8]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35\ is begin \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => Q(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => Q(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => Q(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => Q(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => Q(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => Q(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => Q(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => Q(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => Q(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37\ is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); DI : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 6 downto 0 ); \grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); \reg_out_i_reg[8]_0\ : in STD_LOGIC; \reg_out_i_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \grdc.rd_data_count_i[7]_i_14_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_2_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_3_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_4_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_5_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i[7]_i_6_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_4\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_5\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_6\ : STD_LOGIC; signal \grdc.rd_data_count_i_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[8]_i_2\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[8]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(8 downto 0) <= \^q\(8 downto 0); \grdc.rd_data_count_i[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"718E8E71" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[7]_0\(0), I3 => \grdc.rd_data_count_i_reg[7]_0\(1), I4 => \^q\(2), O => \grdc.rd_data_count_i[7]_i_14_n_0\ ); \grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[7]_0\(5), O => \grdc.rd_data_count_i[7]_i_2_n_0\ ); \grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[7]_0\(4), O => \grdc.rd_data_count_i[7]_i_3_n_0\ ); \grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[7]_0\(3), O => \grdc.rd_data_count_i[7]_i_4_n_0\ ); \grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[7]_0\(2), O => \grdc.rd_data_count_i[7]_i_5_n_0\ ); \grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[7]_0\(1), O => \grdc.rd_data_count_i[7]_i_6_n_0\ ); \grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CO(6) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\, CO(5) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\, CO(4) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\, CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_4\, CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_5\, CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_6\, CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_7\, DI(7) => \grdc.rd_data_count_i[7]_i_2_n_0\, DI(6) => \grdc.rd_data_count_i[7]_i_3_n_0\, DI(5) => \grdc.rd_data_count_i[7]_i_4_n_0\, DI(4) => \grdc.rd_data_count_i[7]_i_5_n_0\, DI(3) => \grdc.rd_data_count_i[7]_i_6_n_0\, DI(2 downto 1) => DI(1 downto 0), DI(0) => \^q\(0), O(7 downto 1) => D(6 downto 0), O(0) => \NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED\(0), S(7 downto 3) => S(6 downto 2), S(2) => \grdc.rd_data_count_i[7]_i_14_n_0\, S(1 downto 0) => S(1 downto 0) ); \grdc.rd_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\(7 downto 1), O(0) => D(7), S(7 downto 1) => B"0000000", S(0) => \grdc.rd_data_count_i_reg[8]\(0) ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(0), Q => \^q\(0), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(1), Q => \^q\(1), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(2), Q => \^q\(2), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(3), Q => \^q\(3), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(4), Q => \^q\(4), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(5), Q => \^q\(5), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(6), Q => \^q\(6), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(7), Q => \^q\(7), R => \reg_out_i_reg[8]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_1\(8), Q => \^q\(8), R => \reg_out_i_reg[8]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[0]_0\ : out STD_LOGIC; wr_pntr_plus1_pf_carry : in STD_LOGIC; \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); clr_full : in STD_LOGIC; wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 8 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\ : STD_LOGIC; signal going_full : STD_LOGIC; begin Q(8 downto 0) <= \^q\(8 downto 0); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\, I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\, I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\, I3 => going_full, I4 => clr_full, O => \reg_out_i_reg[0]_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2), I3 => \^q\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1), I5 => \^q\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(8), I3 => \^q\(8), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7), I5 => \^q\(7), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5), I3 => \^q\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4), I5 => \^q\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\, I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\, I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\, I3 => wr_pntr_plus1_pf_carry, O => going_full ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(3), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(3), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(5), I3 => \^q\(5), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(4), I5 => \^q\(4), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(6), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(6), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(8), I3 => \^q\(8), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(7), I5 => \^q\(7), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0\ ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(0), I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(0), I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(2), I3 => \^q\(2), I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(1), I5 => \^q\(1), O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => \^q\(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => \^q\(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => \^q\(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => \^q\(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => \^q\(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => \^q\(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => \^q\(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => \^q\(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => \^q\(8), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6\ is port ( Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); D : out STD_LOGIC_VECTOR ( 8 downto 0 ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); DI : in STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 7 downto 0 ); \reg_out_i_reg[0]_0\ : in STD_LOGIC; \reg_out_i_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\ : STD_LOGIC; signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\ : label is 35; attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(8 downto 0) <= \^q\(8 downto 0); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\(0), O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \^q\(0), CI_TOP => '0', CO(7) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\, CO(6) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\, CO(5) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\, CO(4) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\, CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4\, CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5\, CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6\, CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7\, DI(7 downto 1) => \^q\(7 downto 1), DI(0) => DI(0), O(7 downto 0) => D(7 downto 0), S(7 downto 0) => S(7 downto 0) ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0\, CI_TOP => '0', CO(7 downto 0) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED\(7 downto 0), DI(7 downto 0) => B"00000000", O(7 downto 1) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED\(7 downto 1), O(0) => D(8), S(7 downto 1) => B"0000000", S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0\ ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(0), Q => \^q\(0), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(1), Q => \^q\(1), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(2), Q => \^q\(2), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(3), Q => \^q\(3), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(4), Q => \^q\(4), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(5), Q => \^q\(5), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(6), Q => \^q\(6), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(7), Q => \^q\(7), R => \reg_out_i_reg[0]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \reg_out_i_reg[8]_0\(8), Q => \^q\(8), R => \reg_out_i_reg[0]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1\ is begin \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => Q(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => Q(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => Q(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => Q(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => Q(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => Q(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => Q(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => Q(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => Q(8), R => wrst_busy ); \reg_out_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(9), Q => Q(9), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1\ is port ( DI : out STD_LOGIC_VECTOR ( 5 downto 0 ); Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[9]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 9 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \reg_out_i_reg_n_0_[9]\ : STD_LOGIC; begin Q(8 downto 0) <= \^q\(8 downto 0); \grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[9]\(5), O => DI(5) ); \grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[9]\(4), O => DI(4) ); \grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[9]\(3), O => DI(3) ); \grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[9]\(2), O => DI(2) ); \grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[9]\(1), O => DI(1) ); \grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"8E" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]\(0), O => DI(0) ); \grdc.rd_data_count_i[9]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[9]\(6), O => \reg_out_i_reg[7]_0\(0) ); \grdc.rd_data_count_i[9]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => \^q\(8), I1 => \grdc.rd_data_count_i_reg[9]\(7), I2 => \grdc.rd_data_count_i_reg[9]\(8), I3 => \reg_out_i_reg_n_0_[9]\, O => S(0) ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(0), Q => \^q\(0), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(1), Q => \^q\(1), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(2), Q => \^q\(2), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(3), Q => \^q\(3), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(4), Q => \^q\(4), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(5), Q => \^q\(5), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(6), Q => \^q\(6), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(7), Q => \^q\(7), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(8), Q => \^q\(8), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(9), Q => \reg_out_i_reg_n_0_[9]\, R => \reg_out_i_reg[9]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5\ is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); wrst_busy : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5\ is begin \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(0), Q => Q(0), R => wrst_busy ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(1), Q => Q(1), R => wrst_busy ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(2), Q => Q(2), R => wrst_busy ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(3), Q => Q(3), R => wrst_busy ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(4), Q => Q(4), R => wrst_busy ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(5), Q => Q(5), R => wrst_busy ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(6), Q => Q(6), R => wrst_busy ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(7), Q => Q(7), R => wrst_busy ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(8), Q => Q(8), R => wrst_busy ); \reg_out_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => D(9), Q => Q(9), R => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7\ is port ( DI : out STD_LOGIC_VECTOR ( 5 downto 0 ); Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grdc.rd_data_count_i_reg[9]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); \reg_out_i_reg[9]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 9 downto 0 ); rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7\ : entity is "xpm_fifo_reg_vec"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \reg_out_i_reg_n_0_[9]\ : STD_LOGIC; begin Q(8 downto 0) <= \^q\(8 downto 0); \grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(6), I1 => \grdc.rd_data_count_i_reg[9]\(5), O => DI(5) ); \grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(5), I1 => \grdc.rd_data_count_i_reg[9]\(4), O => DI(4) ); \grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(4), I1 => \grdc.rd_data_count_i_reg[9]\(3), O => DI(3) ); \grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(3), I1 => \grdc.rd_data_count_i_reg[9]\(2), O => DI(2) ); \grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(2), I1 => \grdc.rd_data_count_i_reg[9]\(1), O => DI(1) ); \grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"8E" ) port map ( I0 => \^q\(1), I1 => \grdc.rd_data_count_i_reg[7]\(0), I2 => \grdc.rd_data_count_i_reg[9]\(0), O => DI(0) ); \grdc.rd_data_count_i[9]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(7), I1 => \grdc.rd_data_count_i_reg[9]\(6), O => \reg_out_i_reg[7]_0\(0) ); \grdc.rd_data_count_i[9]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => \^q\(8), I1 => \grdc.rd_data_count_i_reg[9]\(7), I2 => \grdc.rd_data_count_i_reg[9]\(8), I3 => \reg_out_i_reg_n_0_[9]\, O => S(0) ); \reg_out_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(0), Q => \^q\(0), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(1), Q => \^q\(1), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(2), Q => \^q\(2), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(3), Q => \^q\(3), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(4), Q => \^q\(4), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(5), Q => \^q\(5), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(6), Q => \^q\(6), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(7), Q => \^q\(7), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(8), Q => \^q\(8), R => \reg_out_i_reg[9]_0\ ); \reg_out_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => D(9), Q => \reg_out_i_reg_n_0_[9]\, R => \reg_out_i_reg[9]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is port ( sleep : in STD_LOGIC; clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 7 downto 0 ); dina : in STD_LOGIC_VECTOR ( 49 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; douta : out STD_LOGIC_VECTOR ( 49 downto 0 ); sbiterra : out STD_LOGIC; dbiterra : out STD_LOGIC; clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 49 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; doutb : out STD_LOGIC_VECTOR ( 49 downto 0 ); sbiterrb : out STD_LOGIC; dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute ECC_MODE : integer; attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 12800; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute VERSION : integer; attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 50; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1; attribute XPM_MODULE : string; attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "soft"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 52; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 52; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is signal \\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 18 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.ADDRESS_END\ : integer; attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d50"; attribute \MEM.PORTA.DATA_LSB\ : integer; attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.DATA_MSB\ : integer; attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.ADDRESS_END\ : integer; attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d50"; attribute \MEM.PORTB.DATA_LSB\ : integer; attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.DATA_MSB\ : integer; attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is ""; attribute RDADDR_COLLISION_HWCONFIG : string; attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "DELAYED_WRITE"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 12800; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP"; attribute ram_addr_begin : integer; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_addr_end : integer; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute ram_offset : integer; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_begin : integer; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_end : integer; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; begin dbiterra <= \\; dbiterrb <= \\; douta(49) <= \\; douta(48) <= \\; douta(47) <= \\; douta(46) <= \\; douta(45) <= \\; douta(44) <= \\; douta(43) <= \\; douta(42) <= \\; douta(41) <= \\; douta(40) <= \\; douta(39) <= \\; douta(38) <= \\; douta(37) <= \\; douta(36) <= \\; douta(35) <= \\; douta(34) <= \\; douta(33) <= \\; douta(32) <= \\; douta(31) <= \\; douta(30) <= \\; douta(29) <= \\; douta(28) <= \\; douta(27) <= \\; douta(26) <= \\; douta(25) <= \\; douta(24) <= \\; douta(23) <= \\; douta(22) <= \\; douta(21) <= \\; douta(20) <= \\; douta(19) <= \\; douta(18) <= \\; douta(17) <= \\; douta(16) <= \\; douta(15) <= \\; douta(14) <= \\; douta(13) <= \\; douta(12) <= \\; douta(11) <= \\; douta(10) <= \\; douta(9) <= \\; douta(8) <= \\; douta(7) <= \\; douta(6) <= \\; douta(5) <= \\; douta(4) <= \\; douta(3) <= \\; douta(2) <= \\; douta(1) <= \\; douta(0) <= \\; sbiterra <= \\; sbiterrb <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB36E2 generic map( CASCADE_ORDER_A => "NONE", CASCADE_ORDER_B => "NONE", CLOCK_DOMAINS => "INDEPENDENT", DOA_REG => 1, DOB_REG => 1, ENADDRENA => "FALSE", ENADDRENB => "FALSE", EN_ECC_PIPE => "FALSE", EN_ECC_READ => "FALSE", EN_ECC_WRITE => "FALSE", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RDADDRCHANGEA => "FALSE", RDADDRCHANGEB => "FALSE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SLEEP_ASYNC => "TRUE", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( ADDRARDADDR(14) => '0', ADDRARDADDR(13 downto 6) => addrb(7 downto 0), ADDRARDADDR(5 downto 0) => B"111111", ADDRBWRADDR(14) => '0', ADDRBWRADDR(13 downto 6) => addra(7 downto 0), ADDRBWRADDR(5 downto 0) => B"111111", ADDRENA => '0', ADDRENB => '0', CASDIMUXA => '0', CASDIMUXB => '0', CASDINA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\(31 downto 0), CASDINB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\(31 downto 0), CASDINPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\(3 downto 0), CASDINPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\(3 downto 0), CASDOMUXA => '0', CASDOMUXB => '0', CASDOMUXEN_A => '1', CASDOMUXEN_B => '1', CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\(31 downto 0), CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\(31 downto 0), CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\(3 downto 0), CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\(3 downto 0), CASINDBITERR => '0', CASINSBITERR => '0', CASOREGIMUXA => '0', CASOREGIMUXB => '0', CASOREGIMUXEN_A => '1', CASOREGIMUXEN_B => '1', CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\, CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\, CLKARDCLK => clkb, CLKBWRCLK => clka, DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\, DINADIN(31 downto 0) => dina(31 downto 0), DINBDIN(31 downto 18) => B"11111111111111", DINBDIN(17 downto 0) => dina(49 downto 32), DINPADINP(3 downto 0) => B"1111", DINPBDINP(3 downto 0) => B"1111", DOUTADOUT(31 downto 0) => doutb(31 downto 0), DOUTBDOUT(31 downto 18) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\(31 downto 18), DOUTBDOUT(17 downto 0) => doutb(49 downto 32), DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\(3 downto 0), DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0), ECCPIPECE => '1', ENARDEN => enb, ENBWREN => ena, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => regceb, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => rstb, RSTREGB => '0', SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\, SLEEP => '0', WEA(3 downto 0) => B"0000", WEBWE(7) => ena, WEBWE(6) => ena, WEBWE(5) => ena, WEBWE(4) => ena, WEBWE(3) => ena, WEBWE(2) => ena, WEBWE(1) => ena, WEBWE(0) => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ is port ( sleep : in STD_LOGIC; clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 7 downto 0 ); dina : in STD_LOGIC_VECTOR ( 49 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; douta : out STD_LOGIC_VECTOR ( 49 downto 0 ); sbiterra : out STD_LOGIC; dbiterra : out STD_LOGIC; clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 49 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; doutb : out STD_LOGIC_VECTOR ( 49 downto 0 ); sbiterrb : out STD_LOGIC; dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 12800; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "xpm_memory_base"; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "SYNC"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 50; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 1; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is "soft"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 52; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ : entity is 52; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ is signal \\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 18 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.ADDRESS_END\ : integer; attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d50"; attribute \MEM.PORTA.DATA_LSB\ : integer; attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.DATA_MSB\ : integer; attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.ADDRESS_END\ : integer; attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d50"; attribute \MEM.PORTB.DATA_LSB\ : integer; attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.DATA_MSB\ : integer; attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is ""; attribute RDADDR_COLLISION_HWCONFIG : string; attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "DELAYED_WRITE"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 12800; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP"; attribute ram_addr_begin : integer; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_addr_end : integer; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute ram_offset : integer; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_begin : integer; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_end : integer; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 49; begin dbiterra <= \\; dbiterrb <= \\; douta(49) <= \\; douta(48) <= \\; douta(47) <= \\; douta(46) <= \\; douta(45) <= \\; douta(44) <= \\; douta(43) <= \\; douta(42) <= \\; douta(41) <= \\; douta(40) <= \\; douta(39) <= \\; douta(38) <= \\; douta(37) <= \\; douta(36) <= \\; douta(35) <= \\; douta(34) <= \\; douta(33) <= \\; douta(32) <= \\; douta(31) <= \\; douta(30) <= \\; douta(29) <= \\; douta(28) <= \\; douta(27) <= \\; douta(26) <= \\; douta(25) <= \\; douta(24) <= \\; douta(23) <= \\; douta(22) <= \\; douta(21) <= \\; douta(20) <= \\; douta(19) <= \\; douta(18) <= \\; douta(17) <= \\; douta(16) <= \\; douta(15) <= \\; douta(14) <= \\; douta(13) <= \\; douta(12) <= \\; douta(11) <= \\; douta(10) <= \\; douta(9) <= \\; douta(8) <= \\; douta(7) <= \\; douta(6) <= \\; douta(5) <= \\; douta(4) <= \\; douta(3) <= \\; douta(2) <= \\; douta(1) <= \\; douta(0) <= \\; sbiterra <= \\; sbiterrb <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB36E2 generic map( CASCADE_ORDER_A => "NONE", CASCADE_ORDER_B => "NONE", CLOCK_DOMAINS => "INDEPENDENT", DOA_REG => 1, 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RDADDRCHANGEA => "FALSE", RDADDRCHANGEB => "FALSE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SLEEP_ASYNC => "TRUE", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( ADDRARDADDR(14) => '0', ADDRARDADDR(13 downto 6) => addrb(7 downto 0), ADDRARDADDR(5 downto 0) => B"111111", ADDRBWRADDR(14) => '0', ADDRBWRADDR(13 downto 6) => addra(7 downto 0), ADDRBWRADDR(5 downto 0) => B"111111", ADDRENA => '0', ADDRENB => '0', CASDIMUXA => '0', CASDIMUXB => '0', CASDINA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\(31 downto 0), CASDINB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\(31 downto 0), CASDINPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\(3 downto 0), CASDINPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\(3 downto 0), CASDOMUXA => '0', CASDOMUXB => '0', CASDOMUXEN_A => '1', CASDOMUXEN_B => '1', CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\(31 downto 0), CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\(31 downto 0), CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\(3 downto 0), CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\(3 downto 0), CASINDBITERR => '0', CASINSBITERR => '0', CASOREGIMUXA => '0', CASOREGIMUXB => '0', CASOREGIMUXEN_A => '1', CASOREGIMUXEN_B => '1', CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\, CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\, CLKARDCLK => clkb, CLKBWRCLK => clka, DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\, DINADIN(31 downto 0) => dina(31 downto 0), DINBDIN(31 downto 18) => B"11111111111111", DINBDIN(17 downto 0) => dina(49 downto 32), DINPADINP(3 downto 0) => B"1111", DINPBDINP(3 downto 0) => B"1111", DOUTADOUT(31 downto 0) => doutb(31 downto 0), DOUTBDOUT(31 downto 18) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\(31 downto 18), DOUTBDOUT(17 downto 0) => doutb(49 downto 32), DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\(3 downto 0), DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0), ECCPIPECE => '1', ENARDEN => enb, ENBWREN => ena, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => regceb, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => rstb, RSTREGB => '0', SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\, SLEEP => '0', WEA(3 downto 0) => B"0000", WEBWE(7) => ena, WEBWE(6) => ena, WEBWE(5) => ena, WEBWE(4) => ena, WEBWE(3) => ena, WEBWE(2) => ena, WEBWE(1) => ena, WEBWE(0) => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ is port ( sleep : in STD_LOGIC; clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 8 downto 0 ); dina : in STD_LOGIC_VECTOR ( 40 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; douta : out STD_LOGIC_VECTOR ( 40 downto 0 ); sbiterra : out STD_LOGIC; dbiterra : out STD_LOGIC; clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 8 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 40 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; doutb : out STD_LOGIC_VECTOR ( 40 downto 0 ); sbiterrb : out STD_LOGIC; dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 20992; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "xpm_memory_base"; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 512; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 9; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "SYNC"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 41; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 1; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is "soft"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 44; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ : entity is 44; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ is signal \\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 9 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.ADDRESS_END\ : integer; attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d41"; attribute \MEM.PORTA.DATA_LSB\ : integer; attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.DATA_MSB\ : integer; attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.ADDRESS_END\ : integer; attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d41"; attribute \MEM.PORTB.DATA_LSB\ : integer; attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.DATA_MSB\ : integer; attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is ""; attribute RDADDR_COLLISION_HWCONFIG : string; attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "DELAYED_WRITE"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 20992; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP"; attribute ram_addr_begin : integer; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_addr_end : integer; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute ram_offset : integer; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_begin : integer; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_end : integer; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; begin dbiterra <= \\; dbiterrb <= \\; douta(40) <= \\; douta(39) <= \\; douta(38) <= \\; douta(37) <= \\; douta(36) <= \\; douta(35) <= \\; douta(34) <= \\; douta(33) <= \\; douta(32) <= \\; douta(31) <= \\; douta(30) <= \\; douta(29) <= \\; douta(28) <= \\; douta(27) <= \\; douta(26) <= \\; douta(25) <= \\; douta(24) <= \\; douta(23) <= \\; douta(22) <= \\; douta(21) <= \\; douta(20) <= \\; douta(19) <= \\; douta(18) <= \\; douta(17) <= \\; douta(16) <= \\; douta(15) <= \\; douta(14) <= \\; douta(13) <= \\; douta(12) <= \\; douta(11) <= \\; douta(10) <= \\; douta(9) <= \\; douta(8) <= \\; douta(7) <= \\; douta(6) <= \\; douta(5) <= \\; douta(4) <= \\; douta(3) <= \\; douta(2) <= \\; douta(1) <= \\; douta(0) <= \\; sbiterra <= \\; sbiterrb <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB36E2 generic map( CASCADE_ORDER_A => "NONE", CASCADE_ORDER_B => "NONE", CLOCK_DOMAINS => "INDEPENDENT", DOA_REG => 1, DOB_REG => 1, ENADDRENA => "FALSE", ENADDRENB => "FALSE", EN_ECC_PIPE => "FALSE", EN_ECC_READ => "FALSE", EN_ECC_WRITE => "FALSE", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RDADDRCHANGEA => "FALSE", RDADDRCHANGEB => "FALSE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SLEEP_ASYNC => "TRUE", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( ADDRARDADDR(14 downto 6) => addrb(8 downto 0), ADDRARDADDR(5 downto 0) => B"111111", ADDRBWRADDR(14 downto 6) => addra(8 downto 0), ADDRBWRADDR(5 downto 0) => B"111111", ADDRENA => '0', ADDRENB => '0', CASDIMUXA => '0', CASDIMUXB => '0', CASDINA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\(31 downto 0), CASDINB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\(31 downto 0), CASDINPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\(3 downto 0), CASDINPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\(3 downto 0), CASDOMUXA => '0', CASDOMUXB => '0', CASDOMUXEN_A => '1', CASDOMUXEN_B => '1', CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\(31 downto 0), CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\(31 downto 0), CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\(3 downto 0), CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\(3 downto 0), CASINDBITERR => '0', CASINSBITERR => '0', CASOREGIMUXA => '0', CASOREGIMUXB => '0', CASOREGIMUXEN_A => '1', CASOREGIMUXEN_B => '1', CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\, CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\, CLKARDCLK => clkb, CLKBWRCLK => clka, DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\, DINADIN(31 downto 0) => dina(31 downto 0), DINBDIN(31 downto 9) => B"11111111111111111111111", DINBDIN(8 downto 0) => dina(40 downto 32), DINPADINP(3 downto 0) => B"1111", DINPBDINP(3 downto 0) => B"1111", DOUTADOUT(31 downto 0) => doutb(31 downto 0), DOUTBDOUT(31 downto 9) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\(31 downto 9), DOUTBDOUT(8 downto 0) => doutb(40 downto 32), DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\(3 downto 0), DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0), ECCPIPECE => '1', ENARDEN => enb, ENBWREN => ena, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => regceb, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => rstb, RSTREGB => '0', SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\, SLEEP => '0', WEA(3 downto 0) => B"0000", WEBWE(7) => ena, WEBWE(6) => ena, WEBWE(5) => ena, WEBWE(4) => ena, WEBWE(3) => ena, WEBWE(2) => ena, WEBWE(1) => ena, WEBWE(0) => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ is port ( sleep : in STD_LOGIC; clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 8 downto 0 ); dina : in STD_LOGIC_VECTOR ( 40 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; douta : out STD_LOGIC_VECTOR ( 40 downto 0 ); sbiterra : out STD_LOGIC; dbiterra : out STD_LOGIC; clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 8 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 40 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; doutb : out STD_LOGIC_VECTOR ( 40 downto 0 ); sbiterrb : out STD_LOGIC; dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 20992; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "xpm_memory_base"; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 512; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 9; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "SYNC"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 41; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 1; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is "soft"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 44; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ : entity is 44; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ is signal \\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 9 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.ADDRESS_END\ : integer; attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d41"; attribute \MEM.PORTA.DATA_LSB\ : integer; attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTA.DATA_MSB\ : integer; attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer; attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.ADDRESS_END\ : integer; attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d41"; attribute \MEM.PORTB.DATA_LSB\ : integer; attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute \MEM.PORTB.DATA_MSB\ : integer; attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is ""; attribute RDADDR_COLLISION_HWCONFIG : string; attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "DELAYED_WRITE"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 20992; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP"; attribute ram_addr_begin : integer; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_addr_end : integer; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 511; attribute ram_offset : integer; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_begin : integer; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0; attribute ram_slice_end : integer; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 40; begin dbiterra <= \\; dbiterrb <= \\; douta(40) <= \\; douta(39) <= \\; douta(38) <= \\; douta(37) <= \\; douta(36) <= \\; douta(35) <= \\; douta(34) <= \\; douta(33) <= \\; douta(32) <= \\; douta(31) <= \\; douta(30) <= \\; douta(29) <= \\; douta(28) <= \\; douta(27) <= \\; douta(26) <= \\; douta(25) <= \\; douta(24) <= \\; douta(23) <= \\; douta(22) <= \\; douta(21) <= \\; douta(20) <= \\; douta(19) <= \\; douta(18) <= \\; douta(17) <= \\; douta(16) <= \\; douta(15) <= \\; douta(14) <= \\; douta(13) <= \\; douta(12) <= \\; douta(11) <= \\; douta(10) <= \\; douta(9) <= \\; douta(8) <= \\; douta(7) <= \\; douta(6) <= \\; douta(5) <= \\; douta(4) <= \\; douta(3) <= \\; douta(2) <= \\; douta(1) <= \\; douta(0) <= \\; sbiterra <= \\; sbiterrb <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB36E2 generic map( CASCADE_ORDER_A => "NONE", CASCADE_ORDER_B => "NONE", CLOCK_DOMAINS => "INDEPENDENT", DOA_REG => 1, DOB_REG => 1, ENADDRENA => "FALSE", ENADDRENB => "FALSE", EN_ECC_PIPE => "FALSE", EN_ECC_READ => "FALSE", EN_ECC_WRITE => "FALSE", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RDADDRCHANGEA => "FALSE", RDADDRCHANGEB => "FALSE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SLEEP_ASYNC => "TRUE", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( ADDRARDADDR(14 downto 6) => addrb(8 downto 0), ADDRARDADDR(5 downto 0) => B"111111", ADDRBWRADDR(14 downto 6) => addra(8 downto 0), ADDRBWRADDR(5 downto 0) => B"111111", ADDRENA => '0', ADDRENB => '0', CASDIMUXA => '0', CASDIMUXB => '0', CASDINA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED\(31 downto 0), CASDINB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED\(31 downto 0), CASDINPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED\(3 downto 0), CASDINPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED\(3 downto 0), CASDOMUXA => '0', CASDOMUXB => '0', CASDOMUXEN_A => '1', CASDOMUXEN_B => '1', CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED\(31 downto 0), CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED\(31 downto 0), CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED\(3 downto 0), CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED\(3 downto 0), CASINDBITERR => '0', CASINSBITERR => '0', CASOREGIMUXA => '0', CASOREGIMUXB => '0', CASOREGIMUXEN_A => '1', CASOREGIMUXEN_B => '1', CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED\, CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED\, CLKARDCLK => clkb, CLKBWRCLK => clka, DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED\, DINADIN(31 downto 0) => dina(31 downto 0), DINBDIN(31 downto 9) => B"11111111111111111111111", DINBDIN(8 downto 0) => dina(40 downto 32), DINPADINP(3 downto 0) => B"1111", DINPBDINP(3 downto 0) => B"1111", DOUTADOUT(31 downto 0) => doutb(31 downto 0), DOUTBDOUT(31 downto 9) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED\(31 downto 9), DOUTBDOUT(8 downto 0) => doutb(40 downto 32), DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED\(3 downto 0), DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0), ECCPIPECE => '1', ENARDEN => enb, ENBWREN => ena, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => regceb, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => rstb, RSTREGB => '0', SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED\, SLEEP => '0', WEA(3 downto 0) => B"0000", WEBWE(7) => ena, WEBWE(6) => ena, WEBWE(5) => ena, WEBWE(4) => ena, WEBWE(3) => ena, WEBWE(2) => ena, WEBWE(1) => ena, WEBWE(0) => ena ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ is port ( sleep : in STD_LOGIC; clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 7 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterra : in STD_LOGIC; injectdbiterra : in STD_LOGIC; douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); sbiterra : out STD_LOGIC; dbiterra : out STD_LOGIC; clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterrb : in STD_LOGIC; injectdbiterrb : in STD_LOGIC; doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); sbiterrb : out STD_LOGIC; dbiterrb : out STD_LOGIC ); attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 2048; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "xpm_memory_base"; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "distributed"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "yes"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "SYNC"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 1; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "TRUE"; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is "soft"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ : entity is 8; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ is signal \\ : STD_LOGIC; signal \gen_rd_b.doutb_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0\ : STD_LOGIC; signal \gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6\ : STD_LOGIC; signal \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0\ : STD_LOGIC; signal select_piped_1_reg_pipe_5_reg_n_0 : STD_LOGIC; signal select_piped_3_reg_pipe_6_reg_n_0 : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED\ : STD_LOGIC; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is ""; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 2048; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE : string; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is "RAM_SDP"; attribute dram_emb_xdc : string; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is "yes"; attribute ram_addr_begin : integer; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 0; attribute ram_addr_end : integer; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 63; attribute ram_offset : integer; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 0; attribute ram_slice_begin : integer; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 0; attribute ram_slice_end : integer; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\ : label is 6; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 0; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 63; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 7; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\ : label is 7; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is ""; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 128; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 191; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 0; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\ : label is 6; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 128; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 191; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 7; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\ : label is 7; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is ""; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 192; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 255; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 0; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\ : label is 6; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 192; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 255; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 7; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\ : label is 7; attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is ""; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 64; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 127; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 0; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\ : label is 6; attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 2048; attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is "gen_wr_a.gen_word_narrow.mem"; attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is "RAM_SDP"; attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is "yes"; attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 64; attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 127; attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 0; attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 7; attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\ : label is 7; begin dbiterra <= \\; dbiterrb <= \\; douta(7) <= \\; douta(6) <= \\; douta(5) <= \\; douta(4) <= \\; douta(3) <= \\; douta(2) <= \\; douta(1) <= \\; douta(0) <= \\; sbiterra <= \\; sbiterrb <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_rd_b.doutb_reg_reg_pipe_10_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6\, Q => \gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_11_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5\, Q => \gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_12_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5\, Q => \gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_13_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5\, Q => \gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_14_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5\, Q => \gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_15_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4\, Q => \gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_16_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4\, Q => \gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_17_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4\, Q => \gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_18_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4\, Q => \gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_19_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3\, Q => \gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_1_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_20_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3\, Q => \gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_21_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3\, Q => \gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_22_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3\, Q => \gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_23_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2\, Q => \gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_24_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2\, Q => \gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_25_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2\, Q => \gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_26_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2\, Q => \gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_27_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1\, Q => \gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_28_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1\, Q => \gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_29_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1\, Q => \gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_2_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_30_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1\, Q => \gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_31_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_32_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_33_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_34_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_3_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_4_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0\, Q => \gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_7_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6\, Q => \gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_8_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6\, Q => \gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0\, R => '0' ); \gen_rd_b.doutb_reg_reg_pipe_9_reg\: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6\, Q => \gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0\, R => '0' ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0\, O => \gen_rd_b.doutb_reg\(0) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0\, O => \gen_rd_b.doutb_reg\(1) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0\, O => \gen_rd_b.doutb_reg\(2) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0\, O => \gen_rd_b.doutb_reg\(3) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0\, O => \gen_rd_b.doutb_reg\(4) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0\, O => \gen_rd_b.doutb_reg\(5) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0\, O => \gen_rd_b.doutb_reg\(6) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0\, I1 => \gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0\, I2 => select_piped_3_reg_pipe_6_reg_n_0, I3 => \gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0\, I4 => select_piped_1_reg_pipe_5_reg_n_0, I5 => \gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0\, O => \gen_rd_b.doutb_reg\(7) ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(0), Q => doutb(0), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(1), Q => doutb(1), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(2), Q => doutb(2), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(3), Q => doutb(3), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(4), Q => doutb(4), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(5), Q => doutb(5), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(6), Q => doutb(6), R => rstb ); \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => regceb, D => \gen_rd_b.doutb_reg\(7), Q => doutb(7), R => rstb ); \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6\: unisim.vcomponents.RAM64M8 generic map( INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000", INIT_E => X"0000000000000000", INIT_F => X"0000000000000000", INIT_G => X"0000000000000000", INIT_H => X"0000000000000000" ) port map ( ADDRA(5 downto 0) => addrb(5 downto 0), ADDRB(5 downto 0) => addrb(5 downto 0), ADDRC(5 downto 0) => addrb(5 downto 0), ADDRD(5 downto 0) => addrb(5 downto 0), ADDRE(5 downto 0) => addrb(5 downto 0), ADDRF(5 downto 0) => addrb(5 downto 0), ADDRG(5 downto 0) => addrb(5 downto 0), ADDRH(5 downto 0) => addra(5 downto 0), DIA => dina(0), DIB => dina(1), DIC => dina(2), DID => dina(3), DIE => dina(4), DIF => dina(5), DIG => dina(6), DIH => '0', DOA => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0\, DOB => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1\, DOC => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2\, DOD => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3\, DOE => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4\, DOF => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5\, DOG => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6\, DOH => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => ena, I1 => addra(6), I2 => addra(7), O => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7\: unisim.vcomponents.RAM64X1D generic map( INIT => X"0000000000000000" ) port map ( A0 => addra(0), A1 => addra(1), A2 => addra(2), A3 => addra(3), A4 => addra(4), A5 => addra(5), D => dina(7), DPO => \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0\, DPRA0 => addrb(0), DPRA1 => addrb(1), DPRA2 => addrb(2), DPRA3 => addrb(3), DPRA4 => addrb(4), DPRA5 => addrb(5), SPO => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6\: unisim.vcomponents.RAM64M8 generic map( INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000", INIT_E => X"0000000000000000", INIT_F => X"0000000000000000", INIT_G => X"0000000000000000", INIT_H => X"0000000000000000" ) port map ( ADDRA(5 downto 0) => addrb(5 downto 0), ADDRB(5 downto 0) => addrb(5 downto 0), ADDRC(5 downto 0) => addrb(5 downto 0), ADDRD(5 downto 0) => addrb(5 downto 0), ADDRE(5 downto 0) => addrb(5 downto 0), ADDRF(5 downto 0) => addrb(5 downto 0), ADDRG(5 downto 0) => addrb(5 downto 0), ADDRH(5 downto 0) => addra(5 downto 0), DIA => dina(0), DIB => dina(1), DIC => dina(2), DID => dina(3), DIE => dina(4), DIF => dina(5), DIG => dina(6), DIH => '0', DOA => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0\, DOB => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1\, DOC => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2\, DOD => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3\, DOE => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4\, DOF => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5\, DOG => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6\, DOH => \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => addra(6), I1 => addra(7), I2 => ena, O => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7\: unisim.vcomponents.RAM64X1D generic map( INIT => X"0000000000000000" ) port map ( A0 => addra(0), A1 => addra(1), A2 => addra(2), A3 => addra(3), A4 => addra(4), A5 => addra(5), D => dina(7), DPO => \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0\, DPRA0 => addrb(0), DPRA1 => addrb(1), DPRA2 => addrb(2), DPRA3 => addrb(3), DPRA4 => addrb(4), DPRA5 => addrb(5), SPO => \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6\: unisim.vcomponents.RAM64M8 generic map( INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000", INIT_E => X"0000000000000000", INIT_F => X"0000000000000000", INIT_G => X"0000000000000000", INIT_H => X"0000000000000000" ) port map ( ADDRA(5 downto 0) => addrb(5 downto 0), ADDRB(5 downto 0) => addrb(5 downto 0), ADDRC(5 downto 0) => addrb(5 downto 0), ADDRD(5 downto 0) => addrb(5 downto 0), ADDRE(5 downto 0) => addrb(5 downto 0), ADDRF(5 downto 0) => addrb(5 downto 0), ADDRG(5 downto 0) => addrb(5 downto 0), ADDRH(5 downto 0) => addra(5 downto 0), DIA => dina(0), DIB => dina(1), DIC => dina(2), DID => dina(3), DIE => dina(4), DIF => dina(5), DIG => dina(6), DIH => '0', DOA => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0\, DOB => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1\, DOC => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2\, DOD => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3\, DOE => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4\, DOF => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5\, DOG => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6\, DOH => \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => ena, I1 => addra(6), I2 => addra(7), O => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7\: unisim.vcomponents.RAM64X1D generic map( INIT => X"0000000000000000" ) port map ( A0 => addra(0), A1 => addra(1), A2 => addra(2), A3 => addra(3), A4 => addra(4), A5 => addra(5), D => dina(7), DPO => \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0\, DPRA0 => addrb(0), DPRA1 => addrb(1), DPRA2 => addrb(2), DPRA3 => addrb(3), DPRA4 => addrb(4), DPRA5 => addrb(5), SPO => \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6\: unisim.vcomponents.RAM64M8 generic map( INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000", INIT_E => X"0000000000000000", INIT_F => X"0000000000000000", INIT_G => X"0000000000000000", INIT_H => X"0000000000000000" ) port map ( ADDRA(5 downto 0) => addrb(5 downto 0), ADDRB(5 downto 0) => addrb(5 downto 0), ADDRC(5 downto 0) => addrb(5 downto 0), ADDRD(5 downto 0) => addrb(5 downto 0), ADDRE(5 downto 0) => addrb(5 downto 0), ADDRF(5 downto 0) => addrb(5 downto 0), ADDRG(5 downto 0) => addrb(5 downto 0), ADDRH(5 downto 0) => addra(5 downto 0), DIA => dina(0), DIB => dina(1), DIC => dina(2), DID => dina(3), DIE => dina(4), DIF => dina(5), DIG => dina(6), DIH => '0', DOA => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0\, DOB => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1\, DOC => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2\, DOD => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3\, DOE => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4\, DOF => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5\, DOG => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6\, DOH => \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => addra(7), I1 => addra(6), I2 => ena, O => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0\ ); \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7\: unisim.vcomponents.RAM64X1D generic map( INIT => X"0000000000000000" ) port map ( A0 => addra(0), A1 => addra(1), A2 => addra(2), A3 => addra(3), A4 => addra(4), A5 => addra(5), D => dina(7), DPO => \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0\, DPRA0 => addrb(0), DPRA1 => addrb(1), DPRA2 => addrb(2), DPRA3 => addrb(3), DPRA4 => addrb(4), DPRA5 => addrb(5), SPO => \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED\, WCLK => clka, WE => \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0\ ); select_piped_1_reg_pipe_5_reg: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => addrb(6), Q => select_piped_1_reg_pipe_5_reg_n_0, R => '0' ); select_piped_3_reg_pipe_6_reg: unisim.vcomponents.FDRE port map ( C => clkb, CE => enb, D => addrb(7), Q => select_piped_3_reg_pipe_6_reg_n_0, R => '0' ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block Smodsvllcvd6MuPfdHlFmvR8p+Pe7f/pUBu/EPfJ2zZ5ctuddGasm68DT7c1GLZh6gDWLRVWzeFo 7fcCmPmHOg== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block 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aYtlFJXYRbQbtppE7MCDM/pXlO+OklsMXAIan7aOVF65VaBCZVBWD4vDZBRDgXXQhTotxoYCKd9A IJEg0ka8H0yw1m4O4u4ZSoUWjtYeR/OWM4aIc6ijKhm57nBe1VxcJk19I7dV50O4NDVwAFjydAEM FzCoDWZ6qGgopfh/I5sWFo6i/IkMeRvD7BEBowhIwCb+DbnKvYlmfTqqjDqUSr0Vp/83UQDQj635 XQTxuZ7HYzOWi9TocaSDAkVpxMBi0Sm4b47fJlTsjcAXBBVH7m/mHnTA5CxeAqIjjDdIg6T8r4Iu 6rzEBMRrUqPhlVRFfZjf5BeB1Idh4qV2sUn4XOYbOAwStPj64xENfP4/cbGLMO87hZp8CyR5gzNQ fQupetuJflBXOxvzk4s7bxeYi4cEJPZdgSqyS+3xry4FX+WPfNWsSobokJBTwbs9f2ut8QJH+KV6 EKqslUsvQWeHz5TxBPHzTJn+IUPqMcE7rDLUOuUGHDER9PIDgtfwV0m9ST7xIVJBGZmqqpFq8odV 2awhFNDuqaWVvcs= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is port ( \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC; wrst_busy : out STD_LOGIC; wr_pntr_plus1_pf_carry : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); underflow_i0 : out STD_LOGIC; \gen_rst_ic.fifo_rd_rst_ic_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; rst : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[7]\ : in STD_LOGIC; rst_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \guf.underflow_i_reg\ : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is signal \/i__n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes"; signal \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \__0/i__n_0\ : STD_LOGIC; signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes"; signal \gen_rst_ic.fifo_rd_rst_i0\ : STD_LOGIC; signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; signal \rst_i__0\ : STD_LOGIC; signal \^wrst_busy\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair156"; attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair157"; attribute DEF_VAL : string; attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 3; attribute INIT : string; attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute VERSION : integer; attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair157"; attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 3; attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0"; attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1; attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \grdc.rd_data_count_i[8]_i_1\ : label is "soft_lutpair156"; begin \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\; wrst_busy <= \^wrst_busy\; \/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \/i__n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"03030200FFFFFFFF" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I5 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFEFEEE" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I3 => rst, I4 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0EEE0FFFFEEE0" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I5 => \gen_rst_ic.fifo_rd_rst_wr_i\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I1 => \gen_rst_ic.fifo_rd_rst_wr_i\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \gen_rst_ic.fifo_rd_rst_wr_i\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, R => '0' ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gen_rst_ic.curr_rrst_state\(0), I1 => \gen_rst_ic.curr_rrst_state\(1), O => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \__0/i__n_0\, Q => \gen_rst_ic.curr_rrst_state\(0), R => '0' ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\, Q => \gen_rst_ic.curr_rrst_state\(1), R => '0' ); \__0/i_\: unisim.vcomponents.LUT3 generic map( INIT => X"06" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \__0/i__n_0\ ); \count_value_i[1]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"AAAE" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => ram_empty_i, I2 => Q(1), I3 => Q(0), O => \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) ); \gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \gen_rst_ic.fifo_rd_rst_i0\ ); \gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \gen_rst_ic.fifo_rd_rst_i0\, Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, R => '0' ); \gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEAFFFFFFEA0000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I2 => \rst_i__0\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\, I5 => \gen_rst_ic.fifo_wr_rst_ic\, O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in, I1 => rst, O => \rst_i__0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\, Q => \gen_rst_ic.fifo_wr_rst_ic\, R => '0' ); \gen_rst_ic.rrst_wr_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst port map ( dest_clk => wr_clk, dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\, src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ ); \gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\, I1 => rst, I2 => p_0_in, O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\ ); \gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00010000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\ ); \gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\, Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\, R => '0' ); \gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFEF00" ) port map ( I0 => rst, I1 => p_0_in, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\, I4 => \^wrst_busy\, O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\, Q => \^wrst_busy\, R => '0' ); \gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18\ port map ( dest_clk => rd_clk, dest_rst => \gen_rst_ic.fifo_wr_rst_rd\, src_rst => \gen_rst_ic.fifo_wr_rst_ic\ ); \gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => wr_en, I1 => \count_value_i_reg[7]\, I2 => \^wrst_busy\, I3 => rst_d1, O => wr_pntr_plus1_pf_carry ); \grdc.rd_data_count_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => Q(0), I2 => Q(1), O => SR(0) ); \guf.underflow_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \guf.underflow_i_reg\, I1 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I2 => rd_en, O => underflow_i0 ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => '0', Q => \power_on_rst_reg_n_0_[0]\, R => '0' ); \power_on_rst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \power_on_rst_reg_n_0_[0]\, Q => p_0_in, R => '0' ); wr_rst_busy_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^wrst_busy\, I1 => rst_d1, O => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ is port ( \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC; wrst_busy : out STD_LOGIC; wr_pntr_plus1_pf_carry : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); underflow_i0 : out STD_LOGIC; \gen_rst_ic.fifo_rd_rst_ic_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; rst : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[7]\ : in STD_LOGIC; rst_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \guf.underflow_i_reg\ : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ : entity is "xpm_fifo_rst"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ is signal \/i__n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes"; signal \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \__0/i__n_0\ : STD_LOGIC; signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes"; signal \gen_rst_ic.fifo_rd_rst_i0\ : STD_LOGIC; signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; signal \rst_i__0\ : STD_LOGIC; signal \^wrst_busy\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair124"; attribute DEF_VAL : string; attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 3; attribute INIT : string; attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute VERSION : integer; attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair124"; attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 3; attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0"; attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1; attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \grdc.rd_data_count_i[8]_i_1\ : label is "soft_lutpair123"; begin \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\; wrst_busy <= \^wrst_busy\; \/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \/i__n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"03030200FFFFFFFF" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I5 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFEFEEE" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I3 => rst, I4 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0EEE0FFFFEEE0" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I5 => \gen_rst_ic.fifo_rd_rst_wr_i\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I1 => \gen_rst_ic.fifo_rd_rst_wr_i\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \gen_rst_ic.fifo_rd_rst_wr_i\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, R => '0' ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gen_rst_ic.curr_rrst_state\(0), I1 => \gen_rst_ic.curr_rrst_state\(1), O => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \__0/i__n_0\, Q => \gen_rst_ic.curr_rrst_state\(0), R => '0' ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\, Q => \gen_rst_ic.curr_rrst_state\(1), R => '0' ); \__0/i_\: unisim.vcomponents.LUT3 generic map( INIT => X"06" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \__0/i__n_0\ ); \count_value_i[1]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"AAAE" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => ram_empty_i, I2 => Q(1), I3 => Q(0), O => \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) ); \gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \gen_rst_ic.fifo_rd_rst_i0\ ); \gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \gen_rst_ic.fifo_rd_rst_i0\, Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, R => '0' ); \gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEAFFFFFFEA0000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I2 => \rst_i__0\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\, I5 => \gen_rst_ic.fifo_wr_rst_ic\, O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in, I1 => rst, O => \rst_i__0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\, Q => \gen_rst_ic.fifo_wr_rst_ic\, R => '0' ); \gen_rst_ic.rrst_wr_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11\ port map ( dest_clk => wr_clk, dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\, src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ ); \gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\, I1 => rst, I2 => p_0_in, O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\ ); \gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00010000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\ ); \gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\, Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\, R => '0' ); \gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFEF00" ) port map ( I0 => rst, I1 => p_0_in, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\, I4 => \^wrst_busy\, O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\, Q => \^wrst_busy\, R => '0' ); \gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10\ port map ( dest_clk => rd_clk, dest_rst => \gen_rst_ic.fifo_wr_rst_rd\, src_rst => \gen_rst_ic.fifo_wr_rst_ic\ ); \gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => wr_en, I1 => \count_value_i_reg[7]\, I2 => \^wrst_busy\, I3 => rst_d1, O => wr_pntr_plus1_pf_carry ); \grdc.rd_data_count_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => Q(0), I2 => Q(1), O => SR(0) ); \guf.underflow_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \guf.underflow_i_reg\, I1 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I2 => rd_en, O => underflow_i0 ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => '0', Q => \power_on_rst_reg_n_0_[0]\, R => '0' ); \power_on_rst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \power_on_rst_reg_n_0_[0]\, Q => p_0_in, R => '0' ); wr_rst_busy_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^wrst_busy\, I1 => rst_d1, O => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2\ is port ( \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC; wrst_busy : out STD_LOGIC; wr_pntr_plus1_pf_carry : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); underflow_i0 : out STD_LOGIC; \gen_rst_ic.fifo_rd_rst_ic_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; rst : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[7]\ : in STD_LOGIC; rst_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \guf.underflow_i_reg\ : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2\ : entity is "xpm_fifo_rst"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2\ is signal \/i__n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes"; signal \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \__0/i__n_0\ : STD_LOGIC; signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes"; signal \gen_rst_ic.fifo_rd_rst_i0\ : STD_LOGIC; signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; signal \rst_i__0\ : STD_LOGIC; signal \^wrst_busy\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair90"; attribute DEF_VAL : string; attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 3; attribute INIT : string; attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute VERSION : integer; attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair90"; attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 3; attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0"; attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1; attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \grdc.rd_data_count_i[8]_i_1\ : label is "soft_lutpair89"; begin \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\; wrst_busy <= \^wrst_busy\; \/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \/i__n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"03030200FFFFFFFF" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I5 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFEFEEE" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I3 => rst, I4 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0EEE0FFFFEEE0" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I5 => \gen_rst_ic.fifo_rd_rst_wr_i\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I1 => \gen_rst_ic.fifo_rd_rst_wr_i\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \gen_rst_ic.fifo_rd_rst_wr_i\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, R => '0' ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gen_rst_ic.curr_rrst_state\(0), I1 => \gen_rst_ic.curr_rrst_state\(1), O => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \__0/i__n_0\, Q => \gen_rst_ic.curr_rrst_state\(0), R => '0' ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\, Q => \gen_rst_ic.curr_rrst_state\(1), R => '0' ); \__0/i_\: unisim.vcomponents.LUT3 generic map( INIT => X"06" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \__0/i__n_0\ ); \count_value_i[1]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"AAAE" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => ram_empty_i, I2 => Q(1), I3 => Q(0), O => \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) ); \gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \gen_rst_ic.fifo_rd_rst_i0\ ); \gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \gen_rst_ic.fifo_rd_rst_i0\, Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, R => '0' ); \gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEAFFFFFFEA0000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I2 => \rst_i__0\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\, I5 => \gen_rst_ic.fifo_wr_rst_ic\, O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in, I1 => rst, O => \rst_i__0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\, Q => \gen_rst_ic.fifo_wr_rst_ic\, R => '0' ); \gen_rst_ic.rrst_wr_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13\ port map ( dest_clk => wr_clk, dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\, src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ ); \gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\, I1 => rst, I2 => p_0_in, O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\ ); \gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00010000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\ ); \gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\, Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\, R => '0' ); \gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFEF00" ) port map ( I0 => rst, I1 => p_0_in, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\, I4 => \^wrst_busy\, O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\, Q => \^wrst_busy\, R => '0' ); \gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12\ port map ( dest_clk => rd_clk, dest_rst => \gen_rst_ic.fifo_wr_rst_rd\, src_rst => \gen_rst_ic.fifo_wr_rst_ic\ ); \gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => wr_en, I1 => \count_value_i_reg[7]\, I2 => \^wrst_busy\, I3 => rst_d1, O => wr_pntr_plus1_pf_carry ); \grdc.rd_data_count_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => Q(0), I2 => Q(1), O => SR(0) ); \guf.underflow_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \guf.underflow_i_reg\, I1 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I2 => rd_en, O => underflow_i0 ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => '0', Q => \power_on_rst_reg_n_0_[0]\, R => '0' ); \power_on_rst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \power_on_rst_reg_n_0_[0]\, Q => p_0_in, R => '0' ); wr_rst_busy_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^wrst_busy\, I1 => rst_d1, O => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3\ is port ( \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC; wrst_busy : out STD_LOGIC; wr_pntr_plus1_pf_carry : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); underflow_i0 : out STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; rst : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[8]\ : in STD_LOGIC; rst_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \guf.underflow_i_reg\ : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3\ : entity is "xpm_fifo_rst"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3\ is signal \/i__n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes"; signal \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \__0/i__n_0\ : STD_LOGIC; signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes"; signal \gen_rst_ic.fifo_rd_rst_i0\ : STD_LOGIC; signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; signal \rst_i__0\ : STD_LOGIC; signal \^wrst_busy\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair260"; attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair261"; attribute DEF_VAL : string; attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 3; attribute INIT : string; attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute VERSION : integer; attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair261"; attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 3; attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0"; attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1; attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \grdc.rd_data_count_i[9]_i_1\ : label is "soft_lutpair260"; begin \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\; wrst_busy <= \^wrst_busy\; \/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \/i__n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"03030200FFFFFFFF" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I5 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFEFEEE" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I3 => rst, I4 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0EEE0FFFFEEE0" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I5 => \gen_rst_ic.fifo_rd_rst_wr_i\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I1 => \gen_rst_ic.fifo_rd_rst_wr_i\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \gen_rst_ic.fifo_rd_rst_wr_i\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, R => '0' ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gen_rst_ic.curr_rrst_state\(0), I1 => \gen_rst_ic.curr_rrst_state\(1), O => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \__0/i__n_0\, Q => \gen_rst_ic.curr_rrst_state\(0), R => '0' ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\, Q => \gen_rst_ic.curr_rrst_state\(1), R => '0' ); \__0/i_\: unisim.vcomponents.LUT3 generic map( INIT => X"06" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \__0/i__n_0\ ); \count_value_i[1]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"FF02" ) port map ( I0 => ram_empty_i, I1 => Q(0), I2 => Q(1), I3 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, O => \gen_pf_ic_rc.ram_empty_i_reg\(0) ); \gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \gen_rst_ic.fifo_rd_rst_i0\ ); \gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \gen_rst_ic.fifo_rd_rst_i0\, Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, R => '0' ); \gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEAFFFFFFEA0000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I2 => \rst_i__0\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\, I5 => \gen_rst_ic.fifo_wr_rst_ic\, O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in, I1 => rst, O => \rst_i__0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\, Q => \gen_rst_ic.fifo_wr_rst_ic\, R => '0' ); \gen_rst_ic.rrst_wr_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15\ port map ( dest_clk => wr_clk, dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\, src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ ); \gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\, I1 => rst, I2 => p_0_in, O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\ ); \gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00010000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\ ); \gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\, Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\, R => '0' ); \gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFEF00" ) port map ( I0 => rst, I1 => p_0_in, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\, I4 => \^wrst_busy\, O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\, Q => \^wrst_busy\, R => '0' ); \gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14\ port map ( dest_clk => rd_clk, dest_rst => \gen_rst_ic.fifo_wr_rst_rd\, src_rst => \gen_rst_ic.fifo_wr_rst_ic\ ); \gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => wr_en, I1 => \count_value_i_reg[8]\, I2 => \^wrst_busy\, I3 => rst_d1, O => wr_pntr_plus1_pf_carry ); \grdc.rd_data_count_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F1" ) port map ( I0 => Q(1), I1 => Q(0), I2 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, O => SR(0) ); \guf.underflow_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => \guf.underflow_i_reg\, I2 => rd_en, O => underflow_i0 ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => '0', Q => \power_on_rst_reg_n_0_[0]\, R => '0' ); \power_on_rst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \power_on_rst_reg_n_0_[0]\, Q => p_0_in, R => '0' ); wr_rst_busy_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^wrst_busy\, I1 => rst_d1, O => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4\ is port ( \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC; wrst_busy : out STD_LOGIC; wr_pntr_plus1_pf_carry : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); underflow_i0 : out STD_LOGIC; \gen_pf_ic_rc.ram_empty_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; rst : in STD_LOGIC; wr_en : in STD_LOGIC; \count_value_i_reg[8]\ : in STD_LOGIC; rst_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \guf.underflow_i_reg\ : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4\ : entity is "xpm_fifo_rst"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4\ is signal \/i__n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes"; signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes"; signal \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ : STD_LOGIC; signal \__0/i__n_0\ : STD_LOGIC; signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes"; signal \gen_rst_ic.fifo_rd_rst_i0\ : STD_LOGIC; signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC; signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC; signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC; signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC; signal \rst_i__0\ : STD_LOGIC; signal \^wrst_busy\ : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP : string; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001"; attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11"; attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair200"; attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair201"; attribute DEF_VAL : string; attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 3; attribute INIT : string; attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0"; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute VERSION : integer; attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair201"; attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 3; attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0"; attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1; attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0; attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST"; attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \grdc.rd_data_count_i[9]_i_1\ : label is "soft_lutpair200"; begin \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\; wrst_busy <= \^wrst_busy\; \/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \/i__n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"03030200FFFFFFFF" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I5 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFEFEEE" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I3 => rst, I4 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0EEE0FFFFEEE0" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I5 => \gen_rst_ic.fifo_rd_rst_wr_i\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000C0008" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I1 => \gen_rst_ic.fifo_rd_rst_wr_i\, I2 => rst, I3 => p_0_in, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \gen_rst_ic.fifo_rd_rst_wr_i\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => rst, I3 => p_0_in, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \/i__n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => p_0_in, I2 => rst, I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, R => '0' ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\, Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gen_rst_ic.curr_rrst_state\(0), I1 => \gen_rst_ic.curr_rrst_state\(1), O => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\ ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \__0/i__n_0\, Q => \gen_rst_ic.curr_rrst_state\(0), R => '0' ); \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0\, Q => \gen_rst_ic.curr_rrst_state\(1), R => '0' ); \__0/i_\: unisim.vcomponents.LUT3 generic map( INIT => X"06" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \__0/i__n_0\ ); \count_value_i[1]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"FF02" ) port map ( I0 => ram_empty_i, I1 => Q(0), I2 => Q(1), I3 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, O => \gen_pf_ic_rc.ram_empty_i_reg\(0) ); \gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => \gen_rst_ic.fifo_wr_rst_rd\, I1 => \gen_rst_ic.curr_rrst_state\(1), I2 => \gen_rst_ic.curr_rrst_state\(0), O => \gen_rst_ic.fifo_rd_rst_i0\ ); \gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \gen_rst_ic.fifo_rd_rst_i0\, Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, R => '0' ); \gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEAFFFFFFEA0000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I2 => \rst_i__0\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\, I5 => \gen_rst_ic.fifo_wr_rst_ic\, O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in, I1 => rst, O => \rst_i__0\ ); \gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ ); \gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\, Q => \gen_rst_ic.fifo_wr_rst_ic\, R => '0' ); \gen_rst_ic.rrst_wr_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17\ port map ( dest_clk => wr_clk, dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\, src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ ); \gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\, I1 => rst, I2 => p_0_in, O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\ ); \gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00010000" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\, O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\ ); \gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\, Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\, R => '0' ); \gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFEF00" ) port map ( I0 => rst, I1 => p_0_in, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\, I4 => \^wrst_busy\, O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000116" ) port map ( I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\, I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\, I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\, I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\, I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\, O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ ); \gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\, Q => \^wrst_busy\, R => '0' ); \gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16\ port map ( dest_clk => rd_clk, dest_rst => \gen_rst_ic.fifo_wr_rst_rd\, src_rst => \gen_rst_ic.fifo_wr_rst_ic\ ); \gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => wr_en, I1 => \count_value_i_reg[8]\, I2 => \^wrst_busy\, I3 => rst_d1, O => wr_pntr_plus1_pf_carry ); \grdc.rd_data_count_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F1" ) port map ( I0 => Q(1), I1 => Q(0), I2 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, O => SR(0) ); \guf.underflow_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\, I1 => \guf.underflow_i_reg\, I2 => rd_en, O => underflow_i0 ); \power_on_rst_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => '0', Q => \power_on_rst_reg_n_0_[0]\, R => '0' ); \power_on_rst_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \power_on_rst_reg_n_0_[0]\, Q => p_0_in, R => '0' ); wr_rst_busy_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^wrst_busy\, I1 => rst_d1, O => wr_rst_busy ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block Smodsvllcvd6MuPfdHlFmvR8p+Pe7f/pUBu/EPfJ2zZ5ctuddGasm68DT7c1GLZh6gDWLRVWzeFo 7fcCmPmHOg== `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block s2mDZJeKjJsKFE8Xp2XRbJCl6T2FNVLRNeAmU/UqqR05MWC75Dr4jE6br+1fqFRpw3qEraDZBccO 2KWWAdJBHQOh1fufTlMCJJJEIWl4RL3bkCRsGDbIquWw0kVLdFyOEx6Lt14PvUyTuHVmV8wLyqrH yrV4YPFXV6ypwrcRjr8= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block x+7/agT4n/d9u1QQInxgxce2jZanNSpIonCHAMN9TwcrlJrdb8ZfXZRtPg5W5uDzAYwFlpOMaH7J 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DeQ09YUFQBw0JTF26uqA0nuDjbLnrYEPefeyLOUrJBpeKM5oxzthaiq7942hYg7CtW7HbzYaW+/5 kdcMxBzbdrA6lUI9j4ObVOYZYxQPstBP+agE8fRybPOSkd09aBDWBctCa9ZtYHrX3M+5rdVswznE Aplm9KplDNhfnHwikzJQ94fcv2U9h6odVLKFLsWyE0gix9dPyn+HxRraBY4UJ1t4O8JOZsmC1bUs RyHgwn6moMFx5lhKtsoqHPn2FTJt52XHUVKxypzhM8uIb5ZPVKq5nSoMFRkilzugTvIYMJi89TFK DDI+Cpt0b/kfcV/jmYXZo6jZ9ariQ4PvmDtMIo0g92dck8wnjSnbRiNySM9m0UTjY9iWt931pT+U 18btsakEGvzuBqcCfBrQuuRw2rOfldgyTXpgDblmRsd1gdQSzGIrNKWW8iRRUApdPQgoMJw8iNIp x1Ujs9bKddUML7egFd7UcIc1woIT7pjIobzwKqhRf48Jrl5PT1jFL355uIezRnvi2LRbk58WzpzS OR6EDdRma8sSsb1qAo7hOOZn8uwq38s8PR1y4RB4BCkuaGmPlfHzZ3Ls5tdbW47iUcoxDwpOFPUk QfXtTdJxm3k0O40= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 49 downto 0 ); full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 49 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "0"; attribute ECC_MODE : integer; attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0"; attribute EN_AF : string; attribute EN_AF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0"; attribute EN_OF : string; attribute EN_OF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute EN_PE : string; attribute EN_PE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute EN_PF : string; attribute EN_PF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute EN_UF : string; attribute EN_UF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0"; attribute FIFO_MEMORY_TYPE : integer; attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 256; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 12800; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 128; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 50; attribute READ_MODE : integer; attribute READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "0707"; attribute VERSION : integer; attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 50; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 6; attribute XPM_MODULE : string; attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3; attribute invalid : integer; attribute invalid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "soft"; attribute stage1_valid : integer; attribute stage1_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2; attribute stage2_valid : integer; attribute stage2_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is signal \\ : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal diff_pntr_pe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 8 downto 2 ); signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 8 downto 2 ); signal \^empty\ : STD_LOGIC; signal empty_fwft_i0 : STD_LOGIC; signal \^full\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC; signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.ram_regout_en\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal overflow_i0 : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; signal rd_pntr_ext : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \^rd_rst_busy\ : STD_LOGIC; signal rdp_inst_n_10 : STD_LOGIC; signal rdp_inst_n_19 : STD_LOGIC; signal rdp_inst_n_20 : STD_LOGIC; signal rdp_inst_n_21 : STD_LOGIC; signal rdp_inst_n_22 : STD_LOGIC; signal rdp_inst_n_23 : STD_LOGIC; signal rdp_inst_n_24 : STD_LOGIC; signal rdp_inst_n_25 : STD_LOGIC; signal rdp_inst_n_26 : STD_LOGIC; signal rdp_inst_n_27 : STD_LOGIC; signal rdp_inst_n_28 : STD_LOGIC; signal rdp_inst_n_29 : STD_LOGIC; signal rdp_inst_n_30 : STD_LOGIC; signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_8 : STD_LOGIC; signal rdp_inst_n_9 : STD_LOGIC; signal rdpp1_inst_n_0 : STD_LOGIC; signal rdpp1_inst_n_1 : STD_LOGIC; signal rdpp1_inst_n_2 : STD_LOGIC; signal rdpp1_inst_n_3 : STD_LOGIC; signal rdpp1_inst_n_4 : STD_LOGIC; signal rdpp1_inst_n_5 : STD_LOGIC; signal rdpp1_inst_n_6 : STD_LOGIC; signal rdpp1_inst_n_7 : STD_LOGIC; signal rst_d1 : STD_LOGIC; signal rst_d1_inst_n_1 : STD_LOGIC; signal src_in_bin00_out : STD_LOGIC_VECTOR ( 1 to 1 ); signal underflow_i0 : STD_LOGIC; signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 8 downto 1 ); signal wr_pntr_plus1_pf_carry : STD_LOGIC; signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wrpp2_inst_n_0 : STD_LOGIC; signal wrpp2_inst_n_1 : STD_LOGIC; signal wrpp2_inst_n_2 : STD_LOGIC; signal wrpp2_inst_n_3 : STD_LOGIC; signal wrpp2_inst_n_4 : STD_LOGIC; signal wrpp2_inst_n_5 : STD_LOGIC; signal wrpp2_inst_n_6 : STD_LOGIC; signal wrpp2_inst_n_7 : STD_LOGIC; signal wrst_busy : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 49 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair92"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH : integer; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC : string; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 5; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair91"; attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft"; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE\ : boolean; attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true; attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer; attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 49; attribute \MEM.ADDRESS_SPACE_END\ : integer; attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 511; attribute \MEM.CORE_MEMORY_WIDTH\ : integer; attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 12800; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 52; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 52; attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair91"; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; empty <= \^empty\; full <= \^full\; full_n <= \\; prog_empty <= \^prog_empty\; prog_full <= \^prog_full\; rd_rst_busy <= \^rd_rst_busy\; sbiterr <= \\; wr_ack <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6A85" ) port map ( I0 => curr_fwft_state(0), I1 => rd_en, I2 => curr_fwft_state(1), I3 => ram_empty_i, O => \next_fwft_state__0\(0) ); \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(0), Q => curr_fwft_state(0), R => \^rd_rst_busy\ ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(1), Q => curr_fwft_state(1), R => \^rd_rst_busy\ ); GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8\ port map ( dest_clk => wr_clk, dest_out_bin(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), src_clk => rd_clk, src_in_bin(8) => rdp_inst_n_24, src_in_bin(7) => rdp_inst_n_25, src_in_bin(6) => rdp_inst_n_26, src_in_bin(5) => rdp_inst_n_27, src_in_bin(4) => rdp_inst_n_28, src_in_bin(3) => rdp_inst_n_29, src_in_bin(2) => rdp_inst_n_30, src_in_bin(1) => src_in_bin00_out(1), src_in_bin(0) => rdp_inst_n_31 ); \gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9\ port map ( dest_clk => wr_clk, dest_out_bin(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), src_clk => rd_clk, src_in_bin(7 downto 0) => rd_pntr_ext(7 downto 0) ); \gen_cdc_pntr.rpw_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 port map ( D(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), d_out_reg => \gen_cdc_pntr.rpw_gray_reg_n_8\, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7) => wrpp2_inst_n_0, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6) => wrpp2_inst_n_1, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5) => wrpp2_inst_n_2, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4) => wrpp2_inst_n_3, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3) => wrpp2_inst_n_4, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2) => wrpp2_inst_n_5, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1) => wrpp2_inst_n_6, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0) => wrpp2_inst_n_7, \reg_out_i_reg[7]_0\(7 downto 0) => rd_pntr_wr(7 downto 0), rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); \gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35\ port map ( D(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, wr_clk => wr_clk, wrst_busy => wrst_busy ); \gen_cdc_pntr.wpr_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 port map ( D(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), Q(1 downto 0) => curr_fwft_state(1 downto 0), \gen_pf_ic_rc.ram_empty_i_reg\(7 downto 0) => rd_pntr_ext(7 downto 0), \gen_pf_ic_rc.ram_empty_i_reg_0\(7) => rdpp1_inst_n_0, \gen_pf_ic_rc.ram_empty_i_reg_0\(6) => rdpp1_inst_n_1, \gen_pf_ic_rc.ram_empty_i_reg_0\(5) => rdpp1_inst_n_2, \gen_pf_ic_rc.ram_empty_i_reg_0\(4) => rdpp1_inst_n_3, \gen_pf_ic_rc.ram_empty_i_reg_0\(3) => rdpp1_inst_n_4, \gen_pf_ic_rc.ram_empty_i_reg_0\(2) => rdpp1_inst_n_5, \gen_pf_ic_rc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_6, \gen_pf_ic_rc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_7, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, rd_clk => rd_clk, rd_en => rd_en, \reg_out_i_reg[0]_0\ => \^rd_rst_busy\, \reg_out_i_reg[7]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \reg_out_i_reg[7]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \reg_out_i_reg[7]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \reg_out_i_reg[7]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \reg_out_i_reg[7]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \reg_out_i_reg[7]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \reg_out_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\ ); \gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37\ port map ( D(7 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(8 downto 1), DI(1) => rdp_inst_n_9, DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, S(6) => rdp_inst_n_19, S(5) => rdp_inst_n_20, S(4) => rdp_inst_n_21, S(3) => rdp_inst_n_22, S(2) => rdp_inst_n_23, S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, \grdc.rd_data_count_i_reg[7]\(0) => count_value_i(1), \grdc.rd_data_count_i_reg[7]_0\(5 downto 0) => rd_pntr_ext(6 downto 1), \grdc.rd_data_count_i_reg[8]\(0) => rdp_inst_n_10, rd_clk => rd_clk, \reg_out_i_reg[8]_0\ => \^rd_rst_busy\, \reg_out_i_reg[8]_1\(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4\ port map ( dest_clk => rd_clk, dest_out_bin(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0), src_clk => wr_clk, src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8\ port map ( dest_clk => rd_clk, dest_out_bin(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), src_clk => wr_clk, src_in_bin(7 downto 0) => wr_pntr_ext(7 downto 0) ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F380" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), I3 => \^empty\, O => empty_fwft_i0 ); \gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => empty_fwft_i0, Q => \^empty\, S => \^rd_rst_busy\ ); \gen_fwft.rdpp1_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 port map ( DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(1 downto 0) => count_value_i(1 downto 0), S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, SR(0) => \gen_fwft.count_rst\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \grdc.rd_data_count_i_reg[7]\(1 downto 0) => rd_pntr_ext(1 downto 0), \grdc.rd_data_count_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \grdc.rd_data_count_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(0) => src_in_bin00_out(1) ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gen_cdc_pntr.rpw_gray_reg_n_8\, Q => \^full\, S => wrst_busy ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(0), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(1), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(2), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(3), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(4), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(5), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(6), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(7), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \^prog_empty\, I1 => \^empty\, I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\, I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"01FF" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\, Q => \^prog_empty\, S => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(2), Q => diff_pntr_pf_q(2), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(3), Q => diff_pntr_pf_q(3), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(4), Q => diff_pntr_pf_q(4), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(5), Q => diff_pntr_pf_q(5), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(6), Q => diff_pntr_pf_q(6), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(7), Q => diff_pntr_pf_q(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(8), Q => diff_pntr_pf_q(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => diff_pntr_pf_q(3), I1 => diff_pntr_pf_q(2), I2 => diff_pntr_pf_q(6), I3 => diff_pntr_pf_q(7), I4 => diff_pntr_pf_q(4), I5 => diff_pntr_pf_q(5), O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1_inst_n_1, Q => \^prog_full\, S => wrst_busy ); \gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i0, Q => ram_empty_i, S => \^rd_rst_busy\ ); \gen_sdpram.xpm_memory_base_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base port map ( addra(7 downto 0) => wr_pntr_ext(7 downto 0), addrb(7 downto 0) => rd_pntr_ext(7 downto 0), clka => wr_clk, clkb => rd_clk, dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\, dina(49 downto 0) => din(49 downto 0), dinb(49 downto 0) => B"00000000000000000000000000000000000000000000000000", douta(49 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(49 downto 0), doutb(49 downto 0) => dout(49 downto 0), ena => wr_pntr_plus1_pf_carry, enb => rdp_inst_n_8, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', injectsbiterrb => '0', regcea => '0', regceb => \gen_fwft.ram_regout_en\, rsta => '0', rstb => \^rd_rst_busy\, sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\, sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\, sleep => sleep, wea(0) => '0', web(0) => '0' ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"62" ) port map ( I0 => curr_fwft_state(0), I1 => curr_fwft_state(1), I2 => rd_en, O => \gen_fwft.ram_regout_en\ ); \gof.overflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => overflow_i0, Q => overflow, R => '0' ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(1), Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(2), Q => rd_data_count(1), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(3), Q => rd_data_count(2), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(4), Q => rd_data_count(3), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(5), Q => rd_data_count(4), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(6), Q => rd_data_count(5), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(7), Q => rd_data_count(6), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(8), Q => rd_data_count(7), R => \grdc.rd_data_count_i0\ ); \guf.underflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => underflow_i0, Q => underflow, R => '0' ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(1), Q => wr_data_count(0), R => wrst_busy ); \gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(2), Q => wr_data_count(1), R => wrst_busy ); \gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(3), Q => wr_data_count(2), R => wrst_busy ); \gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(4), Q => wr_data_count(3), R => wrst_busy ); \gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(5), Q => wr_data_count(4), R => wrst_busy ); \gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(6), Q => wr_data_count(5), R => wrst_busy ); \gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(7), Q => wr_data_count(6), R => wrst_busy ); \gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(8), Q => wr_data_count(7), R => wrst_busy ); rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39\ port map ( D(7 downto 0) => diff_pntr_pe(7 downto 0), DI(0) => rdp_inst_n_9, Q(7 downto 0) => rd_pntr_ext(7 downto 0), S(4) => rdp_inst_n_19, S(3) => rdp_inst_n_20, S(2) => rdp_inst_n_21, S(1) => rdp_inst_n_22, S(0) => rdp_inst_n_23, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[7]_0\(0) => rdp_inst_n_10, \count_value_i_reg[8]_0\ => \^rd_rst_busy\, enb => rdp_inst_n_8, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, \grdc.rd_data_count_i_reg[7]\(1 downto 0) => count_value_i(1 downto 0), \grdc.rd_data_count_i_reg[8]\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, \grdc.rd_data_count_i_reg[8]\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, \grdc.rd_data_count_i_reg[8]\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, \grdc.rd_data_count_i_reg[8]\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, \grdc.rd_data_count_i_reg[8]\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, \grdc.rd_data_count_i_reg[8]\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, \grdc.rd_data_count_i_reg[8]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, \grdc.rd_data_count_i_reg[8]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(7) => rdp_inst_n_24, src_in_bin(6) => rdp_inst_n_25, src_in_bin(5) => rdp_inst_n_26, src_in_bin(4) => rdp_inst_n_27, src_in_bin(3) => rdp_inst_n_28, src_in_bin(2) => rdp_inst_n_29, src_in_bin(1) => rdp_inst_n_30, src_in_bin(0) => rdp_inst_n_31 ); rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40\ port map ( E(0) => rdp_inst_n_8, Q(7) => rdpp1_inst_n_0, Q(6) => rdpp1_inst_n_1, Q(5) => rdpp1_inst_n_2, Q(4) => rdpp1_inst_n_3, Q(3) => rdpp1_inst_n_4, Q(2) => rdpp1_inst_n_5, Q(1) => rdpp1_inst_n_6, Q(0) => rdpp1_inst_n_7, \count_value_i_reg[0]_0\ => \^rd_rst_busy\, \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0), ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en ); rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 port map ( Q(0) => diff_pntr_pf_q(8), \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ => rst_d1_inst_n_1, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ => \^full\, overflow_i0 => overflow_i0, prog_full => \^prog_full\, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wrst_busy => wrst_busy ); wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42\ port map ( D(7 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(8 downto 1), Q(8 downto 0) => wr_pntr_ext(8 downto 0), \count_value_i_reg[6]_0\ => \^full\, \gwdc.wr_data_count_i_reg[8]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, \gwdc.wr_data_count_i_reg[8]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, \gwdc.wr_data_count_i_reg[8]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, \gwdc.wr_data_count_i_reg[8]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, \gwdc.wr_data_count_i_reg[8]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, \gwdc.wr_data_count_i_reg[8]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, \gwdc.wr_data_count_i_reg[8]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, \gwdc.wr_data_count_i_reg[8]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, \gwdc.wr_data_count_i_reg[8]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43\ port map ( D(6 downto 0) => diff_pntr_pf_q0(8 downto 2), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), \count_value_i_reg[6]_0\ => \^full\, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7 downto 0) => rd_pntr_wr(7 downto 0), rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44\ port map ( Q(7) => wrpp2_inst_n_0, Q(6) => wrpp2_inst_n_1, Q(5) => wrpp2_inst_n_2, Q(4) => wrpp2_inst_n_3, Q(3) => wrpp2_inst_n_4, Q(2) => wrpp2_inst_n_5, Q(1) => wrpp2_inst_n_6, Q(0) => wrpp2_inst_n_7, \count_value_i_reg[6]_0\ => \^full\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); xpm_fifo_rst_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2\ port map ( Q(1 downto 0) => curr_fwft_state(1 downto 0), SR(0) => \grdc.rd_data_count_i0\, \count_value_i_reg[7]\ => \^full\, \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\, \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) => \gen_fwft.count_rst\, \guf.underflow_i_reg\ => \^empty\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, rst => rst, rst_d1 => rst_d1, underflow_i0 => underflow_i0, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wr_rst_busy => wr_rst_busy, wrst_busy => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 40 downto 0 ); full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 40 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "0"; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0"; attribute EN_AF : string; attribute EN_AF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0"; attribute EN_OF : string; attribute EN_OF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute EN_PE : string; attribute EN_PE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute EN_PF : string; attribute EN_PF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute EN_UF : string; attribute EN_UF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0"; attribute FIFO_MEMORY_TYPE : integer; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 512; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 20992; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 512; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "xpm_fifo_base"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 507; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 382; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 507; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 384; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 10; attribute RD_LATENCY : integer; attribute RD_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 41; attribute READ_MODE : integer; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "0707"; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 41; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 10; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 6; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 3; attribute invalid : integer; attribute invalid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "soft"; attribute stage1_valid : integer; attribute stage1_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2; attribute stage2_valid : integer; attribute stage2_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ is signal \\ : STD_LOGIC; signal clr_full : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal diff_pntr_pe : STD_LOGIC_VECTOR ( 8 downto 0 ); signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 9 downto 2 ); signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 9 downto 2 ); signal \^empty\ : STD_LOGIC; signal empty_fwft_i0 : STD_LOGIC; signal \^full\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC; signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.ram_regout_en\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal overflow_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; signal ram_rd_en_i : STD_LOGIC; signal rd_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \^rd_rst_busy\ : STD_LOGIC; signal rdp_inst_n_0 : STD_LOGIC; signal rdp_inst_n_11 : STD_LOGIC; signal rdp_inst_n_21 : STD_LOGIC; signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_32 : STD_LOGIC; signal rdp_inst_n_33 : STD_LOGIC; signal rdp_inst_n_34 : STD_LOGIC; signal rdp_inst_n_35 : STD_LOGIC; signal rdp_inst_n_36 : STD_LOGIC; signal rdp_inst_n_37 : STD_LOGIC; signal rdp_inst_n_38 : STD_LOGIC; signal rst_d1 : STD_LOGIC; signal rst_d1_inst_n_1 : STD_LOGIC; signal src_in_bin00_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal underflow_i0 : STD_LOGIC; signal wr_pntr_ext : STD_LOGIC_VECTOR ( 9 downto 0 ); signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 9 downto 1 ); signal wr_pntr_plus1_pf_carry : STD_LOGIC; signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 9 downto 0 ); signal wrpp2_inst_n_0 : STD_LOGIC; signal wrpp2_inst_n_1 : STD_LOGIC; signal wrpp2_inst_n_2 : STD_LOGIC; signal wrpp2_inst_n_3 : STD_LOGIC; signal wrpp2_inst_n_4 : STD_LOGIC; signal wrpp2_inst_n_5 : STD_LOGIC; signal wrpp2_inst_n_6 : STD_LOGIC; signal wrpp2_inst_n_7 : STD_LOGIC; signal wrpp2_inst_n_8 : STD_LOGIC; signal wrst_busy : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 40 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair203"; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair203"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH : integer; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 10; attribute XPM_CDC : string; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 5; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 10; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair202"; attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft"; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE\ : boolean; attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true; attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer; attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 40; attribute \MEM.ADDRESS_SPACE_END\ : integer; attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 511; attribute \MEM.CORE_MEMORY_WIDTH\ : integer; attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 20992; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 512; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44; attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair202"; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; empty <= \^empty\; full <= \^full\; full_n <= \\; prog_empty <= \^prog_empty\; prog_full <= \^prog_full\; rd_rst_busy <= \^rd_rst_busy\; sbiterr <= \\; wr_ack <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"69A1" ) port map ( I0 => ram_empty_i, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), I3 => rd_en, O => \next_fwft_state__0\(0) ); \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(0), Q => curr_fwft_state(0), R => \^rd_rst_busy\ ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(1), Q => curr_fwft_state(1), R => \^rd_rst_busy\ ); GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3\ port map ( dest_clk => wr_clk, dest_out_bin(9 downto 0) => rd_pntr_wr_cdc_dc(9 downto 0), src_clk => rd_clk, src_in_bin(9 downto 0) => src_in_bin00_out(9 downto 0) ); \gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12\ port map ( dest_clk => wr_clk, dest_out_bin(8 downto 0) => rd_pntr_wr_cdc(8 downto 0), src_clk => rd_clk, src_in_bin(8 downto 0) => rd_pntr_ext(8 downto 0) ); \gen_cdc_pntr.rpw_gray_reg\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4\ port map ( D(8 downto 0) => rd_pntr_wr_cdc(8 downto 0), Q(8 downto 0) => rd_pntr_wr(8 downto 0), clr_full => clr_full, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(8) => wrpp2_inst_n_0, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(7) => wrpp2_inst_n_1, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(6) => wrpp2_inst_n_2, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(5) => wrpp2_inst_n_3, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(4) => wrpp2_inst_n_4, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(3) => wrpp2_inst_n_5, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(2) => wrpp2_inst_n_6, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(1) => wrpp2_inst_n_7, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(0) => wrpp2_inst_n_8, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(8 downto 0) => wr_pntr_plus1_pf(9 downto 1), \reg_out_i_reg[0]_0\ => \gen_cdc_pntr.rpw_gray_reg_n_9\, wr_clk => wr_clk, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); \gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5\ port map ( D(9 downto 0) => rd_pntr_wr_cdc_dc(9 downto 0), Q(9) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_9\, wr_clk => wr_clk, wrst_busy => wrst_busy ); \gen_cdc_pntr.wpr_gray_reg\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6\ port map ( D(8 downto 0) => diff_pntr_pe(8 downto 0), DI(0) => p_1_in, Q(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, S(7) => rdp_inst_n_31, S(6) => rdp_inst_n_32, S(5) => rdp_inst_n_33, S(4) => rdp_inst_n_34, S(3) => rdp_inst_n_35, S(2) => rdp_inst_n_36, S(1) => rdp_inst_n_37, S(0) => rdp_inst_n_38, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\(0) => rd_pntr_ext(8), rd_clk => rd_clk, \reg_out_i_reg[0]_0\ => \^rd_rst_busy\, \reg_out_i_reg[8]_0\(8 downto 0) => wr_pntr_rd_cdc(8 downto 0) ); \gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7\ port map ( D(9 downto 0) => wr_pntr_rd_cdc_dc(9 downto 0), DI(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\, DI(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\, DI(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\, DI(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\, DI(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\, DI(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\, Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, S(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, \grdc.rd_data_count_i_reg[7]\(0) => count_value_i(1), \grdc.rd_data_count_i_reg[9]\(8) => rdp_inst_n_0, \grdc.rd_data_count_i_reg[9]\(7 downto 0) => rd_pntr_ext(8 downto 1), rd_clk => rd_clk, \reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \reg_out_i_reg[9]_0\ => \^rd_rst_busy\ ); \gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2\ port map ( dest_clk => rd_clk, dest_out_bin(9 downto 0) => wr_pntr_rd_cdc_dc(9 downto 0), src_clk => wr_clk, src_in_bin(9 downto 0) => wr_pntr_ext(9 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11\ port map ( dest_clk => rd_clk, dest_out_bin(8 downto 0) => wr_pntr_rd_cdc(8 downto 0), src_clk => wr_clk, src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0) ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E0CC" ) port map ( I0 => rd_en, I1 => \^empty\, I2 => curr_fwft_state(1), I3 => curr_fwft_state(0), O => empty_fwft_i0 ); \gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => empty_fwft_i0, Q => \^empty\, S => \^rd_rst_busy\ ); \gen_fwft.rdpp1_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 port map ( DI(1) => \gen_fwft.rdpp1_inst_n_3\, DI(0) => \gen_fwft.rdpp1_inst_n_4\, Q(1 downto 0) => count_value_i(1 downto 0), SR(0) => \gen_fwft.count_rst\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, \src_gray_ff_reg[0]\(0) => rd_pntr_ext(0), src_in_bin(0) => src_in_bin00_out(0) ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gen_cdc_pntr.rpw_gray_reg_n_9\, Q => \^full\, S => wrst_busy ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"AABA" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => curr_fwft_state(1), I3 => curr_fwft_state(0), O => p_1_in ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(0), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(1), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(2), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(3), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(4), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(5), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(6), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(7), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(8), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \^prog_empty\, I1 => \^empty\, I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\, I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"01FF" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\, Q => \^prog_empty\, S => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(2), Q => diff_pntr_pf_q(2), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(3), Q => diff_pntr_pf_q(3), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(4), Q => diff_pntr_pf_q(4), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(5), Q => diff_pntr_pf_q(5), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(6), Q => diff_pntr_pf_q(6), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(7), Q => diff_pntr_pf_q(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(8), Q => diff_pntr_pf_q(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(9), Q => diff_pntr_pf_q(9), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => diff_pntr_pf_q(3), I1 => diff_pntr_pf_q(2), I2 => diff_pntr_pf_q(6), I3 => diff_pntr_pf_q(7), I4 => diff_pntr_pf_q(4), I5 => diff_pntr_pf_q(5), O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1_inst_n_1, Q => \^prog_full\, S => wrst_busy ); \gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i0, Q => ram_empty_i, S => \^rd_rst_busy\ ); \gen_sdpram.xpm_memory_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0\ port map ( addra(8 downto 0) => wr_pntr_ext(8 downto 0), addrb(8 downto 0) => rd_pntr_ext(8 downto 0), clka => wr_clk, clkb => rd_clk, dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\, dina(40 downto 0) => din(40 downto 0), dinb(40 downto 0) => B"00000000000000000000000000000000000000000", douta(40 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(40 downto 0), doutb(40 downto 0) => dout(40 downto 0), ena => wr_pntr_plus1_pf_carry, enb => ram_rd_en_i, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', injectsbiterrb => '0', regcea => '0', regceb => \gen_fwft.ram_regout_en\, rsta => '0', rstb => \^rd_rst_busy\, sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\, sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\, sleep => sleep, wea(0) => '0', web(0) => '0' ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"2C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), O => \gen_fwft.ram_regout_en\ ); \gof.overflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => overflow_i0, Q => overflow, R => '0' ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(1), Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(2), Q => rd_data_count(1), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(3), Q => rd_data_count(2), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(4), Q => rd_data_count(3), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(5), Q => rd_data_count(4), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(6), Q => rd_data_count(5), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(7), Q => rd_data_count(6), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(8), Q => rd_data_count(7), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(9), Q => rd_data_count(8), R => \grdc.rd_data_count_i0\ ); \guf.underflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => underflow_i0, Q => underflow, R => '0' ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(1), Q => wr_data_count(0), R => wrst_busy ); \gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(2), Q => wr_data_count(1), R => wrst_busy ); \gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(3), Q => wr_data_count(2), R => wrst_busy ); \gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(4), Q => wr_data_count(3), R => wrst_busy ); \gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(5), Q => wr_data_count(4), R => wrst_busy ); \gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(6), Q => wr_data_count(5), R => wrst_busy ); \gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(7), Q => wr_data_count(6), R => wrst_busy ); \gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(8), Q => wr_data_count(7), R => wrst_busy ); \gwdc.wr_data_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(9), Q => wr_data_count(8), R => wrst_busy ); rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9\ port map ( D(8 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(9 downto 1), DI(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\, DI(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\, DI(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\, DI(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\, DI(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\, DI(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\, DI(1) => \gen_fwft.rdpp1_inst_n_3\, DI(0) => \gen_fwft.rdpp1_inst_n_4\, Q(9) => rdp_inst_n_0, Q(8 downto 0) => rd_pntr_ext(8 downto 0), S(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[1]_0\ => rdp_inst_n_21, \count_value_i_reg[7]_0\(7) => rdp_inst_n_31, \count_value_i_reg[7]_0\(6) => rdp_inst_n_32, \count_value_i_reg[7]_0\(5) => rdp_inst_n_33, \count_value_i_reg[7]_0\(4) => rdp_inst_n_34, \count_value_i_reg[7]_0\(3) => rdp_inst_n_35, \count_value_i_reg[7]_0\(2) => rdp_inst_n_36, \count_value_i_reg[7]_0\(1) => rdp_inst_n_37, \count_value_i_reg[7]_0\(0) => rdp_inst_n_38, \count_value_i_reg[9]_0\ => \^rd_rst_busy\, \gen_pf_ic_rc.ram_empty_i_reg\(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, \gen_pf_ic_rc.ram_empty_i_reg\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.ram_empty_i_reg\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.ram_empty_i_reg\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.ram_empty_i_reg\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.ram_empty_i_reg\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.ram_empty_i_reg\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.ram_empty_i_reg\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.ram_empty_i_reg\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, \grdc.rd_data_count_i_reg[7]\(1 downto 0) => count_value_i(1 downto 0), \grdc.rd_data_count_i_reg[9]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \grdc.rd_data_count_i_reg[9]_0\(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\, \grdc.rd_data_count_i_reg[9]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\, \grdc.rd_data_count_i_reg[9]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, \grdc.rd_data_count_i_reg[9]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, \grdc.rd_data_count_i_reg[9]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, \grdc.rd_data_count_i_reg[9]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, \grdc.rd_data_count_i_reg[9]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, \grdc.rd_data_count_i_reg[9]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, \grdc.rd_data_count_i_reg[9]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, ram_empty_i => ram_empty_i, ram_rd_en_i => ram_rd_en_i, rd_clk => rd_clk, rd_en => rd_en, \reg_out_i_reg[7]\ => rdp_inst_n_11, src_in_bin(8 downto 0) => src_in_bin00_out(9 downto 1) ); rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10\ port map ( E(0) => ram_rd_en_i, Q(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[0]_0\ => \^rd_rst_busy\, \gen_pf_ic_rc.ram_empty_i_reg\ => rdp_inst_n_21, \gen_pf_ic_rc.ram_empty_i_reg_0\ => rdp_inst_n_11, \gen_pf_ic_rc.ram_empty_i_reg_1\(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, \gen_pf_ic_rc.ram_empty_i_reg_1\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.ram_empty_i_reg_1\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.ram_empty_i_reg_1\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.ram_empty_i_reg_1\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.ram_empty_i_reg_1\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.ram_empty_i_reg_1\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.ram_empty_i_reg_1\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.ram_empty_i_reg_1\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, rd_clk => rd_clk, rd_en => rd_en ); rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 port map ( Q(1 downto 0) => diff_pntr_pf_q(9 downto 8), clr_full => clr_full, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ => rst_d1_inst_n_1, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ => \^full\, overflow_i0 => overflow_i0, prog_full => \^prog_full\, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wrst_busy => wrst_busy ); wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ port map ( D(8 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(9 downto 1), Q(9 downto 0) => wr_pntr_ext(9 downto 0), \count_value_i_reg[5]_0\ => \^full\, \gwdc.wr_data_count_i_reg[9]\(9) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, \gwdc.wr_data_count_i_reg[9]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, \gwdc.wr_data_count_i_reg[9]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, \gwdc.wr_data_count_i_reg[9]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, \gwdc.wr_data_count_i_reg[9]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, \gwdc.wr_data_count_i_reg[9]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, \gwdc.wr_data_count_i_reg[9]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, \gwdc.wr_data_count_i_reg[9]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, \gwdc.wr_data_count_i_reg[9]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, \gwdc.wr_data_count_i_reg[9]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_9\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13\ port map ( D(7 downto 0) => diff_pntr_pf_q0(9 downto 2), Q(8 downto 0) => wr_pntr_plus1_pf(9 downto 1), \count_value_i_reg[5]_0\ => \^full\, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(8 downto 0) => rd_pntr_wr(8 downto 0), rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14\ port map ( Q(8) => wrpp2_inst_n_0, Q(7) => wrpp2_inst_n_1, Q(6) => wrpp2_inst_n_2, Q(5) => wrpp2_inst_n_3, Q(4) => wrpp2_inst_n_4, Q(3) => wrpp2_inst_n_5, Q(2) => wrpp2_inst_n_6, Q(1) => wrpp2_inst_n_7, Q(0) => wrpp2_inst_n_8, \count_value_i_reg[5]_0\ => \^full\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); xpm_fifo_rst_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4\ port map ( Q(1 downto 0) => curr_fwft_state(1 downto 0), SR(0) => \grdc.rd_data_count_i0\, \count_value_i_reg[8]\ => \^full\, \gen_pf_ic_rc.ram_empty_i_reg\(0) => \gen_fwft.count_rst\, \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\, \guf.underflow_i_reg\ => \^empty\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, rst => rst, rst_d1 => rst_d1, underflow_i0 => underflow_i0, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wr_rst_busy => wr_rst_busy, wrst_busy => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 40 downto 0 ); full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 40 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "0"; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b0"; attribute EN_AF : string; attribute EN_AF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b0"; attribute EN_OF : string; attribute EN_OF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute EN_PE : string; attribute EN_PE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute EN_PF : string; attribute EN_PF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute EN_UF : string; attribute EN_UF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b0"; attribute FIFO_MEMORY_TYPE : integer; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 512; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 20992; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 512; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "xpm_fifo_base"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 507; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 382; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 507; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 8; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 384; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 9; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 10; attribute RD_LATENCY : integer; attribute RD_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 9; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 41; attribute READ_MODE : integer; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "0707"; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 41; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 9; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 10; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 9; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 9; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 6; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 3; attribute invalid : integer; attribute invalid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is "soft"; attribute stage1_valid : integer; attribute stage1_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 2; attribute stage2_valid : integer; attribute stage2_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ : entity is 1; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ is signal \\ : STD_LOGIC; signal clr_full : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal diff_pntr_pe : STD_LOGIC_VECTOR ( 8 downto 0 ); signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 9 downto 2 ); signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 9 downto 2 ); signal \^empty\ : STD_LOGIC; signal empty_fwft_i0 : STD_LOGIC; signal \^full\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC; signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.ram_regout_en\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal overflow_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; signal ram_rd_en_i : STD_LOGIC; signal rd_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \^rd_rst_busy\ : STD_LOGIC; signal rdp_inst_n_0 : STD_LOGIC; signal rdp_inst_n_11 : STD_LOGIC; signal rdp_inst_n_21 : STD_LOGIC; signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_32 : STD_LOGIC; signal rdp_inst_n_33 : STD_LOGIC; signal rdp_inst_n_34 : STD_LOGIC; signal rdp_inst_n_35 : STD_LOGIC; signal rdp_inst_n_36 : STD_LOGIC; signal rdp_inst_n_37 : STD_LOGIC; signal rdp_inst_n_38 : STD_LOGIC; signal rst_d1 : STD_LOGIC; signal rst_d1_inst_n_1 : STD_LOGIC; signal src_in_bin00_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal underflow_i0 : STD_LOGIC; signal wr_pntr_ext : STD_LOGIC_VECTOR ( 9 downto 0 ); signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 9 downto 1 ); signal wr_pntr_plus1_pf_carry : STD_LOGIC; signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 9 downto 0 ); signal wrpp2_inst_n_0 : STD_LOGIC; signal wrpp2_inst_n_1 : STD_LOGIC; signal wrpp2_inst_n_2 : STD_LOGIC; signal wrpp2_inst_n_3 : STD_LOGIC; signal wrpp2_inst_n_4 : STD_LOGIC; signal wrpp2_inst_n_5 : STD_LOGIC; signal wrpp2_inst_n_6 : STD_LOGIC; signal wrpp2_inst_n_7 : STD_LOGIC; signal wrpp2_inst_n_8 : STD_LOGIC; signal wrst_busy : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 40 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair263"; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair263"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH : integer; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 10; attribute XPM_CDC : string; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 5; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 10; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair262"; attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft"; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE\ : boolean; attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true; attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer; attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 40; attribute \MEM.ADDRESS_SPACE_END\ : integer; attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 511; attribute \MEM.CORE_MEMORY_WIDTH\ : integer; attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 20992; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 512; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 9; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 41; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44; attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair262"; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; empty <= \^empty\; full <= \^full\; full_n <= \\; prog_empty <= \^prog_empty\; prog_full <= \^prog_full\; rd_rst_busy <= \^rd_rst_busy\; sbiterr <= \\; wr_ack <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"69A1" ) port map ( I0 => ram_empty_i, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), I3 => rd_en, O => \next_fwft_state__0\(0) ); \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(0), Q => curr_fwft_state(0), R => \^rd_rst_busy\ ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(1), Q => curr_fwft_state(1), R => \^rd_rst_busy\ ); GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2\ port map ( dest_clk => wr_clk, dest_out_bin(9 downto 0) => rd_pntr_wr_cdc_dc(9 downto 0), src_clk => rd_clk, src_in_bin(9 downto 0) => src_in_bin00_out(9 downto 0) ); \gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10\ port map ( dest_clk => wr_clk, dest_out_bin(8 downto 0) => rd_pntr_wr_cdc(8 downto 0), src_clk => rd_clk, src_in_bin(8 downto 0) => rd_pntr_ext(8 downto 0) ); \gen_cdc_pntr.rpw_gray_reg\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ port map ( D(8 downto 0) => rd_pntr_wr_cdc(8 downto 0), Q(8 downto 0) => rd_pntr_wr(8 downto 0), clr_full => clr_full, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(8) => wrpp2_inst_n_0, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(7) => wrpp2_inst_n_1, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(6) => wrpp2_inst_n_2, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(5) => wrpp2_inst_n_3, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(4) => wrpp2_inst_n_4, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(3) => wrpp2_inst_n_5, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(2) => wrpp2_inst_n_6, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(1) => wrpp2_inst_n_7, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0\(0) => wrpp2_inst_n_8, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(8 downto 0) => wr_pntr_plus1_pf(9 downto 1), \reg_out_i_reg[0]_0\ => \gen_cdc_pntr.rpw_gray_reg_n_9\, wr_clk => wr_clk, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); \gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1\ port map ( D(9 downto 0) => rd_pntr_wr_cdc_dc(9 downto 0), Q(9) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_9\, wr_clk => wr_clk, wrst_busy => wrst_busy ); \gen_cdc_pntr.wpr_gray_reg\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0\ port map ( D(8 downto 0) => diff_pntr_pe(8 downto 0), DI(0) => p_1_in, Q(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, S(7) => rdp_inst_n_31, S(6) => rdp_inst_n_32, S(5) => rdp_inst_n_33, S(4) => rdp_inst_n_34, S(3) => rdp_inst_n_35, S(2) => rdp_inst_n_36, S(1) => rdp_inst_n_37, S(0) => rdp_inst_n_38, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\(0) => rd_pntr_ext(8), rd_clk => rd_clk, \reg_out_i_reg[0]_0\ => \^rd_rst_busy\, \reg_out_i_reg[8]_0\(8 downto 0) => wr_pntr_rd_cdc(8 downto 0) ); \gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1\ port map ( D(9 downto 0) => wr_pntr_rd_cdc_dc(9 downto 0), DI(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\, DI(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\, DI(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\, DI(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\, DI(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\, DI(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\, Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, S(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, \grdc.rd_data_count_i_reg[7]\(0) => count_value_i(1), \grdc.rd_data_count_i_reg[9]\(8) => rdp_inst_n_0, \grdc.rd_data_count_i_reg[9]\(7 downto 0) => rd_pntr_ext(8 downto 1), rd_clk => rd_clk, \reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \reg_out_i_reg[9]_0\ => \^rd_rst_busy\ ); \gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2\ port map ( dest_clk => rd_clk, dest_out_bin(9 downto 0) => wr_pntr_rd_cdc_dc(9 downto 0), src_clk => wr_clk, src_in_bin(9 downto 0) => wr_pntr_ext(9 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9\ port map ( dest_clk => rd_clk, dest_out_bin(8 downto 0) => wr_pntr_rd_cdc(8 downto 0), src_clk => wr_clk, src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0) ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E0CC" ) port map ( I0 => rd_en, I1 => \^empty\, I2 => curr_fwft_state(1), I3 => curr_fwft_state(0), O => empty_fwft_i0 ); \gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => empty_fwft_i0, Q => \^empty\, S => \^rd_rst_busy\ ); \gen_fwft.rdpp1_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn port map ( DI(1) => \gen_fwft.rdpp1_inst_n_3\, DI(0) => \gen_fwft.rdpp1_inst_n_4\, Q(1 downto 0) => count_value_i(1 downto 0), SR(0) => \gen_fwft.count_rst\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, \src_gray_ff_reg[0]\(0) => rd_pntr_ext(0), src_in_bin(0) => src_in_bin00_out(0) ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gen_cdc_pntr.rpw_gray_reg_n_9\, Q => \^full\, S => wrst_busy ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"AABA" ) port map ( I0 => ram_empty_i, I1 => rd_en, I2 => curr_fwft_state(1), I3 => curr_fwft_state(0), O => p_1_in ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(0), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(1), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(2), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(3), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(4), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(5), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(6), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(7), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(8), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \^prog_empty\, I1 => \^empty\, I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\, I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"01FF" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\, Q => \^prog_empty\, S => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(2), Q => diff_pntr_pf_q(2), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(3), Q => diff_pntr_pf_q(3), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(4), Q => diff_pntr_pf_q(4), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(5), Q => diff_pntr_pf_q(5), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(6), Q => diff_pntr_pf_q(6), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(7), Q => diff_pntr_pf_q(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(8), Q => diff_pntr_pf_q(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(9), Q => diff_pntr_pf_q(9), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => diff_pntr_pf_q(3), I1 => diff_pntr_pf_q(2), I2 => diff_pntr_pf_q(6), I3 => diff_pntr_pf_q(7), I4 => diff_pntr_pf_q(4), I5 => diff_pntr_pf_q(5), O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1_inst_n_1, Q => \^prog_full\, S => wrst_busy ); \gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i0, Q => ram_empty_i, S => \^rd_rst_busy\ ); \gen_sdpram.xpm_memory_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2\ port map ( addra(8 downto 0) => wr_pntr_ext(8 downto 0), addrb(8 downto 0) => rd_pntr_ext(8 downto 0), clka => wr_clk, clkb => rd_clk, dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\, dina(40 downto 0) => din(40 downto 0), dinb(40 downto 0) => B"00000000000000000000000000000000000000000", douta(40 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(40 downto 0), doutb(40 downto 0) => dout(40 downto 0), ena => wr_pntr_plus1_pf_carry, enb => ram_rd_en_i, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', injectsbiterrb => '0', regcea => '0', regceb => \gen_fwft.ram_regout_en\, rsta => '0', rstb => \^rd_rst_busy\, sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\, sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\, sleep => sleep, wea(0) => '0', web(0) => '0' ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"2C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), O => \gen_fwft.ram_regout_en\ ); \gof.overflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => overflow_i0, Q => overflow, R => '0' ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(1), Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(2), Q => rd_data_count(1), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(3), Q => rd_data_count(2), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(4), Q => rd_data_count(3), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(5), Q => rd_data_count(4), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(6), Q => rd_data_count(5), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(7), Q => rd_data_count(6), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(8), Q => rd_data_count(7), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(9), Q => rd_data_count(8), R => \grdc.rd_data_count_i0\ ); \guf.underflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => underflow_i0, Q => underflow, R => '0' ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(1), Q => wr_data_count(0), R => wrst_busy ); \gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(2), Q => wr_data_count(1), R => wrst_busy ); \gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(3), Q => wr_data_count(2), R => wrst_busy ); \gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(4), Q => wr_data_count(3), R => wrst_busy ); \gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(5), Q => wr_data_count(4), R => wrst_busy ); \gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(6), Q => wr_data_count(5), R => wrst_busy ); \gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(7), Q => wr_data_count(6), R => wrst_busy ); \gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(8), Q => wr_data_count(7), R => wrst_busy ); \gwdc.wr_data_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(9), Q => wr_data_count(8), R => wrst_busy ); rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ port map ( D(8 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(9 downto 1), DI(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\, DI(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\, DI(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\, DI(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\, DI(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\, DI(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\, DI(1) => \gen_fwft.rdpp1_inst_n_3\, DI(0) => \gen_fwft.rdpp1_inst_n_4\, Q(9) => rdp_inst_n_0, Q(8 downto 0) => rd_pntr_ext(8 downto 0), S(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[1]_0\ => rdp_inst_n_21, \count_value_i_reg[7]_0\(7) => rdp_inst_n_31, \count_value_i_reg[7]_0\(6) => rdp_inst_n_32, \count_value_i_reg[7]_0\(5) => rdp_inst_n_33, \count_value_i_reg[7]_0\(4) => rdp_inst_n_34, \count_value_i_reg[7]_0\(3) => rdp_inst_n_35, \count_value_i_reg[7]_0\(2) => rdp_inst_n_36, \count_value_i_reg[7]_0\(1) => rdp_inst_n_37, \count_value_i_reg[7]_0\(0) => rdp_inst_n_38, \count_value_i_reg[9]_0\ => \^rd_rst_busy\, \gen_pf_ic_rc.ram_empty_i_reg\(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, \gen_pf_ic_rc.ram_empty_i_reg\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.ram_empty_i_reg\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.ram_empty_i_reg\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.ram_empty_i_reg\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.ram_empty_i_reg\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.ram_empty_i_reg\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.ram_empty_i_reg\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.ram_empty_i_reg\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, \grdc.rd_data_count_i_reg[7]\(1 downto 0) => count_value_i(1 downto 0), \grdc.rd_data_count_i_reg[9]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \grdc.rd_data_count_i_reg[9]_0\(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\, \grdc.rd_data_count_i_reg[9]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\, \grdc.rd_data_count_i_reg[9]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, \grdc.rd_data_count_i_reg[9]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, \grdc.rd_data_count_i_reg[9]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, \grdc.rd_data_count_i_reg[9]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, \grdc.rd_data_count_i_reg[9]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, \grdc.rd_data_count_i_reg[9]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, \grdc.rd_data_count_i_reg[9]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, ram_empty_i => ram_empty_i, ram_rd_en_i => ram_rd_en_i, rd_clk => rd_clk, rd_en => rd_en, \reg_out_i_reg[7]\ => rdp_inst_n_11, src_in_bin(8 downto 0) => src_in_bin00_out(9 downto 1) ); rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4\ port map ( E(0) => ram_rd_en_i, Q(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[0]_0\ => \^rd_rst_busy\, \gen_pf_ic_rc.ram_empty_i_reg\ => rdp_inst_n_21, \gen_pf_ic_rc.ram_empty_i_reg_0\ => rdp_inst_n_11, \gen_pf_ic_rc.ram_empty_i_reg_1\(8) => \gen_cdc_pntr.wpr_gray_reg_n_0\, \gen_pf_ic_rc.ram_empty_i_reg_1\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.ram_empty_i_reg_1\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.ram_empty_i_reg_1\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.ram_empty_i_reg_1\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.ram_empty_i_reg_1\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.ram_empty_i_reg_1\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.ram_empty_i_reg_1\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.ram_empty_i_reg_1\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, rd_clk => rd_clk, rd_en => rd_en ); rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit port map ( Q(1 downto 0) => diff_pntr_pf_q(9 downto 8), clr_full => clr_full, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ => rst_d1_inst_n_1, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ => \^full\, overflow_i0 => overflow_i0, prog_full => \^prog_full\, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wrst_busy => wrst_busy ); wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2\ port map ( D(8 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(9 downto 1), Q(9 downto 0) => wr_pntr_ext(9 downto 0), \count_value_i_reg[5]_0\ => \^full\, \gwdc.wr_data_count_i_reg[9]\(9) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, \gwdc.wr_data_count_i_reg[9]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, \gwdc.wr_data_count_i_reg[9]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, \gwdc.wr_data_count_i_reg[9]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, \gwdc.wr_data_count_i_reg[9]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, \gwdc.wr_data_count_i_reg[9]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, \gwdc.wr_data_count_i_reg[9]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, \gwdc.wr_data_count_i_reg[9]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, \gwdc.wr_data_count_i_reg[9]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, \gwdc.wr_data_count_i_reg[9]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_9\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3\ port map ( D(7 downto 0) => diff_pntr_pf_q0(9 downto 2), Q(8 downto 0) => wr_pntr_plus1_pf(9 downto 1), \count_value_i_reg[5]_0\ => \^full\, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]\(8 downto 0) => rd_pntr_wr(8 downto 0), rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5\ port map ( Q(8) => wrpp2_inst_n_0, Q(7) => wrpp2_inst_n_1, Q(6) => wrpp2_inst_n_2, Q(5) => wrpp2_inst_n_3, Q(4) => wrpp2_inst_n_4, Q(3) => wrpp2_inst_n_5, Q(2) => wrpp2_inst_n_6, Q(1) => wrpp2_inst_n_7, Q(0) => wrpp2_inst_n_8, \count_value_i_reg[5]_0\ => \^full\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); xpm_fifo_rst_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3\ port map ( Q(1 downto 0) => curr_fwft_state(1 downto 0), SR(0) => \grdc.rd_data_count_i0\, \count_value_i_reg[8]\ => \^full\, \gen_pf_ic_rc.ram_empty_i_reg\(0) => \gen_fwft.count_rst\, \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\, \guf.underflow_i_reg\ => \^empty\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, rst => rst, rst_d1 => rst_d1, underflow_i0 => underflow_i0, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wr_rst_busy => wr_rst_busy, wrst_busy => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "0"; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b0"; attribute EN_AF : string; attribute EN_AF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b0"; attribute EN_OF : string; attribute EN_OF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute EN_PE : string; attribute EN_PE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute EN_PF : string; attribute EN_PF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute EN_UF : string; attribute EN_UF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b0"; attribute FIFO_MEMORY_TYPE : integer; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 256; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 2048; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "xpm_fifo_base"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 128; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute READ_MODE : integer; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "0707"; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 3; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 3; attribute invalid : integer; attribute invalid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is "soft"; attribute stage1_valid : integer; attribute stage1_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 2; attribute stage2_valid : integer; attribute stage2_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ : entity is 1; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ is signal \\ : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal diff_pntr_pe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 8 downto 2 ); signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 8 downto 2 ); signal \^empty\ : STD_LOGIC; signal empty_fwft_i0 : STD_LOGIC; signal \^full\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC; signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.ram_regout_en\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal overflow_i0 : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; signal rd_pntr_ext : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \^rd_rst_busy\ : STD_LOGIC; signal rdp_inst_n_10 : STD_LOGIC; signal rdp_inst_n_19 : STD_LOGIC; signal rdp_inst_n_20 : STD_LOGIC; signal rdp_inst_n_21 : STD_LOGIC; signal rdp_inst_n_22 : STD_LOGIC; signal rdp_inst_n_23 : STD_LOGIC; signal rdp_inst_n_24 : STD_LOGIC; signal rdp_inst_n_25 : STD_LOGIC; signal rdp_inst_n_26 : STD_LOGIC; signal rdp_inst_n_27 : STD_LOGIC; signal rdp_inst_n_28 : STD_LOGIC; signal rdp_inst_n_29 : STD_LOGIC; signal rdp_inst_n_30 : STD_LOGIC; signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_8 : STD_LOGIC; signal rdp_inst_n_9 : STD_LOGIC; signal rdpp1_inst_n_0 : STD_LOGIC; signal rdpp1_inst_n_1 : STD_LOGIC; signal rdpp1_inst_n_2 : STD_LOGIC; signal rdpp1_inst_n_3 : STD_LOGIC; signal rdpp1_inst_n_4 : STD_LOGIC; signal rdpp1_inst_n_5 : STD_LOGIC; signal rdpp1_inst_n_6 : STD_LOGIC; signal rdpp1_inst_n_7 : STD_LOGIC; signal rst_d1 : STD_LOGIC; signal rst_d1_inst_n_1 : STD_LOGIC; signal src_in_bin00_out : STD_LOGIC_VECTOR ( 1 to 1 ); signal underflow_i0 : STD_LOGIC; signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 8 downto 1 ); signal wr_pntr_plus1_pf_carry : STD_LOGIC; signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wrpp2_inst_n_0 : STD_LOGIC; signal wrpp2_inst_n_1 : STD_LOGIC; signal wrpp2_inst_n_2 : STD_LOGIC; signal wrpp2_inst_n_3 : STD_LOGIC; signal wrpp2_inst_n_4 : STD_LOGIC; signal wrpp2_inst_n_5 : STD_LOGIC; signal wrpp2_inst_n_6 : STD_LOGIC; signal wrpp2_inst_n_7 : STD_LOGIC; signal wrst_busy : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair159"; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair159"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH : integer; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC : string; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 5; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair158"; attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft"; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 2048; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair158"; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; empty <= \^empty\; full <= \^full\; full_n <= \\; prog_empty <= \^prog_empty\; prog_full <= \^prog_full\; rd_rst_busy <= \^rd_rst_busy\; sbiterr <= \\; wr_ack <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6A85" ) port map ( I0 => curr_fwft_state(0), I1 => rd_en, I2 => curr_fwft_state(1), I3 => ram_empty_i, O => \next_fwft_state__0\(0) ); \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(0), Q => curr_fwft_state(0), R => \^rd_rst_busy\ ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(1), Q => curr_fwft_state(1), R => \^rd_rst_busy\ ); GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ port map ( dest_clk => wr_clk, dest_out_bin(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), src_clk => rd_clk, src_in_bin(8) => rdp_inst_n_24, src_in_bin(7) => rdp_inst_n_25, src_in_bin(6) => rdp_inst_n_26, src_in_bin(5) => rdp_inst_n_27, src_in_bin(4) => rdp_inst_n_28, src_in_bin(3) => rdp_inst_n_29, src_in_bin(2) => rdp_inst_n_30, src_in_bin(1) => src_in_bin00_out(1), src_in_bin(0) => rdp_inst_n_31 ); \gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray port map ( dest_clk => wr_clk, dest_out_bin(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), src_clk => rd_clk, src_in_bin(7 downto 0) => rd_pntr_ext(7 downto 0) ); \gen_cdc_pntr.rpw_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec port map ( D(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), d_out_reg => \gen_cdc_pntr.rpw_gray_reg_n_8\, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7) => wrpp2_inst_n_0, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6) => wrpp2_inst_n_1, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5) => wrpp2_inst_n_2, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4) => wrpp2_inst_n_3, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3) => wrpp2_inst_n_4, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2) => wrpp2_inst_n_5, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1) => wrpp2_inst_n_6, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0) => wrpp2_inst_n_7, \reg_out_i_reg[7]_0\(7 downto 0) => rd_pntr_wr(7 downto 0), rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); \gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16\ port map ( D(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, wr_clk => wr_clk, wrst_busy => wrst_busy ); \gen_cdc_pntr.wpr_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 port map ( D(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), Q(1 downto 0) => curr_fwft_state(1 downto 0), \gen_pf_ic_rc.ram_empty_i_reg\(7 downto 0) => rd_pntr_ext(7 downto 0), \gen_pf_ic_rc.ram_empty_i_reg_0\(7) => rdpp1_inst_n_0, \gen_pf_ic_rc.ram_empty_i_reg_0\(6) => rdpp1_inst_n_1, \gen_pf_ic_rc.ram_empty_i_reg_0\(5) => rdpp1_inst_n_2, \gen_pf_ic_rc.ram_empty_i_reg_0\(4) => rdpp1_inst_n_3, \gen_pf_ic_rc.ram_empty_i_reg_0\(3) => rdpp1_inst_n_4, \gen_pf_ic_rc.ram_empty_i_reg_0\(2) => rdpp1_inst_n_5, \gen_pf_ic_rc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_6, \gen_pf_ic_rc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_7, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, rd_clk => rd_clk, rd_en => rd_en, \reg_out_i_reg[0]_0\ => \^rd_rst_busy\, \reg_out_i_reg[7]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \reg_out_i_reg[7]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \reg_out_i_reg[7]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \reg_out_i_reg[7]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \reg_out_i_reg[7]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \reg_out_i_reg[7]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \reg_out_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\ ); \gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18\ port map ( D(7 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(8 downto 1), DI(1) => rdp_inst_n_9, DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, S(6) => rdp_inst_n_19, S(5) => rdp_inst_n_20, S(4) => rdp_inst_n_21, S(3) => rdp_inst_n_22, S(2) => rdp_inst_n_23, S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, \grdc.rd_data_count_i_reg[7]\(0) => count_value_i(1), \grdc.rd_data_count_i_reg[7]_0\(5 downto 0) => rd_pntr_ext(6 downto 1), \grdc.rd_data_count_i_reg[8]\(0) => rdp_inst_n_10, rd_clk => rd_clk, \reg_out_i_reg[8]_0\ => \^rd_rst_busy\, \reg_out_i_reg[8]_1\(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ port map ( dest_clk => rd_clk, dest_out_bin(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0), src_clk => wr_clk, src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10\ port map ( dest_clk => rd_clk, dest_out_bin(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), src_clk => wr_clk, src_in_bin(7 downto 0) => wr_pntr_ext(7 downto 0) ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F380" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), I3 => \^empty\, O => empty_fwft_i0 ); \gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => empty_fwft_i0, Q => \^empty\, S => \^rd_rst_busy\ ); \gen_fwft.rdpp1_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 port map ( DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(1 downto 0) => count_value_i(1 downto 0), S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, SR(0) => \gen_fwft.count_rst\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \grdc.rd_data_count_i_reg[7]\(1 downto 0) => rd_pntr_ext(1 downto 0), \grdc.rd_data_count_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \grdc.rd_data_count_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(0) => src_in_bin00_out(1) ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gen_cdc_pntr.rpw_gray_reg_n_8\, Q => \^full\, S => wrst_busy ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(0), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(1), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(2), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(3), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(4), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(5), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(6), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(7), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \^prog_empty\, I1 => \^empty\, I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\, I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"01FF" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\, Q => \^prog_empty\, S => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(2), Q => diff_pntr_pf_q(2), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(3), Q => diff_pntr_pf_q(3), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(4), Q => diff_pntr_pf_q(4), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(5), Q => diff_pntr_pf_q(5), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(6), Q => diff_pntr_pf_q(6), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(7), Q => diff_pntr_pf_q(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(8), Q => diff_pntr_pf_q(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => diff_pntr_pf_q(3), I1 => diff_pntr_pf_q(2), I2 => diff_pntr_pf_q(6), I3 => diff_pntr_pf_q(7), I4 => diff_pntr_pf_q(4), I5 => diff_pntr_pf_q(5), O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1_inst_n_1, Q => \^prog_full\, S => wrst_busy ); \gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i0, Q => ram_empty_i, S => \^rd_rst_busy\ ); \gen_sdpram.xpm_memory_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1\ port map ( addra(7 downto 0) => wr_pntr_ext(7 downto 0), addrb(7 downto 0) => rd_pntr_ext(7 downto 0), clka => wr_clk, clkb => rd_clk, dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\, dina(7 downto 0) => din(7 downto 0), dinb(7 downto 0) => B"00000000", douta(7 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(7 downto 0), doutb(7 downto 0) => dout(7 downto 0), ena => wr_pntr_plus1_pf_carry, enb => rdp_inst_n_8, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', injectsbiterrb => '0', regcea => '0', regceb => \gen_fwft.ram_regout_en\, rsta => '0', rstb => \^rd_rst_busy\, sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\, sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\, sleep => sleep, wea(0) => '0', web(0) => '0' ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"62" ) port map ( I0 => curr_fwft_state(0), I1 => curr_fwft_state(1), I2 => rd_en, O => \gen_fwft.ram_regout_en\ ); \gof.overflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => overflow_i0, Q => overflow, R => '0' ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(1), Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(2), Q => rd_data_count(1), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(3), Q => rd_data_count(2), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(4), Q => rd_data_count(3), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(5), Q => rd_data_count(4), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(6), Q => rd_data_count(5), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(7), Q => rd_data_count(6), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(8), Q => rd_data_count(7), R => \grdc.rd_data_count_i0\ ); \guf.underflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => underflow_i0, Q => underflow, R => '0' ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(1), Q => wr_data_count(0), R => wrst_busy ); \gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(2), Q => wr_data_count(1), R => wrst_busy ); \gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(3), Q => wr_data_count(2), R => wrst_busy ); \gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(4), Q => wr_data_count(3), R => wrst_busy ); \gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(5), Q => wr_data_count(4), R => wrst_busy ); \gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(6), Q => wr_data_count(5), R => wrst_busy ); \gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(7), Q => wr_data_count(6), R => wrst_busy ); \gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(8), Q => wr_data_count(7), R => wrst_busy ); rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ port map ( D(7 downto 0) => diff_pntr_pe(7 downto 0), DI(0) => rdp_inst_n_9, Q(7 downto 0) => rd_pntr_ext(7 downto 0), S(4) => rdp_inst_n_19, S(3) => rdp_inst_n_20, S(2) => rdp_inst_n_21, S(1) => rdp_inst_n_22, S(0) => rdp_inst_n_23, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[7]_0\(0) => rdp_inst_n_10, \count_value_i_reg[8]_0\ => \^rd_rst_busy\, enb => rdp_inst_n_8, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, \grdc.rd_data_count_i_reg[7]\(1 downto 0) => count_value_i(1 downto 0), \grdc.rd_data_count_i_reg[8]\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, \grdc.rd_data_count_i_reg[8]\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, \grdc.rd_data_count_i_reg[8]\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, \grdc.rd_data_count_i_reg[8]\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, \grdc.rd_data_count_i_reg[8]\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, \grdc.rd_data_count_i_reg[8]\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, \grdc.rd_data_count_i_reg[8]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, \grdc.rd_data_count_i_reg[8]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(7) => rdp_inst_n_24, src_in_bin(6) => rdp_inst_n_25, src_in_bin(5) => rdp_inst_n_26, src_in_bin(4) => rdp_inst_n_27, src_in_bin(3) => rdp_inst_n_28, src_in_bin(2) => rdp_inst_n_29, src_in_bin(1) => rdp_inst_n_30, src_in_bin(0) => rdp_inst_n_31 ); rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ port map ( E(0) => rdp_inst_n_8, Q(7) => rdpp1_inst_n_0, Q(6) => rdpp1_inst_n_1, Q(5) => rdpp1_inst_n_2, Q(4) => rdpp1_inst_n_3, Q(3) => rdpp1_inst_n_4, Q(2) => rdpp1_inst_n_5, Q(1) => rdpp1_inst_n_6, Q(0) => rdpp1_inst_n_7, \count_value_i_reg[0]_0\ => \^rd_rst_busy\, \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0), ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en ); rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 port map ( Q(0) => diff_pntr_pf_q(8), \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ => rst_d1_inst_n_1, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ => \^full\, overflow_i0 => overflow_i0, prog_full => \^prog_full\, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wrst_busy => wrst_busy ); wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21\ port map ( D(7 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(8 downto 1), Q(8 downto 0) => wr_pntr_ext(8 downto 0), \count_value_i_reg[6]_0\ => \^full\, \gwdc.wr_data_count_i_reg[8]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, \gwdc.wr_data_count_i_reg[8]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, \gwdc.wr_data_count_i_reg[8]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, \gwdc.wr_data_count_i_reg[8]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, \gwdc.wr_data_count_i_reg[8]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, \gwdc.wr_data_count_i_reg[8]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, \gwdc.wr_data_count_i_reg[8]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, \gwdc.wr_data_count_i_reg[8]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, \gwdc.wr_data_count_i_reg[8]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22\ port map ( D(6 downto 0) => diff_pntr_pf_q0(8 downto 2), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), \count_value_i_reg[6]_0\ => \^full\, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7 downto 0) => rd_pntr_wr(7 downto 0), rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ port map ( Q(7) => wrpp2_inst_n_0, Q(6) => wrpp2_inst_n_1, Q(5) => wrpp2_inst_n_2, Q(4) => wrpp2_inst_n_3, Q(3) => wrpp2_inst_n_4, Q(2) => wrpp2_inst_n_5, Q(1) => wrpp2_inst_n_6, Q(0) => wrpp2_inst_n_7, \count_value_i_reg[6]_0\ => \^full\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); xpm_fifo_rst_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst port map ( Q(1 downto 0) => curr_fwft_state(1 downto 0), SR(0) => \grdc.rd_data_count_i0\, \count_value_i_reg[7]\ => \^full\, \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\, \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) => \gen_fwft.count_rst\, \guf.underflow_i_reg\ => \^empty\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, rst => rst, rst_d1 => rst_d1, underflow_i0 => underflow_i0, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wr_rst_busy => wr_rst_busy, wrst_busy => wrst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 49 downto 0 ); full : out STD_LOGIC; full_n : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 49 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "0"; attribute ECC_MODE : integer; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b0"; attribute EN_AF : string; attribute EN_AF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b0"; attribute EN_OF : string; attribute EN_OF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute EN_PE : string; attribute EN_PE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute EN_PF : string; attribute EN_PF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute EN_UF : string; attribute EN_UF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b0"; attribute FIFO_MEMORY_TYPE : integer; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 256; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 12800; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "xpm_fifo_base"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 128; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 2; attribute RD_MODE : integer; attribute RD_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 50; attribute READ_MODE : integer; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "0707"; attribute VERSION : integer; attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 50; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 6; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 3; attribute invalid : integer; attribute invalid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 0; attribute keep_hierarchy : string; attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is "soft"; attribute stage1_valid : integer; attribute stage1_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 2; attribute stage2_valid : integer; attribute stage2_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ : entity is 1; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ is signal \\ : STD_LOGIC; signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal diff_pntr_pe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 8 downto 2 ); signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 8 downto 2 ); signal \^empty\ : STD_LOGIC; signal empty_fwft_i0 : STD_LOGIC; signal \^full\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.rpw_gray_reg_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC; signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC; signal \gen_fwft.count_rst\ : STD_LOGIC; signal \gen_fwft.ram_regout_en\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC; signal \gen_fwft.rdpp1_inst_n_5\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC; signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC; signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \grdc.rd_data_count_i0\ : STD_LOGIC; signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal overflow_i0 : STD_LOGIC; signal \^prog_empty\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal ram_empty_i : STD_LOGIC; signal ram_empty_i0 : STD_LOGIC; signal rd_pntr_ext : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \^rd_rst_busy\ : STD_LOGIC; signal rdp_inst_n_10 : STD_LOGIC; signal rdp_inst_n_19 : STD_LOGIC; signal rdp_inst_n_20 : STD_LOGIC; signal rdp_inst_n_21 : STD_LOGIC; signal rdp_inst_n_22 : STD_LOGIC; signal rdp_inst_n_23 : STD_LOGIC; signal rdp_inst_n_24 : STD_LOGIC; signal rdp_inst_n_25 : STD_LOGIC; signal rdp_inst_n_26 : STD_LOGIC; signal rdp_inst_n_27 : STD_LOGIC; signal rdp_inst_n_28 : STD_LOGIC; signal rdp_inst_n_29 : STD_LOGIC; signal rdp_inst_n_30 : STD_LOGIC; signal rdp_inst_n_31 : STD_LOGIC; signal rdp_inst_n_8 : STD_LOGIC; signal rdp_inst_n_9 : STD_LOGIC; signal rdpp1_inst_n_0 : STD_LOGIC; signal rdpp1_inst_n_1 : STD_LOGIC; signal rdpp1_inst_n_2 : STD_LOGIC; signal rdpp1_inst_n_3 : STD_LOGIC; signal rdpp1_inst_n_4 : STD_LOGIC; signal rdpp1_inst_n_5 : STD_LOGIC; signal rdpp1_inst_n_6 : STD_LOGIC; signal rdpp1_inst_n_7 : STD_LOGIC; signal rst_d1 : STD_LOGIC; signal rst_d1_inst_n_1 : STD_LOGIC; signal src_in_bin00_out : STD_LOGIC_VECTOR ( 1 to 1 ); signal underflow_i0 : STD_LOGIC; signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 8 downto 1 ); signal wr_pntr_plus1_pf_carry : STD_LOGIC; signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 7 downto 0 ); signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal wrpp2_inst_n_0 : STD_LOGIC; signal wrpp2_inst_n_1 : STD_LOGIC; signal wrpp2_inst_n_2 : STD_LOGIC; signal wrpp2_inst_n_3 : STD_LOGIC; signal wrpp2_inst_n_4 : STD_LOGIC; signal wrpp2_inst_n_5 : STD_LOGIC; signal wrpp2_inst_n_6 : STD_LOGIC; signal wrpp2_inst_n_7 : STD_LOGIC; signal wrst_busy : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC; signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 49 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair126"; attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair126"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 3; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH : integer; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC : string; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 5; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 9; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 3; attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1; attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0; attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 8; attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY"; attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE"; attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair125"; attribute ADDR_WIDTH_A : integer; attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute ADDR_WIDTH_B : integer; attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute AUTO_SLEEP_TIME : integer; attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute BYTE_WRITE_WIDTH_A : integer; attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute BYTE_WRITE_WIDTH_B : integer; attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute CLOCKING_MODE : integer; attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft"; attribute MAX_NUM_CHAR : integer; attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE\ : boolean; attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true; attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer; attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer; attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 49; attribute \MEM.ADDRESS_SPACE_END\ : integer; attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 511; attribute \MEM.CORE_MEMORY_WIDTH\ : integer; attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute MEMORY_INIT_FILE : string; attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none"; attribute MEMORY_INIT_PARAM : string; attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is ""; attribute MEMORY_OPTIMIZATION : string; attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true"; attribute MEMORY_PRIMITIVE : integer; attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute MEMORY_SIZE : integer; attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 12800; attribute MEMORY_TYPE : integer; attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute MESSAGE_CONTROL : integer; attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute NUM_CHAR_LOC : integer; attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ECC_MODE : string; attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc"; attribute P_ENABLE_BYTE_WRITE_A : integer; attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_ENABLE_BYTE_WRITE_B : integer; attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_MAX_DEPTH_DATA : integer; attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 256; attribute P_MEMORY_OPT : string; attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes"; attribute P_MEMORY_PRIMITIVE : string; attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "block"; attribute P_MIN_WIDTH_DATA : integer; attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_A : integer; attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_B : integer; attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_ECC : integer; attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_MIN_WIDTH_DATA_LDW : integer; attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4; attribute P_MIN_WIDTH_DATA_SHFT : integer; attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_NUM_COLS_WRITE_A : integer; attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_COLS_WRITE_B : integer; attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_A : integer; attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_READ_B : integer; attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_A : integer; attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_NUM_ROWS_WRITE_B : integer; attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute P_SDP_WRITE_MODE : string; attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no"; attribute P_WIDTH_ADDR_LSB_READ_A : integer; attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_READ_B : integer; attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_A : integer; attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_LSB_WRITE_B : integer; attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute P_WIDTH_ADDR_READ_A : integer; attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_READ_B : integer; attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_A : integer; attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_ADDR_WRITE_B : integer; attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8; attribute P_WIDTH_COL_WRITE_A : integer; attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute P_WIDTH_COL_WRITE_B : integer; attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_DATA_WIDTH_A : integer; attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_DATA_WIDTH_B : integer; attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute READ_LATENCY_A : integer; attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_LATENCY_B : integer; attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute READ_RESET_VALUE_A : string; attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute READ_RESET_VALUE_B : string; attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0"; attribute RST_MODE_A : string; attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute RST_MODE_B : string; attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC"; attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_EMBEDDED_CONSTRAINT : integer; attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT : integer; attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute USE_MEM_INIT_MMI : integer; attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0; attribute WRITE_DATA_WIDTH_A : integer; attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute WRITE_DATA_WIDTH_B : integer; attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 50; attribute WRITE_MODE_A : integer; attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_MODE_B : integer; attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2; attribute WRITE_PROTECT : integer; attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1; attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE"; attribute rsta_loop_iter : integer; attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 52; attribute rstb_loop_iter : integer; attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 52; attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair125"; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; empty <= \^empty\; full <= \^full\; full_n <= \\; prog_empty <= \^prog_empty\; prog_full <= \^prog_full\; rd_rst_busy <= \^rd_rst_busy\; sbiterr <= \\; wr_ack <= \\; \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6A85" ) port map ( I0 => curr_fwft_state(0), I1 => rd_en, I2 => curr_fwft_state(1), I3 => ram_empty_i, O => \next_fwft_state__0\(0) ); \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), O => \next_fwft_state__0\(1) ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(0), Q => curr_fwft_state(0), R => \^rd_rst_busy\ ); \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \next_fwft_state__0\(1), Q => curr_fwft_state(1), R => \^rd_rst_busy\ ); GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7\ port map ( dest_clk => wr_clk, dest_out_bin(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), src_clk => rd_clk, src_in_bin(8) => rdp_inst_n_24, src_in_bin(7) => rdp_inst_n_25, src_in_bin(6) => rdp_inst_n_26, src_in_bin(5) => rdp_inst_n_27, src_in_bin(4) => rdp_inst_n_28, src_in_bin(3) => rdp_inst_n_29, src_in_bin(2) => rdp_inst_n_30, src_in_bin(1) => src_in_bin00_out(1), src_in_bin(0) => rdp_inst_n_31 ); \gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7\ port map ( dest_clk => wr_clk, dest_out_bin(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), src_clk => rd_clk, src_in_bin(7 downto 0) => rd_pntr_ext(7 downto 0) ); \gen_cdc_pntr.rpw_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 port map ( D(7 downto 0) => rd_pntr_wr_cdc(7 downto 0), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), d_out_reg => \gen_cdc_pntr.rpw_gray_reg_n_8\, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(7) => wrpp2_inst_n_0, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(6) => wrpp2_inst_n_1, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(5) => wrpp2_inst_n_2, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(4) => wrpp2_inst_n_3, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(3) => wrpp2_inst_n_4, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(2) => wrpp2_inst_n_5, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(1) => wrpp2_inst_n_6, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\(0) => wrpp2_inst_n_7, \reg_out_i_reg[7]_0\(7 downto 0) => rd_pntr_wr(7 downto 0), rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); \gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24\ port map ( D(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0), Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, wr_clk => wr_clk, wrst_busy => wrst_busy ); \gen_cdc_pntr.wpr_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 port map ( D(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), Q(1 downto 0) => curr_fwft_state(1 downto 0), \gen_pf_ic_rc.ram_empty_i_reg\(7 downto 0) => rd_pntr_ext(7 downto 0), \gen_pf_ic_rc.ram_empty_i_reg_0\(7) => rdpp1_inst_n_0, \gen_pf_ic_rc.ram_empty_i_reg_0\(6) => rdpp1_inst_n_1, \gen_pf_ic_rc.ram_empty_i_reg_0\(5) => rdpp1_inst_n_2, \gen_pf_ic_rc.ram_empty_i_reg_0\(4) => rdpp1_inst_n_3, \gen_pf_ic_rc.ram_empty_i_reg_0\(3) => rdpp1_inst_n_4, \gen_pf_ic_rc.ram_empty_i_reg_0\(2) => rdpp1_inst_n_5, \gen_pf_ic_rc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_6, \gen_pf_ic_rc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_7, ram_empty_i => ram_empty_i, ram_empty_i0 => ram_empty_i0, rd_clk => rd_clk, rd_en => rd_en, \reg_out_i_reg[0]_0\ => \^rd_rst_busy\, \reg_out_i_reg[7]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \reg_out_i_reg[7]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \reg_out_i_reg[7]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \reg_out_i_reg[7]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \reg_out_i_reg[7]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \reg_out_i_reg[7]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \reg_out_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\ ); \gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26\ port map ( D(7 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(8 downto 1), DI(1) => rdp_inst_n_9, DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, S(6) => rdp_inst_n_19, S(5) => rdp_inst_n_20, S(4) => rdp_inst_n_21, S(3) => rdp_inst_n_22, S(2) => rdp_inst_n_23, S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, \grdc.rd_data_count_i_reg[7]\(0) => count_value_i(1), \grdc.rd_data_count_i_reg[7]_0\(5 downto 0) => rd_pntr_ext(6 downto 1), \grdc.rd_data_count_i_reg[8]\(0) => rdp_inst_n_10, rd_clk => rd_clk, \reg_out_i_reg[8]_0\ => \^rd_rst_busy\, \reg_out_i_reg[8]_1\(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3\ port map ( dest_clk => rd_clk, dest_out_bin(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0), src_clk => wr_clk, src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0) ); \gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6\ port map ( dest_clk => rd_clk, dest_out_bin(7 downto 0) => wr_pntr_rd_cdc(7 downto 0), src_clk => wr_clk, src_in_bin(7 downto 0) => wr_pntr_ext(7 downto 0) ); \gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F380" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), I3 => \^empty\, O => empty_fwft_i0 ); \gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => empty_fwft_i0, Q => \^empty\, S => \^rd_rst_busy\ ); \gen_fwft.rdpp1_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 port map ( DI(0) => \gen_fwft.rdpp1_inst_n_5\, Q(1 downto 0) => count_value_i(1 downto 0), S(1) => \gen_fwft.rdpp1_inst_n_3\, S(0) => \gen_fwft.rdpp1_inst_n_4\, SR(0) => \gen_fwft.count_rst\, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \grdc.rd_data_count_i_reg[7]\(1 downto 0) => rd_pntr_ext(1 downto 0), \grdc.rd_data_count_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, \grdc.rd_data_count_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(0) => src_in_bin00_out(1) ); \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gen_cdc_pntr.rpw_gray_reg_n_8\, Q => \^full\, S => wrst_busy ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(0), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(1), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(2), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(3), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(4), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(5), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(6), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => diff_pntr_pe(7), Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, R => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \^prog_empty\, I1 => \^empty\, I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\, I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"01FF" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\, I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\, I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\, I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\, O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ ); \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\, Q => \^prog_empty\, S => \^rd_rst_busy\ ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(2), Q => diff_pntr_pf_q(2), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(3), Q => diff_pntr_pf_q(3), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(4), Q => diff_pntr_pf_q(4), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(5), Q => diff_pntr_pf_q(5), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(6), Q => diff_pntr_pf_q(6), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(7), Q => diff_pntr_pf_q(7), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => diff_pntr_pf_q0(8), Q => diff_pntr_pf_q(8), R => wrst_busy ); \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => diff_pntr_pf_q(3), I1 => diff_pntr_pf_q(2), I2 => diff_pntr_pf_q(6), I3 => diff_pntr_pf_q(7), I4 => diff_pntr_pf_q(4), I5 => diff_pntr_pf_q(5), O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ ); \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1_inst_n_1, Q => \^prog_full\, S => wrst_busy ); \gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i0, Q => ram_empty_i, S => \^rd_rst_busy\ ); \gen_sdpram.xpm_memory_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2\ port map ( addra(7 downto 0) => wr_pntr_ext(7 downto 0), addrb(7 downto 0) => rd_pntr_ext(7 downto 0), clka => wr_clk, clkb => rd_clk, dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\, dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\, dina(49 downto 0) => din(49 downto 0), dinb(49 downto 0) => B"00000000000000000000000000000000000000000000000000", douta(49 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(49 downto 0), doutb(49 downto 0) => dout(49 downto 0), ena => wr_pntr_plus1_pf_carry, enb => rdp_inst_n_8, injectdbiterra => '0', injectdbiterrb => '0', injectsbiterra => '0', injectsbiterrb => '0', regcea => '0', regceb => \gen_fwft.ram_regout_en\, rsta => '0', rstb => \^rd_rst_busy\, sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\, sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\, sleep => sleep, wea(0) => '0', web(0) => '0' ); \gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"62" ) port map ( I0 => curr_fwft_state(0), I1 => curr_fwft_state(1), I2 => rd_en, O => \gen_fwft.ram_regout_en\ ); \gof.overflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => overflow_i0, Q => overflow, R => '0' ); \grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(1), Q => rd_data_count(0), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(2), Q => rd_data_count(1), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(3), Q => rd_data_count(2), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(4), Q => rd_data_count(3), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(5), Q => rd_data_count(4), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(6), Q => rd_data_count(5), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(7), Q => rd_data_count(6), R => \grdc.rd_data_count_i0\ ); \grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rd_clk, CE => '1', D => \grdc.diff_wr_rd_pntr_rdc\(8), Q => rd_data_count(7), R => \grdc.rd_data_count_i0\ ); \guf.underflow_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => underflow_i0, Q => underflow, R => '0' ); \gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(1), Q => wr_data_count(0), R => wrst_busy ); \gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(2), Q => wr_data_count(1), R => wrst_busy ); \gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(3), Q => wr_data_count(2), R => wrst_busy ); \gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(4), Q => wr_data_count(3), R => wrst_busy ); \gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(5), Q => wr_data_count(4), R => wrst_busy ); \gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(6), Q => wr_data_count(5), R => wrst_busy ); \gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(7), Q => wr_data_count(6), R => wrst_busy ); \gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => wr_clk, CE => '1', D => \gwdc.diff_wr_rd_pntr1_out\(8), Q => wr_data_count(7), R => wrst_busy ); rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28\ port map ( D(7 downto 0) => diff_pntr_pe(7 downto 0), DI(0) => rdp_inst_n_9, Q(7 downto 0) => rd_pntr_ext(7 downto 0), S(4) => rdp_inst_n_19, S(3) => rdp_inst_n_20, S(2) => rdp_inst_n_21, S(1) => rdp_inst_n_22, S(0) => rdp_inst_n_23, \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0), \count_value_i_reg[7]_0\(0) => rdp_inst_n_10, \count_value_i_reg[8]_0\ => \^rd_rst_busy\, enb => rdp_inst_n_8, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\, \grdc.rd_data_count_i_reg[7]\(1 downto 0) => count_value_i(1 downto 0), \grdc.rd_data_count_i_reg[8]\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\, \grdc.rd_data_count_i_reg[8]\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\, \grdc.rd_data_count_i_reg[8]\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\, \grdc.rd_data_count_i_reg[8]\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\, \grdc.rd_data_count_i_reg[8]\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\, \grdc.rd_data_count_i_reg[8]\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\, \grdc.rd_data_count_i_reg[8]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\, \grdc.rd_data_count_i_reg[8]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, src_in_bin(7) => rdp_inst_n_24, src_in_bin(6) => rdp_inst_n_25, src_in_bin(5) => rdp_inst_n_26, src_in_bin(4) => rdp_inst_n_27, src_in_bin(3) => rdp_inst_n_28, src_in_bin(2) => rdp_inst_n_29, src_in_bin(1) => rdp_inst_n_30, src_in_bin(0) => rdp_inst_n_31 ); rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29\ port map ( E(0) => rdp_inst_n_8, Q(7) => rdpp1_inst_n_0, Q(6) => rdpp1_inst_n_1, Q(5) => rdpp1_inst_n_2, Q(4) => rdpp1_inst_n_3, Q(3) => rdpp1_inst_n_4, Q(2) => rdpp1_inst_n_5, Q(1) => rdpp1_inst_n_6, Q(0) => rdpp1_inst_n_7, \count_value_i_reg[0]_0\ => \^rd_rst_busy\, \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0), ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en ); rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 port map ( Q(0) => diff_pntr_pf_q(8), \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ => rst_d1_inst_n_1, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0\ => \^full\, overflow_i0 => overflow_i0, prog_full => \^prog_full\, rst => rst, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wrst_busy => wrst_busy ); wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31\ port map ( D(7 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(8 downto 1), Q(8 downto 0) => wr_pntr_ext(8 downto 0), \count_value_i_reg[6]_0\ => \^full\, \gwdc.wr_data_count_i_reg[8]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\, \gwdc.wr_data_count_i_reg[8]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\, \gwdc.wr_data_count_i_reg[8]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\, \gwdc.wr_data_count_i_reg[8]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\, \gwdc.wr_data_count_i_reg[8]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\, \gwdc.wr_data_count_i_reg[8]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\, \gwdc.wr_data_count_i_reg[8]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\, \gwdc.wr_data_count_i_reg[8]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\, \gwdc.wr_data_count_i_reg[8]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32\ port map ( D(6 downto 0) => diff_pntr_pf_q0(8 downto 2), Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1), \count_value_i_reg[6]_0\ => \^full\, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7 downto 0) => rd_pntr_wr(7 downto 0), rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33\ port map ( Q(7) => wrpp2_inst_n_0, Q(6) => wrpp2_inst_n_1, Q(5) => wrpp2_inst_n_2, Q(4) => wrpp2_inst_n_3, Q(3) => wrpp2_inst_n_4, Q(2) => wrpp2_inst_n_5, Q(1) => wrpp2_inst_n_6, Q(0) => wrpp2_inst_n_7, \count_value_i_reg[6]_0\ => \^full\, rst_d1 => rst_d1, wr_clk => wr_clk, wr_en => wr_en, wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry, wrst_busy => wrst_busy ); xpm_fifo_rst_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ port map ( Q(1 downto 0) => curr_fwft_state(1 downto 0), SR(0) => \grdc.rd_data_count_i0\, \count_value_i_reg[7]\ => \^full\, \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\, \gen_rst_ic.fifo_rd_rst_ic_reg_1\(0) => \gen_fwft.count_rst\, \guf.underflow_i_reg\ => \^empty\, ram_empty_i => ram_empty_i, rd_clk => rd_clk, rd_en => rd_en, rst => rst, rst_d1 => rst_d1, underflow_i0 => underflow_i0, wr_clk => wr_clk, wr_en => wr_en, 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Tr0FKItnhLv1XJt0SALidcTtwqW9LKGlijz7gCvs/RdMRH9UyA/7z/5oAaJmt/5+iqB9/fSJl4Na tl+yamHbP90eNFFZp54MberZx0OHEL05nieRjkJqMZ3YcinE0SUJyvB137ZV9zYP+KWCO8rAxK50 gNEPuOe1MD98MDaFydHFaw/NoUHallR2MY4tbHhw6kigKtrEGiYcy3x7WDeFdRLXDCHYwHxc4w+4 uGxGsCbsZFAov/TTRomkuLFP/GfZv2EoIBDnGa3EL4brrG2B37gHGen2kbNCLpW88gjL4Eg4ZIF0 09mxaPZGe0XXIdYRnhNX5Dpcn69OpR/JloGLDbdbeqIn1IFkFDEibfW6xbpYf4VPQVYNl3TeiVDI 5zFLblIMK9L6AyHq5q1bCKXkFlwwPhd9LG1P+Ea8PaI5OBhQE5dpD6P/A1E+6UROXoWKLwJlLENm JAtaSIS29m0j0nyr0F5ic+nHI2cgu6MHYdrMFl7hNEFIzVG4Lz1A8NtjPcZe461fElBAe9srHCHT FvjZTnoBH6Bq+EzlN2Is+GWZdnwx5rzGMBIl6JcR6m4ahXWVtpZ4PnS0kz1rUakWv/TNtUqXbPJb zE7ZHGScfwFmvZbrr0bQa3OPtfIo1+JU3/vnMU+PnOKSBpTKhgxislLTFz5MEazHTFAF30VvE4i/ o2sYNwpIOJFRSu4k/0u7vXwArDly8/QtnZSv1xXwtvFrXG9HLQDFkfefDyxuxvc8bECJsWNALd3f YV+6J0QKVuCrCoSLVOBdkurNBkk3/rZ2U99VAKTKC32nRUWhm/axymMKEoDJjWy5yIvLWKk2cYeK sJQr2jPGA/hD4ytBe5B0YUZ1LUNDao7Xy2/wLe4JCUQHzf6dQBMWt2ggDAmEcaL5Skl+ `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 49 downto 0 ); full : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 49 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute CDC_SYNC_STAGES : integer; attribute CDC_SYNC_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 3; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "0"; attribute ECC_MODE : string; attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "no_ecc"; attribute EN_ADV_FEATURE_ASYNC : string; attribute EN_ADV_FEATURE_ASYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "16'b0000011100000111"; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "block"; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 1; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 128; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute P_ECC_MODE : integer; attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute P_FIFO_MEMORY_TYPE : integer; attribute P_FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 2; attribute P_READ_MODE : integer; attribute P_READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 1; attribute P_WAKEUP_TIME : integer; attribute P_WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 2; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 50; attribute READ_MODE : string; attribute READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "fwft"; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "0707"; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 50; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "TRUE"; attribute dont_touch : string; attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "true"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "true"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async is signal \\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC; attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0"; attribute ECC_MODE_integer : integer; attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_AF : string; attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_OF : string; attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PE : string; attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PF : string; attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_UF : string; attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute FIFO_MEMORY_TYPE_integer : integer; attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 12800; attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 128; attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute RD_MODE : integer; attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 50; attribute READ_MODE_integer : integer; attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707"; attribute VERSION : integer; attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 50; attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6; attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute invalid : integer; attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute stage1_valid : integer; attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute stage2_valid : integer; attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; sbiterr <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gnuram_async_fifo.xpm_fifo_base_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base port map ( almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\, almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\, data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\, dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\, din(49 downto 0) => din(49 downto 0), dout(49 downto 0) => dout(49 downto 0), empty => empty, full => full, full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\, injectdbiterr => '0', injectsbiterr => '0', overflow => overflow, prog_empty => prog_empty, prog_full => prog_full, rd_clk => rd_clk, rd_data_count(7 downto 0) => rd_data_count(7 downto 0), rd_en => rd_en, rd_rst_busy => rd_rst_busy, rst => rst, sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\, sleep => sleep, underflow => underflow, wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\, wr_clk => wr_clk, wr_data_count(7 downto 0) => wr_data_count(7 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 40 downto 0 ); full : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 40 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute CDC_SYNC_STAGES : integer; attribute CDC_SYNC_STAGES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 3; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "0"; attribute ECC_MODE : string; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "no_ecc"; attribute EN_ADV_FEATURE_ASYNC : string; attribute EN_ADV_FEATURE_ASYNC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "16'b0000011100000111"; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "block"; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 512; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "xpm_fifo_async"; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 384; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute P_ECC_MODE : integer; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute P_FIFO_MEMORY_TYPE : integer; attribute P_FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 2; attribute P_READ_MODE : integer; attribute P_READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 1; attribute P_WAKEUP_TIME : integer; attribute P_WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 2; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 9; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 41; attribute READ_MODE : string; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "fwft"; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "0707"; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 0; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 41; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "TRUE"; attribute dont_touch : string; attribute dont_touch of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "true"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ : entity is "true"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0\ is signal \\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC; attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0"; attribute ECC_MODE_integer : integer; attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_AF : string; attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_OF : string; attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PE : string; attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PF : string; attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_UF : string; attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute FIFO_MEMORY_TYPE_integer : integer; attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 512; attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 20992; attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 512; attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 507; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 382; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 507; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 384; attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute RD_LATENCY : integer; attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute RD_MODE : integer; attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 41; attribute READ_MODE_integer : integer; attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707"; attribute VERSION : integer; attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 41; attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6; attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute invalid : integer; attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute stage1_valid : integer; attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute stage2_valid : integer; attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; sbiterr <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ port map ( almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\, almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\, data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\, dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\, din(40 downto 0) => din(40 downto 0), dout(40 downto 0) => dout(40 downto 0), empty => empty, full => full, full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\, injectdbiterr => '0', injectsbiterr => '0', overflow => overflow, prog_empty => prog_empty, prog_full => prog_full, rd_clk => rd_clk, rd_data_count(8 downto 0) => rd_data_count(8 downto 0), rd_en => rd_en, rd_rst_busy => rd_rst_busy, rst => rst, sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\, sleep => sleep, underflow => underflow, wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\, wr_clk => wr_clk, wr_data_count(8 downto 0) => wr_data_count(8 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 40 downto 0 ); full : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 40 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute CDC_SYNC_STAGES : integer; attribute CDC_SYNC_STAGES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 3; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "0"; attribute ECC_MODE : string; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "no_ecc"; attribute EN_ADV_FEATURE_ASYNC : string; attribute EN_ADV_FEATURE_ASYNC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "16'b0000011100000111"; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "block"; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 512; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "xpm_fifo_async"; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 384; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute P_ECC_MODE : integer; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute P_FIFO_MEMORY_TYPE : integer; attribute P_FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 2; attribute P_READ_MODE : integer; attribute P_READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 1; attribute P_WAKEUP_TIME : integer; attribute P_WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 2; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 9; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 41; attribute READ_MODE : string; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "fwft"; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "0707"; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 0; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 41; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is 9; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "TRUE"; attribute dont_touch : string; attribute dont_touch of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "true"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ : entity is "true"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1\ is signal \\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC; attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0"; attribute ECC_MODE_integer : integer; attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_AF : string; attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_OF : string; attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PE : string; attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PF : string; attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_UF : string; attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute FIFO_MEMORY_TYPE_integer : integer; attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 512; attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 20992; attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 512; attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 507; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 382; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 507; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 384; attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute RD_LATENCY : integer; attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute RD_MODE : integer; attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 41; attribute READ_MODE_integer : integer; attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707"; attribute VERSION : integer; attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 41; attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6; attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute invalid : integer; attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute stage1_valid : integer; attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute stage2_valid : integer; attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; sbiterr <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1\ port map ( almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\, almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\, data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\, dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\, din(40 downto 0) => din(40 downto 0), dout(40 downto 0) => dout(40 downto 0), empty => empty, full => full, full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\, injectdbiterr => '0', injectsbiterr => '0', overflow => overflow, prog_empty => prog_empty, prog_full => prog_full, rd_clk => rd_clk, rd_data_count(8 downto 0) => rd_data_count(8 downto 0), rd_en => rd_en, rd_rst_busy => rd_rst_busy, rst => rst, sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\, sleep => sleep, underflow => underflow, wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\, wr_clk => wr_clk, wr_data_count(8 downto 0) => wr_data_count(8 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); full : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute CDC_SYNC_STAGES : integer; attribute CDC_SYNC_STAGES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 3; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "0"; attribute ECC_MODE : string; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "no_ecc"; attribute EN_ADV_FEATURE_ASYNC : string; attribute EN_ADV_FEATURE_ASYNC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "16'b0000011100000111"; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "distributed"; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "xpm_fifo_async"; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 128; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute P_ECC_MODE : integer; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute P_FIFO_MEMORY_TYPE : integer; attribute P_FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 1; attribute P_READ_MODE : integer; attribute P_READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 1; attribute P_WAKEUP_TIME : integer; attribute P_WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 2; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8; attribute READ_MODE : string; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "fwft"; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "0707"; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "TRUE"; attribute dont_touch : string; attribute dont_touch of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "true"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "true"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ is signal \\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC; attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0"; attribute ECC_MODE_integer : integer; attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_AF : string; attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_OF : string; attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PE : string; attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PF : string; attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_UF : string; attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute FIFO_MEMORY_TYPE_integer : integer; attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2048; attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 128; attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute RD_MODE : integer; attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute READ_MODE_integer : integer; attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707"; attribute VERSION : integer; attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute invalid : integer; attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute stage1_valid : integer; attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute stage2_valid : integer; attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; sbiterr <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1\ port map ( almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\, almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\, data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\, dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), empty => empty, full => full, full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\, injectdbiterr => '0', injectsbiterr => '0', overflow => overflow, prog_empty => prog_empty, prog_full => prog_full, rd_clk => rd_clk, rd_data_count(7 downto 0) => rd_data_count(7 downto 0), rd_en => rd_en, rd_rst_busy => rd_rst_busy, rst => rst, sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\, sleep => sleep, underflow => underflow, wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\, wr_clk => wr_clk, wr_data_count(7 downto 0) => wr_data_count(7 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ is port ( sleep : in STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 49 downto 0 ); full : out STD_LOGIC; prog_full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); overflow : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 49 downto 0 ); empty : out STD_LOGIC; prog_empty : out STD_LOGIC; rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 ); underflow : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; almost_empty : out STD_LOGIC; data_valid : out STD_LOGIC; injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC ); attribute CASCADE_HEIGHT : integer; attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute CDC_SYNC_STAGES : integer; attribute CDC_SYNC_STAGES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 3; attribute DOUT_RESET_VALUE : string; attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "0"; attribute ECC_MODE : string; attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "no_ecc"; attribute EN_ADV_FEATURE_ASYNC : string; attribute EN_ADV_FEATURE_ASYNC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "16'b0000011100000111"; attribute FIFO_MEMORY_TYPE : string; attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "block"; attribute FIFO_READ_LATENCY : integer; attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute FIFO_WRITE_DEPTH : integer; attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 256; attribute FULL_RESET_VALUE : integer; attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "xpm_fifo_async"; attribute PROG_EMPTY_THRESH : integer; attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 10; attribute PROG_FULL_THRESH : integer; attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 128; attribute P_COMMON_CLOCK : integer; attribute P_COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute P_ECC_MODE : integer; attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute P_FIFO_MEMORY_TYPE : integer; attribute P_FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 2; attribute P_READ_MODE : integer; attribute P_READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 1; attribute P_WAKEUP_TIME : integer; attribute P_WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 2; attribute RD_DATA_COUNT_WIDTH : integer; attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 8; attribute READ_DATA_WIDTH : integer; attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 50; attribute READ_MODE : string; attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "fwft"; attribute RELATED_CLOCKS : integer; attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute USE_ADV_FEATURES : string; attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "0707"; attribute WAKEUP_TIME : integer; attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 0; attribute WRITE_DATA_WIDTH : integer; attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 50; attribute WR_DATA_COUNT_WIDTH : integer; attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is 8; attribute XPM_MODULE : string; attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "TRUE"; attribute dont_touch : string; attribute dont_touch of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "true"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ : entity is "true"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1\ is signal \\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC; signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC; attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute CDC_DEST_SYNC_FF : integer; attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute COMMON_CLOCK : integer; attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0"; attribute ECC_MODE_integer : integer; attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute ENABLE_ECC : integer; attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute EN_ADV_FEATURE : string; attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111"; attribute EN_AE : string; attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_AF : string; attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_DVLD : string; attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_OF : string; attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PE : string; attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_PF : string; attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_RDC : string; attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_UF : string; attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute EN_WACK : string; attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute EN_WDC : string; attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute FG_EQ_ASYM_DOUT : string; attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0"; attribute FIFO_MEMORY_TYPE_integer : integer; attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_MEM_TYPE : integer; attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute FIFO_READ_DEPTH : integer; attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute FIFO_SIZE : integer; attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 12800; attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256; attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute FULL_RST_VAL : string; attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft"; attribute PE_THRESH_ADJ : integer; attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PE_THRESH_MAX : integer; attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PE_THRESH_MIN : integer; attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5; attribute PF_THRESH_ADJ : integer; attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 126; attribute PF_THRESH_MAX : integer; attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251; attribute PF_THRESH_MIN : integer; attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10; attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 128; attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute RD_DC_WIDTH_EXT : integer; attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute RD_LATENCY : integer; attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute RD_MODE : integer; attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RD_PNTR_WIDTH : integer; attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 50; attribute READ_MODE_integer : integer; attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute READ_MODE_LL : integer; attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute REMOVE_WR_RD_PROT_LOGIC : integer; attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707"; attribute VERSION : integer; attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WIDTH_RATIO : integer; attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 50; attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_DC_WIDTH_EXT : integer; attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9; attribute WR_DEPTH_LOG : integer; attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_PNTR_WIDTH : integer; attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8; attribute WR_RD_RATIO : integer; attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute WR_WIDTH_LOG : integer; attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6; attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE"; attribute both_stages_valid : integer; attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3; attribute invalid : integer; attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0; attribute stage1_valid : integer; attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2; attribute stage2_valid : integer; attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1; begin almost_empty <= \\; almost_full <= \\; data_valid <= \\; dbiterr <= \\; sbiterr <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1\ port map ( almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\, almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\, data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\, dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\, din(49 downto 0) => din(49 downto 0), dout(49 downto 0) => dout(49 downto 0), empty => empty, full => full, full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\, injectdbiterr => '0', injectsbiterr => '0', overflow => overflow, prog_empty => prog_empty, prog_full => prog_full, rd_clk => rd_clk, rd_data_count(7 downto 0) => rd_data_count(7 downto 0), rd_en => rd_en, rd_rst_busy => rd_rst_busy, rst => rst, sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\, sleep => sleep, underflow => underflow, wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\, wr_clk => wr_clk, wr_data_count(7 downto 0) => wr_data_count(7 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block 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`protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( m_aclk : in STD_LOGIC; m_aresetn : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC; axi_c2c_s2m_intr_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_c2c_m2s_intr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); axi_c2c_phy_clk : in STD_LOGIC; axi_c2c_aurora_channel_up : in STD_LOGIC; axi_c2c_aurora_tx_tready : in STD_LOGIC; axi_c2c_aurora_tx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); axi_c2c_aurora_tx_tvalid : out STD_LOGIC; axi_c2c_aurora_rx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); axi_c2c_aurora_rx_tvalid : in STD_LOGIC; aurora_do_cc : out STD_LOGIC; aurora_pma_init_in : in STD_LOGIC; aurora_init_clk : in STD_LOGIC; aurora_pma_init_out : out STD_LOGIC; aurora_mmcm_not_locked : in STD_LOGIC; aurora_reset_pb : out STD_LOGIC; axi_c2c_config_error_out : out STD_LOGIC; axi_c2c_link_status_out : out STD_LOGIC; axi_c2c_multi_bit_error_out : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_chip2chip_64B66B,axi_chip2chip_v5_0_9,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_chip2chip_v5_0_9,Vivado 2020.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal \\ : STD_LOGIC; signal \^axi_c2c_aurora_tx_tdata\ : STD_LOGIC_VECTOR ( 63 downto 0 ); signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_axi_c2c_config_error_out_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_link_error_out_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_aclk_out_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_lite_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_lite_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_lite_bready_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_lite_rready_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_lite_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_lite_arready_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_lite_awready_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_lite_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_lite_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_lite_wready_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_inst_axi_c2c_aurora_tx_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 62 to 62 ); signal NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 ); signal NLW_inst_m_axi_lite_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_m_axi_lite_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_lite_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_m_axi_lite_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_lite_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_m_axi_lite_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_s_axi_lite_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_s_axi_lite_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_s_axi_lite_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute ADDR_MUX_RATIO : integer; attribute ADDR_MUX_RATIO of inst : label is 1; attribute ADDR_MUX_RATIO_ID_WID_0_TO_12 : integer; attribute ADDR_MUX_RATIO_ID_WID_0_TO_12 of inst : label is 1; attribute AFIFO_DATA_SIZE : integer; attribute AFIFO_DATA_SIZE of inst : label is 50; attribute AFIFO_DATA_SIZE_M2 : integer; attribute AFIFO_DATA_SIZE_M2 of inst : label is 0; attribute AFIFO_DATA_SIZE_M3 : integer; attribute AFIFO_DATA_SIZE_M3 of inst : label is 2; attribute AFIFO_DATA_SIZE_M4 : integer; attribute AFIFO_DATA_SIZE_M4 of inst : label is 2; attribute AFIFO_TIE_WIDTH : integer; attribute AFIFO_TIE_WIDTH of inst : label is 1; attribute AFIFO_WIDTH : integer; attribute AFIFO_WIDTH of inst : label is 50; attribute AR_CH_FC : integer; attribute AR_CH_FC of inst : label is 128; attribute AR_CH_FIFO_DEPTH : integer; attribute AR_CH_FIFO_DEPTH of inst : label is 256; attribute AR_CH_PTR_WIDTH : integer; attribute AR_CH_PTR_WIDTH of inst : label is 8; attribute AWB_FC_WIDTH : integer; attribute AWB_FC_WIDTH of inst : label is 2; attribute AW_CH_FC : integer; attribute AW_CH_FC of inst : label is 128; attribute AW_CH_FIFO_DEPTH : integer; attribute AW_CH_FIFO_DEPTH of inst : label is 256; attribute AW_CH_PTR_WIDTH : integer; attribute AW_CH_PTR_WIDTH of inst : label is 8; attribute AXILITE_WIDTH : integer; attribute AXILITE_WIDTH of inst : label is 20; attribute BFIFO_DATA_SIZE : integer; attribute BFIFO_DATA_SIZE of inst : label is 8; attribute BFIFO_WIDTH : integer; attribute BFIFO_WIDTH of inst : label is 8; attribute BR_CH_FC : integer; attribute BR_CH_FC of inst : label is 128; attribute BR_CH_FIFO_DEPTH : integer; attribute BR_CH_FIFO_DEPTH of inst : label is 256; attribute BR_CH_PTR_WIDTH : integer; attribute BR_CH_PTR_WIDTH of inst : label is 8; attribute C_AURORA_WIDTH : integer; attribute C_AURORA_WIDTH of inst : label is 64; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_BRST_WIDTH : integer; attribute C_AXI_BRST_WIDTH of inst : label is 2; attribute C_AXI_BUS_TYPE : integer; attribute C_AXI_BUS_TYPE of inst : label is 0; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 6; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of inst : label is 8; attribute C_AXI_LITE_ADDR_WIDTH : integer; attribute C_AXI_LITE_ADDR_WIDTH of inst : label is 32; attribute C_AXI_LITE_DATA_WIDTH : integer; attribute C_AXI_LITE_DATA_WIDTH of inst : label is 32; attribute C_AXI_LITE_PROT_WIDTH : integer; attribute C_AXI_LITE_PROT_WIDTH of inst : label is 2; attribute C_AXI_LITE_RESP_WIDTH : integer; attribute C_AXI_LITE_RESP_WIDTH of inst : label is 2; attribute C_AXI_LITE_STB_WIDTH : integer; attribute C_AXI_LITE_STB_WIDTH of inst : label is 4; attribute C_AXI_RESP_WIDTH : integer; attribute C_AXI_RESP_WIDTH of inst : label is 2; attribute C_AXI_SIZE_WIDTH : integer; attribute C_AXI_SIZE_WIDTH of inst : label is 3; attribute C_AXI_SIZE_WIDTH_INTERNAL : integer; attribute C_AXI_SIZE_WIDTH_INTERNAL of inst : label is 2; attribute C_AXI_STB_WIDTH : integer; attribute C_AXI_STB_WIDTH of inst : label is 4; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 4; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of inst : label is 0; attribute C_DISABLE_CLK_SHIFT : integer; attribute C_DISABLE_CLK_SHIFT of inst : label is 0; attribute C_DISABLE_DESKEW : integer; attribute C_DISABLE_DESKEW of inst : label is 0; attribute C_ECC_ENABLE : integer; attribute C_ECC_ENABLE of inst : label is 1; attribute C_EN_AXI_LINK_HNDLR : integer; attribute C_EN_AXI_LINK_HNDLR of inst : label is 0; attribute C_EN_LEGACY_MODE : integer; attribute C_EN_LEGACY_MODE of inst : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "kintexu"; attribute C_FIFO_DEPTH_LH : integer; attribute C_FIFO_DEPTH_LH of inst : label is 256; attribute C_INCLUDE_AXILITE : integer; attribute C_INCLUDE_AXILITE of inst : label is 0; attribute C_INSTANCE : string; attribute C_INSTANCE of inst : label is "axi_c2c"; attribute C_INTERFACE_MODE : integer; attribute C_INTERFACE_MODE of inst : label is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of inst : label is 2; attribute C_INTERRUPT_WIDTH : integer; attribute C_INTERRUPT_WIDTH of inst : label is 4; attribute C_MASTER_FPGA : integer; attribute C_MASTER_FPGA of inst : label is 0; attribute C_NUM_OF_IO : integer; attribute C_NUM_OF_IO of inst : label is 20; attribute C_PHY_SELECT : integer; attribute C_PHY_SELECT of inst : label is 1; attribute C_RD_CNTR_WIDTH : integer; attribute C_RD_CNTR_WIDTH of inst : label is 8; attribute C_SELECTIO_DDR : integer; attribute C_SELECTIO_DDR of inst : label is 0; attribute C_SELECTIO_PHY_CLK : integer; attribute C_SELECTIO_PHY_CLK of inst : label is 100; attribute C_SELECTIO_WIDTH : integer; attribute C_SELECTIO_WIDTH of inst : label is 9; attribute C_SIMULATION : integer; attribute C_SIMULATION of inst : label is 0; attribute C_SYNC_STAGE : integer; attribute C_SYNC_STAGE of inst : label is 3; attribute C_USE_DIFF_CLK : integer; attribute C_USE_DIFF_CLK of inst : label is 0; attribute C_USE_DIFF_IO : integer; attribute C_USE_DIFF_IO of inst : label is 0; attribute C_WIDTH_CONVERSION : integer; attribute C_WIDTH_CONVERSION of inst : label is 1; attribute C_WR_CNTR_WIDTH : integer; attribute C_WR_CNTR_WIDTH of inst : label is 8; attribute DATA_MUX_RATIO : integer; attribute DATA_MUX_RATIO of inst : label is 1; attribute DATA_MUX_RATIO_ID_WID_0_TO_12 : integer; attribute DATA_MUX_RATIO_ID_WID_0_TO_12 of inst : label is 1; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute EN_ECC : integer; attribute EN_ECC of inst : label is 1; attribute PHY_CTRL_WIDTH : integer; attribute PHY_CTRL_WIDTH of inst : label is 3; attribute PHY_DATA_WIDTH : integer; attribute PHY_DATA_WIDTH of inst : label is 64; attribute RB_FC_WIDTH : integer; attribute RB_FC_WIDTH of inst : label is 3; attribute RFIFO_DATA_SIZE : integer; attribute RFIFO_DATA_SIZE of inst : label is 41; attribute RFIFO_DATA_SIZE_M2 : integer; attribute RFIFO_DATA_SIZE_M2 of inst : label is 1; attribute RFIFO_DATA_SIZE_M3 : integer; attribute RFIFO_DATA_SIZE_M3 of inst : label is 2; attribute RFIFO_DATA_SIZE_M4 : integer; attribute RFIFO_DATA_SIZE_M4 of inst : label is 1; attribute RFIFO_TIE_WIDTH : integer; attribute RFIFO_TIE_WIDTH of inst : label is 1; attribute RFIFO_WIDTH : integer; attribute RFIFO_WIDTH of inst : label is 41; attribute TDM_ID_WIDTH : integer; attribute TDM_ID_WIDTH of inst : label is 2; attribute TDM_VAL_BITS : integer; attribute TDM_VAL_BITS of inst : label is 1; attribute WFIFO_DATA_SIZE : integer; attribute WFIFO_DATA_SIZE of inst : label is 41; attribute WFIFO_DATA_SIZE_M2 : integer; attribute WFIFO_DATA_SIZE_M2 of inst : label is 1; attribute WFIFO_DATA_SIZE_M3 : integer; attribute WFIFO_DATA_SIZE_M3 of inst : label is 2; attribute WFIFO_DATA_SIZE_M4 : integer; attribute WFIFO_DATA_SIZE_M4 of inst : label is 1; attribute WFIFO_TIE_WIDTH : integer; attribute WFIFO_TIE_WIDTH of inst : label is 1; attribute WFIFO_WIDTH : integer; attribute WFIFO_WIDTH of inst : label is 41; attribute is_du_within_envelope : string; attribute is_du_within_envelope of inst : label is "true"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aurora_init_clk : signal is "xilinx.com:signal:clock:1.0 INIT_CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aurora_init_clk : signal is "XIL_INTERFACENAME INIT_CLK, ASSOCIATED_RESET aurora_pma_init_out, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; attribute X_INTERFACE_INFO of aurora_mmcm_not_locked : signal is "xilinx.com:signal:reset:1.0 AURORA_MMCM_NOT_LOCKED RST"; attribute X_INTERFACE_PARAMETER of aurora_mmcm_not_locked : signal is "XIL_INTERFACENAME AURORA_MMCM_NOT_LOCKED, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; attribute X_INTERFACE_INFO of aurora_pma_init_in : signal is "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_IN RST"; attribute X_INTERFACE_PARAMETER of aurora_pma_init_in : signal is "XIL_INTERFACENAME AURORA_PMA_INIT_IN, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; attribute X_INTERFACE_INFO of aurora_pma_init_out : signal is "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_OUT RST"; attribute X_INTERFACE_PARAMETER of aurora_pma_init_out : signal is "XIL_INTERFACENAME AURORA_PMA_INIT_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; attribute X_INTERFACE_INFO of aurora_reset_pb : signal is "xilinx.com:signal:reset:1.0 AURORA_RST_OUT RST"; attribute X_INTERFACE_PARAMETER of aurora_reset_pb : signal is "XIL_INTERFACENAME AURORA_RST_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; attribute X_INTERFACE_INFO of axi_c2c_aurora_rx_tvalid : signal is "xilinx.com:interface:axis:1.0 AXIS_RX TVALID"; attribute X_INTERFACE_PARAMETER of axi_c2c_aurora_rx_tvalid : signal is "XIL_INTERFACENAME AXIS_RX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; attribute X_INTERFACE_INFO of axi_c2c_aurora_tx_tready : signal is "xilinx.com:interface:axis:1.0 AXIS_TX TREADY"; attribute X_INTERFACE_INFO of axi_c2c_aurora_tx_tvalid : signal is "xilinx.com:interface:axis:1.0 AXIS_TX TVALID"; attribute X_INTERFACE_PARAMETER of axi_c2c_aurora_tx_tvalid : signal is "XIL_INTERFACENAME AXIS_TX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; attribute X_INTERFACE_INFO of axi_c2c_phy_clk : signal is "xilinx.com:signal:clock:1.0 axi_c2c_phy_clk CLK"; attribute X_INTERFACE_PARAMETER of axi_c2c_phy_clk : signal is "XIL_INTERFACENAME axi_c2c_phy_clk, ASSOCIATED_BUSIF AXIS_TX:AXIS_RX, ASSOCIATED_RESET aurora_reset_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; attribute X_INTERFACE_INFO of m_aclk : signal is "xilinx.com:signal:clock:1.0 m_aclk CLK"; attribute X_INTERFACE_PARAMETER of m_aclk : signal is "XIL_INTERFACENAME m_aclk, ASSOCIATED_BUSIF m_axi, ASSOCIATED_RESET m_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; attribute X_INTERFACE_INFO of m_aresetn : signal is "xilinx.com:signal:reset:1.0 m_aresetn RST"; attribute X_INTERFACE_PARAMETER of m_aresetn : signal is "XIL_INTERFACENAME m_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 m_axi ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 m_axi ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 m_axi AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 m_axi AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 m_axi BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 m_axi BVALID"; attribute X_INTERFACE_INFO of m_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 m_axi RLAST"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 m_axi RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME m_axi, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 4, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 m_axi RVALID"; attribute X_INTERFACE_INFO of m_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 m_axi WLAST"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 m_axi WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 m_axi WVALID"; attribute X_INTERFACE_INFO of axi_c2c_aurora_rx_tdata : signal is "xilinx.com:interface:axis:1.0 AXIS_RX TDATA"; attribute X_INTERFACE_INFO of axi_c2c_aurora_tx_tdata : signal is "xilinx.com:interface:axis:1.0 AXIS_TX TDATA"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 m_axi ARADDR"; attribute X_INTERFACE_INFO of m_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 m_axi ARBURST"; attribute X_INTERFACE_INFO of m_axi_arid : signal is "xilinx.com:interface:aximm:1.0 m_axi ARID"; attribute X_INTERFACE_INFO of m_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 m_axi ARLEN"; attribute X_INTERFACE_INFO of m_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 m_axi ARSIZE"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 m_axi AWADDR"; attribute X_INTERFACE_INFO of m_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 m_axi AWBURST"; attribute X_INTERFACE_INFO of m_axi_awid : signal is "xilinx.com:interface:aximm:1.0 m_axi AWID"; attribute X_INTERFACE_INFO of m_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 m_axi AWLEN"; attribute X_INTERFACE_INFO of m_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 m_axi AWSIZE"; attribute X_INTERFACE_INFO of m_axi_bid : signal is "xilinx.com:interface:aximm:1.0 m_axi BID"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 m_axi BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 m_axi RDATA"; attribute X_INTERFACE_INFO of m_axi_rid : signal is "xilinx.com:interface:aximm:1.0 m_axi RID"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 m_axi RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 m_axi WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 m_axi WSTRB"; attribute X_INTERFACE_INFO of m_axi_wuser : signal is "xilinx.com:interface:aximm:1.0 m_axi WUSER"; begin axi_c2c_aurora_tx_tdata(63) <= \^axi_c2c_aurora_tx_tdata\(63); axi_c2c_aurora_tx_tdata(62) <= \\; axi_c2c_aurora_tx_tdata(61 downto 0) <= \^axi_c2c_aurora_tx_tdata\(61 downto 0); axi_c2c_config_error_out <= \\; m_axi_arsize(2) <= \\; m_axi_arsize(1 downto 0) <= \^m_axi_arsize\(1 downto 0); m_axi_awsize(2) <= \\; m_axi_awsize(1 downto 0) <= \^m_axi_awsize\(1 downto 0); GND: unisim.vcomponents.GND port map ( G => \\ ); inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_chip2chip_v5_0_9 port map ( aurora_do_cc => aurora_do_cc, aurora_init_clk => aurora_init_clk, aurora_mmcm_not_locked => aurora_mmcm_not_locked, aurora_pma_init_in => aurora_pma_init_in, aurora_pma_init_out => aurora_pma_init_out, aurora_reset_pb => aurora_reset_pb, axi_c2c_aurora_channel_up => axi_c2c_aurora_channel_up, axi_c2c_aurora_rx_tdata(63 downto 0) => axi_c2c_aurora_rx_tdata(63 downto 0), axi_c2c_aurora_rx_tvalid => axi_c2c_aurora_rx_tvalid, axi_c2c_aurora_tx_tdata(63) => \^axi_c2c_aurora_tx_tdata\(63), axi_c2c_aurora_tx_tdata(62) => NLW_inst_axi_c2c_aurora_tx_tdata_UNCONNECTED(62), axi_c2c_aurora_tx_tdata(61 downto 0) => \^axi_c2c_aurora_tx_tdata\(61 downto 0), axi_c2c_aurora_tx_tready => axi_c2c_aurora_tx_tready, axi_c2c_aurora_tx_tvalid => axi_c2c_aurora_tx_tvalid, axi_c2c_config_error_out => NLW_inst_axi_c2c_config_error_out_UNCONNECTED, axi_c2c_link_error_out => NLW_inst_axi_c2c_link_error_out_UNCONNECTED, axi_c2c_link_status_out => axi_c2c_link_status_out, axi_c2c_lnk_hndlr_in_progress => NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED, axi_c2c_m2s_intr_in(3 downto 0) => B"0000", axi_c2c_m2s_intr_out(3 downto 0) => axi_c2c_m2s_intr_out(3 downto 0), axi_c2c_multi_bit_error_out => axi_c2c_multi_bit_error_out, axi_c2c_phy_clk => axi_c2c_phy_clk, axi_c2c_s2m_intr_in(3 downto 0) => axi_c2c_s2m_intr_in(3 downto 0), axi_c2c_s2m_intr_out(3 downto 0) => NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED(3 downto 0), axi_c2c_selio_rx_clk_in => '0', axi_c2c_selio_rx_data_in(8 downto 0) => B"000000000", axi_c2c_selio_rx_diff_clk_in_n => '0', axi_c2c_selio_rx_diff_clk_in_p => '0', axi_c2c_selio_rx_diff_data_in_n(8 downto 0) => B"000000000", axi_c2c_selio_rx_diff_data_in_p(8 downto 0) => B"000000000", axi_c2c_selio_tx_clk_out => NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED, axi_c2c_selio_tx_data_out(8 downto 0) => NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED(8 downto 0), axi_c2c_selio_tx_diff_clk_out_n => NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED, axi_c2c_selio_tx_diff_clk_out_p => NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED, axi_c2c_selio_tx_diff_data_out_n(8 downto 0) => NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED(8 downto 0), axi_c2c_selio_tx_diff_data_out_p(8 downto 0) => NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED(8 downto 0), idelay_ref_clk => '0', m_aclk => m_aclk, m_aclk_out => NLW_inst_m_aclk_out_UNCONNECTED, m_aresetn => m_aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arid(5 downto 0) => m_axi_arid(5 downto 0), m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0), m_axi_arready => m_axi_arready, m_axi_arsize(2) => NLW_inst_m_axi_arsize_UNCONNECTED(2), m_axi_arsize(1 downto 0) => \^m_axi_arsize\(1 downto 0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), m_axi_awid(5 downto 0) => m_axi_awid(5 downto 0), m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0), m_axi_awready => m_axi_awready, m_axi_awsize(2) => NLW_inst_m_axi_awsize_UNCONNECTED(2), m_axi_awsize(1 downto 0) => \^m_axi_awsize\(1 downto 0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(5 downto 0) => m_axi_bid(5 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_lite_aclk => '0', m_axi_lite_araddr(31 downto 0) => NLW_inst_m_axi_lite_araddr_UNCONNECTED(31 downto 0), m_axi_lite_arprot(1 downto 0) => NLW_inst_m_axi_lite_arprot_UNCONNECTED(1 downto 0), m_axi_lite_arready => '0', m_axi_lite_arvalid => NLW_inst_m_axi_lite_arvalid_UNCONNECTED, m_axi_lite_awaddr(31 downto 0) => NLW_inst_m_axi_lite_awaddr_UNCONNECTED(31 downto 0), m_axi_lite_awprot(1 downto 0) => NLW_inst_m_axi_lite_awprot_UNCONNECTED(1 downto 0), m_axi_lite_awready => '0', m_axi_lite_awvalid => NLW_inst_m_axi_lite_awvalid_UNCONNECTED, m_axi_lite_bready => NLW_inst_m_axi_lite_bready_UNCONNECTED, m_axi_lite_bresp(1 downto 0) => B"00", m_axi_lite_bvalid => '0', m_axi_lite_rdata(31 downto 0) => B"00000000000000000000000000000000", m_axi_lite_rready => NLW_inst_m_axi_lite_rready_UNCONNECTED, m_axi_lite_rresp(1 downto 0) => B"00", m_axi_lite_rvalid => '0', m_axi_lite_wdata(31 downto 0) => NLW_inst_m_axi_lite_wdata_UNCONNECTED(31 downto 0), m_axi_lite_wready => '0', m_axi_lite_wstrb(3 downto 0) => NLW_inst_m_axi_lite_wstrb_UNCONNECTED(3 downto 0), m_axi_lite_wvalid => NLW_inst_m_axi_lite_wvalid_UNCONNECTED, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(5 downto 0) => m_axi_rid(5 downto 0), m_axi_rlast => m_axi_rlast, m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wlast => m_axi_wlast, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(3 downto 0) => m_axi_wuser(3 downto 0), m_axi_wvalid => m_axi_wvalid, s_aclk => '0', s_aresetn => '1', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(5 downto 0) => B"000000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_inst_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(5 downto 0) => B"000000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(5 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(5 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED, s_axi_lite_aclk => '0', s_axi_lite_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_lite_arprot(1 downto 0) => B"00", s_axi_lite_arready => NLW_inst_s_axi_lite_arready_UNCONNECTED, s_axi_lite_arvalid => '0', s_axi_lite_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_lite_awprot(1 downto 0) => B"00", s_axi_lite_awready => NLW_inst_s_axi_lite_awready_UNCONNECTED, s_axi_lite_awvalid => '0', s_axi_lite_bready => '0', s_axi_lite_bresp(1 downto 0) => NLW_inst_s_axi_lite_bresp_UNCONNECTED(1 downto 0), s_axi_lite_bvalid => NLW_inst_s_axi_lite_bvalid_UNCONNECTED, s_axi_lite_rdata(31 downto 0) => NLW_inst_s_axi_lite_rdata_UNCONNECTED(31 downto 0), s_axi_lite_rready => '0', s_axi_lite_rresp(1 downto 0) => NLW_inst_s_axi_lite_rresp_UNCONNECTED(1 downto 0), s_axi_lite_rvalid => NLW_inst_s_axi_lite_rvalid_UNCONNECTED, s_axi_lite_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_lite_wready => NLW_inst_s_axi_lite_wready_UNCONNECTED, s_axi_lite_wstrb(3 downto 0) => B"0000", s_axi_lite_wvalid => '0', s_axi_rdata(31 downto 0) => NLW_inst_s_axi_rdata_UNCONNECTED(31 downto 0), s_axi_rid(5 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(5 downto 0), s_axi_rlast => NLW_inst_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_inst_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_inst_s_axi_rvalid_UNCONNECTED, s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED, s_axi_wstrb(3 downto 0) => B"0000", s_axi_wuser(3 downto 0) => B"0000", s_axi_wvalid => '0' ); end STRUCTURE;