// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 // Date : Fri Mar 12 21:30:35 2021 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ axi_chip2chip_64B66B_sim_netlist.v // Design : axi_chip2chip_64B66B // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xcku115-flva2104-1-c // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "axi_chip2chip_64B66B,axi_chip2chip_v5_0_9,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_chip2chip_v5_0_9,Vivado 2020.2" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (m_aclk, m_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awvalid, m_axi_awready, m_axi_wuser, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready, axi_c2c_s2m_intr_in, axi_c2c_m2s_intr_out, axi_c2c_phy_clk, axi_c2c_aurora_channel_up, axi_c2c_aurora_tx_tready, axi_c2c_aurora_tx_tdata, axi_c2c_aurora_tx_tvalid, axi_c2c_aurora_rx_tdata, axi_c2c_aurora_rx_tvalid, aurora_do_cc, aurora_pma_init_in, aurora_init_clk, aurora_pma_init_out, aurora_mmcm_not_locked, aurora_reset_pb, axi_c2c_config_error_out, axi_c2c_link_status_out, axi_c2c_multi_bit_error_out); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_aclk, ASSOCIATED_BUSIF m_axi, ASSOCIATED_RESET m_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input m_aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_aresetn RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input m_aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWID" *) output [5:0]m_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWADDR" *) output [31:0]m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWLEN" *) output [7:0]m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWSIZE" *) output [2:0]m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWBURST" *) output [1:0]m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWVALID" *) output m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWREADY" *) input m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WUSER" *) output [3:0]m_axi_wuser; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WDATA" *) output [31:0]m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WSTRB" *) output [3:0]m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WLAST" *) output m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WVALID" *) output m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WREADY" *) input m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BID" *) input [5:0]m_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BRESP" *) input [1:0]m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BVALID" *) input m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BREADY" *) output m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARID" *) output [5:0]m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARADDR" *) output [31:0]m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARLEN" *) output [7:0]m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARSIZE" *) output [2:0]m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARBURST" *) output [1:0]m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARVALID" *) output m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARREADY" *) input m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RID" *) input [5:0]m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RDATA" *) input [31:0]m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RRESP" *) input [1:0]m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RLAST" *) input m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RVALID" *) input m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 4, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready; input [3:0]axi_c2c_s2m_intr_in; output [3:0]axi_c2c_m2s_intr_out; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axi_c2c_phy_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axi_c2c_phy_clk, ASSOCIATED_BUSIF AXIS_TX:AXIS_RX, ASSOCIATED_RESET aurora_reset_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input axi_c2c_phy_clk; input axi_c2c_aurora_channel_up; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TREADY" *) input axi_c2c_aurora_tx_tready; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TDATA" *) output [63:0]axi_c2c_aurora_tx_tdata; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_TX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output axi_c2c_aurora_tx_tvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_RX TDATA" *) input [63:0]axi_c2c_aurora_rx_tdata; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_RX TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_RX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input axi_c2c_aurora_rx_tvalid; output aurora_do_cc; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_IN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_PMA_INIT_IN, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input aurora_pma_init_in; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 INIT_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INIT_CLK, ASSOCIATED_RESET aurora_pma_init_out, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input aurora_init_clk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_OUT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_PMA_INIT_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output aurora_pma_init_out; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_MMCM_NOT_LOCKED RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_MMCM_NOT_LOCKED, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input aurora_mmcm_not_locked; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_RST_OUT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_RST_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output aurora_reset_pb; output axi_c2c_config_error_out; output axi_c2c_link_status_out; output axi_c2c_multi_bit_error_out; wire \ ; wire aurora_do_cc; wire aurora_init_clk; wire aurora_mmcm_not_locked; wire aurora_pma_init_in; wire aurora_pma_init_out; wire aurora_reset_pb; wire axi_c2c_aurora_channel_up; wire [63:0]axi_c2c_aurora_rx_tdata; wire axi_c2c_aurora_rx_tvalid; wire [63:0]\^axi_c2c_aurora_tx_tdata ; wire axi_c2c_aurora_tx_tready; wire axi_c2c_aurora_tx_tvalid; wire axi_c2c_link_status_out; wire [3:0]axi_c2c_m2s_intr_out; wire axi_c2c_multi_bit_error_out; wire axi_c2c_phy_clk; wire [3:0]axi_c2c_s2m_intr_in; wire m_aclk; wire m_aresetn; wire [31:0]m_axi_araddr; wire [1:0]m_axi_arburst; wire [5:0]m_axi_arid; wire [7:0]m_axi_arlen; wire m_axi_arready; wire [1:0]\^m_axi_arsize ; wire m_axi_arvalid; wire [31:0]m_axi_awaddr; wire [1:0]m_axi_awburst; wire [5:0]m_axi_awid; wire [7:0]m_axi_awlen; wire m_axi_awready; wire [1:0]\^m_axi_awsize ; wire m_axi_awvalid; wire [5:0]m_axi_bid; wire m_axi_bready; wire [1:0]m_axi_bresp; wire m_axi_bvalid; wire [31:0]m_axi_rdata; wire [5:0]m_axi_rid; wire m_axi_rlast; wire m_axi_rready; wire [1:0]m_axi_rresp; wire m_axi_rvalid; wire [31:0]m_axi_wdata; wire m_axi_wlast; wire m_axi_wready; wire [3:0]m_axi_wstrb; wire [3:0]m_axi_wuser; wire m_axi_wvalid; wire NLW_inst_axi_c2c_config_error_out_UNCONNECTED; wire NLW_inst_axi_c2c_link_error_out_UNCONNECTED; wire NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED; wire NLW_inst_m_aclk_out_UNCONNECTED; wire NLW_inst_m_axi_lite_arvalid_UNCONNECTED; wire NLW_inst_m_axi_lite_awvalid_UNCONNECTED; wire NLW_inst_m_axi_lite_bready_UNCONNECTED; wire NLW_inst_m_axi_lite_rready_UNCONNECTED; wire NLW_inst_m_axi_lite_wvalid_UNCONNECTED; wire NLW_inst_s_axi_arready_UNCONNECTED; wire NLW_inst_s_axi_awready_UNCONNECTED; wire NLW_inst_s_axi_bvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_arready_UNCONNECTED; wire NLW_inst_s_axi_lite_awready_UNCONNECTED; wire NLW_inst_s_axi_lite_bvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_rvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_wready_UNCONNECTED; wire NLW_inst_s_axi_rlast_UNCONNECTED; wire NLW_inst_s_axi_rvalid_UNCONNECTED; wire NLW_inst_s_axi_wready_UNCONNECTED; wire [62:62]NLW_inst_axi_c2c_aurora_tx_tdata_UNCONNECTED; wire [3:0]NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED; wire [2:2]NLW_inst_m_axi_arsize_UNCONNECTED; wire [2:2]NLW_inst_m_axi_awsize_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_araddr_UNCONNECTED; wire [1:0]NLW_inst_m_axi_lite_arprot_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_awaddr_UNCONNECTED; wire [1:0]NLW_inst_m_axi_lite_awprot_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_wdata_UNCONNECTED; wire [3:0]NLW_inst_m_axi_lite_wstrb_UNCONNECTED; wire [5:0]NLW_inst_s_axi_bid_UNCONNECTED; wire [1:0]NLW_inst_s_axi_bresp_UNCONNECTED; wire [1:0]NLW_inst_s_axi_lite_bresp_UNCONNECTED; wire [31:0]NLW_inst_s_axi_lite_rdata_UNCONNECTED; wire [1:0]NLW_inst_s_axi_lite_rresp_UNCONNECTED; wire [31:0]NLW_inst_s_axi_rdata_UNCONNECTED; wire [5:0]NLW_inst_s_axi_rid_UNCONNECTED; wire [1:0]NLW_inst_s_axi_rresp_UNCONNECTED; assign axi_c2c_aurora_tx_tdata[63] = \^axi_c2c_aurora_tx_tdata [63]; assign axi_c2c_aurora_tx_tdata[62] = \ ; assign axi_c2c_aurora_tx_tdata[61:0] = \^axi_c2c_aurora_tx_tdata [61:0]; assign axi_c2c_config_error_out = \ ; assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1:0] = \^m_axi_arsize [1:0]; assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1:0] = \^m_axi_awsize [1:0]; GND GND (.G(\ )); (* ADDR_MUX_RATIO = "1" *) (* ADDR_MUX_RATIO_ID_WID_0_TO_12 = "1" *) (* AFIFO_DATA_SIZE = "50" *) (* AFIFO_DATA_SIZE_M2 = "0" *) (* AFIFO_DATA_SIZE_M3 = "2" *) (* AFIFO_DATA_SIZE_M4 = "2" *) (* AFIFO_TIE_WIDTH = "1" *) (* AFIFO_WIDTH = "50" *) (* AR_CH_FC = "128" *) (* AR_CH_FIFO_DEPTH = "256" *) (* AR_CH_PTR_WIDTH = "8" *) (* AWB_FC_WIDTH = "2" *) (* AW_CH_FC = "128" *) (* AW_CH_FIFO_DEPTH = "256" *) (* AW_CH_PTR_WIDTH = "8" *) (* AXILITE_WIDTH = "20" *) (* BFIFO_DATA_SIZE = "8" *) (* BFIFO_WIDTH = "8" *) (* BR_CH_FC = "128" *) (* BR_CH_FIFO_DEPTH = "256" *) (* BR_CH_PTR_WIDTH = "8" *) (* C_AURORA_WIDTH = "64" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_BRST_WIDTH = "2" *) (* C_AXI_BUS_TYPE = "0" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "6" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LITE_ADDR_WIDTH = "32" *) (* C_AXI_LITE_DATA_WIDTH = "32" *) (* C_AXI_LITE_PROT_WIDTH = "2" *) (* C_AXI_LITE_RESP_WIDTH = "2" *) (* C_AXI_LITE_STB_WIDTH = "4" *) (* C_AXI_RESP_WIDTH = "2" *) (* C_AXI_SIZE_WIDTH = "3" *) (* C_AXI_SIZE_WIDTH_INTERNAL = "2" *) (* C_AXI_STB_WIDTH = "4" *) (* C_AXI_WUSER_WIDTH = "4" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_CLK_SHIFT = "0" *) (* C_DISABLE_DESKEW = "0" *) (* C_ECC_ENABLE = "1" *) (* C_EN_AXI_LINK_HNDLR = "0" *) (* C_EN_LEGACY_MODE = "0" *) (* C_FAMILY = "kintexu" *) (* C_FIFO_DEPTH_LH = "256" *) (* C_INCLUDE_AXILITE = "0" *) (* C_INSTANCE = "axi_c2c" *) (* C_INTERFACE_MODE = "0" *) (* C_INTERFACE_TYPE = "2" *) (* C_INTERRUPT_WIDTH = "4" *) (* C_MASTER_FPGA = "0" *) (* C_NUM_OF_IO = "20" *) (* C_PHY_SELECT = "1" *) (* C_RD_CNTR_WIDTH = "8" *) (* C_SELECTIO_DDR = "0" *) (* C_SELECTIO_PHY_CLK = "100" *) (* C_SELECTIO_WIDTH = "9" *) (* C_SIMULATION = "0" *) (* C_SYNC_STAGE = "3" *) (* C_USE_DIFF_CLK = "0" *) (* C_USE_DIFF_IO = "0" *) (* C_WIDTH_CONVERSION = "1" *) (* C_WR_CNTR_WIDTH = "8" *) (* DATA_MUX_RATIO = "1" *) (* DATA_MUX_RATIO_ID_WID_0_TO_12 = "1" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* EN_ECC = "1" *) (* PHY_CTRL_WIDTH = "3" *) (* PHY_DATA_WIDTH = "64" *) (* RB_FC_WIDTH = "3" *) (* RFIFO_DATA_SIZE = "41" *) (* RFIFO_DATA_SIZE_M2 = "1" *) (* RFIFO_DATA_SIZE_M3 = "2" *) (* RFIFO_DATA_SIZE_M4 = "1" *) (* RFIFO_TIE_WIDTH = "1" *) (* RFIFO_WIDTH = "41" *) (* TDM_ID_WIDTH = "2" *) (* TDM_VAL_BITS = "1" *) (* WFIFO_DATA_SIZE = "41" *) (* WFIFO_DATA_SIZE_M2 = "1" *) (* WFIFO_DATA_SIZE_M3 = "2" *) (* WFIFO_DATA_SIZE_M4 = "1" *) (* WFIFO_TIE_WIDTH = "1" *) (* WFIFO_WIDTH = "41" *) (* is_du_within_envelope = "true" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_chip2chip_v5_0_9 inst (.aurora_do_cc(aurora_do_cc), .aurora_init_clk(aurora_init_clk), .aurora_mmcm_not_locked(aurora_mmcm_not_locked), .aurora_pma_init_in(aurora_pma_init_in), .aurora_pma_init_out(aurora_pma_init_out), .aurora_reset_pb(aurora_reset_pb), .axi_c2c_aurora_channel_up(axi_c2c_aurora_channel_up), .axi_c2c_aurora_rx_tdata(axi_c2c_aurora_rx_tdata), .axi_c2c_aurora_rx_tvalid(axi_c2c_aurora_rx_tvalid), .axi_c2c_aurora_tx_tdata(\^axi_c2c_aurora_tx_tdata ), .axi_c2c_aurora_tx_tready(axi_c2c_aurora_tx_tready), .axi_c2c_aurora_tx_tvalid(axi_c2c_aurora_tx_tvalid), .axi_c2c_config_error_out(NLW_inst_axi_c2c_config_error_out_UNCONNECTED), .axi_c2c_link_error_out(NLW_inst_axi_c2c_link_error_out_UNCONNECTED), .axi_c2c_link_status_out(axi_c2c_link_status_out), .axi_c2c_lnk_hndlr_in_progress(NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED), .axi_c2c_m2s_intr_in({1'b0,1'b0,1'b0,1'b0}), .axi_c2c_m2s_intr_out(axi_c2c_m2s_intr_out), .axi_c2c_multi_bit_error_out(axi_c2c_multi_bit_error_out), .axi_c2c_phy_clk(axi_c2c_phy_clk), .axi_c2c_s2m_intr_in(axi_c2c_s2m_intr_in), .axi_c2c_s2m_intr_out(NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED[3:0]), .axi_c2c_selio_rx_clk_in(1'b0), .axi_c2c_selio_rx_data_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_rx_diff_clk_in_n(1'b0), .axi_c2c_selio_rx_diff_clk_in_p(1'b0), .axi_c2c_selio_rx_diff_data_in_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_rx_diff_data_in_p({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_tx_clk_out(NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED), .axi_c2c_selio_tx_data_out(NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED[8:0]), .axi_c2c_selio_tx_diff_clk_out_n(NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED), .axi_c2c_selio_tx_diff_clk_out_p(NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED), .axi_c2c_selio_tx_diff_data_out_n(NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED[8:0]), .axi_c2c_selio_tx_diff_data_out_p(NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED[8:0]), .idelay_ref_clk(1'b0), .m_aclk(m_aclk), .m_aclk_out(NLW_inst_m_aclk_out_UNCONNECTED), .m_aresetn(m_aresetn), .m_axi_araddr(m_axi_araddr), .m_axi_arburst(m_axi_arburst), .m_axi_arid(m_axi_arid), .m_axi_arlen(m_axi_arlen), .m_axi_arready(m_axi_arready), .m_axi_arsize({NLW_inst_m_axi_arsize_UNCONNECTED[2],\^m_axi_arsize }), .m_axi_arvalid(m_axi_arvalid), .m_axi_awaddr(m_axi_awaddr), .m_axi_awburst(m_axi_awburst), .m_axi_awid(m_axi_awid), .m_axi_awlen(m_axi_awlen), .m_axi_awready(m_axi_awready), .m_axi_awsize({NLW_inst_m_axi_awsize_UNCONNECTED[2],\^m_axi_awsize }), .m_axi_awvalid(m_axi_awvalid), .m_axi_bid(m_axi_bid), .m_axi_bready(m_axi_bready), .m_axi_bresp(m_axi_bresp), .m_axi_bvalid(m_axi_bvalid), .m_axi_lite_aclk(1'b0), .m_axi_lite_araddr(NLW_inst_m_axi_lite_araddr_UNCONNECTED[31:0]), .m_axi_lite_arprot(NLW_inst_m_axi_lite_arprot_UNCONNECTED[1:0]), .m_axi_lite_arready(1'b0), .m_axi_lite_arvalid(NLW_inst_m_axi_lite_arvalid_UNCONNECTED), .m_axi_lite_awaddr(NLW_inst_m_axi_lite_awaddr_UNCONNECTED[31:0]), .m_axi_lite_awprot(NLW_inst_m_axi_lite_awprot_UNCONNECTED[1:0]), .m_axi_lite_awready(1'b0), .m_axi_lite_awvalid(NLW_inst_m_axi_lite_awvalid_UNCONNECTED), .m_axi_lite_bready(NLW_inst_m_axi_lite_bready_UNCONNECTED), .m_axi_lite_bresp({1'b0,1'b0}), .m_axi_lite_bvalid(1'b0), .m_axi_lite_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_lite_rready(NLW_inst_m_axi_lite_rready_UNCONNECTED), .m_axi_lite_rresp({1'b0,1'b0}), .m_axi_lite_rvalid(1'b0), .m_axi_lite_wdata(NLW_inst_m_axi_lite_wdata_UNCONNECTED[31:0]), .m_axi_lite_wready(1'b0), .m_axi_lite_wstrb(NLW_inst_m_axi_lite_wstrb_UNCONNECTED[3:0]), .m_axi_lite_wvalid(NLW_inst_m_axi_lite_wvalid_UNCONNECTED), .m_axi_rdata(m_axi_rdata), .m_axi_rid(m_axi_rid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready), .m_axi_rresp(m_axi_rresp), .m_axi_rvalid(m_axi_rvalid), .m_axi_wdata(m_axi_wdata), .m_axi_wlast(m_axi_wlast), .m_axi_wready(m_axi_wready), .m_axi_wstrb(m_axi_wstrb), .m_axi_wuser(m_axi_wuser), .m_axi_wvalid(m_axi_wvalid), .s_aclk(1'b0), .s_aresetn(1'b1), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_inst_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[5:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_inst_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_inst_s_axi_bvalid_UNCONNECTED), .s_axi_lite_aclk(1'b0), .s_axi_lite_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_arprot({1'b0,1'b0}), .s_axi_lite_arready(NLW_inst_s_axi_lite_arready_UNCONNECTED), .s_axi_lite_arvalid(1'b0), .s_axi_lite_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_awprot({1'b0,1'b0}), .s_axi_lite_awready(NLW_inst_s_axi_lite_awready_UNCONNECTED), .s_axi_lite_awvalid(1'b0), .s_axi_lite_bready(1'b0), .s_axi_lite_bresp(NLW_inst_s_axi_lite_bresp_UNCONNECTED[1:0]), .s_axi_lite_bvalid(NLW_inst_s_axi_lite_bvalid_UNCONNECTED), .s_axi_lite_rdata(NLW_inst_s_axi_lite_rdata_UNCONNECTED[31:0]), .s_axi_lite_rready(1'b0), .s_axi_lite_rresp(NLW_inst_s_axi_lite_rresp_UNCONNECTED[1:0]), .s_axi_lite_rvalid(NLW_inst_s_axi_lite_rvalid_UNCONNECTED), .s_axi_lite_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_wready(NLW_inst_s_axi_lite_wready_UNCONNECTED), .s_axi_lite_wstrb({1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_wvalid(1'b0), .s_axi_rdata(NLW_inst_s_axi_rdata_UNCONNECTED[31:0]), .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[5:0]), .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_inst_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_inst_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_inst_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser({1'b0,1'b0,1'b0,1'b0}), .s_axi_wvalid(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[4] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[4] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [9]), .Q(\dest_graysync_ff[3] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [9]), .Q(\dest_graysync_ff[4] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [3]), .I4(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\dest_graysync_ff[4] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[4] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [9]), .I4(\dest_graysync_ff[4] [7]), .I5(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [9]), .I2(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[4] [8]), .I1(\dest_graysync_ff[4] [9]), .O(\^dest_out_bin [8])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[4] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[4] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [9]), .Q(\dest_graysync_ff[3] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [9]), .Q(\dest_graysync_ff[4] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [3]), .I4(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\dest_graysync_ff[4] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[4] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [9]), .I4(\dest_graysync_ff[4] [7]), .I5(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [9]), .I2(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[4] [8]), .I1(\dest_graysync_ff[4] [9]), .O(\^dest_out_bin [8])); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[2] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [3]), .I4(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\dest_graysync_ff[2] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [9]), .I4(\dest_graysync_ff[2] [7]), .I5(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [9]), .I2(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[2] [8]), .I1(\dest_graysync_ff[2] [9]), .O(\^dest_out_bin [8])); LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[2] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [3]), .I4(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\dest_graysync_ff[2] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [9]), .I4(\dest_graysync_ff[2] [7]), .I5(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [9]), .I2(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[2] [8]), .I1(\dest_graysync_ff[2] [9]), .O(\^dest_out_bin [8])); LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn (Q, src_in_bin, DI, ram_empty_i, rd_en, \count_value_i_reg[0]_0 , \src_gray_ff_reg[0] , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]DI; input ram_empty_i; input rd_en; input [1:0]\count_value_i_reg[0]_0 ; input [0:0]\src_gray_ff_reg[0] ; input [0:0]SR; input rd_clk; wire [1:0]DI; wire [1:0]Q; wire [0:0]SR; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]\src_gray_ff_reg[0] ; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h696A9999)) \count_value_i[0]_i_1__2 (.I0(Q[0]), .I1(ram_empty_i), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [0]), .I4(\count_value_i_reg[0]_0 [1]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT4 #( .INIT(16'h9855)) \count_value_i[1]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'h9A9AAAAAA6A666A6)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(rd_en), .I5(ram_empty_i), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(src_in_bin)); LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[1])); LUT2 #( .INIT(4'h6)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[0])); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair2" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair2" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair0" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair0" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair1" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair1" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 (Q, src_in_bin, DI, ram_empty_i, rd_en, \count_value_i_reg[0]_0 , \src_gray_ff_reg[0] , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]DI; input ram_empty_i; input rd_en; input [1:0]\count_value_i_reg[0]_0 ; input [0:0]\src_gray_ff_reg[0] ; input [0:0]SR; input rd_clk; wire [1:0]DI; wire [1:0]Q; wire [0:0]SR; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]\src_gray_ff_reg[0] ; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h696A9999)) \count_value_i[0]_i_1__2 (.I0(Q[0]), .I1(ram_empty_i), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [0]), .I4(\count_value_i_reg[0]_0 [1]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT4 #( .INIT(16'h9855)) \count_value_i[1]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'h9A9AAAAAA6A666A6)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(rd_en), .I5(ram_empty_i), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(src_in_bin)); LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[1])); LUT2 #( .INIT(4'h6)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[0])); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair155" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair122" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair88" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3 (Q, ram_rd_en_i, \reg_out_i_reg[7] , src_in_bin, \count_value_i_reg[1]_0 , D, \count_value_i_reg[7]_0 , \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \grdc.rd_data_count_i_reg[7] , DI, \grdc.rd_data_count_i_reg[9] , S, \grdc.rd_data_count_i_reg[9]_0 , \count_value_i_reg[9]_0 , rd_clk); output [9:0]Q; output ram_rd_en_i; output \reg_out_i_reg[7] ; output [8:0]src_in_bin; output \count_value_i_reg[1]_0 ; output [8:0]D; output [7:0]\count_value_i_reg[7]_0 ; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]DI; input [0:0]\grdc.rd_data_count_i_reg[9] ; input [0:0]S; input [8:0]\grdc.rd_data_count_i_reg[9]_0 ; input \count_value_i_reg[9]_0 ; input rd_clk; wire [8:0]D; wire [7:0]DI; wire [9:0]Q; wire [0:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[8]_i_1__3_n_0 ; wire \count_value_i[9]_i_1__0_n_0 ; wire \count_value_i[9]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \count_value_i_reg[1]_0 ; wire [7:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[9]_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_8_n_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire \grdc.rd_data_count_i[7]_i_10_n_0 ; wire \grdc.rd_data_count_i[7]_i_11_n_0 ; wire \grdc.rd_data_count_i[7]_i_12_n_0 ; wire \grdc.rd_data_count_i[7]_i_13_n_0 ; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_15_n_0 ; wire \grdc.rd_data_count_i[7]_i_16_n_0 ; wire \grdc.rd_data_count_i[7]_i_17_n_0 ; wire \grdc.rd_data_count_i[9]_i_5_n_0 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[9] ; wire [8:0]\grdc.rd_data_count_i_reg[9]_0 ; wire \grdc.rd_data_count_i_reg[9]_i_2_n_7 ; wire ram_empty_i; wire ram_rd_en_i; wire rd_clk; wire rd_en; wire \reg_out_i_reg[7] ; wire [8:0]src_in_bin; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED ; wire [7:2]\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'hAABA5545)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\count_value_i[6]_i_2__3_n_0 ), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(\count_value_i[6]_i_2__3_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__3 (.I0(Q[6]), .I1(Q[5]), .I2(\count_value_i[9]_i_2__0_n_0 ), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT5 #( .INIT(32'hBFFF4000)) \count_value_i[8]_i_1__3 (.I0(\count_value_i[9]_i_2__0_n_0 ), .I1(Q[5]), .I2(Q[6]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00008000)) \count_value_i[9]_i_1__0 (.I0(Q[8]), .I1(Q[7]), .I2(Q[6]), .I3(Q[5]), .I4(\count_value_i[9]_i_2__0_n_0 ), .I5(Q[9]), .O(\count_value_i[9]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[9]_i_2__0 (.I0(Q[0]), .I1(ram_rd_en_i), .I2(Q[1]), .I3(Q[2]), .I4(Q[3]), .I5(Q[4]), .O(\count_value_i[9]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[8]_i_1__3_n_0 ), .Q(Q[8]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[9]_i_1__0_n_0 ), .Q(Q[9]), .R(\count_value_i_reg[9]_0 )); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .I3(Q[9]), .O(src_in_bin[8])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT5 #( .INIT(32'hFFFFFFFE)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[5]), .I1(Q[3]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[4]), .I4(Q[6]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT5 #( .INIT(32'hFFFFDD4D)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12 (.I0(\grdc.rd_data_count_i_reg[7] [1]), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .I4(Q[2]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT5 #( .INIT(32'hAAAAAAA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .O(src_in_bin[5])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .I3(Q[5]), .O(src_in_bin[4])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hEFAAFFEF10550010)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT5 #( .INIT(32'h9A55AA9A)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT4 #( .INIT(16'h6696)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .O(src_in_bin[0])); LUT5 #( .INIT(32'hAABA5545)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i_reg[7]_0 [0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[7]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .O(\count_value_i_reg[7]_0 [7])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\count_value_i_reg[7]_0 [6])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[5]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\count_value_i_reg[7]_0 [5])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .O(\count_value_i_reg[7]_0 [4])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .O(\count_value_i_reg[7]_0 [3])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[2]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[7]_0 [2])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .O(\count_value_i_reg[7]_0 [1])); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I2(Q[0]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I4(Q[2]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[1]_0 )); LUT6 #( .INIT(64'h8200008200000000)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I2(Q[7]), .I3(Q[8]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [8]), .I5(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 ), .O(\reg_out_i_reg[7] )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_8 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I2(Q[3]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I4(Q[5]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 )); LUT4 #( .INIT(16'h00FB)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(ram_empty_i), .O(ram_rd_en_i)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9]_0 [6]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[9]_0 [7]), .O(\grdc.rd_data_count_i[7]_i_10_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9]_0 [5]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[9]_0 [6]), .O(\grdc.rd_data_count_i[7]_i_11_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9]_0 [4]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[9]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_12_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9]_0 [3]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[9]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_13_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9]_0 [2]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[9]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT5 #( .INIT(32'h2BD4D42B)) \grdc.rd_data_count_i[7]_i_15 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(Q[2]), .I4(\grdc.rd_data_count_i_reg[9]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_15_n_0 )); LUT5 #( .INIT(32'hD22D2DD2)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[1]), .O(\grdc.rd_data_count_i[7]_i_16_n_0 )); LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_17 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [0]), .O(\grdc.rd_data_count_i[7]_i_17_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[9]_i_5 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9]_0 [7]), .I2(Q[8]), .I3(\grdc.rd_data_count_i_reg[9]_0 [8]), .O(\grdc.rd_data_count_i[9]_i_5_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI(DI), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\grdc.rd_data_count_i[7]_i_10_n_0 ,\grdc.rd_data_count_i[7]_i_11_n_0 ,\grdc.rd_data_count_i[7]_i_12_n_0 ,\grdc.rd_data_count_i[7]_i_13_n_0 ,\grdc.rd_data_count_i[7]_i_14_n_0 ,\grdc.rd_data_count_i[7]_i_15_n_0 ,\grdc.rd_data_count_i[7]_i_16_n_0 ,\grdc.rd_data_count_i[7]_i_17_n_0 })); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[9]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED [7:1],\grdc.rd_data_count_i_reg[9]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[9] }), .O({\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S,\grdc.rd_data_count_i[9]_i_5_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[9] , wr_clk); output [9:0]Q; output [8:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [9:0]\gwdc.wr_data_count_i_reg[9] ; input wr_clk; wire [8:0]D; wire [9:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[9]_i_1_n_0 ; wire \count_value_i[9]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[9]_i_2_n_0 ; wire \gwdc.wr_data_count_i[9]_i_3_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [9:0]\gwdc.wr_data_count_i_reg[9] ; wire \gwdc.wr_data_count_i_reg[9]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[9]_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\count_value_i[9]_i_2_n_0 ), .I3(Q[6]), .I4(Q[8]), .I5(Q[9]), .O(\count_value_i[9]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[9]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[9]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[9]_i_1_n_0 ), .Q(Q[9]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[9] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[9] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[9] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[9] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[9] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[9] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[9] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[9] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_2 (.I0(Q[9]), .I1(\gwdc.wr_data_count_i_reg[9] [9]), .O(\gwdc.wr_data_count_i[9]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_3 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[9] [8]), .O(\gwdc.wr_data_count_i[9]_i_3_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[9]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [7:1],\gwdc.wr_data_count_i_reg[9]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[8]}), .O({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_2_n_0 ,\gwdc.wr_data_count_i[9]_i_3_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[9] , wr_clk); output [9:0]Q; output [8:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [9:0]\gwdc.wr_data_count_i_reg[9] ; input wr_clk; wire [8:0]D; wire [9:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[9]_i_1_n_0 ; wire \count_value_i[9]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[9]_i_2_n_0 ; wire \gwdc.wr_data_count_i[9]_i_3_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [9:0]\gwdc.wr_data_count_i_reg[9] ; wire \gwdc.wr_data_count_i_reg[9]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[9]_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\count_value_i[9]_i_2_n_0 ), .I3(Q[6]), .I4(Q[8]), .I5(Q[9]), .O(\count_value_i[9]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[9]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[9]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[9]_i_1_n_0 ), .Q(Q[9]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[9] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[9] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[9] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[9] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[9] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[9] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[9] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[9] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_2 (.I0(Q[9]), .I1(\gwdc.wr_data_count_i_reg[9] [9]), .O(\gwdc.wr_data_count_i[9]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_3 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[9] [8]), .O(\gwdc.wr_data_count_i[9]_i_3_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[9]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [7:1],\gwdc.wr_data_count_i_reg[9]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[8]}), .O({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_2_n_0 ,\gwdc.wr_data_count_i[9]_i_3_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9 (Q, ram_rd_en_i, \reg_out_i_reg[7] , src_in_bin, \count_value_i_reg[1]_0 , D, \count_value_i_reg[7]_0 , \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \grdc.rd_data_count_i_reg[7] , DI, \grdc.rd_data_count_i_reg[9] , S, \grdc.rd_data_count_i_reg[9]_0 , \count_value_i_reg[9]_0 , rd_clk); output [9:0]Q; output ram_rd_en_i; output \reg_out_i_reg[7] ; output [8:0]src_in_bin; output \count_value_i_reg[1]_0 ; output [8:0]D; output [7:0]\count_value_i_reg[7]_0 ; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]DI; input [0:0]\grdc.rd_data_count_i_reg[9] ; input [0:0]S; input [8:0]\grdc.rd_data_count_i_reg[9]_0 ; input \count_value_i_reg[9]_0 ; input rd_clk; wire [8:0]D; wire [7:0]DI; wire [9:0]Q; wire [0:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[8]_i_1__3_n_0 ; wire \count_value_i[9]_i_1__0_n_0 ; wire \count_value_i[9]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \count_value_i_reg[1]_0 ; wire [7:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[9]_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_8_n_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire \grdc.rd_data_count_i[7]_i_10_n_0 ; wire \grdc.rd_data_count_i[7]_i_11_n_0 ; wire \grdc.rd_data_count_i[7]_i_12_n_0 ; wire \grdc.rd_data_count_i[7]_i_13_n_0 ; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_15_n_0 ; wire \grdc.rd_data_count_i[7]_i_16_n_0 ; wire \grdc.rd_data_count_i[7]_i_17_n_0 ; wire \grdc.rd_data_count_i[9]_i_5_n_0 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[9] ; wire [8:0]\grdc.rd_data_count_i_reg[9]_0 ; wire \grdc.rd_data_count_i_reg[9]_i_2_n_7 ; wire ram_empty_i; wire ram_rd_en_i; wire rd_clk; wire rd_en; wire \reg_out_i_reg[7] ; wire [8:0]src_in_bin; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED ; wire [7:2]\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'hAABA5545)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\count_value_i[6]_i_2__3_n_0 ), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(\count_value_i[6]_i_2__3_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__3 (.I0(Q[6]), .I1(Q[5]), .I2(\count_value_i[9]_i_2__0_n_0 ), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT5 #( .INIT(32'hBFFF4000)) \count_value_i[8]_i_1__3 (.I0(\count_value_i[9]_i_2__0_n_0 ), .I1(Q[5]), .I2(Q[6]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00008000)) \count_value_i[9]_i_1__0 (.I0(Q[8]), .I1(Q[7]), .I2(Q[6]), .I3(Q[5]), .I4(\count_value_i[9]_i_2__0_n_0 ), .I5(Q[9]), .O(\count_value_i[9]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[9]_i_2__0 (.I0(Q[0]), .I1(ram_rd_en_i), .I2(Q[1]), .I3(Q[2]), .I4(Q[3]), .I5(Q[4]), .O(\count_value_i[9]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[8]_i_1__3_n_0 ), .Q(Q[8]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[9]_i_1__0_n_0 ), .Q(Q[9]), .R(\count_value_i_reg[9]_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .I3(Q[9]), .O(src_in_bin[8])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'hFFFFFFFE)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[5]), .I1(Q[3]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[4]), .I4(Q[6]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'hFFFFDD4D)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12 (.I0(\grdc.rd_data_count_i_reg[7] [1]), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .I4(Q[2]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'hAAAAAAA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .O(src_in_bin[5])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .I3(Q[5]), .O(src_in_bin[4])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hEFAAFFEF10550010)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'h9A55AA9A)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT4 #( .INIT(16'h6696)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .O(src_in_bin[0])); LUT5 #( .INIT(32'hAABA5545)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i_reg[7]_0 [0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[7]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .O(\count_value_i_reg[7]_0 [7])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\count_value_i_reg[7]_0 [6])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[5]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\count_value_i_reg[7]_0 [5])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .O(\count_value_i_reg[7]_0 [4])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .O(\count_value_i_reg[7]_0 [3])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[2]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[7]_0 [2])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .O(\count_value_i_reg[7]_0 [1])); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I2(Q[0]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I4(Q[2]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[1]_0 )); LUT6 #( .INIT(64'h8200008200000000)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I2(Q[7]), .I3(Q[8]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [8]), .I5(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 ), .O(\reg_out_i_reg[7] )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_8 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I2(Q[3]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I4(Q[5]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 )); LUT4 #( .INIT(16'h00FB)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(ram_empty_i), .O(ram_rd_en_i)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9]_0 [6]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[9]_0 [7]), .O(\grdc.rd_data_count_i[7]_i_10_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9]_0 [5]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[9]_0 [6]), .O(\grdc.rd_data_count_i[7]_i_11_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9]_0 [4]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[9]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_12_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9]_0 [3]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[9]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_13_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9]_0 [2]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[9]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT5 #( .INIT(32'h2BD4D42B)) \grdc.rd_data_count_i[7]_i_15 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(Q[2]), .I4(\grdc.rd_data_count_i_reg[9]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_15_n_0 )); LUT5 #( .INIT(32'hD22D2DD2)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[1]), .O(\grdc.rd_data_count_i[7]_i_16_n_0 )); LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_17 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [0]), .O(\grdc.rd_data_count_i[7]_i_17_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[9]_i_5 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9]_0 [7]), .I2(Q[8]), .I3(\grdc.rd_data_count_i_reg[9]_0 [8]), .O(\grdc.rd_data_count_i[9]_i_5_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI(DI), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\grdc.rd_data_count_i[7]_i_10_n_0 ,\grdc.rd_data_count_i[7]_i_11_n_0 ,\grdc.rd_data_count_i[7]_i_12_n_0 ,\grdc.rd_data_count_i[7]_i_13_n_0 ,\grdc.rd_data_count_i[7]_i_14_n_0 ,\grdc.rd_data_count_i[7]_i_15_n_0 ,\grdc.rd_data_count_i[7]_i_16_n_0 ,\grdc.rd_data_count_i[7]_i_17_n_0 })); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[9]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED [7:1],\grdc.rd_data_count_i_reg[9]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[9] }), .O({\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S,\grdc.rd_data_count_i[9]_i_5_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4 (ram_empty_i0, E, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg_1 , \count_value_i_reg[0]_0 , rd_clk); output ram_empty_i0; input [0:0]E; input \gen_pf_ic_rc.ram_empty_i_reg ; input \gen_pf_ic_rc.ram_empty_i_reg_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [1:0]Q; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__2_n_0 ; wire \count_value_i[8]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire \count_value_i_reg_n_0_[0] ; wire \count_value_i_reg_n_0_[1] ; wire \count_value_i_reg_n_0_[2] ; wire \count_value_i_reg_n_0_[3] ; wire \count_value_i_reg_n_0_[4] ; wire \count_value_i_reg_n_0_[5] ; wire \count_value_i_reg_n_0_[6] ; wire \count_value_i_reg_n_0_[7] ; wire \count_value_i_reg_n_0_[8] ; wire \gen_pf_ic_rc.ram_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_reg ; wire \gen_pf_ic_rc.ram_empty_i_reg_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h04FB)) \count_value_i[0]_i_1__3 (.I0(rd_en), .I1(Q[1]), .I2(Q[0]), .I3(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[0]_i_1__3_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(rd_en), .I3(\count_value_i_reg_n_0_[0] ), .I4(\count_value_i_reg_n_0_[1] ), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(\count_value_i_reg_n_0_[2] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[0] ), .I3(\count_value_i_reg_n_0_[3] ), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i_reg_n_0_[3] ), .I4(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\count_value_i_reg_n_0_[3] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i[6]_i_2__2_n_0 ), .I4(\count_value_i_reg_n_0_[5] ), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(\count_value_i[6]_i_2__2_n_0 ), .I1(\count_value_i_reg_n_0_[2] ), .I2(\count_value_i_reg_n_0_[3] ), .I3(\count_value_i_reg_n_0_[4] ), .I4(\count_value_i_reg_n_0_[5] ), .I5(\count_value_i_reg_n_0_[6] ), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__2 (.I0(\count_value_i_reg_n_0_[1] ), .I1(Q[0]), .I2(Q[1]), .I3(rd_en), .I4(ram_empty_i), .I5(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__2 (.I0(\count_value_i_reg_n_0_[6] ), .I1(\count_value_i_reg_n_0_[5] ), .I2(\count_value_i[8]_i_2__1_n_0 ), .I3(\count_value_i_reg_n_0_[7] ), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT5 #( .INIT(32'hDFFF2000)) \count_value_i[8]_i_1__2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\count_value_i[8]_i_2__1_n_0 ), .I2(\count_value_i_reg_n_0_[5] ), .I3(\count_value_i_reg_n_0_[6] ), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[8]_i_2__1 (.I0(\count_value_i_reg_n_0_[0] ), .I1(E), .I2(\count_value_i_reg_n_0_[1] ), .I3(\count_value_i_reg_n_0_[2] ), .I4(\count_value_i_reg_n_0_[3] ), .I5(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[8]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(\count_value_i_reg_n_0_[0] ), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[1] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[2] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[3] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[4] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[5] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[6] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[7] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(E), .D(\count_value_i[8]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[0]_0 )); LUT6 #( .INIT(64'hFFFF800080008000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ), .I1(E), .I2(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 ), .I3(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I4(\gen_pf_ic_rc.ram_empty_i_reg ), .I5(\gen_pf_ic_rc.ram_empty_i_reg_0 ), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [7]), .I2(\count_value_i_reg_n_0_[6] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [8]), .I5(\count_value_i_reg_n_0_[8] ), .O(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\count_value_i_reg_n_0_[1] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [1]), .I2(\count_value_i_reg_n_0_[0] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [0]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [2]), .I5(\count_value_i_reg_n_0_[2] ), .O(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [4]), .I2(\count_value_i_reg_n_0_[3] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [3]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [5]), .I5(\count_value_i_reg_n_0_[5] ), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10 (ram_empty_i0, E, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg_1 , \count_value_i_reg[0]_0 , rd_clk); output ram_empty_i0; input [0:0]E; input \gen_pf_ic_rc.ram_empty_i_reg ; input \gen_pf_ic_rc.ram_empty_i_reg_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [1:0]Q; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__2_n_0 ; wire \count_value_i[8]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire \count_value_i_reg_n_0_[0] ; wire \count_value_i_reg_n_0_[1] ; wire \count_value_i_reg_n_0_[2] ; wire \count_value_i_reg_n_0_[3] ; wire \count_value_i_reg_n_0_[4] ; wire \count_value_i_reg_n_0_[5] ; wire \count_value_i_reg_n_0_[6] ; wire \count_value_i_reg_n_0_[7] ; wire \count_value_i_reg_n_0_[8] ; wire \gen_pf_ic_rc.ram_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_reg ; wire \gen_pf_ic_rc.ram_empty_i_reg_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h04FB)) \count_value_i[0]_i_1__3 (.I0(rd_en), .I1(Q[1]), .I2(Q[0]), .I3(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[0]_i_1__3_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(rd_en), .I3(\count_value_i_reg_n_0_[0] ), .I4(\count_value_i_reg_n_0_[1] ), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(\count_value_i_reg_n_0_[2] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[0] ), .I3(\count_value_i_reg_n_0_[3] ), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i_reg_n_0_[3] ), .I4(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\count_value_i_reg_n_0_[3] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i[6]_i_2__2_n_0 ), .I4(\count_value_i_reg_n_0_[5] ), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(\count_value_i[6]_i_2__2_n_0 ), .I1(\count_value_i_reg_n_0_[2] ), .I2(\count_value_i_reg_n_0_[3] ), .I3(\count_value_i_reg_n_0_[4] ), .I4(\count_value_i_reg_n_0_[5] ), .I5(\count_value_i_reg_n_0_[6] ), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__2 (.I0(\count_value_i_reg_n_0_[1] ), .I1(Q[0]), .I2(Q[1]), .I3(rd_en), .I4(ram_empty_i), .I5(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__2 (.I0(\count_value_i_reg_n_0_[6] ), .I1(\count_value_i_reg_n_0_[5] ), .I2(\count_value_i[8]_i_2__1_n_0 ), .I3(\count_value_i_reg_n_0_[7] ), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'hDFFF2000)) \count_value_i[8]_i_1__2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\count_value_i[8]_i_2__1_n_0 ), .I2(\count_value_i_reg_n_0_[5] ), .I3(\count_value_i_reg_n_0_[6] ), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[8]_i_2__1 (.I0(\count_value_i_reg_n_0_[0] ), .I1(E), .I2(\count_value_i_reg_n_0_[1] ), .I3(\count_value_i_reg_n_0_[2] ), .I4(\count_value_i_reg_n_0_[3] ), .I5(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[8]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(\count_value_i_reg_n_0_[0] ), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[1] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[2] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[3] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[4] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[5] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[6] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[7] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(E), .D(\count_value_i[8]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[0]_0 )); LUT6 #( .INIT(64'hFFFF800080008000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ), .I1(E), .I2(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 ), .I3(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I4(\gen_pf_ic_rc.ram_empty_i_reg ), .I5(\gen_pf_ic_rc.ram_empty_i_reg_0 ), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [7]), .I2(\count_value_i_reg_n_0_[6] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [8]), .I5(\count_value_i_reg_n_0_[8] ), .O(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\count_value_i_reg_n_0_[1] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [1]), .I2(\count_value_i_reg_n_0_[0] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [0]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [2]), .I5(\count_value_i_reg_n_0_[2] ), .O(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [4]), .I2(\count_value_i_reg_n_0_[3] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [3]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [5]), .I5(\count_value_i_reg_n_0_[5] ), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [8]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1 (.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [8]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1 (.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, wr_clk); output [8:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [8:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1__1_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire \count_value_i_reg[5]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair259" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__1_n_0 ), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, wr_clk); output [8:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [8:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1__1_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire \count_value_i_reg[5]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair199" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__1_n_0 ), .Q(Q[8]), .R(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [49:0]din; wire [49:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [40:0]din; wire [40:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized0__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [40:0]din; wire [40:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "distributed" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "1" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [7:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [7:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [7:0]din; wire [7:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "1" *) (* FIFO_MEM_TYPE = "1" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [49:0]din; wire [49:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [49:0]din; wire [49:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [49:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair92" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__8 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__9 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__4 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__8 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_38 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "49" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "50" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [49:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_39 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_40 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_42 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_43 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_44 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output full_n; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire clr_full; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [8:0]diff_pntr_pe; wire [9:2]diff_pntr_pf_q; wire [9:2]diff_pntr_pf_q0; wire [40:0]din; wire [40:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.rpw_gray_reg_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [9:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [9:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire p_1_in; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire ram_rd_en_i; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire [8:0]rd_pntr_ext; wire [8:0]rd_pntr_wr; wire [8:0]rd_pntr_wr_cdc; wire [9:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_0; wire rdp_inst_n_11; wire rdp_inst_n_21; wire rdp_inst_n_31; wire rdp_inst_n_32; wire rdp_inst_n_33; wire rdp_inst_n_34; wire rdp_inst_n_35; wire rdp_inst_n_36; wire rdp_inst_n_37; wire rdp_inst_n_38; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [9:0]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire [9:0]wr_pntr_ext; wire [9:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [8:0]wr_pntr_rd_cdc; wire [9:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrpp2_inst_n_8; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [40:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair203" *) LUT4 #( .INIT(16'h69A1)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(ram_empty_i), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .I3(rd_en), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin(src_in_bin00_out)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__12 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(rd_pntr_wr), .clr_full(clr_full), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (wr_pntr_plus1_pf), .\reg_out_i_reg[0]_0 (\gen_cdc_pntr.rpw_gray_reg_n_9 ), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6 \gen_cdc_pntr.wpr_gray_reg (.D(diff_pntr_pe), .DI(p_1_in), .Q({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .S({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (rd_pntr_ext[8]), .rd_clk(rd_clk), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[8]_0 (wr_pntr_rd_cdc)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7 \gen_cdc_pntr.wpr_gray_reg_dc (.D(wr_pntr_rd_cdc_dc), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[9] ({rdp_inst_n_0,rd_pntr_ext[8:1]}), .rd_clk(rd_clk), .\reg_out_i_reg[7]_0 (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\reg_out_i_reg[9]_0 (rd_rst_busy)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__11 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[8:0])); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'hE0CC)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(empty), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_8 \gen_fwft.rdpp1_inst (.DI({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q(count_value_i), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .\src_gray_ff_reg[0] (rd_pntr_ext[0]), .src_in_bin(src_in_bin00_out[0])); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_9 ), .Q(full), .S(wrst_busy)); LUT4 #( .INIT(16'hAABA)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(p_1_in)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[8]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I4(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[9]), .Q(diff_pntr_pf_q[9]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "40" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "41" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[8:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [40:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(ram_rd_en_i), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT3 #( .INIT(8'h2C)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [9]), .Q(rd_data_count[8]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [9]), .Q(wr_data_count[8]), .R(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_9 rdp_inst (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q({rdp_inst_n_0,rd_pntr_ext}), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[1]_0 (rdp_inst_n_21), .\count_value_i_reg[7]_0 ({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\count_value_i_reg[9]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[9] (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\grdc.rd_data_count_i_reg[9]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .ram_empty_i(ram_empty_i), .ram_rd_en_i(ram_rd_en_i), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[7] (rdp_inst_n_11), .src_in_bin(src_in_bin00_out[9:1])); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_10 rdpp1_inst (.E(ram_rd_en_i), .Q(curr_fwft_state), .\count_value_i_reg[0]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg (rdp_inst_n_21), .\gen_pf_ic_rc.ram_empty_i_reg_0 (rdp_inst_n_11), .\gen_pf_ic_rc.ram_empty_i_reg_1 ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 rst_d1_inst (.Q(diff_pntr_pf_q[9:8]), .clr_full(clr_full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[5]_0 (full), .\gwdc.wr_data_count_i_reg[9] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_13 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[5]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5_14 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\count_value_i_reg[5]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[8] (full), .\gen_pf_ic_rc.ram_empty_i_reg (\gen_fwft.count_rst ), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output full_n; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire clr_full; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [8:0]diff_pntr_pe; wire [9:2]diff_pntr_pf_q; wire [9:2]diff_pntr_pf_q0; wire [40:0]din; wire [40:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.rpw_gray_reg_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [9:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [9:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire p_1_in; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire ram_rd_en_i; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire [8:0]rd_pntr_ext; wire [8:0]rd_pntr_wr; wire [8:0]rd_pntr_wr_cdc; wire [9:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_0; wire rdp_inst_n_11; wire rdp_inst_n_21; wire rdp_inst_n_31; wire rdp_inst_n_32; wire rdp_inst_n_33; wire rdp_inst_n_34; wire rdp_inst_n_35; wire rdp_inst_n_36; wire rdp_inst_n_37; wire rdp_inst_n_38; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [9:0]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire [9:0]wr_pntr_ext; wire [9:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [8:0]wr_pntr_rd_cdc; wire [9:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrpp2_inst_n_8; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [40:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair263" *) LUT4 #( .INIT(16'h69A1)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(ram_empty_i), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .I3(rd_en), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized3__2 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin(src_in_bin00_out)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__10 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(rd_pntr_wr), .clr_full(clr_full), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (wr_pntr_plus1_pf), .\reg_out_i_reg[0]_0 (\gen_cdc_pntr.rpw_gray_reg_n_9 ), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0 \gen_cdc_pntr.wpr_gray_reg (.D(diff_pntr_pe), .DI(p_1_in), .Q({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .S({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (rd_pntr_ext[8]), .rd_clk(rd_clk), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[8]_0 (wr_pntr_rd_cdc)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1 \gen_cdc_pntr.wpr_gray_reg_dc (.D(wr_pntr_rd_cdc_dc), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[9] ({rdp_inst_n_0,rd_pntr_ext[8:1]}), .rd_clk(rd_clk), .\reg_out_i_reg[7]_0 (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\reg_out_i_reg[9]_0 (rd_rst_busy)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized2__2 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__9 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[8:0])); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT4 #( .INIT(16'hE0CC)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(empty), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn \gen_fwft.rdpp1_inst (.DI({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q(count_value_i), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .\src_gray_ff_reg[0] (rd_pntr_ext[0]), .src_in_bin(src_in_bin00_out[0])); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_9 ), .Q(full), .S(wrst_busy)); LUT4 #( .INIT(16'hAABA)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(p_1_in)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[8]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I4(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[9]), .Q(diff_pntr_pf_q[9]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "40" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "41" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[8:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [40:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(ram_rd_en_i), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT3 #( .INIT(8'h2C)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [9]), .Q(rd_data_count[8]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [9]), .Q(wr_data_count[8]), .R(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3 rdp_inst (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q({rdp_inst_n_0,rd_pntr_ext}), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[1]_0 (rdp_inst_n_21), .\count_value_i_reg[7]_0 ({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\count_value_i_reg[9]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[9] (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\grdc.rd_data_count_i_reg[9]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .ram_empty_i(ram_empty_i), .ram_rd_en_i(ram_rd_en_i), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[7] (rdp_inst_n_11), .src_in_bin(src_in_bin00_out[9:1])); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4 rdpp1_inst (.E(ram_rd_en_i), .Q(curr_fwft_state), .\count_value_i_reg[0]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg (rdp_inst_n_21), .\gen_pf_ic_rc.ram_empty_i_reg_0 (rdp_inst_n_11), .\gen_pf_ic_rc.ram_empty_i_reg_1 ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit rst_d1_inst (.Q(diff_pntr_pf_q[9:8]), .clr_full(clr_full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_2 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[5]_0 (full), .\gwdc.wr_data_count_i_reg[9] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized4_3 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[5]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized5 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\count_value_i_reg[5]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[8] (full), .\gen_pf_ic_rc.ram_empty_i_reg (\gen_fwft.count_rst ), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "1" *) (* FIFO_MEM_TYPE = "1" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [7:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [7:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [7:0]din; wire [7:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [7:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__10 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_19 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "1" *) (* MEMORY_SIZE = "2048" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "distributed" *) (* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *) (* P_MIN_WIDTH_DATA_B = "8" *) (* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "8" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *) (* READ_DATA_WIDTH_A = "8" *) (* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "1" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *) (* WRITE_DATA_WIDTH_B = "8" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "1" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "8" *) (* rstb_loop_iter = "8" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [7:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_21 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_22 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [49:0]din; wire [49:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [49:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair126" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__7 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__7 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__3 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__6 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_27 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "49" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "50" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [49:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_28 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_29 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_31 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_32 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_33 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , clr_full, overflow_i0, wrst_busy, wr_clk, Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output clr_full; output overflow_i0; input wrst_busy; input wr_clk; input [1:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [1:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); LUT6 #( .INIT(64'h00FF00E0000000E0)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I2(Q[1]), .I3(clr_full), .I4(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I5(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_11 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , clr_full, overflow_i0, wrst_busy, wr_clk, Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output clr_full; output overflow_i0; input wrst_busy; input wr_clk; input [1:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [1:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); LUT6 #( .INIT(64'h00FF00E0000000E0)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I2(Q[1]), .I3(clr_full), .I4(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I5(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_20 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_30 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_41 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_17 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_23 (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_25 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_34 (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_36 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0 (Q, \reg_out_i_reg[0]_0 , wr_pntr_plus1_pf_carry, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 , \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , clr_full, wrst_busy, D, wr_clk); output [8:0]Q; output \reg_out_i_reg[0]_0 ; input wr_pntr_plus1_pf_carry; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input clr_full; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire clr_full; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full; wire \reg_out_i_reg[0]_0 ; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'h0000FF80)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I3(going_full), .I4(clr_full), .O(\reg_out_i_reg[0]_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ), .I3(wr_pntr_plus1_pf_carry), .O(going_full)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_0 (Q, D, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] , DI, S, \reg_out_i_reg[0]_0 , \reg_out_i_reg[8]_0 , rd_clk); output [8:0]Q; output [8:0]D; input [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; input [0:0]DI; input [7:0]S; input \reg_out_i_reg[0]_0 ; input [8:0]\reg_out_i_reg[8]_0 ; input rd_clk; wire [8:0]D; wire [0:0]DI; wire [8:0]Q; wire [7:0]S; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; wire rd_clk; wire \reg_out_i_reg[0]_0 ; wire [8:0]\reg_out_i_reg[8]_0 ; wire [7:0]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED ; LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(Q[0]), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({Q[7:1],DI}), .O(D[7:0]), .S(S)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED [7:1],D[8]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [0]), .Q(Q[0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [1]), .Q(Q[1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [2]), .Q(Q[2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [3]), .Q(Q[3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [4]), .Q(Q[4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [5]), .Q(Q[5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [6]), .Q(Q[6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [7]), .Q(Q[7]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [8]), .Q(Q[8]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_16 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_18 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_24 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_26 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_35 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_37 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_4 (Q, \reg_out_i_reg[0]_0 , wr_pntr_plus1_pf_carry, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 , \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , clr_full, wrst_busy, D, wr_clk); output [8:0]Q; output \reg_out_i_reg[0]_0 ; input wr_pntr_plus1_pf_carry; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input clr_full; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire clr_full; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full; wire \reg_out_i_reg[0]_0 ; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'h0000FF80)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I3(going_full), .I4(clr_full), .O(\reg_out_i_reg[0]_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ), .I3(wr_pntr_plus1_pf_carry), .O(going_full)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_6 (Q, D, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] , DI, S, \reg_out_i_reg[0]_0 , \reg_out_i_reg[8]_0 , rd_clk); output [8:0]Q; output [8:0]D; input [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; input [0:0]DI; input [7:0]S; input \reg_out_i_reg[0]_0 ; input [8:0]\reg_out_i_reg[8]_0 ; input rd_clk; wire [8:0]D; wire [0:0]DI; wire [8:0]Q; wire [7:0]S; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; wire rd_clk; wire \reg_out_i_reg[0]_0 ; wire [8:0]\reg_out_i_reg[8]_0 ; wire [7:0]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED ; LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(Q[0]), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({Q[7:1],DI}), .O(D[7:0]), .S(S)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED [7:1],D[8]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [0]), .Q(Q[0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [1]), .Q(Q[1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [2]), .Q(Q[2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [3]), .Q(Q[3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [4]), .Q(Q[4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [5]), .Q(Q[5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [6]), .Q(Q[6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [7]), .Q(Q[7]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [8]), .Q(Q[8]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1 (Q, wrst_busy, D, wr_clk); output [9:0]Q; input wrst_busy; input [9:0]D; input wr_clk; wire [9:0]D; wire [9:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(D[9]), .Q(Q[9]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_1 (DI, Q, \reg_out_i_reg[7]_0 , S, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[9] , \reg_out_i_reg[9]_0 , D, rd_clk); output [5:0]DI; output [8:0]Q; output [0:0]\reg_out_i_reg[7]_0 ; output [0:0]S; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [8:0]\grdc.rd_data_count_i_reg[9] ; input \reg_out_i_reg[9]_0 ; input [9:0]D; input rd_clk; wire [9:0]D; wire [5:0]DI; wire [8:0]Q; wire [0:0]S; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [8:0]\grdc.rd_data_count_i_reg[9] ; wire rd_clk; wire [0:0]\reg_out_i_reg[7]_0 ; wire \reg_out_i_reg[9]_0 ; wire \reg_out_i_reg_n_0_[9] ; LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9] [5]), .O(DI[5])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9] [4]), .O(DI[4])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9] [3]), .O(DI[3])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9] [2]), .O(DI[2])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9] [1]), .O(DI[1])); LUT3 #( .INIT(8'h8E)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[9] [0]), .O(DI[0])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[9]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9] [6]), .O(\reg_out_i_reg[7]_0 )); LUT4 #( .INIT(16'hD22D)) \grdc.rd_data_count_i[9]_i_4 (.I0(Q[8]), .I1(\grdc.rd_data_count_i_reg[9] [7]), .I2(\grdc.rd_data_count_i_reg[9] [8]), .I3(\reg_out_i_reg_n_0_[9] ), .O(S)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(D[9]), .Q(\reg_out_i_reg_n_0_[9] ), .R(\reg_out_i_reg[9]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_5 (Q, wrst_busy, D, wr_clk); output [9:0]Q; input wrst_busy; input [9:0]D; input wr_clk; wire [9:0]D; wire [9:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(D[9]), .Q(Q[9]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized1_7 (DI, Q, \reg_out_i_reg[7]_0 , S, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[9] , \reg_out_i_reg[9]_0 , D, rd_clk); output [5:0]DI; output [8:0]Q; output [0:0]\reg_out_i_reg[7]_0 ; output [0:0]S; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [8:0]\grdc.rd_data_count_i_reg[9] ; input \reg_out_i_reg[9]_0 ; input [9:0]D; input rd_clk; wire [9:0]D; wire [5:0]DI; wire [8:0]Q; wire [0:0]S; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [8:0]\grdc.rd_data_count_i_reg[9] ; wire rd_clk; wire [0:0]\reg_out_i_reg[7]_0 ; wire \reg_out_i_reg[9]_0 ; wire \reg_out_i_reg_n_0_[9] ; LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9] [5]), .O(DI[5])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9] [4]), .O(DI[4])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9] [3]), .O(DI[3])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9] [2]), .O(DI[2])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9] [1]), .O(DI[1])); LUT3 #( .INIT(8'h8E)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[9] [0]), .O(DI[0])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[9]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9] [6]), .O(\reg_out_i_reg[7]_0 )); LUT4 #( .INIT(16'hD22D)) \grdc.rd_data_count_i[9]_i_4 (.I0(Q[8]), .I1(\grdc.rd_data_count_i_reg[9] [7]), .I2(\grdc.rd_data_count_i_reg[9] [8]), .I3(\reg_out_i_reg_n_0_[9] ), .O(S)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(D[9]), .Q(\reg_out_i_reg_n_0_[9] ), .R(\reg_out_i_reg[9]_0 )); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__18 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__11 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__10 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__2 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__13 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__12 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__3 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_pf_ic_rc.ram_empty_i_reg , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[8] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[8] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[8] ; wire [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT4 #( .INIT(16'hFF02)) \count_value_i[1]_i_1__4 (.I0(ram_empty_i), .I1(Q[0]), .I2(Q[1]), .I3(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(\gen_pf_ic_rc.ram_empty_i_reg )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__15 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__14 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[8] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT3 #( .INIT(8'hF1)) \grdc.rd_data_count_i[9]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(\guf.underflow_i_reg ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__4 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_pf_ic_rc.ram_empty_i_reg , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[8] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[8] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[8] ; wire [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT4 #( .INIT(16'hFF02)) \count_value_i[1]_i_1__4 (.I0(ram_empty_i), .I1(Q[0]), .I2(Q[1]), .I3(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(\gen_pf_ic_rc.ram_empty_i_reg )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__17 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__16 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[8] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT3 #( .INIT(8'hF1)) \grdc.rd_data_count_i[9]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(\guf.underflow_i_reg ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [49:0]dina; input injectsbiterra; input injectdbiterra; output [49:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [49:0]dinb; input injectsbiterrb; input injectdbiterrb; output [49:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [49:0]dina; wire [49:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:18]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "49" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "49" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "12800" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "49" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({1'b0,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b0,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[49:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:18],doutb[49:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__2 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [49:0]dina; input injectsbiterra; input injectdbiterra; output [49:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [49:0]dinb; input injectsbiterrb; input injectdbiterrb; output [49:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [49:0]dina; wire [49:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:18]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "49" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "49" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "12800" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "49" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({1'b0,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b0,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[49:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:18],doutb[49:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [8:0]addra; input [40:0]dina; input injectsbiterra; input injectdbiterra; output [40:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [8:0]addrb; input [40:0]dinb; input injectsbiterrb; input injectdbiterrb; output [40:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [8:0]addra; wire [8:0]addrb; wire clka; wire clkb; wire [40:0]dina; wire [40:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:9]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "40" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "40" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "20992" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "40" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[40:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:9],doutb[40:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized0__2 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [8:0]addra; input [40:0]dina; input injectsbiterra; input injectdbiterra; output [40:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [8:0]addrb; input [40:0]dinb; input injectsbiterrb; input injectdbiterrb; output [40:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [8:0]addra; wire [8:0]addrb; wire clka; wire clkb; wire [40:0]dina; wire [40:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:9]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "40" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "40" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "20992" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "40" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[40:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:9],doutb[40:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "1" *) (* MEMORY_SIZE = "2048" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "distributed" *) (* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *) (* P_MIN_WIDTH_DATA_B = "8" *) (* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "8" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *) (* READ_DATA_WIDTH_A = "8" *) (* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "1" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *) (* WRITE_DATA_WIDTH_B = "8" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "1" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "8" *) (* rstb_loop_iter = "8" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__parameterized1 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [7:0]dina; input injectsbiterra; input injectdbiterra; output [7:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [7:0]dinb; input injectsbiterrb; input injectdbiterrb; output [7:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [7:0]dina; wire [7:0]doutb; wire ena; wire enb; wire [7:0]\gen_rd_b.doutb_reg ; wire \gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ; wire regceb; wire rstb; wire select_piped_1_reg_pipe_5_reg_n_0; wire select_piped_3_reg_pipe_6_reg_n_0; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); FDRE \gen_rd_b.doutb_reg_reg_pipe_10_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_11_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_12_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_13_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_14_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_15_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_16_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_17_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_18_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_19_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_1_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_20_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_21_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_22_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_23_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_24_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_25_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_26_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_27_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_28_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_29_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_2_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_30_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_31_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_32_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_33_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_34_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_3_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_4_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_7_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_8_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_9_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][0]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ), .O(\gen_rd_b.doutb_reg [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][1]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ), .O(\gen_rd_b.doutb_reg [1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ), .O(\gen_rd_b.doutb_reg [2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][3]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ), .O(\gen_rd_b.doutb_reg [3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][4]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ), .O(\gen_rd_b.doutb_reg [4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][5]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ), .O(\gen_rd_b.doutb_reg [5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][6]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ), .O(\gen_rd_b.doutb_reg [6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][7]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ), .O(\gen_rd_b.doutb_reg [7])); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][0] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [0]), .Q(doutb[0]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][1] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [1]), .Q(doutb[1]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [2]), .Q(doutb[2]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][3] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [3]), .Q(doutb[3]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][4] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [4]), .Q(doutb[4]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][5] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [5]), .Q(doutb[5]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][6] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [6]), .Q(doutb[6]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][7] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [7]), .Q(doutb[7]), .R(rstb)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "63" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h02)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1 (.I0(ena), .I1(addra[6]), .I2(addra[7]), .O(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "63" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "128" *) (* ram_addr_end = "191" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h40)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1 (.I0(addra[6]), .I1(addra[7]), .I2(ena), .O(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "128" *) (* ram_addr_end = "191" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "192" *) (* ram_addr_end = "255" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1 (.I0(ena), .I1(addra[6]), .I2(addra[7]), .O(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "192" *) (* ram_addr_end = "255" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "64" *) (* ram_addr_end = "127" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h40)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1 (.I0(addra[7]), .I1(addra[6]), .I2(ena), .O(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "64" *) (* ram_addr_end = "127" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); FDRE select_piped_1_reg_pipe_5_reg (.C(clkb), .CE(enb), .D(addrb[6]), .Q(select_piped_1_reg_pipe_5_reg_n_0), .R(1'b0)); FDRE select_piped_3_reg_pipe_6_reg (.C(clkb), .CE(enb), .D(addrb[7]), .Q(select_piped_3_reg_pipe_6_reg_n_0), .R(1'b0)); endmodule `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) `pragma protect key_block Smodsvllcvd6MuPfdHlFmvR8p+Pe7f/pUBu/EPfJ2zZ5ctuddGasm68DT7c1GLZh6gDWLRVWzeFo 7fcCmPmHOg== `pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block s2mDZJeKjJsKFE8Xp2XRbJCl6T2FNVLRNeAmU/UqqR05MWC75Dr4jE6br+1fqFRpw3qEraDZBccO 2KWWAdJBHQOh1fufTlMCJJJEIWl4RL3bkCRsGDbIquWw0kVLdFyOEx6Lt14PvUyTuHVmV8wLyqrH yrV4YPFXV6ypwrcRjr8= `pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block x+7/agT4n/d9u1QQInxgxce2jZanNSpIonCHAMN9TwcrlJrdb8ZfXZRtPg5W5uDzAYwFlpOMaH7J K0bU2N1bJd5SulzzWFr2xmwWwHkajiQbUTVM/qR72fbwtXA37wmHeH5Tj2maA3ysmVCEOBf+PzRU Skp4HmB39p3hznf7ivb9O+sIfUNHxZBRzkiGh0ybjA8gVC3hy9NdrtQe0RHj+KDnauKeW/7F5h28 Wru9E7eo717pSBIWiXC0+XEYHLyZH8UN1U/iAvPNkpqEn4OvzptabgKAiRn6ijsrWWhVztYbGXt2 qOtTlmttFPVT2ywiD8/sG81mWcXtkBnjurP1Bw== `pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block a+uyg/DogHrar2B20X0VgKpDYxx8u5tU3WA15lXV858Y9HTfE/D5Ryjp0R5g+o4hU/5agZ7PQugj +Mvi/rKN+IHrEnVKSjN5RJGFUfDKEXQdedEiVI1lKvTljh6/DbxkqYVn8yzilcIXSBDhoq5uXOcx Mwmzc2s6rW0NV5Q8EbxCcgTrGYzpifzEoYV0jTlScpaPkDqnEcq5FfdczU1m49BoU+M4J77FaKjN pv9iayEPhHjY2K5BE74HpvcRAZiQ5f6Gm3FLXXd/9cLd2FDmDBtno+HFPjWV03VK9Wa3oqggUaWc 2+IraP0j0iYXzF9j3MybI+65W/eukw9H5L3ICg== `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block pIB9TJIKMKujbrZdwkCbRqImY/XmmtgVYJYP8sQJB8aidnWCgifLnFKwPxN8+uM6n92XDeuSl2uf spMy7uFl+uyL+JqlCjJUGfHM+H03Wu2cccoisOYpY+XRV9nieltHFTy8wDgpVV0w3KMf+UV1TZtt 4ztD5z48R4BbG/Ue0sk= `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Vn0eykMtydiA29PmAvGfWqzU/OcR9L9ZRcvug6TYIDc7Wxv5/GyVdGrNdRktD0f9KubgBa0urkHZ OVAc1qpm7pKiLBUVlFacwXaioX9Q1FD1SAxilHWB5ltYgZegy2ez2lryio4r3lIYsEXOpFFCfoTj JjvYIAKkVicZbUdPFn9Cw7BgtAyIBox5+wMxN4Woz2ieR6XD0tXW5bIK6OUZiDKv6cMDmQ7o/QLx ki3QAGoSbICwuLgoE01RbtjZTocaCLZT+wrDC/IcJB+d70CbAiRE5s6cmmTsX/12AcCznkVRMaTv CR0SNb0Ps+0ZVYz9aKP8giXb5qLYBT0vftbPPg== `pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Yt83c3DmqkpWc1KPkPbqmHqaLoT3qlzJzC6nkvkkrCh8yH/Ym2KZkrIxp3XDJeaAtDhQXBkh650y O3wUe60ck9zvA8HWGhS5BPgIw9rnangrhcvzCScfI0OfwQ6h5ZsgVFFGvkBnBgniaJ4N2G3Zujop aYKZKOok233c5nuk6znEO/qIaPnWVPy2jruPlSPfu+7OpnFaiOVBJx+VJC4YR2E6xdvjMTM4vPrQ /etKY/AYxfvM028Lxnt9Xc+CVCVOYyV5dT4unPuM89uabGBKMCLWKBA9mKxBmXNUT2MSjOds3Dut JQa6ypo8M2SEm2GGxI67ytaHq3pYFSh7UBopoA== `pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block rWZCM2OLTdFeNt3/3w1nV8cDE8ru50QBdnwQU2vQ/RCdITRg6R67t+HHT+nMg7iJ9FgoAWWbslZP nNrhWQS1A/eoyQsI+cbuwUT7rIPRLBRpJIXKI5TnO0alZwYyePXXbSzmnbSbbxoRhXVgbY4MQ2gT 8KcbIZfsV8RKXGHsAbt8vPQSHgOXcZFD4+w2IU/VGk/KAnGsIVvTUcijNi7Q7vBbI8ceiHiKg55T nv14J6fhUXK2vndlaXvQ7Uoqcxdpu2PDWj9CiInYu5QBGzJWoMPwzfLfxB+Am5azcUDCf8FUy4IO oArsrBt5MXGK/KRLLr4vcSvW+yOxJzfrZPG8Mw== `pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block SP+xNpp1Ho2r2B0A7yOizrsTj3eBYEq/2auUnNB7Pjs4H7cFrz5pVVFE+c9sc68Oe7YL/0e2v/jK M9zSnmOQjteVTNuriozBDU8b7ZbRl2EIwBoHjxxr3APjuHMe7B00kUieij2E3nkqNJFL0VhqMYz8 1rSTpPERO5jBUCzhjyi1cdOHrQNzt2kVY0SgJDtNz6oN07397z0su0vaN0DNs6qAu5DF5mGIdPdP vD4c7qy0B0wcB0NQPx5Gxr+54OL3AKN3BsuWEOCrY2vztdCtXoep3lXDB3fw1rOXfb0ELNDv2CtF a8UzUmODOsTlTsU5nvL0uTLS58RWaxXYE14rnQ== `pragma protect data_method = "AES128-CBC" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 347264) `pragma protect data_block Ib4jsHwm1oZvm67saP09SVPFj3n8gj6ObJOOSYGI35Q795wU5bpYK1/IM1fnIkSRxv6G6GELd5we XeCkWa/q0vSo07bu8dqP40qfnxUYhg1iYYb+jW9kZ2zy3kYNBoC32q7rAlLVjMD7QbpBUW7klq9F 192Op4/eNc5fC9Qz0NcUearttKA0OmS659PetJYK2uGNWYCeWZHcq7tbmPgu5ZEcSEqeD0AtHSgj r94/elfJO9EV+FzlqJ86R/ZRa6dbAzm1gkkoE0qW2eLpKRWA2AwZq3n0D9Bj00E21bV8SRY4OHpt zCxNfLb4FI5BBf1EImaXQPBMBD1SH0HJiI/QftG6EPoH1YeNVMtJaKYZVZ/Ku08kwr3LFDEmrFou wvQ3r3QeWyus+7boliUpLCO7Ig9hg+jQPH9cTcqUCYLJZ97WsFQk2usEWfOaf4AxITWzCHHYZ8ak +QpXcCW5Zqxblba6/QEGAHz1xn7toJVGaC1+PWkbvF0aLfmEtVNgRBQjpr38WgD5XIe6Y03mWpMT LPak6oV223slpxkHowjh4UgQdXHBmVD7mPmWCcZ8H4pnRxGIpaTIVl4T0sDQQUddWFJIFQiUSUP5 BgiKMrqn8LirR0Qce0eH8A+C/6D3L7EF5Mn/Wq3+punZCXSRf5oY9kfdXkwEgQ7+1kfmuAo6ld01 HCvWwOcxXQPUZaulWh38zJiDJGo0OPT7bhgjf5rL6cU4dsGPtZg7fsCR6HrSArRZcaKyvLkZUrKn TmCqra5kRuIOD2urrmtNTna1TIcigZIn615BAa22IHFA787rY0GxuMEipgwOQbrRzme35LPdTZG5 JYrdyad0lXUcM3+RNtXixfDLmXUqQHqnWfSmLum9MSFMYtx/IedNKzmi/WAn8c5fE0V4hbsR8HdC 2XRFhh5+K1gZCChkfK+J2gcrbq6vw4JrH2FDrXygCc+fKR9/Z4Wv/wU3Y5ibNupg3TPN4It3P/J9 HP4q25HAMtcolg4jrmM0M+hVwJcI7NW0Ffe1RgPSsbsbj0xnsN/O9ZCIIqgCUGWxGKPTCGSgWnGP tzQlCuUPrh7zO7I8gDkerzmO/aMwqbyf/myVa29bzYWYCbIGCoD9GxTmQiZDHjBONZszJb6oTN1M PSDfPQBApAB9lajMUYoQkl9y27g3ZnHloXQW6nJqTK1n+Q61B9Ru0Z4HTgFYNpl8JeCtwf6JIUhp QkmmRYPAcmj1hL1BdIIqht8kSJ/lymLturcb5GkIbFUgzofFEGhZ7aqrfni6uSIIQDaFGSbEzcqF hRg2q1ET7FVF2BQ0sfQUfZbeANV3QU5tf3KB7uAdKKsd+BPVSAaPLz1Y6X+hcU5dHjIK6rfLSQmF zgN/kv/3cN+R4KLwZuT85ayKcZY7eLHr/xkWLJKxfOHNd3WapVeB1WqLcD/cB5O0RrOueFuwXmvI IH94/ZvZzLSn+zu0G3TyYMyzVNRUOryPZXEXSLPNQBXRgBQioCZD+yJmY4smTpw4FBP+IEFXHyLq R7IA7h4FC8tMvVQR5/9s690y8hz5y0+765rlRIlGYGYEsFrY4Ys91q088IXjtVzOj6P9nvm1WhTf wlJSGMkl/tgwXSAM07Fm2GQJrTFQooGFqCTKnKj6wLff+BTyFqTbf92zzhRIKG+RTbpYRsPYbt0n 3XsdCr4ZDHyA6y0vb7uwKGGQfaY3qvYGXpTdsMpQLTAQ6h8/eY39Z3O4q+OEoOUvMDjzQohphJ/H pmNVwiB8p3/ZEw/Lx+IuroLY8DO/z06BW1NddKTa/NhXh9jz7/mKO2yDCgjPKtkPLlnxMHkdNXlU h52XkhDrklOEUkxPxTXC5CFHfxbjlB8Yc0T+AvrpeQMC9Wc7nTWX3efoM7/M50/OZ8M3e01EEAhi 4SkJ3zeqLb0TfIl2k1rom9SC0qpz2eSmtnlgvW1HxP9iyfyWZqD0hX3Q/p+dx8lcMPUfhA4goQqT u8+A1VL3B3fzG0wNrmh0sSEcNbXKD3fTXAEABII34PkwR7b2d4Jr2w3CLA8pMX9zq1DMMOXANDxj GMvBfMwhvNYpwHNrEOPYNRikADsuh6HsPQ/IgXoJ6UMx4XS0NdUznGUOdtjwOAI/nVx0M7OOG7bV s+xRJ4I0E8+AdGS/eaRyTDJMIDLAMUr+RQosi6coOcxH8M3or7LPxMHKAQnAceEKE9UQfdCG/RML p5nzl5vkb6PyHUFbaX7yZDvoRyXgyzlAHQwcBgX2DI9c+oCB2G4JBpNhKNAJ1BcOsmE7QGVAVGYj +EmWClVUV7O87HDaK6eM14oEzit+z9Rm1WSZtGIB+ULdJcT1ZaimTuLZIHBboGumvenDBegZ+3+S wbW1aLdeVreLgBlrCpXFyWif1bhwODJVoIDVSmSrdZAXRhnkrbceftsmiTG2n2oRlsd3XeNobfnj fvrrPDBdFd+j3s9ehWUnILiAatalt+s0798y7p4Yk+3e2E3NhIHwqcisuUsDV3fSThrVLypIeHPQ r6CibzMtAIKrjrfnh0zTyPM48lHtuEa2ANQW4A4vCzVO6UAamwDjObP+KlHadYB09WOcGIk3jDlq EwPkSVpdFF+wZsB9IHcjoWDUyYh5OXseUEUsKnEF1G/tN9E8OKslgOTJoWPXoBBUO/SMQP8nbxkV YcCvEnmZrC9gxDy0eoaZFPB81vBxcYRfE7LTCrJeAdrjFrSnlziArM0Y+/kYea58/BmJsWWUj/Yg 7Nly3BmId//EXn6FMwejZQUcnJkXPIMZM8HuC/9H9v/mcYuI+P+6HsJG6u93/8oUaQ6Mi7ut3aGg 4a8IyckNlTOzsrt7G7JIha0upC2fEGDXldEXsj+qeUQ7w94nuK4wVCa94kvTm9ocwptiUTTxO6rB lz3+HQEIlbf667LdpDS7EcCjIhZIGNitETTR4Yp/VGrtdzfENEmiuy5zQ0BUUoL0vgr+13Sa5rRr 0SzNOLBThc8/kNV/soANk1cTz9a7c9DpY3s+Z8qEwSpzpxuewojftd5PY1LbetbCxZ1qmMWeqyMJ wQnbPeodMxCekhImnCTSnweBw5hLEinl29hfAMBCZwz5qlOy6VDjwLA/lgKAh0QowOO/EgiRCssH 1htksxOSdyzu5onF3eJwJ75PUOrhZVq1nt0Zx30nnE+ehyIXswTV9u8NPanIW04OfbYTrYcL1iXa xDmcWdpNpLzl7DfMjt7ChFudenRlZ6GuyWc1t/HUZkUXwQvs/++lzKnEa+kLmD/9wFWw/E0cVK36 yXRjgdJI3t6IWXtWFBGka++fuGuP7QYpSjAvTNq5eAg+HPZGZ72KIP7ZZxl9SMr59KzRz1vjsDiy Q0bpcK+er6fA2vXOXdFKONQdTqBGnEGCgWStQ5+hfGz+BKB0UzplsPnlFbjZXLKs6IT4DirGGsH1 brnAo2hK8agQgh5ZLGf1CAcPgUQ+sbkOmDDVv7Gt0SYxZSPuKRbaxIgbj0PiRwI1bitZyRsVLXXR zOhm66HuKXHzXAf+PueGqMc5abn2Kzi9mn9KHOi90X8f+fj5g9kR8hl2pDaW8EvoSMLhYo3mSKts gE2LVhcOo7C4O1sOJiM7k2kCVezTjQfYN7JiYxHmQUfR+68bIi2nmLUPtPLzAZ+865Mh2Anc6qC/ cOgASjdDIsAu/iWfjsb5uf+c0Wy28RqeOVNWDaf2bGrC9S7pDmEqhUvbJ+9VKJFEOleXrqcNfU2G 1bw3krXoJDzKoQ2YBDcwdZvkA065rdcPsdMLG7qnKnchjgFcjA+8YXgQJ3TiXVdpdfKmDK7xnn32 /wYa9dXA7fqFJNSazdKWCpEID8upRDvucRW5rWg1kORcLKZ+4RMJRg8J3bOxMoNCOtgnLUzxpLRl CMKVACfMUJY6ZGrEkW1eH1MePkp7ZR99134b5naUDIfFYipy2plt8q4YkesNy0MPTiQMdTAmR0SZ hhG1idYekv5um1pDB0kDG54Be+LvDZTODtsL3NqbzIBEx4ILDhv1soFY7sI80SqFfJHNMuXTvrgI TX+ttKr6okYXupRhqnytNqtywTZHg2rsqgBtRbl0ZRXUI6OyFf+SfzIJ5AzO7m2bW4+SvCMnVjMj iwxBrtpM5wn89/THUmBU0LPWFkeRVjes3H8m33+Sdzmep8+hw8O8+QbW2NZoMLksNFVe8CGADIRS gz4Z7flLElPGEcWv252Kpi4Ve9VmgkZJwDjGHD43eubmgXqOvP1bbl8VJdveIc/cbrgz4JiFjsMt zTjLAVDNVJyDRQuPEEt2X1+tLSpPt8QQpIQNT8Aok+Fjlzq5j0F2yzSci778dtdGmSzozpQIFIQG o/IbNz6EnELdqCwgqD5aDZRgh3b3hS698xLftuJOVbRKJl30GeTIqgv5dP+wS3M3nf8JPy5XB50K HljCnGWKhegyAjAQ1fQO81LoYEOZgT0x73q7P2xzLnZa/rQQr17gGx/Pfx41a8FbuMkbwpriUnL3 HMlbdnf2nJCf2gjz1fI91GVVP8jjMMl2iAWynBSA7I1ETyLjdiEku/yo7wVm32Sxam0X+BLQ4s4G XA8XvuVKjULj+tkaipvXAfRA09I2mJHFqcrO93n4MarDFt5qHn7mKCmbMpLB1nIkYPYOCTGYp06v WtyyUK7+a57PDqyt6nIMwp/i3UNXVUNHOJ3TwWnK92ZE+c6Kb0Dvu1nKp323TSwz4XTXGrIdLvoe fGSxyWoLyO0JrajYpcUudAEV7yE5PHZ9Ht8mbKSfHGG00JhIj7exA9bV9mMieOkVJRTaop3OGA0Q qeiqlQIdZcRUI9uI+xpSXx8TAOBZEZhJ7IAZPG9ytXVAMdV5jaUBi1e5E1TC3JeZlcJ5XcemgR3I AiVjTd/y/dgetvqOjgrXCpFU+ADgFnG6LityFRzJ2rOWy6RdLyalEQeaLqn+t5XUqTM+qmt0b1rK yfVij3TWJqRsgHGgnIy0hLSgBC7zMwfbtQQ1KVTa32i1PNJ6TBfWVzzzICLb6p+hfYtwl8C3ojox kK4j8xjZJx5m3wMDZdlr+fW/ZKa0gtM2kKTdJvMaZVjZuvI+39DoZWjgX+ibeuxHANctJUwEzYsu KD95hFihgKdhiA/eP9+LeB9unayQk6Imy2t1wUoY14IblXP/9+ysLVaQ0K7/pi9I8vy6j8o4oFkO eCCU0mLiqx46q/1ozRtdNGJ2c08pPtTv4QgPJ8n7ivlCKvg2Pwqj355S503UJOJ2zQN2qCpegFRC 8rji6EOUx3HAi4ZuNf3t3Y+L8WCOqXjuC7O+6C6fVcozqrYOzR6slbCUQh/eM74dpjm4GSpxKoQp KUQ6edcT9Kr6ZJLSnOJtcy+hPSmuRV2BFAKH1xEJ8sIyIQapFNHcSZHRumWS63sjr652n0A2Kal8 nhuE5OXIwTadfq2uHpkPCjQUn05oAMoN5yDipPLAbgSAJP44zgwiUOLgQ4xHCz1/0UjC6cpyzL5K vGi0mmiG56PJI0bLipxjOkGyEpIKMSeLDHqiqFYUMELF3RDwHfLH5qXUdzzo/JnFQ7n1BcAaY5eh aB48xdD8J9xqD8dfl09Bf4fueNC+8aE66UzVUmX8YOoiIauna0ZUsOofVYrlUrJJAYqWe+NJSdcU 5fR8tDqkEt8pu8Wvj08rLdq4Pk2ywZ9TGJZxC18FqCXMjrtSMKBKw/ubs/Cx+EPpRlwB3iCQD6ZU cT3hPzs1u1kKwg9aSlGEusujgw1eO1KBSe8dNUw3J1yDwmWPT/UAKyF1j9amqQ2G5pvFY0pt5iaR 9z92irNYyPyxtt8T1DsAjy3/QN1bca+rfkoxgNLdxlkwl/ImBiGNYOFf0vbfIlbN7LKNVSsHE3AV Ue74jfp4mk+Kd6wzMvlCyrm7+7PfBO1ylwQrMsdJFpX9xKBeReAr1UpYd7kaXdzdD8mtH7G7lmYj pIKwtYrzO+SUWOvjuEmOyjaeCMoY0ssoBV3gu3x7X5cztMFJVYO9Bh5fiRuPrK+Qn+5PQpHJdFLB mTyFjNzpJrlYXmX76nt2iihoCRLSm260meF7Brx/ZAimiF1nMroN7BcHdQje8A8EHOum46Csj8Nf xyteTqXsNUijl+CRSJ6nnIFDSWLoI3HEFeNYybxnzqSXWq6EKb14F2lwS8x2yBAzPHcvYDeZunT5 2G+PXxfWAWw3lqzDn2WQVo+o6+NRaueNbVtIf/kuav65kQNdEbOM5ZypTlGqpaGvvKO9O0EYCYqy CdeMDR6vmtIvNxx8nraKFTO5fBl3b3tIkbI8AoWrfZTl0DWmHgubPT+RLw6vbcgvn2fBnUAnsmHG FrI8phn/yL9ImKos+iiD1p3S9gDHnUqykXcLdZWFw285ZrbzXsLrkLg3s7wIyHRzHjrI/7hW42ns 1AZVWW5RQ154tWezXjA3IY0G5mlm0saaHJskoSe9EDAtyfvlEqg9kh4G6MqA2VF+RMg3SKGGuZ4l N/VE1N+bqBQGKKBLpnpL+FSgHh11HMx1qc1AYLAiqwyfWoPi7KJFd18Ozd/nqob8uomiWlQbWfY+ 4YXuM+bSpuc0huCaBQZ3DJp0kl5jI4kuW+tP433m3r/XY5t5tOpM0u+3IFsS0Pj4jx2dF34e4lcd RTd93ByEFFmDfu/2b3wrkNIaqdPmeLDTUYY/J32F/X1yuc2ySb1LTUNn8OB/ct1aLtkQofLyW5nM KA3HXsoAS+M/9IRbWyloCfuJBsKuYLoquMy11Q49jW1/u8E8nawzHFFHCoFjrE+8gTcSHVMt7qBm iSbZvUBVadfAWjacGbFwbJp4rNrcWeGmgPWfzr40UMENpvOSKbJuP4owDsDelWnHYirC3wHjGaZf /5L505FY1xbL8MMjiGmK8VwZWgoqnSnpIVATdzbiQmQ8/iqRQKNOo4lLTVcGJvIsQp3qJ3F8u/wW V6U0zamGFTu7zCdlu08bfkOVfPziuB5oS3dwnJpQ0BVSFcLDyRHM31PSVobJqflMkJtosprmvMAN NzG/znZmbxdASsrWquYdRskIJ/nq5TDsa7eD5wxLVWUw3cQoBAAuUhSfOZaFfuM+gD11cxcoI1fl Xg9Hj48JLSa4LjCGUnepaWsBWYxj71S7V5T94yHC8ePo0Y99hBpPhS45JdBYTvmMdsLR5CQBgnH6 KrSJS8jaE+7DFAz40/TmF8s8pdpl+xXfXIY4QUIuGxnRJCGSsDWeXN8sNVAN4TNR71nVBy3iBtPq Z4fMqQLAqACGoRthlq2o/Csrf9o4CWMce6AWlUry1uhPBB21AxxuqpYF0lWewAGgs56UfCd5qCqK D4PjV8vhAWublRuVkWJqrhBFV0W5Z0lgLSMw4g/Qem8wu26cA+nb1Fj8MZg4A797xCOzDTsrxv7E ZYUZMuA9x9kRtD58UDvijaDSGEYpx1+P3CpL9G+sCbn6nTNDIHtEtgPeaOTqIynlXsLH4ev1p3Lm 5GPSbHtuFbNOQ4LK26pH2D0QxCT9TRMJD9faBgzsnxoPoLLk7tT9BP3vHP8YJO0VLsUEcRfac4Xm ahui7blRVVqrdejADJVuRM4H+4n/F0QyJAqs9R7kbDH/V6Iu7Xi2Emo1R/x5kzK+Y8hbIHy1dIGr S2DWclY/2Ii+Vw0Zxv0fZa5Rnja65wNQ7mlJ+5ovThLObsw1XagEQt5hTuKvf0Wo/3uYa95GwAeg iZxn6qJvkDwYnmkXxs39cwI1jJVBQ/Cn0mCPNLD5W/ZFfZ0YUwtcR4YcBNOpdT508xgKeku63Eyf 0PVNa14naRkor+WPX+7q2KYZLiHHI3u3eufwAHGZXCn1IAcI/AHCZAxlhsLAGG/APgXPhmfvsU3C 2SGMYfQfZSzNILaKFXSP6wP0yH0nIKK48HLgrPojNShiMxdlgSyU241X8yRAW2mvMg6p3jlf+rhA m5lhR0BEnUmHc6FH6pkEBIwZgZdlOB6zvLxNjhUtqjNCJUFTuJpnnYzlT/LZeSQeb+or2Uy59WLZ ADOkvU/OtsFFgnRCMeu9fxOGh35gve0KWwkoti1PYhtyXwOcCnVTREX9ED17B2K3YWJig+/Y8RBG uk3pdnGF4h5t1UZ4JPh1I+tFn6GWju6x0JdlfJh3AVq4J4+WB55eubM7JYnl4HiHqgFEDSsfMY3E FFxCyhvsY2jsECVAqbaMsR/2wcJrLjkPKI+uayk6UbS1iLjgYv4Un4jylyyuZfY896EDEl4gniMQ xKc4znbbepcijFsqscgzbB443wSa+aY+SKUYeVBA0/kR8eyPZohe+nIwv9DCPH7fm7O1O/fOvjbf fuEMHB4K+QFKJH89Y1v6/kiEArsUe/XcnYdT66TY9GX22savvu9/LqD1Yhws5N/X0ODsuIcWXKCR VBC5gsEILjzwzVPnW3rE+29sTy8aTBSHOckkR6SwO3rEHo8Nnjv1N7X4c7GuKB7WZclzw5g+qsn6 ys3t2EmlmxJTUwkKhe4JwhFmGjJE/7oIbDZUCgQOozXCDcJzYcUyumut1N8dkzRfb51aB5WtVM6Q 7t8MlOwchyf8wDwpBsryL1BzvhPzklK7gCjTk3nL8TMWi8C0coMCrdiagtSQrQYXp4Vdu2O00fmH Q71y7IRE+Ok2BCWG8FHTjkWGLpOGjMO906S6z/VwTiOPyXu01DNhz694N9qiypkYsYneJ2VgSX8W 8Q1zgQ0MSTnf7RudHvupKlgWq5G87uL95HG9GjtldkbFB9XZRZqMiHlUluyq273h4PLwQU7AAdXx wPoTjK/p9UB4ccZv8HuILq0cv54DUH4sF7df1E4ifejC42XGAzanZp2ZOAUAIu5V8krVopQFqd8p mgqyHNEtELkqDsCTF6TL2TtflpmCtPdQrvUEUtGVOh+kYEbgdNxYWmgOitlru/U6S3iqhOa6eKkS 7hciUyMx5qgqtc0UyfcaIHx+8YSUmICG7eR9iGzobT6o5nsJYPO8Nwb6WepPz1RbM11ferEbdeX3 /jeMGQ0msm9gFHmRc0KfkQ1FivxS6MwB419ICnmIzWh1KrNJl4UVs9dOGTDIrfRitK1JREwszYOU a/tk2n2/thqPNnWXRAqEEqhpMohq1szcxI8d6FaYt7v4RvbSo5zxkWSVm0PgBJ4HjZ0pFG1cROdA ddZk6mAgNiO/TL5AEHinNdPxJfFk8W8cfMnBymltulIfYNLC//lBZgpKe+jrFenGJ6U8p9qdyd+u Re91r7zfr4jcgoxCjAf4/2RlbqRSB1zCWaiJnyrlEChCjMmFXViK0YDZg8fD/u44wPJHUCnjwwsJ UBxpoBRb3AXDrJfxnVvNBNffIkq0/zVj7r0XsI7lMfgMuIcx3w2KHLRgaGZaxn1SsMc8tV7askCn hZJGbm2zwEhqHSuNkBRSqnpqLiVzxobK42E5sgyGU+PEzSPJvCoayRb/irlUobvEJVjL499V+fh/ ttMig+FfpJS8EjeuWBBEPWLumZC0fw6zTq8ayAf2teXwLHDntYzD2VDSWIbOhrxkv619hMvI+8fv dY6aojJX8xOEQhsTgh2AHJq3uHoEm+MQqxfBIbhCVf4/R5wQp7XGSDZLqffDlI6yD9KNku5J09a1 2cCMaq3Vb0l5uwm9BCko16umMVFuLnpHJtJ0z1Dx9V/ScZmWtYA3xJyZGH62PSf004WdEUoxq2O0 VH3lx/TLdAx7lmCJtwubNtTfWVkM5CqJXECY/SrrzIcvFCX1OQIgVMZl/hbhprLP2/DyR1Uveea4 6+IBRBTlpZuf88fRn1/plIv61aaE+AtvZ0vEkR5DKSFSAEn62RIhC97yrP8BrP6jtOKHLeqT0Sn4 bm7vG44geyklMi16G+AanNP/Y2R9eKGqRVGAjicl4ChAcW/6VXGTn7iV2MvdTYMKL0Cpam3CO16l ZD6YPMKdSRzStRjVIC+TotP4eU90polClc/jy7TbOMlpYRZJUJ9S2NeJY6RNsuSUNUhWMilbLjF6 1TfN41hAI84D2hwO5nZVHCyIOB8X+uCeflAbfkRkEi8ARwiv9eeMsHAb7oLLcS3nKWlBncHD0npE FtM8LnOKHDpOFS4dUM5YyMhWWTOUpxAaeRuUxj8XMilxiHUhRCIlikCuxAIEvkLGO0+c4rW+feFG K5u/iZC3h2UsN6oEGNPCN9UOq6kfq43/mjJRyaO8rcSHyO8MUYBnQFwKWXyC5EK+6Ch2Ceb5QFtc EPyzEyF7N6bk48vnhe5sEIHC1N5oQpwRvleUCZWti37wgLjeSzNVJjBzpR/JwCx8daOLwaUqewbi 2wenxThdBNwmVKogWMgb3bHvuzvj44WuIhTK4P7CffmS7Kg7pWzALyHZWGJ9mfpe5oEEE0vtjMj4 aqQW5eD5Hb4TNv9hOnZ3pefL8/HLb2h1Y1Jia3saJlA4BH492tKqnrAh/FYyjUeuoH6TOBUFqlpo ZIUC7FwY8/OzEpaex5K537ka5EX3ZRVGVmlgK9wF85Mqsf12uaBu2dcN6TKvbyH09KfIKhuJzS5d p0R1hO+KtLH9Tn6z5eBstcO+G2ByPL/iSGNaMqL69/R3XIpcvJnnL3djlYRtMRnPCx8RPl0jfXdV skyTkjFLyT88jXklMOZ5C4+SCQp92qvpGR0HY6yaOCQfcke2nfV5dz9Eu7uFuwy2mxr9TSXG7S5d VMOeDVQAs/p1rwNypbHbphzFr9iB+yCgNKT+ri5dfrOpycVbynhQcz81BY+NXEDite8r3GiHOsre ZRgiW7hjWVK0kulxOhDN6LKodXKu1N8SpjECFY/E/Ep8lBM/x2Fg/cMz+U/HccOdoexwObwWhpUJ 0iXL/afOLAO6Zo7fu597u8BYX/eDTIGhGKlZIK55GjKyIzlI2C2d9oRFLjW20HHQKlLM80f7xZBc vZkuEp7RSDoRI9Oijbq3bmA1ip5MJbTo0JlHlJRdIHyCWj83wrmcGFnwJ8/uT3C7CEcG74ge6QAy KS2Dkg7Mjm2Mj+opckTeJjvsvKyO5b4axTN3uj8uVEeQFrLqG7wgn8QEL7FkZdHETvL9mxnk3DLW AKGOlJGRqs+Y2eKWRT1QnrAbRN1QjlGlD6V7VA1m1rLFFRBkwtWqY3WRxoQr7ZTLdPTkwzdYbChp hWlb5hyBEaCAwhG6JAm8HDrHWrOpC+BSla+N4ssUTT3mOOq+faTyfxdd2ftYa07g6PkDTx5UaC7o LbH5uHnqk/cFWaKUwukXxUNFjXaaqLpAud8pvp5cr47xk9okj0QexfSRTR06hGshkUvBuTYtCG1C CbUaWniMwsVwGL+TKrLm7vAUdxQr20ek+jH/N1XFa5xjBrwDHt93S+9h5Eich/Ce03dFv8/QZLvS RC91IlkGsVRL6lsxBAC4oHI/ZPYJqSVDv4AGwsSLP1jihnL+lVA294dUpbUDabLt0Hr1kwRBr73r d1a+QCS5PWhCf7XpoG57P/FTDmqt/EnkB55vRt36PE05IbBToD36bMh6BEBXONeGCSOs1an2P9CZ 8RKUTImNnIiC8HgSrZ/pDXYQ4E9pw/LHCeNw1LTMBf091a91BNkDdqEy2uVzyrRzRpzHYMTNZE7J 5oRXlX82VUn1aZan2b+xJIoIc8VBBU+UQ630rLtkdFKdJEpg2rtn9l6qqTtzVlp7ufol+475P7S4 WRKDrXAGT/SczP5A7Vu7P7V1yAipazcCPxoSV0FCnMuP3SFbu9Nxakx/OafOUGy9AQHuooDgVUs1 WcJKp5Diw3JEwtZM/1lWN+M0GPIyE9H0JOPLV8TCT3h+2cm9r6pWPhDYeyDmExuQmjzEE2sQcb6H zNgZKNv1naxiGRkPO+wzTft91t6/PzHRQ0LYL5H6e+GdCeTpcXmqAmhILXZebTLngXMw29MYuSQy S6++lQFef+Rf2ZnNXXmaSYTFePKrQzTnSSmQCmxS2ZKzgfHM0y4WYxPJZgIORpWqnU6w/FQr06AV IYN8YWFLF9sW9MeWo6kJ6MnOK8EpEKrXZbLng5Zcd0v9PTkXkTl/RkL+rroZok8DNS4//WGtzbOY 4IIstAJqiufrR2mjC1o17ihKKaErsB9c5wMaPWHp32qCXNy994pOLEBoPjvnLgWd5JzhSgM5I/Jn blIsFWaA0C/sOr0qFvMawCJ/9BXpk6TBOQWBBH9+yh04PUiP+UzdJyvqOa/udwc70wMfsUmkpIv6 T/rPJQ8a7g5bTRlC/LB86wtGafY0zbPcxlCaSJmOnL5dzfb40e1rLa/AwmE369xDpIbT38g6GeH9 UTkpywMptAzGQ77fGTjWDejAdEHv/DymGXQyzWQxLFW3pj0RTJU8+dsoVk4Ad67/sYO0SOMw14jE sngdfgTXg3N5FPduRGUr5g+9GXmJnwsWUp0YTI/GK1CxqepzQszg0NS03iHWR2RUpEFGyRvmV+55 QszbLuiA99T3UB4jcTfygn9Zj2fGj4gtL8UWcxIYuas9cSrIaDvGPs4GJoqNhLOmXjx7bcYIX8cE Xbj7F8y7X0eqIllZ0dLYqb4RyF91apt0S/jM7VSpE3sNZnuRUk+Bd7NEsmsnAItu4Lx/Oux+I95Q HP5n/iWgPjT52OOxYSkh3gLVB/1L9UXEVBSD40Kajf5PF7fyTtkSNRgYvnDflBaMqD4jjO712DVB j7qDCCShbFVQ9s8xov2XM0gRANUAgLLyRzfk/bOI+TQOto68tYN6q+8tcArAbI4nNK1Snq1vZkcE 8lLOI02ptWBsbQu4swHeGaOucwUSvDxPuwXZgOAnP4Fvn3aTUdRowgjKfrUMzeF09lsyQHUGjvzN hWDYpfEl8mc6JAIVfWxJkcuSFk+4fGHdx7xVktuNhhq0F3u8MC8z8tO6RWH7qlwS+sBVsQT5ugmL RrWRRNOP4hjInXvBPSThXRI4wZrdQZsHJnIYUIACp50iTZFLJgDCZWaFJS+ItMH/iptb62EkjBJ+ OUBTzaf1g4cnQf84uP1EpehVcUA+2bXzHhegZ4+grB25J8hLR2iZ4PCtHThfiFmnQ/ZrRy4BhBWb zWibE8UcsSaffz2dc+3Jr3PhC5rE4aq23gDhF3ShNkrUgfAuDdAiZkODAUtXvkAwYTenSA0gSxtB BDeCRjLgbtNFWnW7bSg4pR4SZMKAI99gdF+kll6bkTHntynFEqz9SuMxlIW1JEmBjbjYb3NtEOr1 aXBLpO1w2F6EDoHl0HWGAFjP+dUvXrP0/d+Wznixm6TeQVP1beOSCPX3nRT2PRgTP1bRlFcgMAMM QNdxFRIjOUKKsYMbsrYcZUwN521aoAShtQm4bHBL0DQXs6Y0bLGlAx14zyNeuXnmEbskOatvEddT NRLNQHr0sE/m5xlvfgt39GqUbZ06ihwlsC6uqauFtQ4RTySwnv8VSP8nHGTL95GAEj+nc7hc9UGW yHGsA+tulzrayXMCgDMzCm27oaT/I43K6G763kbC/GLUBoZ4phgGrrQ79q/KTyIGhqmE4Nv5So9b CBFPqmniyYUMo1QLQa/E2J3HaCxP7EpNwc5d+IKLoLGaz0LYtU24tUoY0LrZod8PxVEPfgA3KQ4n AuS2oZkQLVvoJri7jUpEwA1dkHXdhRP61+3BWSzugTfk5yQKRsX3aKtq+G7E/67ZzVuiZB3nooFb EavXGEp2HjTLqNsVX74mPYj8SHEUd+o3CdEfz7msDc3ZWHeK//u83NTCmedKQ2AfRTWwm/WCecui I9wPZVqi1skvvY0zkAcso4Yjyh+SnrNeGCaeFjtzlw+ce9GziZeRZFqrjUPgwhe0AIJgKX5bdYmK ptXf8f1i3VCyE39BpTcijsJk4EwVp7PypToev5pDDe4HNIRmCvCN/CyBpFu1ViDu9SH+y254j3Im 1NoPi9oaGL7hQD2tQy+ez1mysEp56AqAAHu1Iga33wRes4hfa8AtUjwB8YWwAXya4IZzn7DWcQ84 JIc3O/oe5XzxAHLSP3oOVjF+CSEQ5fiCEIuDaW3tDdi0dnehA1JuGba3S71oXLXMkY/g6pX7Yiem 2C0Y8LuVX5RnMM+IMcXLQn2nW6DpmP3QXQkxQp+zK40IdpyKpjpUl5DgduJVRjy0uHXcdb/ys0Od gO+gx3gXCHUXGfN/FZVCJ9mVW0Ee0oN395TIZw2whOfvwWsiXPR37ahkjAG1zBrpt2Ox8Uhn29fa EiAMYHTXMe978ODKXKvRk9eQjaq7/IwjM+eVb1cRTCb6bLT9hO2D0PO5dBNBV0X8ZgVsXFpwu+6g LEgaAzAnSUfEVlNf0860JfmNbF9hyohvxFPktx+3LhVzaaVoJpu4Fr6CJCFpitGD08Irz7HyrP5P Fdc0mGZUqgjPJ8HyZ14Rt9cDRUgwFdS3v2FuyjwVm8f/3va4iFy/hIVp9MHynS5nAYWARUrnJmyh UWMiQXjNgZEmzt/R+tKvHB206qEpJMMdL8HB+RZCG5ji53x6Gv6C3rI7SLBK7iqDG/epK3ZYYk6b p3f9wpDbT48U97MKj1+DR3ijRfks51VIb4p1oBFO3jwlLT8Bt3XRMqaVWoe2SoU89jba41Uw07KI 2vozO9jtNU/AgTxakIfYMuXrqzid03XbCR4YGOkFlHHG0ZZocnu6yxEHw//rJGsHCxzjcKug8CUs ogSMygCK1a26P3EZHfkBTSc5akPw7/dB3UYS+X8cDBuIok0hyDJwmEaIH3/huuYDhHDmQ6HRCSXF +Cdpfs0VjD/BIOQ7Y/YdGzbIqu3tTyvwY9lV2FlCpq/wqXzAk8umAqOAerM74gFxUcPGPY6JBW8w Mw1fembX7u43Uoi1qt9rrlqbVSk5sovXZD7ZwvshdJwVot2RXh01hjLXkCZLCVg4HTmwYYkGbRww DXfxNjKyXHVM+r2gaKwXGiRsyi5HGsomLPoHdAaL6d2f8Tu6/kxjUiMrfTZG6LV7zk6udQZvY0bE qb0bG1SgOmuyrDKw4NlRxYI9CGwD3a8S4RGLh0FMXvrnHkUwoI40wGw9PRrA18D+BfQcOjT4jo2+ QltkPKjnMkf1krZsVdrE2Bv6L/VQPlsPmrpGK16aQCOpO7cq6wmDGXFlBiwpUYc7C4o6FonlZ4+s cunOHJcpp8pRYZR3LBckUmaLFGs4eZEhLBWvzaQ8EtAXNWY+h7rdtMT/oI5kJdDUCxD/XvCfpIdo 9aBuaOl5sHYOWmzbkxlexU6f3x2iyeMgZW1oPuzNwjYJEMy3YX3GbAwXbAlm2syQRfjaMzVe7bKL djA5eqmZ6Tsok8B/KfY86Bg4DipK0bT1YZ+xDm96YtwgVXc3OYKD0gmfxCUMlyB/3swr4N7Hzo6r LfdQJSlo47NoeJyZgxiQfCK3dz5hBVPxs60ghSDx3R/dyeFOaICrLM9yVJIy4MAMamWwj1Rk774n Hz0UVVH8rI179toQDFsdHTHB36geN/fuVfQHQECRBAaA2LIv/FAhDO6SauAngO11NEaWImGYyFt3 DnG2bDLMEhv0XMYkuBBkLHeuj0TuuxfYScwmJuYSl8yHVAuYvVX+BXCVUHDbF+6pKXXO7cDcEAbm vqYbY2YuUwHVC5hQiW8YMdVXH8TsI0W8KKVS17FnDVRpyk2cXoFuS5/mSZkLx8ie7nI13Hkd8S7d aO0snwJFj+Z12ZHfQbkX4EgpAvD9fgZ4n5PKJ/jONMeSgp7l1es53Omm7pQykgAxVB875qgAXTg3 7yuKgVg1V76Y7UnmIAjErYlyoCPBZmef0jKZ6M8ONspk3EqNueRi27sWo1bSkdTwbCqHGuvC+YDc vq0O+jCuyofwlm4ObtzLKEopO1jhErJ0kZsdJmnymABDODWy4D3IVDCMHC3RRCyOoTDqpgd8CidA BYvJyWAmzoCQpfD3JipQEYgeOcB0B/DsEXTKiuK9VSimcrZnrkgh6bnaOSdH6tSTzCg3eYsLxxgc lXcs2U/FEnAodYEeAPwwNEsSHHU5AmgyKMO18sCeSynqz6b2kxpB55IgTRD+XLIYEVXLS3bLAhMu amRHTksAosxqTEYFbtC0zM4SqQT11wrYOQm+vD8lvtV7t20TmjMmVMb3c/R4nP1RtVDOnP0x2RiC DsoRltpgR4yTnldTeXL5/qmR7CQnY5YZQO8MQfL6xrzs0CZVSSJVfDdWskO6v4WiMEVAt/m/xGIj Udxae5f5Blegzh7AMbi+3W+zdpEbL3lLhBwrqHhBQ0Yy3GKAjU+m29dcuvpMjN/E5GtiHfaxGOlV n9Q78fmfHSGbxAPX0lRfM8FF0qkJhc3qIHk5O6+3kyHUmc0WrHKu3kbC6astGSlPe1N2Wf5w82m6 dqIp2BPYgzJhC64rNvyjKf6xLxYfhIUipjDm4XOvU7aBzK41EcL+TP7oz80im0iqIedAQJKVLZK7 877ThZqBaLp4w1RfuPGjYD0hJjg715zpw3Pp6Vk2vdnK6CaMTHhosi2TcVegQgzkKy8WIKjK0qZa Zjn/5ZdwQYC49zLR1g0LB0LvqK+pxw1BWKaulH7dZbWBtoOCIYjpzyf47778LrjswJ+uJ1CJ6dQ0 Hj5nsswIEFKooGngkcFMNRZNT0JPRvVlP4OOHe6ZN6OCTolaKnEZF2hN1KAJdlagoYCHa8hiJl4V 4EKGS1ZCX0u572fxQZg9vyIYz0+SH4166SSoguDEoNJMUkrjrApZuWvmcXmrLIOerjnRUV/gJU0L jqAf2ZBYJqoAdZObm9o77S3UUy3jm7UQPVbUqkaf4gfOatga+hyJhm020fDcI5oO/Um3hNsHCkus yIkUz7oJanzb89XzGVxhU62xNiIRxzRrOeqacmosQANWJOKY6ZcZY2OOpgjhhtBnJ833ZNXcL0G5 v1jqnNPlsk8KAY4JxdAYUDTmMc10NgxhX8D9kzLGeDIonyesWVwcK2jZzDQA3DgzzlMxwoB/K4MG yz4Zk92RcNLsksbQoj6RKnfyYaBsRfNgOj2BA7D+qSHbQVmLQQ4GswpEwAtPvABMjstD3BrPmGnw 3+RiYBpEf1gBh3LTnzKwNIevbeP2My0Of+TtdDRlTPbGgEgJwq5tTpNR93Hz99enZL1Xz3DskqOB gQaceGmJSmLJdZ8UEKWUEFf/MOB5ewCk5j3B2X4vre0h5GqT1ins23EsF1caTiccamp862vkSWHx R6AvoVuZ+66WCJtMyoh9HXCczBDQv8Nlk4GAOE0tZzRaZ6fJ8u3CtHTxdv89M86oh6ShikNz28Pv xwGXZanOZCmN9dj2z1dhzBo5YShMrAaJIK5jMPQzv4/ezGxhTjVpNFNNYLOJB/y4cga6vSee0XJ0 EBuByQLuo49mmCJI7JC418wmsn9RU6ftq2JWfN1Ix+ShuaYUDkriOJd5swG6rpoyqSgTLsiDOXnE 9U76Gub05FmDUiyeq8DsLuFcZKLk0jQw5HK/xYlqoy2rdIb4i917WorRD70t4j7R1T2PWxgrMhsb eJTQi29ipPOQGgoGWxSOqKft+FqvDpa3xmmUrdP7ui7+wmhJLBvNLzPE9UJ8z/n3MF1YGEpKSFaP iPC18WOmOEWJKDGWqw+OHNo5XwIuzeLbpyAAsH3eg9dLCEem6K5MM4HKEKKPYCan3oxPfGxbIhvA xaWUWPlX1j9SQjBRKRfaYPtfhDnjav5JIduL8b+Y+94hjcJazlZpw7VILkU9Q5JqgzZgXbvwLgLj 2BhiuTBMbzqFZVQZHOJtnseJX4Pg6fGKPNqqekm9yG12r3xYDP7ax/v1qjQeHKgAlQgt99CJt1k/ 9pZTkC7qrkm0EjAMHOARc+3Xc4X3bvuUufP0EoWceLaFnPQBLORY6wwoRLvqwyOsCppHKm31KKCg KX5HupLCLJ9APxYk7Ro8j0x9+lfSAGQQiUmKhwdELl+81em3k8604D4BXZxhJ4FPBV6ZS0+x5aUH H7mCkLb4aKsNZI9vtr+F6bvmgDaVTYzUslXn0v4PHV5TUtCtgDwEFLVLUMmByH4MC/kMpN7h7kc9 M9IHJkye0yi3f0wrWonOzthXuYp4pmhIRixaDz6H00pMLIefnCuC/FI8H48+wYkQ869/eyFqrXhR rStPJ7+5ck3LmX38oLAy+sWXKm6WQupn1+ejRUdOrtSfrtxD01DfhrbNxSFjzYbvK8twJQZfIfma FkzwdI7moNKQkwl/T0Px3nvsjl7ouZw82O2NLlDQ6z/pbGYvjGlG8oLV0LvTI7s8oEkA2JC1J4zX IQ+0qzcoatIzTaoSA5Up4+tXH1TC+M8KrZ09XMdPCSScSNmqpYM/jXIKN7vamABvdnGexg6XUG9q PdvrFxdNsM3pXJXX4BaZOeioeCNJTn/YZvnbWVSp0+VN0kKc+mBqMOCiZAUO5JzkUsu8I4YrP3/R UxOzBjw7ruiGwxVkEuaFZBsxMIw/qdOd14quQkH6rnSRRrPgPyOKuRZjHtrWQ/BBQuTNG0R0+2NH mpmFyhrWK+c7TlAmojk0Vx15A2NgLSzxZdW9KuqoMZQvpFlVvYYeKnYfgh0B1ktw3ZW9YJyrN8N9 Ss75ABh/RnnxthYvH5g6FzfoZB5VTrsqJS0DwNt/K8phQWQKOpaMgZTZ61O9sN11WPABj6eyJYP7 t71p6IuUlBHvM62Umq752+E51Jo7MziBlrctvhioyjedOZk2Lghpjf1DpjuExxX+56M8byoR8sc0 bE7bAjmytxiiygg0opFOsBuJetdCI+UiwMUOSzvDa6pq2n2CQt+0FcIvV+bwtRHG4ObEUBy2KuvM UgSsIimGmLy4J95kc2vst6NivN3ds1MHGMjPXwmHv8cnk5uFSIu3cLOr9XUYdr2kYkzAZ286JDyr TRx140OLIc5JnbuTxsythsmnH7jiTgc4vvShVUUcXaQANL1VA+rlyTVz9J5NeKzwr7p91Gk1AK8K AzN4haPy9hVk6v2Rz9aTgqCqeqOgwWjq9pIgdc12qbwHBrmhPhd7bYPCQ6PG1uSOs0DITxZ/QlDa RU6E8jVARtkoMWl2/tgcgDmTxfv7vcqfS5anG9V5ZUVjGC6bqYezKfcutouii3iiLEv9XtlPumEy OcH5ZfIK0N3Q15mN3fewBaZ1rqlMSjVPKig6g7QrszK3iBWPtDp72slAE/t4FpWp5W4tmG3lku16 ZaJdoh6ZpKyyLgYUz2+oPF7mzhHsgKSp7PVIz2/xrhpheXuRBh0PrWbcew79yCy3U3CvZY9/BFQn D5r0MgnYNh6vySAtaXspORyQXxeESYtRdgXewngNNuihpV49YAElzvAfXFnPvFH9p33TUtNNghVN CNlUHXV7P9TKDeY2LIfgxLtsiapG9bRUtF4yqWpNYZdIiCcHBH+84DghPsTKDa2k9VEIMmzbc6lp b3UrUJmNoF0GLhyY4MSx4xEvzWi9H9fR13uCl4eL7WqnadrKKnmhIVXo8KVDl1HycJhVMBpEXjH/ dFTl6iQsD5rPBjFant7I97Q/KtQM8J/sFV3L/EOPG6Mk1It5HZp2093++vM9ZTb5ZCHtJaLGVgi7 252QRJeq/yaU/rkZ/3ugwweh8oo+dxAvAGJF346WDGt3e0qCIanipID/sXVNl3RPLFWQokCUfkRi CNuL/nQe5ZcOR3+yRf+M6sM6BwfgA7Z9Io4GMuS3TB81KSvZPVJKnxhITbE0iZP6G6QkcEtwupPl MNkTyDucK12Q3uJrdwqvVSlo39eQG+sT/0TepxGtVAv2hEijqpGHFl0hyfj2wN8JIO5ZgjGsISYc RA4pXxcrP7r/HREGTri8N2dtJFCf1c+/tWM3BZ/HrTWtJf4KhAhF4/C4BvTwxYsi35F+4AfUppiz WzKjAKq1SQWvC97Hj65QUSOiTYuL10kA/864dNWVmw/M4dk6U1FzSmJjL/rQmkBOU8G/q00Ve/pL E1gh5avoEUcjdv1UM+D9l4WtQbf488Hw+/OxFVxI9MZ/wAtUI30C5UkqDdxh9Zk8z+5PyrsRN6ms rFdjFHR5jRKYYfJeLAkFr/Rjc12qKjRr08L7PZT+OoDWZwp7a1YQflHD8VGJbYkW5dKD1iBlZMo9 5NhIrwaOhKK8QBQIMa9mWAog4AzHk1sGpIjMXiry7WVo8M9SLRaRoUzrJPy4bdcP3Z4z4iSNQnc1 nI5vBP5O/Dkuh7QfUpB3Mv+ycweQlyfLqGrURuTHQARHjKyADJqABshWiErJrDMphrlMtAGjrsnj Ei2AgZR+QXaLtb5WdDldtWCt2/NOuiEm7VZxsJFFNLEUpjszlHDYDGMQps1lYVbtW9b5S2aS4h5t n6+aYheR7Gr1gwn9MOZSUOuIQlOypBYwGtB+WWLU+e2DHMyzPYl3/eWbzM+2uyWzhOYmpMt272I9 J7qR6BTnYltBndD4QfBKmGoXPUWhkSl+w3LNWUZGslHT+83OAwVe8wP7pBskiquLx227DSVYqvd3 cnAzYv+IyrQwl/6PAgLmTws4vmgTWxSPnp9DXNnAME21fJXYZiqYTI2pGYQoq6F4Wrs7W/X+/bHC vPaM6GPVHssaaZqyZaHjTj5DdcpJ86FdQqJHiuTHhWrHUvmIbbZvrm4PNwrcI7Pmlr96ohb3vuYT ggxQ+CAFO2CuEHZmMW9OdIz01cZOefumk2u2UwQRJjXDiYOanxiljMn0lqKsP6K7h2njX3bkzOod VC6R9XfILZehiRRKmDRQxabuTP865todO+K7TeAkFYB7qfRI8S12j7WwAtGtuKcjQzysDa0PuC2a eMzuwsH6Sr1IWV9gxbeVU8uvNvsrGmv1xfXWTI9a2BXu2373YmWfCIWmLUjZOXYeC5CTpCLpuU/w WKyPlfPb6tr/tRFIAAHyKo3vWcND/pObU+34CG9qv7PebDvF3cvKCgw40V5XqgxstyzfRDX4Feg6 4V+WYmq4wpiPdJ+A8Nrko+4rKUn2vquND5/y6ihLegDSVgE4EsurM47hlSFc56DPqZZYsg8wZbc2 42EXTM4ZY4fh4r4ttNvttIRLGE/lVgB4SnrhoWusDzBjoREER5rQVwjCjec4ddZD/Ib44vXYTM// r3LtaJEbZlYFR4+oQnqAQ1St1joLxtgNPdThQgbT1w/2jg9NEYV+rhI4FKLYUPL2TMR1fOerjSEE K2i3J21w6ECtbdLvCM12KGFgHAH45JinFKLpAb1X/Q3zWZhy0wwIvV5tmjJ73EcSabgG7lqoQ5Ee xg6RhtXIOlA/G9R7TLR8MN79crby+mgzcRis16XXshOSokXEh5Ft0JuMhrIjmqbAX9zpevw/Xcvb ekVK2+mXvSd/fclCiBgMGCJJGtIo+z+2bN7LZq+60bLLE7yyARwTV8LMqYrMxaOIrR1/LNIoRz6S 57175OUauzTQtx7yTjb+8i9/1S9YJoAYWZbC1jntfLJLj/VqSVqvwCd0dPk+CnKBu2xb3297U8uI 5ea+0eNPkU8obMdfIFewCxOJR9HYsnvjUg8+WSyXL3obGrfUjGWJVbOi//HQoYT2SuqYuHjurqyC uLntFM2IR5AqkRjPj/J2dtMzVNabvgtDUmvvUXTNa8Ie844x3h4zqa+wCLHdJSy+2pbKvXhv0lm5 deIYmr8iceoBCt02c/Wk8KhyE7mqhProBmh5OPuZ3YSXFt3yVYPplVlkyQLPAjiVd9gbAgqxrbyv BdZSugvTft1aP1sLYXycdnK7zB6eX/etEhlTWoQ911q07G0sJcdQhcpN6Rie5s4OW61QaqEBHsBR kNn6Vi3cSjt3S6h9+Bn6xNJcTatle4CN+B59r/Xk0z164nui8wuH16Ie5ghi/mNc046oDdK1V+02 hRAVsgzpzSG5GDlQBKNqkEXld8Qaj1031/ZZcatjTpf/6kekCE/YBH0KHevZhiGyp39sq7Pr87aQ qKeGZRsgbcuBO6iUJAPGcCiuJS8H/U6w0rw8Hy8o70DWAl+bsCZYp8/CHxEnhFmbcWq3y5z2Ai2Y AoUjKoom/ybdEiLvvC28bBbEmOE3DJH4zKnKySELrJ/NGnYfz7eSYCHz6H2NxlHxCAJf5bm1vMBv Q4s5QfwKiLaKUzXrL1nVG+29N8/ekOBNtM1vKIL9ibNJEuyu+lhSJtVmE2IoZOZttwYSq0DWXoNg pY+EMrzFB+U9GpF0S3MsKAj1AMNd0u+IH0QUiVdhuFgDYu6RH0oZDLlgSRmS0+S5iPjtGRfaSL3r eCEg02GEIAL5Hs1CTPfwhfK244oary/yajZlKUbEaWj+5ggZidQ/KtqISDWB/p/qre7TzMEaBLjp 57pMmPea3nS2rsCEdL/6g7ZkltewEwsp3jo+LFZrNuku/e3lne8Azg7md8D6bjPn+oWqF72U93kH O7GP3j+7EMQP9FaVP3NDQ4K4jcJy3g0KUxv4vHLptAE4h7bUrru7x3uNtdsS+SHoyiFaoEBOOVmM SYkMuzKyv8Qq7EqKIIZlv5rlBdoggGjiyrIpekaMYZomO77ePUg84JCg0fdmzkQu6W/WDwH44zTt Kg8HjDeza/r5/TvvKoQJiU7oY54kLFuoHo7sde3XZ8Ebb45QZH2QFS7yaULuxUnTnYfhv8XJeU83 vQy07+sjXcHJ+eh+OPz7zzKHU4BVrHrcfRd9PbyRTNhxI1/K8bck4YFM7SC0SkVV8WBi1JlifCJS R4V5jxgWO6cOWP2TNcPmZRELyBwOdBkJD4R8eJCfCCBdfVs6FKUGHvtaeSlINuOKAbWHc43lkpvd RgS58CaW0TZv/69LqDX+SjVyALA168+UrwI+Fg0BTrxktIa9tTBM/Sa2RRLmU4m9pEaHAyRwq/yB S5A1l1oevXJrWZszuwB2c7APPyTvYpL+zO38QHE73Zyz7Sx7Cx3M1apni1AYEB/ZeSJFYT8YT4um gvlg/fXKN3VsdKnPwf+25KrdmGAg+lO+mooJR2aLv/rzrqec5QRToIQXeesrS8CiA8zi/8Lw7Fut 7wANe0skYYx/FNxpGAr8+nkTR67n6F2srxNuZeH9KpoYQjl3TLy0SqpsQArUT0/wjsnHZ7LzaKgU iL3BzVycFBpMxkIrgoRaO92hEXYBgGYr8tE48K1F/cRtGE6wEmyBsSvyjfDGdGzcJANwQbEPIdBm ALsw/6AuIXKqCB6TRIlR8/pxao5clRVTakLHKo443TvoVXCPVx8PvPi+j0ETmavCzL+kXLittoYZ 8ODjLIaEtN3TqXm9Zo2hFS91jqFzOLgXls7gD0fw1v1FD6yTUq71Z41x1Wx/ZmWyPXB0ByZCWMsS FLDiH9L+G2bw8GVtXZBItuxZ1PVwZ9t+u/AvsPKr56m55mL0p83VH2Y/YpPiXiqpIIGAMbWfgrme tEnnpwRbr9Vae9nLlsYCYBtqTa3PNLcFNbeGaxkGuJK67kQnxLB442nKRdLnZPVgbz1o4DGkXNAO EQCHjMtDziITvJIrZfdftXyby//pn8xW8UfG3WJEHji1pTgiDKmPwBgsIJDpvWIG0erI4aCgB/Zv d85zMUW7WSQhNKCXIIJEbJpynF0sU2JO2rd+qT2qyfvBeR+i2ZsU79Oyp5HuTF8UhSvRaAaScIUS +Ja4zLC+9o8mrwvUAIeNauxnqw49Svnf728Hh5xil1rFMiMUZaQEQ7fTlpNmK/yfap2pepR9g1jj R0oyUseI7stjeRpIzyA2vHNNwfJOWQZeHC40gFbVItNAgSiVeOItISCZ/yhAHH6wcVizRwhrXb1K TbuBVelJg2b/nXbtDob8n5gettcK/YCzhTkQQSoue4GLc88pncDvnPN2wIrASj14pRUMr4nP88UG I4Cqs8huBQQZdtFoekOSHNBxZFrVXRwY4IupeLYZ/pLxbTGMwXkzbXlz938MCaTEXKnfh6p/mRN9 BBiWu5MxvUX8BNByEShICpvho2o/MhTezVC9WljOq/z3cNLdq3zf5COBqwI/FFFCJCEQcozLCkJl fbrGtWET+uSscUGp5SvEHl7hAW/ay8nW8DP3FGqS8MLN6b4124x+FZWfA0a3JMuxyMjaY3d0T9C5 N69B0dFI/0i72BRxwI0LAzA39+BcDC+ce+QGkzVRQsxWw94qXQLgTbMpEgCLv3kr/OJ5A0CleZHo TO7OvtqJjGOKT+1aMb5uwAFQm3AVbGVziDIUSJlfa1uFNypglF9L/0gulq5dKlhMmUdhNpOwo4XQ uM/JCHGNyQKeNS0gY5SAk/3f9I50RIfbHn60yfqjNfwrEU5h5Hl1R5qOQSrmODccUeon6vl8eDGn qDrou/BvJvWrjI5gBipQrxLRw4zenW0VI8dEhdl3oLxDHujg51AnKIC15eUuemujBnwFsvt2cyBw 2qOesIZV+Om0sGuF8Keqfp2yypZytcTPnJ8UF9qHvdZII8YnvUaN7XICYlFJM9tu80kN3cizt8Gd E8aCQwEYz6sxb9BLq3CQqOefDD43poGRhl9mNPYKb/OSjbt+kJYpBQ6npb3lqWzuiRdfsgphgPn1 H2Se7w7BiawgaK3N2x/yuTz3WDBty2gXeRi2ZF6TdCJKJagMi/WelL589UXdCdholmd3G3uSb4mH TvhoZuxXz13MjDsRxev9VP19G7CU4x8aowYEyS31JHurIb5bCWmzjNlK0P3eLGQnfH9ERoR4tgJu URmeybfDodRXJdr9z9sX5VbJ9b1goX9+o1vALNzoCt9NJ0qHx2QeAP2hgdQ1g+NGX/m6C8d7fdy0 Ej48PYEMrxCYS8RAg1NUVZLt8ercZ+Hux8scDS227MFLwDejtp/7bhGYeJDj6QQ66fXTrjs31z4T TWK1LwRv3/ExtKTj3wjQrkKXdn8CG8xLOI+P0W5yZgIUjBcTQFf+bLwR1DkQ77sucodQ7gK4/fU4 L416/jBEaVP6LkN333aJP9kBJ1gtke4XSb/fJ5lI+1hvngw4LFVy3AyjyxllAyYseJctY5EHnLt9 ihhyTglUgvcwWbLv/CwEHkuJKERAuKCTPZVrURpmFUNB/s/s82vnAKvvlYjsgkGN2uxa/BmWS4iQ 0xcjzm9jmj4HME9Cd7h89J94zboDgkrt5paBlBZhbrj3IWxPpMbvELrOsP22t0CBN4JBmE9kWX3i eEZwvvAvH3pTLBUKMAfFtjr5X3tEqAGFp9SG275DZdIlmCRH5+i8Rp+8AA+HaIGC1YoX2z79BRQk q7tKhRY+4LTGmzCcZMH96EuidCCLHxvWT/DmyM5rUAnLO6ARnHTc0u6P1p7mD+GAwOpghrxEWad9 L74N60wdVin1WH3CAnt+B6kNIeLYHA6x2iDGgLLoKMaCYVlJljtqCSRin50NYGPqvLpD2g9RrmME qm2YT2MhF58miJC4T1nhqnUFZXL+RQgTSkpngNg8YWa2qgTqd/S3hJhsX+D74f8yEX14+u0qarRV CAu83oTo1hyXuHu6lXD3pqHTwDEvegb/SpDGPNPBoQpK6wH8eHbgY70cSX99+9Gs2ZEIsDgzJ27y nmCttGd4caCGwQ5BEC9wvdLDwD9KwPW2S+mTQrOEKeFVwChcx98oKu+y63RKROoyyrPpCd0t7TqS LDksJCIKa0c/H7MxPdUqH9Yl9kI71RifaggDIyS9WEuESYsQDGZ+m+XAeJsFBmXmtrHvgBLSzbUL mkH7fq96viRxeEd/fYHvEHJ7uStRkHqMf75Vt0HwI/eZj1dR7oZrNi2a8FA+P90D65OX1GxAM7iR TbY8Z7LM9bnkODgxgl6TLrtIHuJ/a3kdycUrBpEoalP4RSVKlHhIhAqUYyMEByVQ3AbUUEZyDFC3 Cdn1Avnq+0va+yI1eDf1xgj3jb4wkUanT+WIqtBu+EAZSnEIU0WbOKtdnGtPIGb/eElA41ZbdzI4 sL7+ECzk/HA+MUcAixbr3yHKHm1px2Gmxey1m+OepkVkYCoXu0ZGiC8bW5LnwmBu8PowPVy7Rd8r 1PC9+03aNcsGL5zPCAVM+UjkEsayKJAuVh6bY2WIoTv8AQPeonxyWLSTF5S6vaTqgX1iqCrPpjP+ CESO2l4dfQv+aUx38tj2kF+UMufbJwpSX5f9Ii8JKosyWBEnBv1zFW7LratJjV5CpO8rsUWDOeiq 2FVhAQcPsWzMKIl8CFe/IqfidRKgeAieoilleFe4Q3/YKDzKPsmtHnlYbwwBOHvS0WbCZcQWY9ag bJ/CBmGGIqTPP7PPH5ltGeXzA7bQfQgCSTAVuDVjfOw2dRJkgfAqEdWkSqLmxrowBlDiEbvbJ16c VcUhk5f9PXwU+IyysPpaLMh0UBYpvitot3iLQ6HYUTxDbjQZofMNaZ1oinkA/IZodzZFVW6pr1jM Xe1NfFHg5jcczpmUU8ug7AiD2tx6SUVQ8uhqcQDp51OcwKINi8GGQ6hho9vESwalPszT4M+JPhX6 xUN6pS4aSMx0l9a5Xr1ky0Kdj6iTrw2BgiY7+54TROH7jJYwgEziHU6RBZ8K2+4vIeFrgxxzKiFY TiwssFpy9rbcWJG4o36PFHtRgfK2bRkWRBoht5uQN8g3DA0IXHxHftpJsGh1DriXGTaRb/uyou9R XINcD5E64+9LFWBJ9S4fqEHBwXe/Fv6n7u6SbJwknxgvdrvm87GCFfd7Ycs4IH3JpKtL3lkifV3x +Z+yy7ZMCNFC2AC4TRVFHn9RGx4ovOLPUL0r2wN0QVuamuqBpSLDHPJaDc10zLCfb2XjMPNKUivr HmxOlY7rIn5gbX91zM4hwAIJd0STbXr130fUr5/gTsm8CECgtrxARniTvnbyJvJD0xHyfQGUUvH6 uu4MF4onHu0dEP6NnaqOdS+ubbihYrfpqK99aCN/VDL15Fh7iyVyeMsafCtvpIvfBGw3K8HuAfns e70T0iSfAINy1+/Flp9CJTxgnJyxnkXmB9ORK3Yshc8YQzEwg+9ANqZA5XeXH+55qehOvGDXoq/T l+djUwmTaUKPo2ov8GnPID1eDC9tA7iFrspD7s444Ynb9K2TEeiO/oGjRMkXhAbWsk0TK1BdcapF xo3vooGZpSAzON5rWQfH4tJIsGdBtNosv+8XPtpDH6uGeTaMxPuVmOz+ryT2djVvBvHn4deBKP6h MXyIaUhr7GrzDPAJHPpx4Ae2Pbp9/ljCz/j7bpaGGGg0wQYKP1yP3AYl8zNk97wbxmkiubUhdywK yozcprb6g1u28GL1AT3a8hoaJeKzNnCzz4H0Gn0HhGaDNOoaNsc8b3xIT5P7eXU8XVSrgsQzAjdg kH09cMGpF5oMtxOb0FZAmq2wxGH72hbEzqbPW3qB61itsCgGk5AIYVONahCXwoStojstFuII5VNR jGSNCoIZOAvVSSx88nfvZ4zhs3RUf1qpJIM/EINzOMmLPpotogyQ77buu/LBTocejYJqWly7eOO0 UhyWQLcfSyuUnvcKW20YELhLbmD2zg6FH9BGdffQ53CecbqvaMvhSAxurYRxQSCNhfcGIxfcz//A fm87agzFcB/ZhhaBN16fuVZOYiZ+YfkvGahFq05aENw6KHMIjfpUnu8bfvS6JmbGILGs5QncE7Gc NrKZ+/Il6glnXO9OLzhVYxD7+wWIc9S/j1nWHgNYrOSWUuxaDzBGl/374+AqCjBD9O+QsaVIRQp9 wkGGtJc+xDQS9Jfo+9dKWsJlkN9SWGpw4cqNO6zRmV35psGLzeEvqW0m2EdFmGQk1o/kfy2UbJ9l JaKMmzg74lvlMBi+U8su5H1cV4vRXiXeQjRtPEm40fw9Aounfrq2SoxaE2o4fplYxJblTfgLYyh1 nbobwTOLoTPSmjsaEGtJ5117TY0OdoCDUA9pmdQ/O1VQkCdCAhhi8YqYQsd1qzfpf+AjAx3hJi5p QFK0ePVEzkxtjz4r4jKBEBIU1jq/XUKe8gaKbc2lfz+KlugboX0TdddErrpKgA4GsXHZ8yDb+inN uOSspvc4i3D5o5z6Bx3bSaA0OjMglxLVHxLlvSCtG87cE8tY8bgwpTlDbVLtCDn0l1CgNi7VOYnV ug5LGWrN2qKQ67jBxu35JAMVCIc6C3qS52cW1UOUhFvy0AxKKju7f5n4mTHT8TaYxPJldlUWEXZw xIhWc0fGo5ghtxamA6ItecK6St7EJ75J+qqAmaSgJypbgH3xm6LsOFSjsWA8sN7/XplrWRlgcCXp 3Uu3689/O/dxEYAdb/sxwsy6VWIAp/pfnsK4V/AGkdfoft0XW3VmzMCjEueO/7cZjrzvRDmLRUzh JyhGxqZvadZmbJYXSKpnUSwIutP6PSp14qbxIQ0UB/KlOoQsJJStZHZPbvqTR9k6oi47Xfxh7kIQ X/tUu3J4c2h+CRymdSTQWqeXWB8ruHkH7jQOMcNcQU1GyPHxKR+oywF757/7s0949ZtXVsfDji1l lJxqPUMW2JUsma/ABF3GPmJA2wNJFs3tWK6d6hOcKDdQgpvYWkbKE+wINJeN1tcerT8ft3qVGdot zs+z2vbm0wnMEDoNKBCQKqy/16hsAprTdpRDCkigxg9gLuOMSKeEcyvY89QVCmVVgXHedxsbiu0B TqITtSeu05lxlWXdpGgr1P4jskOiboqAmEazXrz09OPgIepRhEIlZM5DbtEP58LaQaRWUdf4exXM +ypCKMWeqHjAckKwKuF5sbEoHfK06C6hR8kOxMvLRGjg703vUaCOEGVndqYk1FtTbU1M7cSjjoed kK+AjVk097lElZasT0UeUg8tfA81Mq+K96yeIQc0AwKhI6rwu7upqRKnBEnW7rdVszpr0U60SKVH 0btUgqOv54ISoY0mIuQw+c7z4j7Ce37dvuGNyuf5vctcr14+zdeyvgi/03uj9Kq7svaMDj52wiIf nU56I+cDfr35xjWu7GbTcI4OdQsE02H3vFxhaDSd5Cy3+tWrjQmFQc3HHP8hsjD5qutiJVWD6zak Wvf17dLQ/lX6Ts/9EdXfF8L4y+cfvsH4wWGTrC/JU0PKIG1vK8CmjETcGXNbWsbSz9e3w53R0EvS HU5YKuF60cLIPZRIQm873nzmRGJcF94scLGU9c14vTkelFID5XtgQuZPHlzw1HVhA2EDG0YM2wce KSny8mDBesCfRkGnEuL26VmbmZAG0iayKHgIcynRXwMwfZ1iAkkpol+uROqlEeEdcVnR1DUu2g4d H9vBqvOomcaIR+opcVrxajY5YbkRWYcFMsEuW9ujP1y4hPYXqSDEHG3lg4lYjhVeYnKOaP8Tsdwx VIX+69t9FRX5H+qW0njBz/2kdExS4zElfJvo1kEoV0wU5CZOXmeAlWjHVX1DlbxRgLaFL36W0xAO nz6D/EmXt/T2zwJyaOdly25SlXPSxSSePzrofx/cKTq59kCQcx3pjmcOtj+at8u0lGNsr01bIGWY ygkXN32+8O6vGNdTbJT7QZgJTsMGwq0AGUt3Vx/hH2p93oNRZruDE57ytHEMitSVP9rnnjxAParL uQikAgBOK/tSr8wQ9yOVDDwqYX6PtFXiPQO5yBUuGAmQX2hm257/H+YVk5pwYQB1ru8PLFEmIEfS G9Ow1exQmfhB2i6fkLUpARSdNxVMC1N9tM4Nws1KDyTqt5WgfnZkawYnZ9B52+49W8hEb1S6+EiO xEaIepxlJL0iHhKUTiQWbCTTxCIZoRGppSXQOCFFaCbvs/b8YyLtc++vlppPWDP+xkA/qVT7zoJb Lu0HJYzM/I9ifFnFP7iV//7HKBUP5hCTgxChepaiRO33K74+cSP0XUesw7+dADbBFZXRLJdCGTOI Nnn6ECiGjOD1M9tcQFqAp1fwppeLmllstrrH8YYljIW8EK1DC2W0IaLblzyVYWfROcarhZv8z1km OUI2yq4SAznNLmD2KqBHft/JrLuPOYTZoFGte0eVJBZu4NQlCdgu5F65jMUoWddE/5lmXm6TP/Wj VlAiLQrxn+I2CN2i2UlMDusJZyYxrGKsZeKuAD4dkFv4dzL3QqsOHV5xN4HWqlF24T1NwTQn0J6r IXSgn/VIRyCUr49aDTmUzdyWC4nhcqglnEMxe/XJwT7Me/Kw2yH08ZeXyXJwuO8CbTcudXOmpOMv WJv+wovr3Js++vvMAjI9enL9CgVbJpiJAZcbaCGsao4mvgOSdLFs3k5O4vKs57ED21kl2SY57gdd Lr1KoZZ9ZVkiVQnitijEF18rQ+tilJm3SvKbadK5gJpvZujJ6NNMDBkmRx9E7YF20GN4Da1JAaBb GmkkNc1mREJ7wxMAA0zT4tRy8AfDnRg3S6EBtzPFKbTBrYhwk1HOpFGYATsuKMQCbpDYXlfYLlTW NMYIytdlGwTMFJ9RTJsRGHsPxKGaFwUokOuaHpDYxeX9P/K3F8TzTVYxF4harjNdZOpRpQbdy/6X tTJJynAdJVRDasC4saF4RQuo9rqgC9trJWhlkg/IagX6SFuyQ8kosjKkhcR2Ag3EmDLpjx7RR0TF 86tsBbGLMne2kYm5+Q1GosAWZVLP5LBKF6TaHoRKMGFuPCKXetu8o5ys7XpIEKEY0EkWWrEMiTmy Pdi+LhELvC4fncWVSZ8GQ5NopHhNJaaGTNc24qfJGGs3LK71hxiVJlcuEsVYQsPila9tmlHvawCP KvCHeuvISqzc58VvVVp1XZ/T/vADaCcOUsVrgfc5H5H/75Y2nER2FPywrdyV51P0DUSax6S5UFD8 zBhLsnQPpJeRY2gj6Ot7KoVCntIPrSA0as3GuDel59bt+ylKXyW9m5zRpJmsBJzNY17yBBDAlFRK 7VAa/NQlaoQ9VAWm8w6hyFzjKSErrXLKb60IbIaeEw6aQawmlEhqXe0BqXC1zPQ+XKOlQvb/NfM7 2j9kOXJQmbr8qBkJUoRXtPOtdQm41yugyDYq1VXusKVDU7IvcFiaXkQT7J69A7X10F+/EHJ64uKy ehKg6sRKpi1XOjgyhxgEIzzxmZ3N8kXO4r7/MAQkSZtSVnfY/ASoA6xjORtf+5K4g2QzloZ9nk9G XB0can+0kO95q8e4Ih2+lvcZ9ti07+rPK6ZFwV5mA1sl5gDFHIUfHcisa1u+P3CDmilY61bV5NaL pEQiRMoUuuL9GlWD4r8dBNIqe5EcfBnb/RV4c4nzueljXNq4jAL4yqy6acEtzCYB+Q2FowLCJt2c F9YOnB8xodaMQo2ELoSDkwAUNPLoPXk68SiiOn3xrZLmO8f+X2CJbD5RPhgtWCPu31bgBr/Zbf7m uFJRRu/XxfU85ZWHDGiC31R+aG9gIwcI+obQV8mJgfrrDbFphkYWDRtxt+0MHTgPCK0Ki30ap+Xd U6Df6WN3Y567WHX0iz9bx/4KYcuHietb5fC6nxmlCNopLoceHWETdImdSx/W1H1ze9NjVC+REzTj s3ZSwXXKNnAIwnJS/n/HetjfpSz/JbstWBg7M2GYqvD+Gy3XQXa43GyDka98IUTIdG7u8VG1Ii+J Q6RH5sfkbAb+s7AlYW31rmpEyThQ0F0kFF3kydANer1Jla3ACOTHC4XSUHzBzBA9/8R3b7TogUsA Y+nM9e+iRMELQltn1ENoB4YBN/mpib8XR4JOqYj4KJDccN3C9R6JQL90s/j1uYKpNci1XUfeKRnK /kCivLmFsoGY0ZjU2zp/4J0H7QV+/eSnfMXKwrwcph1JiPelI9rf1I6Bia6fjLrak7HiJ3AS6zaR bpGtU8vv5iugMix7IuNNxVY/SgnLS8O9u78E/zjZNloSbMXGh4vSjp/zC+HiYVuMNby6JM+CWvH0 hv3KsmjNz2d45c3JS6r8/6hv9mYHjESKFoEkVJvo33jsEOLtHJdSfx723dJaLRJoqN9PSgDxQTx7 91zUQdVO/EQRmqUQuDhFbpSevHjAm74pHf5js5CMp7jK5ljV0kXEGpAhFQapD79/VrEKpxUHa/X+ mbrrGl33qWgV8pqGsZiiN3V9oS+r7HipLHGs1Fts2AUERiRfLgoBJziJ2ZL3bQa5HmD9Y8u2doKA V4s3SmHI8dK5jo0kw0fu335cwYaYZpEb4nBViabh2YcdetPEmKmfcOR7q58wKRfozitaRoVzGWQB kMa1G0OWjOkHTM0v5xwFjQQQMvow8X/q9P5p3BuFrU2M5rArgJiVE92vvZLiMaJackPyMj4Qk1NW v3cBs7LnNNadWMenpew29Gr4llT3PR1Ih9/TPDbf5JpNWAy6owuabr7hIYNgp3Y1s4Hl2nVbtQOh JePrCU3jDNqgtibElXqjz8YJSbQtcByy3kQtfTJ+m6SYtESL+GLuNtwAAqvnkvqZ2Kn7PIV17m8j 5MzAQc9F+4O48bM0Aa98IGckYfmBTwKs+OuXJnxGnoQ8pflMNdkgGxx20QQGvz35tqY6wcXP0wyq opcxdxR211eQMKubM0GxLI3cb6Hcamz56ps8uOEFsD9ihxBV/TZ6AEeoJGrpo0kwztFPuDJpwTRB gt2ZTU5eVLnU/ouZjzTlHeDxdB9zwwoy+OqhMA7UKS2zNMfcO5vFvBQ4rMQqLOgoRg/2MWVPppSf Y5bGjVeqeivTYTUNMTEPiRYhUMRMFPZ1K8OufQDQCO4r5JTaseI+nNAdcMdcQSKE8Y0YgMWiEQRS sQaMsbix4SN+SI9+o1C2xA5iBvbCRCnfb5u2WC6odcLjBxlgoJSdckAXt4HKLK4BlXoFxFK5IPFm PplTDsBI/RXKNy/M5c0nsgnuGhzbaFjnmTPfw0o+XtVXKReavrHxYORGqkbLGTfraz4Tcpleo27t DemW2KTltdWgSw07HUp4f77vJl7Z8CH62ofi22PnJjcop5uqlg1c2KrS5N0tRMOSnvC4hs3mvqw3 ArFUFpDjUcuU6jWGJSOmhUjLsrLMNHNFyOy5L9cv2sFOm4T6XegapH1ACU6LFxZQlaGcYUxKzH1D cGP84+7k/vkAY0wBocn4D2MeaQ4H2yySL8JETaI6YIvlepr4bVrasCIosNF2rXM4UQnRlWV863gK p48LcMEcB+trZrG3XcwmFnIOBOpLqmSmOYCuNU2UZXeEZFLPw/MZsT1KurMsAX5imuTEUOqsnkBZ ZcN4w0xw5dP76/Vd10A3e4j7F2K4/WqDGIcV3LDy4eKkpDCJJAjwmf/7pnHgcP4WM9Nq/wCpWlvK RmFHPFwVlxfZwuXM2uKqPTHNUuOZw7sCgxiPjoCOjjYuok2Siar7kNodl/dUGK9Vp1lNVUwaRDKC hSGtPkZnmkgdlbhBUKlNPn6dLFY7tbTIhS9mnKwosFJAVLRJ4ZgRDvjDBWQI+/GBRbYjf5VBFxVM 3IBUVXj5nUv3rDQokE1/sTbn68Nsyy08x55P7SPpB3YoNN9TE13xLpuZLZnlufhkNIsqnhqjLlCL L1B2JlQXsLHC8zS2kp73beYYZ4735eZIH62EhgjGBKgSP2Rf9AfjZpksXxl/LLTrg9E4tQMl05df u1/uaa69rFzPBjQCCb0Jz38ly1s0ifQe411MV7o+RnR/1BbLVAW5Q2ou3tCaHZSRo4dqBglX81D6 yERI4B6qeidVFqsYF0D2Dkm/RXv/sYHjz+Eb5I4nIJIl5pCTyMB5FTDILDCIamZBJg7CACNScbB3 OokYsN81T2Difs/IJyeyLLi34c3hiHaVW049HS4NdTd185BaFHAzxR6L4fGstVMWgo0RnKMOFKOB PuJU+X9yI71nXe8MK6q/BxYNlxL/4LTJwh0D/u9edm+O2Bh3c3fUaRSJDQHdx5zbyuMSx6u1bC5Z oOQppmdGf6oKHN62rj4RSi4IFSAvg4Z34xJoM5ilPLzhdLnTXMn7G4K1vtigPbJ1rllndtGq9cn8 Z+g38fuC7dkZJ5nMnZG01YLBjXcsxSkLh3sncKgeJialJlyEc51yXQIBDkKjyylsNtdGpj2u4Vsn yzx/+IEeRfYUxfM+XtFKHcpNFUfUd2vMCibUH/+v8D8L4Wrj0deEcByYBf540ROLTfx8RT3p0efN apgEyWjkumyXvsOoYqUl1qyb57hMlis+3OXMbk2jpSusk+7hZR43tV0le+KXUQYUsnut2H+kYXFx Kt/cRik1U9hMm46nx4yMFP9RdAs4COlSB8QkdYzZ9JzmMp4bQKMMZri2QX9eGpZpqlbDiCqc7w/q iOrulPsy+ZHfHR6oB/O/HlxU9hbdgJhqsjNa4QIGppv7M2bKwuaqvk1z+sadsv4/KgMCqrVZ8w/w 3ql6DFLO4IV7R8IwEU06g52yc8CC3gfBS3QwQGGHujdqpsLR8uqZRnQNZ62DPEsvOsXKzkIISwT0 Ml4xaDg1cliP4IU8uBvpyicmTx+NVggiKSrCemiFTHZzYBZLcf5xZPd9l7HVApXJSz63l765QVym fLmrSqDyhtUNtFIvqCeRJpplugX9S9HdNx3872mNFj3n1uRT+F2nrsu6YszVq9D5FEHysJf34dnu r8HAkZj6Tv3uZxO/fzpOVBuPfOlOlNjTRc2uWXY2IbQts8kg/TZN9b8evti3IWl+lujXiwWYA/ne 9QyMfP/2sdoVmE+t5bSj65CqzsRBtFiUa5rpXcXIVA+6VQNrEQM+TuXCMIHYQqRIeWh0zQIko9FZ PUJGVxSmOmNqLL8J5WyRSBJy57uz8WW+KNVAMhhJpOCebnyAUZWJrmM4UgmqGvO0qH4JZciNv0FR bt/GkZ0k9C5oFJOaKB88OQkEBCZpgy4hPRKeF7v5rNSUPCVzTMcPEZYgXuTBIXEoFDRVsCpdMCl6 sLco2+rYPIS5NXSsg0Uassj/E7PAjHZrO7zPlyfLdPHScXJOFZJXfAo5oOQGAHFFc572hM4x86XI uJXwQS98ZarKyotOPm1CDs6Be/knfka4xi1G6/b1m/OsYRSunJ6O7tHOW80uHHRT3ninoM+bmxDK LnLw8CuMO9swYyzjOK/YwWc9KmTOTrSxI2VOsZskZI23arjJypD1I94akk8TOPktvBD+NQMooYF0 4Qa74tU7HeieYUWD0XQhuTrHZu/pmgwFNfTJE+1kK8pqqaLEo0cz5MBtaBdAecRfvsw3tDYVb2C/ l7/6gwKf8Wxy2eks5brtxRYBOoclFV78pu0iXAgEK82MRS/i4FcauV8lDb/+m40K8kYuhPvgteZI iuzMpQGtQEuKo8a+Ng6ib/6a6h2zQVpXh0KylYJEp3BCvfNHZE4eqxK03/m2aHq9Ia+ZwRo7TUxw iaCs0xz4KOxjbCiwuBTkt+jyiyb3jwT4WU+zjFjWLgyxMETc7iwoMIufu93tT3/RY6ov4I08UQuy pbVXwJxmEXvTz03aAoo2eKm8i4m8y2/ttKrQXGlR/jQVx1p2+yCvLlaq3/fmzGkiXDVPWkWC3WLC Ithzw2JyN2Epm2gkSzuiNKoIfzu8EbcyphpqR/rK5F1G7eNDqTRaii+D3vtzkp4G7sQTksmMUXW2 erKKwEGlX7M4ZPuMiY857qE7yAovfhh3cThfGY8QboZOI/PX4CpPlaPIw23FkyZSazK7ZSaGTHXw IdMxZgx/K/vrcVYO1aV3/AjdLEO1k05ez7YS7mDxTo4+exWkqId3fhAMBoUqj24Qr7o+c33BYNVC fxOjEslflidrzymy4XpQxOTVSqPumQ3kOLeYa/7sBEGnQ6PFZtRTeG7pFVMA9SEWVbIqipeFhG4F zBZOWO7nlGPfml3gl81kKwYA8DViXVeAVPIfjFdpn6kCDHcisXdEmikk9Fhe0pHckBPJ/x+4UKfL /J2cJ2NiB+VGexgKUMsF5QdrLR2v6jsYD28ncG+fsNWLL+Hi4Qxd4FB0QMgS5qixYv3Yi7bZngFu UAOffxJ0uJxpB3YCs6ffhSOOFB7xFP9duJhP70WXeb0YAEgptFZIL9nbTX9rZGk+kott7wyeM6J9 x/wwhk0Vqqv527ytlnoFMFhwOvTs/zXt/MC2z/RR1TPCMscWxws7SC+IfsOMAj7gMOC0lf7aQvea n59APecQT7I9Uur0MumS86cyY8tgpddD7q7mNqWwtpEKH9wwj0YvA1RaAJmxV3o5JdK+3MeX6+Zz Lfw4bb/ijdCGk763T/d67gOfYzr7TXRursjWexlZMLfdlFO+kkiVKT3149apRlzB+k5TP7TuCVqS is7zwNCrf2DR3hbK0aRm3PiDpeJi9rUJe0K2+sKLpmMoXR342IEIjEWFdoAx51KMoVDACIx/A+Q3 BpvFoP6vbTmr8pcQZsuGtSf18xlrJxrY6o/PNDacvF25Zx63xgO9jrHdstzjcUS//QVgQDKhLdIS 3nUqUzPzzpQrFTsrV8mZhBcWQ68Hdh7ylkktL2jewPcfqvGO4XOugN99jVYQcxQP6mQTfXfRzyk/ jsQ3jfcIW1eoFa5RqImIH32hEt40OHx2fqJNbi2jFNGg5bZUN5VDSbTH3TiB8D3O15QyJwQxOTvb RkNZ97p/dXbUtUwz3uF/m7LFB8U07UTyID88vCTAEYRMgfa6Ku8HwFwxp1NdCDwCk12OnhdEzVHZ 6vxPC1z3EnHUqIpuaXBStYzbv1JhlbD2Yv5Q5M/k50z2hvoETGntus865UdSgIgWlQJawwXo8Q6s 1mXZ47hcwI2c4UPEZc7UXwLkYYXP5McjaB2CbkwYUB0oJmbIbJm7oK8DK2I+AYVtPlamKOOJY95K KK4mICjhn31zzq3F5VSlVKw8xNxuLcdkxYM6Zzmd1g1ArKzyrE6apkbcv9sRVymnpgQBCx8MbI4p t1aqO3n5mVuYJBeff2MtTMxxQkUEqCrBzVn9nZKE0eGIRa37ywnFe8BLsk0/5zjetONNqPMeFtvp MOk639jcvhcKIcW1APlYLCuD7O+srGfzunYIydk3Mtpy27O1heq1zH8OjCMcIHQkNdCWBjsKYIxa UvR2ugPwpPVMNtFM6Kw421+t5UAUgqWSTEswRv7P9/IdmfTSif/zS9cpgzDoHwQU4aIu5qf47JSm hbOY3OPsqC+hZUO26SzLjiP2W/zPjvh05PWvxKHPBQ3/jQu6I5PF0T1eEUjGxubizSXJnJdFOsYJ i+tc1J5LXP1/9Lm4ce09Cxt0HLmFNGxxSHFf61stSTkSpKJfiIalt18UT972tCV9fHee6lHjsZ5y sv7d0HLITijK7yK0d7BMPN4gU6kG1KgTQef3iL7cqrJRpe8p9/87GSODLEfO7+3CB4l1ZfaBkTos jqTOrTv9TGlgNCWUo3bAlYsTZ1dXgyJt0Yz7WyU+ojGVuNKcghz9ZlNGpwSXnylIGLWP/BfSK4J8 G0tAIZKj0yx+VCb3K4It2JRVj+Iq0KiTfdRHZdwD0BpvzrI/Z/Wqp2/XcBJDRyxTKfMJrJizP4Eg Zm4unsJzEJB4ZG6nQ+0COnX1UC2724+oidEJAfu8pW2HIAORhuPPq/cVAoEKNrfud5RY6/MlbmnW 3qGRl21TR1VonjprLofvkfalLwjo/V3czQs89Iuw/F9azIVD5nO49oP5vTqPYP/GHjiTDaoEpSj/ 3Bh0ysHWWaJiHtKelxzqrqRLmyNbcSaod4DEr/SJhbR4Zg8yDVWqIb4Aa3L792nmNQDT/0Rk4/L/ Ehdo5Y+4DYLYU6jwQnbNurdDJx8lqB+udighdS2QzUCLWgkCAseUIkJGZjQc9LGOByS2mwLWDMjl 3+vdnl2XEw2/taTAKV6D25ad7gMhhlRMNKOoPzYQSKwLHd77BjOM8QjQbgN3J0v8LJ2U/CvRBrq1 WrqZSs6ndMZI3kwqP5k0rcVU6aZLaFC7ah930Nh0u2UcJR0c4WvJ7o6DCmcXrTCH9UM6Tl9OmknQ iPjtNEIpj/+KVt3BsgXZUkL8UxGl9+VpsTCXmx1hTU3WQgmtJvRD78LGY/xpISCkWYeRu/6OUMcX MubhitIKKcAHP/SDwrS1gAU2b4GB8W0ioC+kih0nkMBkivvxBhO3sQN6DO0iTiqQfD+7HHct83Ve awb8lHfRVHxtTfGArhH+OGEwhRfkRsgmJjYl/iT+aPi4ijnbwSlAUTcN8Eqnz962kpAVtABHaM4F 671MytD1LeVMIJrAmPhr0EnvYuELRvw7NxqEoybw0Jsg4/4DwM0lNwiUynmt+nm0IPmXC/pYn/RS aqjeXS1/Zteasv2jmK4JrDg1d569mWYeIGfDYCdBKqPQ6ir3sVtbfqpT8awNRTDkmssAXyYb03ru 95GpFIXbBALAklQ2HB2imyCnDC58fow39zRfaxYcEudHZ4mNZKUua64nQgSPseMGXP8oCAPYLqHi 6R9YMNUXadI4WhhZFTcXHZGEfLdHOHqOgP9E87DjufvXlhw1TNECHRFHGD8VvQ6culvhTVkBi7Hk +82+49Qyq2zYVJyWpSIqX2BN9CIXHQDpf01ag9Zs0zVMlUfBI9wi+ruMNKFcms/otgIA2xJ7+oUK qXyQFA2qZer+8KNk/DAFXrskGMdQ7nCgvGbhxR5XV3K2u5LlHctwk0j2nOyvd8Y0JhBMOJYWlgzc EQWf37iWxOJG1hcQ/aVV6mA6cG8U92dELJuQQWtsVnRgHMLcfwL0VdHHu3BGO5gj+/OQSb6dLF2s p/uyzoj2OirbjhAtaAUi6ZsU7ShB1FeTYtvjqkF7btVy9EPTVvRnlfWHUsd8ZAyCrCV60r/P9BC4 d6m1FfrlZynQmgjxpIZJdQF2gUeAiz3IbYO+5rsdVwa5TBVDO24n0mvUj5hFqWaGEUBpS27dGrmb ChgZbVvSqfA6FzucTuWgDLRswLhWYdHJlLnmI1irMEvI+sPJ9zLA+s2W1KfdNdYU31Fyf+LcEBe7 QOhGaOniRIdkujWpBa9X0YnsIjlQ+Tzn2JEjldZy21IBAL0n+BPObxlBGNWrtsqmbA1FJHfASMur uxmTIwFg1VHVtGitFhrHxMsKgKVVeV5oFDm7/GLL2oPKGwMUA40tf/U/KazaswJVk29Lwmv/4wbj H7WqT8Pml6WM3xVrNZYvTHeaIo3sXW64K9BdFtmE90kGzhGhONZgDaM/ChbpR6RZFkSbITaGHlxw YPlXDSMjwXJ6wTb9AGZ6hFVBwJJ3xRIsCXUHPMpL6MlwCT/geN0NGLMoZpH46ajDlMSKtcpuyVbW fyZyzKKQwMhny0VB8YUkAOKXrUzuW/1ZCejkAYMiide7XoVnweVQ9PQApqZMUD2sFz1RQ3Viy74d C8xJ8nw6EDAw78RA91mJ8yLgkd61Se83h90gvw3YV6OeyHFAdYUu+s1GPjNrjIlJI4uUlZLxIf5C 6iN6DVy/YcDlsYnFkULSitS6YMcFVXl6//tWku2BMF2m8DLIoNQN53QwYOi730OmexBNcAGNRZrD Y3bSOPJLMcmGyp8oABjjEimCtaeF+tosnA90dLBl4lEJ2buTYCuEdx1PBvOx/Z4ThKa/tuzd6Lio thXjp29Yvfpk3EG0P9MOQvNOExs7eS5nIgkPoyEsnnNbepazEuMCFKcNgcI/ffhR8CvTZKiSwXJk 5tjQ6i1stL3RKyDRK255vRGIr+TMvCiI8ZmlsBxte+UO/cf7uxSF1xJAYz8UWcFpp5qOYPHJk6Ri Hnz1IMjgyQ3UlyBTgzfGZHr3Y2xsRn9pmyWBDo5MjmZ+IKpr0WOR1w0nVxy/wJYeLySu0XPIqckf GxRUi/turFm17PcBOAE5AGrMXC/AJ1stTKEM5eqFt6vaEi4iGp1IYhioYnip9k6HepHImVplE5M2 4o5tclee76wXijQRmK7nprpFr6r4z38riprFtiMuzZwa6IRIYld66HhOxO2CPoMTC4pnsM2t41s1 T7Flt/qgRZuYGUHEBh7f6NiosoM/UJIgvX1rHFUKSjPviCZIFNSyORiCOwWFUVOwMr+Bhvh/BryI D6afwLTmp/Jtcki/a09EiGUSidyB9LHPgW23nnKQCNR9HqxKIt/XoREbOeyKhY+T2z4N64XyK28h dalyEiut+/wtBlfisr9mLHZHLMyOQaafy+XJ/eiXs83fjvkdLeFepqr2q0+ZYJAv8vuRJllLSJFr JMRL2KF17IpPNzEOs344EuerVb7MYB5D+HF3fHskG1goCsYWAlRz9W047d9m12vxuvQCkE9BI3hQ OJabaaQDu/cnR9eQB2KX4aB2/x1jpwpxmSGtPY/YlMJ4y477n9EqEhN4aUCaFV3tgj0YQP1o1Cb0 AfknrOlvI7yw5II48/7c3UrXnQzQN/zRxLI5qxA+vR2gUy+j4vIxQygaCtVXgu12MaO8NpCUu/6C 13PAT9gEx+ZDKU4u4lb4DPzxrkZXxvu85FE46UVTuVJXGbfMK87H7X+vQ4sSKbGd3IJ8DMr7oWLb PKNRVxXSwTCRvIZvsb3cbTXnJFxMMmx2Rxy8eQwHD4D3E22N4hrEtDQdsnGZ8utDoVZduNe3okyP JjVJqC/JO2kuGzrC7cF4FnV04jxAvvHwFoxlMY6QUEsmiTz8ZrWXMt8DclY4fBwxqkmmek3LgrcR vhzQyBS7Yj5k+Cd8NFjHrPIYb/c+0a9t14uO4fVVlTJpFo9+jag3Ez3FAZVHyHZInqaTpIUafUQI K7RevwtoIhQXZtFkoCG2zI2+cfskyn5Vc7I2DUnNqii+UXNnkFN/dOQGmtaky7TgJWSQhnt7fdlf d12RbAKJaZ9XaJpwhwxA9rifIp+TqoTSZ4391nnJz7aeOHniNxWY3saw1GLByfZPvE4n+X6pChki HQm4lFMHxIys28ZKFuveaObGC8lRkY+OrnXtbjkp0+Iifxoh+WZhlea9PBuZw4Yj6x5Z++fgo+hb mQQgh3rDM2ugP8T4i3uvgk9fc5OuUBK//avHvJm5Lr4FO+kUbvE/V8zmE2EgD2SzGmOhW/vb1WNx PRiyjDTWH/lO+YbKHSADL7SrGZsUpaTbr2QPLLrLLSV7ujCkEalx5FS0MZr7/Hh03FMh/hGGR2Jx LbAq5IwjMu0jEdtWDcZhqBFd939k3Zk6imEAq7k5T0yB/gKRvJg7+YGfyfjwb31wLgsrINu3Rgje HfqGnuPKg2YnEY2CUS1oEMJeu3r819qjsGXe8uo3FL4r5sBtAI9cBTx9NInoDxzlYcSKnWrk+dCh Tmo6Eun+46KknChVmwvmL98H0obqeDIaDxco+AMmoO2Te0oIvPUM5BUGP7h7ttSz3v8gegbAnMwB taS2tOuAIPasv4jT9zuxKWZ9cwkNOR9aeD1JX3iwI5UHNJhH6HtUIPp881Rozi52SGAhTS4gcODX 1Hk6NgWL/iHVI/sY0lP+7PjAZNl+2OS1s4jBVQZqIwWjKcBPoQkBDUJLdn+irWl43vaN1rR6b2LE r48Kw9o+tp2KARCK2bn4sL8hP6rURyGIsqrEDwHM/AQ1uCqglwhNEik8qfA6zEu8CxCN3qhxG4s9 iqJbiFEkPqSdrx1fjqi07ucXOH/EBejAkRFHaWW4uy0H4Z85b7+/lmQOm4jbjndSptqB2I8c2Wwc U490oui59Bz/2VQ4xAWBD67G6/+3DDWdqEZrrENr74GTCiX1udBiQoBIfaUGUhSG9FMljt/EOh+g 8/OcJMwYh1gu4HDXFMpKBu5BeuLyC2f3fsSbJAnP+jf8Q8ah7BMN5WHkxmcoOxqsTkOnPn1C89y6 vziQk2lv8YZA3QOqsLrtDQE11Tm2cJE9DW8h5YwGyOgtToSp4YA6sLSNC/+3mMGSUaIYbdL4AIiy hqcqwKirJtGL7q4ipTWYqIevWHDstKROwGVpsy0YkgYMvYiKrreMYuxMsi7iys3vJVSLrXScMRAF 2smqUWXD9MMukDRwYtCY+iWaXOjTs7EsebJ7p5JWVHKX+f+AsxW7oEdtKLi/H/DZxUK+fg2818/q BKp+jlCp+JhcUq8SxkrJmhhKtrNFwWPoJKw+3DWBhI/smS+gGBK9dIb6q0td8w5D8DScCTzxqQwb TnK0SGqfFTdxym6cT/Fh1H4bNWaBzH1pvpwyI5XqFgWO50A841u2MYq24Mrer7/Z2ZeWBOC+2bzf MneXbB5lvCah1zvAVjxoMGmsnxFPLusdqpnxgE3MUSpnD97L5Korfxv7pVWzCpZvlghCRA91QDcZ lBcuS/96+kM7HKEjxe+DokgHeihkg4u5yYOJ6mxun463mwIEIYNx9eVtDBdh17nGKwMv/tNqGxFp jP7q/3P0Au66ccP2HBpdOQFESXDD1u+hvjX1CM6gK8Zt3wj2My/3ygusCV6Ao7hiZ3/GuaIm72S2 oNKrJdPuU0HqJu8mlzoSjNylHN3Cw9ytEOkpnupH8LaHlhIkyjVZfIOSAFhEreNUAVu+b3rSsRmg q7GnGdbcSHBZ78j1V8Pm5Oa+NBUSuG/jyx7Qix7gDbCIFa1GI/BoSnxW8dqILWnxm2/Dq2MDnJmA Cu8FnDAMFw8DnQi5UmRyINpOuL1jC0SbGGDWCuRUBb9EvEwHrKmkRwueXZtFe5CJm4fPggjsmS1J WtEcaSB6UIR9AMhMHnL9o4AN6rEiEy0cGNe0nBNKzCf31aDpxSAW6NaJvcrGlXEMQcmHPOy2211t 4nX/7zO9+OFLm0fTIb1654FBX/5qzZh8Exj0ZV6jyYHZR/YTZlF5Z8kywUeHyXZbWJLXQdfMvMn9 xTf3bpFORAqR3Y0/aN9h+LtgQF7grF0419KtZmwQYb6t7Z2rOTgPqq4V9KHKDVAbNj9omdj6MbKe i2zuox8SjmiPzLPmoAWYx08HJgj6Ebt9vseVLMOxhnUdmf4K4Kj+fCIGinX7kWqruTSpVf9OCQ6K h85Hs06Bfj9KG7V7nRYD2cok3KzVzPbm/DX5/MiKONVW9KgVKRqsys56pUkFVfOWmeM3bjAizwES 9x8e7hTfSRzrFpVZ+4yYF4VxQfL0tcKwVsDYzFxmsXVoTSh/omsGMcztg9ZLRxHRCHpV7sBP4WUN RQcU2ZKIXhKO3RMwd8VPbDZKdBDrrd5pxmeu2jx/cm5RuAY9zBD5kj2ENrP2CdbRnNTMR65JHpUQ 91XLNjdpuN5aJQCDxI2/37fnqwF2v5giig8fFStce5lKdqrtx00TDMSSCJVtZCoiuE/F6QS4Dqxl 9KLEABNSxoioB+hTMEJ4h78XrNyQPoYYEMBzIE6Hql1vS5H/wyt6Q2C6gJY5WOsbQeVkF5b7sb/o ov721LVDnDmEXweLF29OICAGqFvdDlJxreT6cyEIKgtQjytB8jFiA30ajdTAe74fS9Nj/KvGYMR3 OkiYMCNsqGZnaYTd/X+/RIAdV49tdlQ73JEK7mLgzQ2fBoLM6gGjGchEz+vcDE+Br3ij0iisnXDt gL+YgsjoBi5CACYOko5YSy1qcuv6K9Tx8uDThM+9IWvrGws7fbW+xdu44gm/rG1/HlbfYCDePkED x5IVRbHS5jIexu7DWGubGS0dS1WVB4Z3Bo4gJGcPdjSsmLdCZbXAYq4FOHxfZ3vjnxE+6sZxVVlB Db7DM+YCwR5P2cLPoRicGy72GukSqRU5nCziaFVl7+FvYK+Fa/9E6S3g9zPF/nn2SU/HO5Q89FQy T2fArCh8T64HAMC+NFm7tChc5YvLPYruaFHwDVarOqds5dSlY/0z2kBhXHCvqwCsScWofRBf/hMg ntFvZJOTLLPZsZvr/guSvUN4ijnQsYa+SnIgN+gskjvhBcrncDs+NamijcSwayyvB6T8slhDR9hN kdBhJZ/c0LnmqCKgai4771JUVbJMFdJ9Pg+rcW/3kne/lKPQFXgVpoGgZ/RP+9pyUJFodkH+Hbzr FM5N8getYYMLWnQoP5mThPRuEh7Jw9dCIAK8rTlI4AgVcd2HsbmQTHPCVZ1Co/udAG5xVaZokbju MPz1rtuXiXitaN9W+GIhD3cmuszZs2NjYBU7VJQamAXlZStEXxHh03T/GIQ+1jp/Zrbc1mqINogI pVGKqOB0ulIVOBit8+yIgnvyTxo5/i6wez8+Fp+Gsc816nx89/a01gpu+HEuwCHXEwfA1nB0oZgu xm0ve3HTE30mZu6qo1TWqqbXKfwRh0qxSIhLyJ+0dMukuTVvRYizA9p6slpoH5eESsg4aYlorLp5 xK0YiokqYmF41EZ8IO8LLGxa70eee2zd3r/PG34QR2l9cblvfq4SMggRiJOyadzX1q2saicL7GI9 dNh1qp85aF6mdVwpSnP0bfun8qgBHxDxwzNEx9Q7n+bVgYeOx7Vor5M/BhAw+5nMvvEMV9NA9KUV hlg4rJZMBQD5MhPXlV03otPUc9yiBfiW/D0hqlaDX3z1Sh+a1qM974OwX5fX7ApXiJdJsJl0IY5c /3SBRMKIE86br7kFOXq/FKTZ5Hk+Cxk3KhsRPmy2vD5OSvPaWBV443w9iPBeJuDtsXJZ9SmRg5g+ bemmlDSO+xJYUlVg7AI+E2KfdFiYGYEEx3BhM/rhTytlOiM0Vqjg0YD+fEb3e0nLSRA0YOEKKgOJ QReymI8U8JkkL3rkvdcMOy+94SG/E4LRiOgcM2LgHCz5pcAb+oqAYZ/bTvLb01uZjzkJFxpddwn3 6CRQF4Cy7rEeReF8jyzUSvin8fy70E4gxWN2rFp0ECiBE7cinrw1NIZOSN+K1qks1dglYy/Kswt9 WI8WQQ9Ja2X2lAe/Mu/Gi16swcg+qHKGNl1Ys/3isqlxxH4Kq+4u3tIgnJ+i6pOX7kLBEoZwcolY 7TJIXOzepdTKkmMjb4dRcTUsznUjP/cpfHRBRSS+TvfJnlIZrZ2byNh77Uc3UNVq9WJcVFqlcujC L7VqViT20dkRsLRbUCnasME5/XhKt4jG+xwS6CwVlh0XzX62haEC8LsTF2vPwUyC3SR1qnJEp5li J+TQk1HU1QF4PJ900jlJ7WIhX6rrCyjyvc2jGXKvQbcmIBxPXxotrt20UEJldW6iKxsYpLnMVcl3 FoT40XljhUE5lF96rVVoTCYVL1pOvN8Zu5QtPwF2LdpqPdif/H8Ely94QqSJXLhLp+EPNPnaHXqu gej55ghbwymAiC79qLg/tjRIkzstKH/GzeX1k4rLL1WZ5/MDBNIcUidtV/N7LkQ4AKOBfOHRCQpZ ie2+KVQ4yjjoVDJ/EtIhkr7QgUIPBZ2HAevDnNBSJJP7WAl9PJeXRFySVZXGYX5FfmyGNhux5FPC ctuUvwLPwqpjNuo09s3GBPZ2+3uNYUdrOzuFy4fz6RblqPips/YoPlD0YnUEy9e7XAnsbsx9656K vByAe+tzskh/PioBF1rwatFwFhfZdCYBZSFAKY1/98seaWV3+0uFAruu8eGm64FoueFFqT9YCLqQ cutNay9yI8z7mAJiCYCQJC6NRO3yeL+/48phjCXsuzmtdT/+G8zTOh8mzkaP2YQuyfJcX4jzqeyM mvuCD+CmcSFgjh0PSR9oxOv0xhc44lil0GIgigVs0lkBcFwwVrFhJ1HuwDz4dL1mSRVEQcVc0+34 o4lWAfsKmCxFNdFKVa7mGsID9ZzFC+5NbVSM/SLuK2fbS07vvOP/YOe2l15lHehkFF2dEgH8wCc/ X1KUPfnCiKatfqY60mZX+fvpyfCvS2+63vyrpiNCxyjZnYP/uw+HG8rcP5XTjWL/ub7Wq6iwBlyG LHuTVI6nA/QVZJmK1ZdZ9QzxeMoB2Tt7E+UIcO6cNOFG9RPX6ZUxqz/77KYqC7d1uZAYSE/UgpQ0 4dlDedHfwAuQLDhdVNVPn6ZZbd6Xb7+/lWEcNVsK9Oo+8m5wKiCvCExIAevburNiqmPrfE59AHjm qmxnIiIZlVTGic1thw3GE77pOwNf7hO6UvkV9gZ/pKBDUyIduscOVGgM479z4guzHB5h5GdOTWsg ayaMxfOgr2jXOT5q6YZUZgQMAxUwlU8EXPN3r8hWM2dfkKY48vu0HHslBzj/NUKRxhzIx8WmwAit Tp+yjbO/IZplRSmRAGhQCUBwAKoIh/RYkvwamOdOYn0q7EhIiFbppDH6NlfP+qUAWYr+XUrMeRKw hzSg7a0iDV/R56nYKC1EjMxfAfjLHGjKoAGZGmhnSETBueqba+B3202RXmpTrOflAgFmHb1wNix4 jCOPYWeESAAlstkCNcmdSzl5O4wrCU/zItedKcXPwVis28pEEfc13aggUxafnLHPXhvL3e1uliwc i4b95ApcQ63TkVRgG/NAhOdwNWK78JjoFPqYygg+PErPhgx7fur9e3iXq+yogSsLAorxCan+4CeM pjqouH+hlBXmLBWDC7kvKuC2MoYmpVDTt2/BtaxD+A9uD2WvUDQj475thqwIHAtgzkF8AwOoNUuC f9gJG8c1puIMWDJq16F5eOX15+FaPLauAnSdse7iC6HTWDLpdnV7tBm/P95ZlvNonxy8ZJaVUReh n9JuHUp7XleX1YxwLmC1Ni/xOfb5V6RmEUS57zxX9fqV8SRLTF3LabzpdW/RiqMhIoBBZQIZFXCE ECqaaWqMN4Wse6FaiPpIQo+93mSJUBWvI/gKzSiaX1ob5hjdQphr5BQjatDQxY12Ss4in5V9otpF 6G0URoAxCnnKMttV8ub1B5dQRFqsHjhkxn7Z1ZAHmC6HhFUq7udNseEcF4XE1vlQHIfRMLUBUylT YNT96FxK+bEcnrGDG4SEjTr1uN/WBFwjrohx0+MSnUB4Z+QQZ4X4QSSX9IdLXFv+TbTX5tGcVdIl oyxDGCt+FsDwBrGdY9tqbvLngoMfOXFCcjq7dGnCd4xpw00MoN95aH3E0N/eChCLfKAKSLy5atrA BLfgldp5qQEHm9xi4Z8hv2MKGVwZEN4pXnQr6hVpo6mVQVMZw2d7L6tBC5/nY9QGB/2kUgkDdHUu QZQpCjV1dJjlq6CTgnna1xtWI0z3mTuc5Vay+lHFoJJW5n0sTdt8KX6cQbCC8pBz8vA+0t94qtA/ 9yi66MeSOwds5BjxpaShoV1syUDqESfQbczYR0QQjYq4X692b7GavQ2LbD6F/6+LMh7ZbONSVeUW 1gsTgKR1+0uBIsTcLWU3NYglHrh4KwxX9eiwy1SNp+DirCxbVE+OYLeUqQF1FSDxL0Nt3TToQ/7k 1ya4e147ekxmUZwQTTtZwRTXgs2h/OQPttaImQHGCBWyG2Z6bgfsn3vlS4dCcH/syAi1a+OnX8BJ UY52pb0Mahr+Wq0VvDR42PGmikiOxh9x2dkTUChkpXTJT8h8CpRfGhjsKQs1Mn4x041q3PAsvJdM psuAtyjVJ49o1UwSIT+tH4jA7PktJW3i7IO/575J9dayFQfulbX0CyPwuXyf9EqHFSHHtNqmWoMQ klYRAI3sQEcDHDCgkPnj0n543UwIfKEj6Pvr4EqKfjUbzaa9uCOabSOJBWGM+SHqwyrnGgYRR9D0 mgNZG4GXh0rvIdQWi7R7KKaIlZ2vZZxXhqgB8KrcdmU+j6n9XFS16sGcfgK/s0l7MHylsPWUkhd5 w8d4hSHp5Weuyw7+kNjHTsstk4/Ugm1PYOSpPFJPzNiJuAH/OpJneRq53XqgE/jHjD6efnJ+krbN X08MYiZMwzdaYY6MQE2oqW8M1PDc6UmivGYdK/6U6fbqcSnki5ZO+Z/3jog//3StyysQPuyVRNmi EItu6qz1l+IDlLLh9W9Afk7vG95AUE4IXQKxPaOGcrAuiIZXjkbKdiotP+GdtasFoSVgToxeieIc f2U1zLXVLYbGXNEoUbFkz74K/UcU7TTLmh6aRa3qwUbEKVYMOUgV3Bk1EXQ6pR9DG9qb28vDnQbY BDr5vYOGKlKN3haonFYq74NbR7U5x41yYT2HEYyrXv0qz0b1JmbaWBKFjhh1z3sL793rYdJY328X slsTa2mOhX+BzqlfLkPc3LY55IzJahPPyMLKfNnv/5Q2UTo3Othnq53qVUBNf68Dh/brLS0FTX4A cReSoPwGfe5/i3Q/mGbzVXtc25C5Ufxu5iK4XnnG+TELpsoAUzV8TMAteSp0K4Q3cyjyuYsffb6w m9d4pPq2q3rwUPX2VS8whf3I5uvNDIz9wNjAwq5vjNAgaFLrSkUIrEqKoUdQmN6SnoDHQ8eFumpE /2SXC2OyhB2IOmXDcZEux+tnnc/01dAAHQHMF8T/3koA0pOhbXbMkkxOJw0pVI2NKDyz7hVq+nli B27fga5x+RM/I4d7VAgQIG7fgvN7mQ4b2gb9OZJFswYcuWaLoosBPFIuZrxyajx8Ge8El20NSJ2h I0VTGkzonvdITSNIBZ0j2El9zxTB+6vLfDiW1ouk3BaRTZqrblU2WpBS7ZEa01iUkWJEjeyy+ez+ 2mTDeXq+ReoRyEe0rLJdxwUTSdoNygGJWY7zz2u5YMHCpZHa4iuYtpx/ntSTAL6QFPSWbR3gzf7Z jUwAoUsXbesqyebluztLVn7kQl0HE58B5v+reoF8u/bi0QdoJx4ks+dOhdutadiLK51CUXJqF6yI +pD9043c29CQRS2mBf/5iYR3ikCdsgMvHWCpPgoPBf0sSWNs3Kh/cH5KvJi1Lczn3dyyN17kmSWx 4vGVVzVPBiy5+PtfltgY/OiecrHASLEpQWcdLgJiHkYpBkrGcnKKJmscQy0gG5q1Q6grqE1Mbidj rIpxFcSTi+az+lEAgrId77t/dNXKXpujdJ/31xihhyNL2O1yx7f9o50W1I2QV0P+2mZOgH6U/peA aajaHzvk02qPKV6kHwgXShPpZNtburbdXzKmP8jSvMGDQBkDt54Sl4tnwow4D88yyVYQGWJj1ZpB kVIYazfaa3XG5VnGBPwlR/8yfMX+UlzYQDo31cZ9eo+Nkf/fw/Dj74Xmc47JSxjm7cWQL2YQFAKS SzZB44iiFqLBnJHNvZQmRMFu3fvcJ7+BQceiEXT2xLSWnnfqKNda5ybl0NtUltf3XYoL5Chn6X1t o+W/hvnDWaoc5RNyqen51DXA00+A0/VniJsvvvYtd97zLFPVZiOv4Zqi2T18LlyaJpG1QMTFgD2h FuI8MQ7/k38gbJFPmQVIznsXSJluP4T+tAq0LzlEG325NlgRBy77KAx+haH2NAU0knSVcZg4c39d Ka7XDBYufzbJjPT1xi2BiiM2w0BQ8polwGZ6o/FRHi+fK7nRDnC3DxlW1pOLSLVFVrTzr7Fwym69 Vsbw4RQfz3kaHMZPLDQeOWpoJniCDuhYFdol/Ys88JSexkSuL1jF9HhF1nxCNE6pE+wF5xfhEtl8 0p33B/T4CE/X4lBUgnnsirRrYom7PTNNPeBEiPG0ULcnHYMfEAtJyY8tquNlhKBwYm25OIa1NXdt up9ZQ8OPD9Mk+zkTqy+ZvIasXohtlv+vHP8cnYddSTI0pGySkL0wHpfbsh+o2tlHih746DwDKtCd FZnDNzQZNv4kkZM5O76f3Y0ItXNmriMBDD3La0byM+/qNyYrjdUtpKUsCfCmUasxhiCtVlM1P40x GMa545c0z/1WmjHGuUbeW6nTE8jLVlMOlWFEEbQvvXVD/09PU6WRWwLJkyzk5N5JkXY4vwB5VCrU 1IDMHZsCFUxlsaSapuqLSmVQx4uU/G2KynYMQKlBN8DJHO4my999u6BeGOZQAgrBrdALNQfIGcZl YkTddEu9RCl+YMFcgwKzkT0G48zQoXvGVPrj+gy5dVHbqo+Sgx9YssmzsulaWXcWeSoQQqoLevud YeCW4om1mv4ZkbojOCxLOkk4CWgu65Pv/ARPMGo22kdW5dw3Xi29Td7ZuFoi+7ULSfu28VVUN1M5 zS+N4QPHkhaccfiO56CrgKUFRl6Dnbew/dx/AGzoPN/AizGQKLGhxPmVxQ/Zy999SorJctsMgxBU 6qWXGd73GF5M3xi+HmAlIEoA5u+7L9BTCwr9kTkJYBlRCdeVQd/DQU88HCB+/v5XRwWcSH3jgJPR i3/7BaZEjlbho4GfbSe+V113iK0zk4mfbtA8YytsRmLIaBhX595v/1MMAFtF2tDl+ewzKNR8csA5 8LwgHFV7npuu2eLJ2VGKAdqMigUFFncbVi0x0uIOj+d8EfR27MTndXPHHN4bgr8qEP7HSpwFDPdK NsErO6x0uFXtr1UwTjFAv1Ob7fVt017sPEgueU8DOagMWb8Zdm6/w7Hn3W/RX8t5ZuvMm9ewNNgV ACVF3gVdN4LDq8CL7t74OFlWQZe9nQP4FdoI/toZcrEk2XTv+GKLkoHCWU6t287ZuwABr3ipH4nZ Lm/HniQFmwBl+UrrKsHxNBT90Af7CBhOHRZFXFYXDAknUD4o0GnU9RosuPjX/ZYtkrHvYMEh3/0u eSep3oukd+HsziCAlo10mKRydZ1y6dT6s491rudMTA7xD3CFq9ncGQhCsWfGhP6XVXAQq83+fFgP KPEirIU97U0SPqQB309zEpNISGi/szQF0iujolUCH3UO2QOoHXXvf6w5xPvUvBRLX78+PIhIYDlW LeHDh5ldBJQJy3yCqwfrqQH8zQo+r+agVNBtIdBUFnMsc1bOd4rYvJXHvkPF9gWj9Ws0pf1s9KgV E5LvB2730vcUdFEgIGFVuqGEBN2lzIUXh4L90K7Jkp5KLGrgGE15j2w/K+/V9aRDYRW6fRnuFFk8 CKFE9Ojx3IvObTCf5eZ90QN5gGTMbDAvsuCCso/cI5mzVnT2B8L3Pq4oYGIssAfwiurazVrAxpFY sVX0O+psRUWXaTCQtO4bmZ/59RwifDufTcR9gmMiaTDCR0X3SxuDWlewE36hMTxFSkS5eiHxFD+T 7+Fzg9uSHLO9czyO30y2ise0NONXvdv8QZhQENvXNaABdC0o1BoQ8HgPHWUyS0B1Hl99St3+RDmY cOVesLYBiplTfskQmOYm/zoNQqNnjfyS6r/yldJWu8JhTit0LmrBMGNYDKpJGOMQtFUrGHtCsZpJ rx+87hD/A5IxdrjwGwV0iF3fACsYTdMYMlAVwP/yKKWxzYG66sbT2Z01vj7kKWM7NNcMMWd8dV3A exmH1Pe9Hopx+seJ/ET61/soetsmNc0CeraP377FGuhRwxsd6uxe6WUuYfxfpgoPY6c1D8goVAP7 5euM5KhJN9qAXT24BvZuJFSNPIXZ19YbjvhFd+4klIa/3BuFpZgI3wAObGXA0GxmxrT9cYfUFKMA b1x/2EaXEKBIULOpkDYThdi/B5QSVHNGgqgaSz0WCuK8wvj00Vz9cBKO0aNoZ5Bs/CXibrYhPpD4 EK/UGrv6Y7LlY3vxZWXxMOmnqfkPE4Q68EEaMksZj+A0r/gJGZGbbU6MnPl0/90ZTWt+4kJGcjwZ hbxvCoj8SIMMS7DwbrB97k0peDvsU6OrxWSKMv21OmcrThh3nSQeDj7uodY28BS6qV7/aPgLd47J BkQ7IQl9WuY6rG9P5Fg885O3BheQ51M/ZQMxnQ4cG2PN0gTrRmNPhDph20h8EbsJnp60VWqUDhrg w2YF92k6TWx+nJHplr9T7TQ+aRRqwGjKwE0S0B8D7TqkWRqHSauArPWc4gAy3+fr9QABaph24MO1 T6m7SSjyHUQWVfdtDJLIb4aTzbRAtxFGc6kMSnL3HpRSv4Fux2u/xB9azPuypfqvTurOnBHPKx4o M6yZsS8LXp+wbFitWuTTL6ff1Hx9WFMJg8zvIwaVzwVo1MkWVH5QHUZGUZHcGRGWnBU5jz2qVRAx W6ISbUJIcLXJccTxMrjIANpFhnu7SOvpMjfWZxaqCPK+fS4h+OCEcmAjsTqD10ZszSu0XAnGg3FU rpArUOmdd3p+k75PVAFUvpSM+SX9Jan7UT545Pg9WrD/SxTfxsQ6+zcQn/qEDUCEv9tDLvfgZhHm SvJZ9PMEtLYVOG0tcd6ourmy8cY8RP0QQiPK8kpmcEKIsVYBl14+rUyrkPBQXKQTq2nVjcDPhDVr Dq4JSfTq14djUZvbCa60PgEQKoiIQuLmu7QjigEdPeGeQvBmIV9q+xZzYj7S7Irh2Oy/HhrbKCh8 1C6/6wt1jlU+qXEF79VmvEO2VjkNmCC/mJ8IS2BuXsJWFhaEQI68Tgly9wlD1OxMyM0hNVxu4P6z csBphrwkBgNf+zlVkMMzZA+Yreu4o/dMqs1WGw9l47TZZlts6slJ3f0Sl7q/N/GViqcvY70yo0PG Apcm0HVPtj980JvMuOIbr9qD7krNIVMnoYIyDUPiVkIS/tQ06NZ2XmDui0p3cfphLMpgQ2hmO/xt 09O9lsnmcpzUb6UmY6K/S23fm8ZINro7A88CljBUwSMwqUQy7u1P1ePxjsceIqtca1ZnQeXc4dat d9QYw5QQ07tHbWpPcjtZI5OZs44kLXOWkSoY72p6PTPEUgk1vOKQgBWHhiGEM1Rzo7gUvnMksg86 iMsZPzhbLTwcIGX7f4njiZLlH/Nm4z4CH6W2fEAenH2HrKmKvhoAUYIjpOkkXqyJarRR9zKtzrjc PIXMdr6j2kZGLEFj8r61kNkC7vsebaIGb4DwQBy1ijFhoctjlrEnjMEPl5rW1CG4MBtQn0ufc4KS Zp0clcoV3EvEy3/tM5xgoa2STD1TaPWg/M4wWwRJ20YfhSQ/EjnQixr+loEX5xFgot1ThbdRBY00 QNNGt6nSY+1iIhZCpmICBPRD1dTJzqZ152HoUErLxNyCsiOnpP4dJeEc0yIaNcScRZddV4cEbga8 /2H4bnq0Ay4PiXAONl0xhU4rtO93yzqJNlOh+d8tJRGoGCTWPYxv/1ZBD0o5/SIpMdbTn4Q6vNB+ FDTiBzv+gmjkNEWHlp0lSNaEsojyw44BdEppPkQ1lzRZewqvKUGZmUZXjnItI4KDRTc0RvTvjjPb rs7TTLMA5uaYUrc7kk/YiDcxsxH9Ei44gZjvWxQqXuovFnyYFQ/ozO3Xi+DdKegszMUEL0EdnlKM RJnhaYmoG/ynxdpgqvOAEWxBEEC8Ek1XQ0ZiEnp0O1Owya4LpC9Mng/FXSwnCQxK+nvA23NYk+X9 X2s0AnI8au/j7kcU0/Y+rB1pMUAsJbixH8Abl8IgYEUSmP29/1N0dNu0MDF5PCpHh3yi6uyF6HBX 4KPoPO8EaXyXFydzNzIx5EiUSQAbEZ7t1rZEI/wo5t3NuJ1hqdfXsSOFF9RJuEhOjbUAGuDh/wY/ M7yXe9IIisrdHDXwG61NKGN4+Fq05FwGqlW0t1OkVqmP4gQmqNTiugLNnfQXPUeEHd4dwQnNxC3i 32JDTQlqYrNkUdOFBgWubZi4STW19yvqRtanBlw16QUgyWVYmAMEUTsxv9Mh7LO9pYGTNtd3bvSa pPFgmr4vkQVwCBW1PSqR3KeN3J4B1458Jo1osNW9KxeyXEDs5kQDXVYyVqybSivPcOsMBq6vrsWG 03wPbjrrkiHfo1aZBXJEZTBHTngLHORCUDiKsljFezCwj7GOP0x+B4kuqTYaHzjXLk4WjaHodwEx eN1/w17kuCdM8cgGcZfKLGQObhG6JOY20ZFz5qOjh84C6yjta5iwKxCr0TdxJfJCEzygHVa0CtoU 8iRP6Y2Bysy69b2nEdO5K/zZXCYXl15a1nsnCVB0Awi6kFhHM56OWOW8fRG3oaO3y3OTj67wAD6p dJDnx9VYAjN/aRRsJZ16C5Lh0t1uioBlaTxVZf0k2CvOroIuut3k6qWWLkBsIk7ere3I9L8czcrb 8FfT+db/BqbY30lM04joaB2lnvQtcUQDfsKpb2aWlCssrY6xnnSIc+xidycoiXrhe9OrdSlQqbnE o1hfpiRCKI9suabb3+NKi7L8Don3DJiFjh/ExAxXoqeGZwQYJyE70SVXQHfxCENFIeWQ6qxaK1fm pjB+vLD9Wi6Rm3uWdCyoLbd6bxoVL++tsndLzYUHmBMDZa8W3ytkh6cno0FVMztVAObi3q8l/1P2 TVQUrSYA/Do/pEDmfX6GDZg/CD6PbD9KPXKexK9W2buf+Vwj30q1S7qPzKsHjtWMa4aRh7IStNZC NzttDz+e2p+D57GmzRhReKXSIqOyscOsHu0eNY4SQLekVvf/mVQOqqcGZn281iS1GJfUCimtwd0q gf05TJptHGuSzz1XWvme4wAoTXh5U2XbZ8Nqg8dbXLfaFyuFE5utHqwoVr3hIOQGSO/VYPNEtL3m mv0V3dzk6XtHmvk1LazMRw31QnroHcAhq61GERYxpeBA65j0jTVoS239nKL4FppdVy6Dq2IfnmBS 8Wspzug/gyure60T+hehXhcJ6VzhjdUhUmA2WdjwP2h4vStOtxlY69iDzyBGr6Y52qGpGVyOOUar OtqHP8jwye6xMEOCcRQboD9OuLSqRZX5jI1floRagP9dXDj3DNrZVt4Iz4ZRzsz7pheZVa6kzkVP Rz38Q50AHp6HQJ/ab7gLauTgH/Llkk2GNLuiFoY6mKhP7LpIymCpCOvrIP/Rasr3iXGT7mKO8nMs 8Y9xC1NkWegRn4QV7daRdlMrJXL0jN8rVxfiM9cdgiDVOE57j81nob4daM2VXz4aewaxiatrYo+U UMqtT+63vnGHfmMmIPhitFtbRu8yxetMKhUAjeJBZ+xR5z5MjakA34kkIU/XCrqRrmhiiAnYFRX9 RfOTNDHj2nXPQaPZ1/Lubj4ICQoDlKR5UIFZCLI7zIT7mxbMdFe3waecXAw7goU0P3NBXlFozpxs ward8VM0hgJH/Lv4+GMNVRy28xMpXDNr1jc6bQ+bYmQtcf+WkHkgf7j4RTv+L8+Bd4QC6hdROfBW KWLOEktlQcCfQZMVqbaiY9ubixTF1NGW0XX3pciK02D0gWJdEE5Y1V30R6GIBv/m37YXmoveVzNd dRHo1lCSBp2dy2z2b0nVAMoGMmzMbsvaoIHaZUGov4PJDBAVams0pqdvFdSmLaZKgKWXBjJ8QprR 2q4GThOdW/LorZHOhL9wMY9AxoXuPv71UWDinBPS+JJcLRtGLFofF+YeNxU+LI64D3BHXPrkmTk2 Wpsira5lTEK7wNhCDrn0fbTt/zTelxZwr4xPS7XUjRYvUry0Uiha60/ul4PXKDQWtw6Ga0PZi7Nv 6JiA+g4RkzkrgEbSjAF4dH0ogvcL9/4H4lWNxSTj9fVUccBBkbm0bKuU/7vKy0tzN7PX1kI2kn7v BAY1/r8JXmVkrlxsk7HOAtYJncNgNACn06S7JZUfneGpzAIzb2nss3Ct56zssOVCNPh1ZkTMy/QS we8qB/jv1GXdtLpDWqxFTWBt49kFDeqyR1KHiqM0i8BwefNoeWbsyQdYCV1ZDgQmDpPK9qT7CBJe T+GQFI4RAeKGN4/RMu6S0A3uhhbYYggK8hFKK5pnbksUmN4u6QzOl8f4hukSy4mROuYGNUDgN9nb W18fCw+Q/hred0hfj+0PlX0PLsJtxEGDGkLS49zeplraZjMvNB5gfmxRug8vjfQ4akI9sf5ynhsa 6ue7s+j+3lCfjqGK3J3kxjkuq3C3lnU6KwjHQ3zk7Gmr6B1EGtrc8BAi1saRE+0/apqVO5ZxepRz T6KKjtXAe7IIYwjOLWC4rrSRgrWfXbKJlyhGRNQyjXdbSBepufj8s4lYNorw+CgtjHYBZ/QSCHgv tMBPqJncAKz170vqJBQEAIyFXXvb4uZioXiA3HA3JtYosecnsjsTn6JI0877QhLbFqN8gcksEjS7 DDRsiipJsbTvee4GHkjt10eK/a/Zls8s8+LMSKNWrxskEW4xAK26Mwa5fa+zuqVNXbPqvn+ops33 IepyKudnLHZIAfqhHrz324zgWLh9ljGUIKGja97K02QLevjJFwsnrUnButbs0KkDlFAwlQKOMTNa RI/U7xlMzOXXK0Y+HWjLo1+hZ5mwb9qS3tJfmbtwqZujAX30hmL5Ap81Bj2jPVk5I3/2fqq9t0jg G4/aeJtM9ygaLimCp6u1IO4W5wQc86Fx6300oijGq0VdYTSmRRhw37Q2CmFGEm4Dnsu1mN97XM0x u0gxGu84rbPi8UQTvIWx1bJr0dppjyCYQwITszTRF5U+AjeX2SWfFNrf6W6PJIkg4FwR5xoPXx1U 2uws2vO7YEi0lkh4ahNghvoXOWdz/kuahvcUpq3UG9C0itC9+56zvZj9MzJKnp29AZtW0RYWvodW LqOmthoX2grXJRzofkKV9lrpyfjwsjfmuftVGzFrYeBL9UicDYnGNcvzxD9NgVUjbwBn9fssSfiV mvb3giVsaxgE0dQF+nOwfeNnVstE0QEwulcUXCOnrKrit0YxeDYke1oELUz3EDuMn6F+PRhFa6ov 6yZUepmitnXzQUKxH9fvQAJzWoBUuQ5tZ3PvgifOpJrShXztMg1Dy40UrgNakmxcyl9cMiUfcw0X 873sJ/M/b0cjbDySqy6uyQY5yT0cJVdVYNFB1Q097yGhypq4UNCntOsdaT6zMioDqIdUgFJ/7VZQ bUwE/mpTkwPZdPJbm4M0/MSSw5kL8kDdBzZrN3pjGzBPQ/KwhmtPXoNhbU2W44gEbCI/8dL0TgmB KjacZc7w3nZ99qovXMD1U7f1/k2ZnFVaqncciZD5wq0R4ujWMQ5RqsFtLD0qwG07PAeCCWgn9vZc QpC6Kui90kKwMh5EdV+ViTdGcxhJ2QQjjTLT72VVph+IMBomDmz6cMJe5Hhwq6vWa/0TpzKiKrTM ufaCOYLYvOcN/ow8uVtnhcTl94/9tu3k1VANYPjczYYQGChWB6uaXRjyQPVdOv8mhrGjsW4RhqaR xWcKnCe7DvBDjZVtPjPRKBLPXrFX9GPVtP9XWam7uYwmktKbMpUtES+z4Dy5hgnyEtwzCsMvw2Hm l54hwH7f4o4zYjOxTnowJ8U1OihW/E2Rbf52pkqTTmOsE7PMIZzp+9olKLmQ7qEi6R54rfYe5s/O 2oiW7XIqQUrR3O6twLMV7KzfhqDyAGZvm8WO9VunCJkOOr0fI2g1z7OlMf/aC168kQ5+P4yadU55 kb2ED3tkMNTcry5eWQ7QKTvVY5N2z47xn+ZKLEfXi8lLCOtAyLP0nYzWhf1Rbtvm+a65NK31oYoe 2SVEQ7QMMEemdagQMw2wZwZY/kveP6mEWKjL3cDGLgKzBWKrNTQgkGXjnY8+f0ulYAfSfb75SQ8H 4uged/kVa3ih8XYvN09g95lyeQ0xKoj4hBiCnEzXFpasoMG6Nj6rmWPo+AgqFXwAOjuINzUHV0hj KZdBWV9g9lBffRh1/LXNGnWJzvKjLYCqWoXLZTf0LybXAWxMOrj3Dal/ClxFwYhHEJe1pWxFPBxq T4cKycv3ioISas11K2YTWZGeIm5oCdMhzTROWfn8mnub/o7g/uSNkqvJ6lyW9OKkGpVh+i1wg/kn M7PPFDWXSZ/CU9If8k7UmCUp4DgRzQZCfLY6meQn2QqsuPLGsI5dicTANkHVyd4hqhWCFgyupiIF W2S4INLhTUiji/nRYFQiTgjfiYHFafNgFag8I9LRWNbLiIfkCICHvTr5iwuSG/fns35gHhk4DuhH +y7B1hHswHqw6lG2AcpNaje67ggRENi94FW+HRF3fb8HryFaBm2ZO6MHCCrFTyFiBueVNfc4i5H9 osSKqT5sZUr0aQaGisQYDwm5D+EzR9fMya6hHVBxLp5hqObzXesUfr4ULmldplbDMmlz6WLHl540 +uspmyGKH29eBZxinRsnrYM7e/SRRh6aHaRMh2+W9wo6CZI871atWQQ3xXrAZSdJ51h014t0Nghq 2xiVlvYTkGD5yiz1O6YqQPO1yn8fr1KCjtIzyILo+RmAyognM7xOMeZG4gOM40f8Eu5JCRXPAVm0 8hWpxkERCgidJ0X71cUZTSJCGvcE7k50PEhk/vgf0eOLwUipXKVA5dW1g/dRk3zieL3X8pF0/N9b Kyyu8bpIS3qg68sn8n8JVwzV2qCrwhDSFjJTl9CN6vnupwpb/BDp13JwiyA5DCigoTCH5qGeSzfi 1CnGOCMSqYQIXUGH67Qa5ZjOb3R8SmLGNDTCM50ki00/S/sSuopQafqzpOqP/hpdYSofee+3F+O6 wkvVZcp3kz2EjIlNuSR8W4TqTDmCebX1WxpHs0a1xWj/Br0xCdh4ckhJO2VYIqOoW8CcrfzMh7U0 6NUlHwrGX4udAzC4vj9Ti6aO2tWryItbSwPORDjJ6F8RJNIEAq/N1jbXNlQAtDAWtFpAFUNpLjgz mxMk1JMQc8dGIpXsL/Hdyvck6MSSV0NexN+KwvxEmCvqPg7if54WmVmsZsELDgnm/LKaxJX5qK2Y 7aQfG8CnnZ8xJ8uN0zSiwn7xs/ckyGkMbjNuIKNkjZkb5MYzyrFpERHnzPPYMMHCt2EdKkH7Ospa Np2SXZuLYiPRHcezOMXe2kZz3gCKYMeSJ6A6D9xXy5IPbQj9ENqzqziia5CCVm65ReohfNxs9d6Y 9eN4LmqTOsHzfuUpmc+w4cTKCcTMSDFNGmegkdLRNMp/q5cg8SRmU7maSg/avDBKamB6cUp9ILUe DFvE05jqDi+8pikHNgNTzRjwpozLWaVYq967fesv+M7lfRKLX2o0oONfwOQ4tmcniIx4ueCJxkxn x7EZokf7ZdL4JMLiM5alCqVrJz/IVEqkHueG7S3kJDs7SZ3aEiErTSMdFoVVEaRaHdQILsHPWkNj 3bnpxwL3mCe5FLXw3QJrzsXV6YVEZgQT+6ifYDhsh9CvO2+LKZ+2zLjXZFdLdGGcjCA/tEZVfO9q gM+NTpTjmp3Q4DAPW+5VtdXJ/incZGPwKrQU8ZRXq7HoERjYm+5av/xxPeRgqssqQojsk72z09ye denbRt4WvxZ/3FjKrddiZZH7bg0dWE3pf1X4E3v8CDmVLsIUUgmFKgADDqx3hxDE6WjD2rFNMYHp hztbrGnOEzinAFlgPOBRoS6rRJeFplMspqHlkA4bWp2a1cYf9JjqQGiSQY0QmxXuZjeb7Kn5oK7M 9uxnICO2ky7zL9j8oFuoLBqNvS2i4Gu+HMWMgTtxB/l4LnFCx0RoPb5Z+20mPKI6neBIdBmoTDK5 ATifvflvgSZz+FPYVKwyNnksaq0u7P7J0yUr3xRmtOat+RdsOhYQa9iz/CODshS6bvbvtzD3nVCC QVeq7UKMIqjFks8FRtP5RNWc/jQOCA/Jfgscro2myqPFoRI9G77f8mGGqTqIAS47wZ+9JR+bg+1F Wfz64QPNGcoWe23fQTO6zCcM7eUifAonqlEo/LDJYuGTEUd3tM2CgwWkdVDGi0jLy1+QdGHITQ81 dK4GuzZTZXP8vSBnFYSEzzf9vLSvio+SrmhSsqgC7FGgQNgf4I7TZb8ZNRfFLrws2miSmKrsVd31 NsLOUCSdGDAgSav03HcG4pfaern4cddynZcEbualAWYSyc9u1Yl4SjjZ+g1JTOLN/YbQsiZBNon2 aTyzM+nkg83xp9NezAiG7gvgij2JHDQKdfDMQ1uPppGcK0IMFC5RruTm39ipki4/Or7DdJbU2807 8HqmNQl3VYZMiWDEqSDSG9G8NtSm8rR44BM/vQKey+OvTiAnPvM1reJk0IOIPZ+ne/uYORlM+nOO j6JvfDGHFoy+eyEHUNQh796il4f8ZbGCBVLodltLm7gIRa9ohQvHK9AnWsDhlqdlLrdHPoqQbOHX imnFPfMDb42EOmiWUIIcqiuDILyHoxYui/PS7tiZRsXAUVPMKDAITOQYb0CR1JTj2byPZC/Xutcx fiayRarClsWBw8s9UZeA00iBdlUTnFojoWqar0cpHn+MDkNfYI1JxDB2xpjMH75jshH8tb/8/uF1 HkEnAjJfooVWy3N6XcsIv1pCV64dln9EgRwvQ8dZnJZXCNoLTGJAuAof6uT7DEwlNjQGDqFjNixP FtVAAbSP/qJ1/7zt6DBnXX66iDdwppl0CUwfiu7b9CWgCFalnibwD/zFAOmWYfnWs/vPV2XbMnbW 6SUKVzGMq+4xS52TS5W16fHGnHCX8LYmFlYtlkpkIUAVZS2jOrEBTceT1noxXxMdHKGIZuH93C8L cix3+OcwNQ7dKC3jNHbcxKArgPXqtkDIFPHdLn3/yiJkWqzocez47JRlZBAOhOLTB1VMWLI6Jlv+ 6z4SjHtipN20E6kB1Xny50vJM7uqMkG4XZDefBb/KVYHX4oyZDk3NVOpDdNFd3nYngrFygWM/OJv MWBdSjqXnDr5YQTabotzcdqEw/SmPvjVdcuJK4nGwyuB0hRgObB6oI7BupBGQ2QJyCLqbSN/1/73 oaTSFIcBd6nVOhSHl+U1rmWh8F/5o2UqpwH+tUIl/DDxcr0N6WA89t4PcW0a3fc22nGWJ8/QjVDr FetdE0D/Tw3KmnVRRTxdY5TJWsSxMWOiK9dWFgWowB0OfVicuGi3uG8RvwKgyjvZLUzbquYIS5a6 KWoMfMiMd+LW826paDsFK5fZZs0Sdjz1/YW3iAB0AzmB1YXmQtBFPckq7xpCQyf40SeXJeitRtBp 6/kemIOknKHXzZfkcaHnl6pAGPloEOKMGnQMJnk+Y9tTukyNawwnDzmCySwWYRFq+kBcWMDZ51jz E3Q/4I/SmLvLcv6kAFiNeLTRA9KKbDJ42xmopLo/BbBNJfjUeagPGSjaYvyUH4g8k1oDQCS+t3/t TuZPyMMIpOPhmSRO743opf65V88y8iynaw/6jVoWAtrm3Cz91dK4DK0MpCytc3+IkZztqOz6h48w XxZ8x/npv4KRRbrUXwGKMhwHPfFDvH9/SnxiCdZLAvyjLdwJyZ5VmgyFdnCOYxeKtvNBJFw4GZVw +r4HZ1arpdL1/lc8bH5XrEOOrKCgbB4xterbFudh3QY5tggLEXRFWbFKTSgDtLk5xfh4bz5Q3L1a 9WuwBF1VzwzSe/Kq0RpKhq2wA/GwsYUBqukhpeYSFPTi5IrbUN0J3pAgSzl9axe9MUIq+SK1p/Bp R9y7q+EY+bvx7KGlcXYpLkPtyInCWfZSLx1Ml8sslWc17vKgAI9AbpYofMOi+cYobc6/V2chRpib hCcyOwDGSqBBNlGaKt1q6lDzKPmqjuoK2wYtL8d86aLN7BtQ4em74DZVUvToBMQj3pYy4oHIh0Js tvygpKKa+pq2UaGLCe3eNDdUzimmbBDYGcwEn/dsdgwZo9CeJn6ZUARF194mDcxQuWKn758zvSVT LtvUWrNGN3McLzcno/az0fPAj0uNJG2I3tGpqJENxWSvSqYZ4rufclahBLkL2rzFrjkaESb2Kudh xm3xMQzBasu0jy08ZHEqn1hgbdVbybyTZxxSig8YA0kHobl2fUT6CI15LfwgnERwEggT2wgYNT1O pYKY2tlZJbB4+/rAuCR4deFiOL9P3hJYg0AmY91lLoG66UvF3nb98B/K5IFMZgirv8LcL72lKsE6 4EOlKyiv7vQ0p2MR10del5PSZNnU5CvRHNHN2NIOhTdz+cHurjVLkStt+NcnVnQmBRlYZF7nD724 tZ+dLMDKcsB4I7Ln/tbip4h4O14XWapAHplO+dN4ZxXuHymvEUKkNYcGdTa4cGCaZzH26Liq1ato DdU1rLEKfVBgQc17So2U+stD7SvGoLz8pA1PUrwBLXlLMtHJP/y+3/f6fQNxwSRUDnBaEHZIazd2 M2oySdSakZA1WAEaLHB/4njy9tZptcLjh5b/70yC9X8FVEvyklCSApKvE8oLZPSO3eOjXAqeDK9M Fw3JpZeu2hG3L+UP9/TxbhvIg1glqYYiT9tvGx5tYDDOCMwBrUIzI0N9Tc2eFsnvEXq3cUYFiTNX phgJ5dEatgZv53P0ZArKACwX7f8BKiGOOlDc1bHZ+t2RxAhBAE1czsW8D7BiquLYB75A/DWxKP+/ bb911Oeaws55ytmtWgjUVARmJhnjMTYNADKAaRgYxY+Y1IxkGGW5O9ppN6vyCGy3TlAgP/+KIbT1 hapaYin5fHY+eiMVkhSTtE9DgSa5Zd9spxLN+5874IA1AYoyaA2TZiXET12JVfiBwkM2+OXeJ2Sd OqvttXimQNCUdJvTYgd6Gfn9pg6Agf7NbJGuCbxxpeQ4/7SO4dCdx7/P171cl0e0vnfSbvT15W+O 3mi3TicohxTt5v9Y6v2CN975F/y1BL4crih+7FDYraB+mZb7twzot/02Q7RwQOUmFgaKH52RGIV7 7jS7qoT/9PrzVHwLQnDPWsutVP43i2xBmvUn5k/G4vmoSLeTBuWW1ucVGywVrKpyZWonao8XUHHK mtPJ1+6mClT7vcUYw3/6Dj21hYZ5tAR/dG0Nf23hq+Pntf3YKFJyh4G5As6b74j77hbaVjy6wntY azVLIuFSWJwJ9THMopW2/5A2yf3bms7W0ggBwfEtRRD3eNzRwJcOH/xTj00d8yRe9YFSF/zen6jG M01N7TX4vcTidAA+603Ppne6p7kOZBAz01/kDdE7tCtokE6kMMpny+mP+H9Nlds6D9/uWWGQ9Vpq 5G49P6KfwMytlzZfy1XmAmebur70sriLoQBOcweKpeU7wG2tLUZRGz/PwMfI0CBba534vMtU++hr SW5245TeAyOWj11rFK6aNUwiD/tBlUjGeURvj1NS8iGAePYXAwruyvXC8L5a1USBDz58WTtvC/OD Z+wZJb0tu1FVDPnMxOKtNfyd+yr8rcdwQlJ6lXtt7ntjOqEB8lIo9aM53c8w9XROsDpoBHPh/rNI zxxwAaRMC13QvvhYC9YtWhoKCWUCF9rw3TKvgUTb1KvLvIw5Gv/ch0M6QRLZlSEszlDNf+WnW8it iLzdvEwGnHhc7XGFFnb4xjFOUaGm4cwyR+voIgIZLDscCZCJxw5QR/0/XhnKJfuJ/JQTjw6+VeZ1 UXOcFKW04jVKnbScQplAhSihcnRyjeIUtsC0pEKJyu6hpbqJ5FFjpTPPQDqYfy74jhvlzsWkJP51 Qg5GXqCIwXX5jK9QpfWNkKwrEpLX2gmh8BLMevC9hh7OLWCrayYM2jUaPOSxTC4l4DBIzp45wqIL CR85DFM5gUhSF5T3qOiqOlkGqn5buqAHF3FdFFpeeKwi5KAiNXZcIc49LzVL2affLEpNxwpp75uQ V7PdjfbkyPryAEm2eXYlN3A8678t4YCQTjaO+24Mz10pUYfPpneuD/bOn0+eCGm6XGoLxY5qG6fg YEExLVQYOb0fhOjcs9TszqBuvqrvUARf/tH6DRTwhT6Uh/st6Ap2UeNcYkLapK8Vh76aiyu/bDx0 ouokRBsxfKmhpGB+p3kTtdMzeQ6iZuonEfMa524Ib99LtG3cUPSqUs9ATV0Ok46pm/7yzuaJnjrN QUB4PLao/a6IuL89uI3Vx2mQBlwiKz0lqlak8hvqzskr8IA1I6/C8UdXGB80IpMPrceUe5huPWcl peyLMpwCXUyE2SeP+53EOooHX0Iy1QaegH5iuB66qPad5557//7zA8Dgm1gDFy7UnBnM0hvbvHr2 YHq0sCzwWA7dHxDtZnNYB5JBoH6w6zCGM2yqYlQoxDNub25e1umZlx96Seyt5KkxFd1iaylIndM+ Dz6X/jzbGLzhBrrk+wkqmC/TP9h/mHZxLUOakFjau7KN6T9AkxrrFwGblB+4Oh+ZoeNOZKfxeGwJ XOeZHbyW0x7i9J9usUKm7Gy47Vc2j4fdWl03TDfZ0m6HLuTRCyf25kx7/P/3TNmsfvNO4KKHfYrr dMaOSwzX2aYPFAhRf2KK+D2UMvEyrrYwcUzeE6aDSD+xvbkYba/fMe3VasIQP6HuzH43cJ5V19J7 5DXYcp6pZ+VGh6YKAwHhnqPM/fISt5/gJPYXc2y2eBEb7SADLik9efBQJf81FWXGClja8q1l9nZE BQ8zrjeIM3Y0h3pWnnZHUkwLD0QnqRB8FuBL4VlLOi+ls3gX/gUssd54CgSg1vii2MRLlF5wwcez 0WeYTA7uhw3sBSP1mCGW0WlBtwKqgIIWDNGkZpUFhnt+SypVoRt5zjYrm2CW1htu4OUa18buuGTg B7g7cw3ZVs+8I7nMW+OAIFsCoKYUbq4ab2PwqG3gQXlyEIwl2H4Fhba6GSTuhUAE34sDP4pcyUWw ksBtuT7ymN3VHcMC8s1QnrxTK3hfjTDWimYbDMUEzu/lwQ3Ug+DiaIuxpiM/cvPEu6UfkWwbIa5M W3kG/g5Ax4HGK9mzNPCahagDk6tcTYSRKPJ4j6mUndH9rZH7Wgy71plk1wD/gNxP168x1USMjncz sikrOTT7ibIg4uyoykVMyuq6K+8XoGAcu4pAlQgKLInET/D6llI7dEppNVMuhzYtPUZrvfvda8fi 4u778AR+iFYcuN+tG+w2/K4zIH+xrQ2Min5r+XFS/UkS0TzKtnuK0Ti76GOEfJuivGsQzeO0Ua+K hEgoR6kptOdB+t55dq13BNJ6QppscW8rUqv8iM6dCYJ51eTnm2PfvGMTP2+LYP3HhFznDGGRgXqc zapllQ+wlneyy98ysvmVbcJ4KPxWERUOmEBr3/pjftFgFt+8SON/1h2Au363wh1DJg6zwnZ0pZGW VGcqhsUWkOdkupjrHoCG8tljsU5hCX2LH/bGuASqrpl2jv/mzT/JKgeRvKTAuWtNwBphTvbX2DJ7 GIKEt582RHOa+ISDYzxD/lB8n4ocv162It5nKL/c8CPY3KY+/pQ+fYQJyHpdys/QayI1jui+9TRt m7gzu8bH/Tgo7qgqOQ38/qqnSBBPQsFs9hJCTXX2n0UjhBObK5nhT+sy0jox0gVIGOl/sebZblZA roxZHfFSt6f2d6RXdZwugO7vsQj8jvULE1LbRLej3Tj2Vc650ty1VjV9KruOw+rgwjlNqo9JyzNo rOse68M+R1lJIM2LXmVp71jDyxCZF10Y1WHbtsJ/H6twz4UN2tqusaScgOXBcq1v/vehBKHuH4yz OPDWFtVnXKKIv6cH90IyqJohYCvJJ3vOqsaDO0QCX19vf+YCn8mnJ9ahT/+JQ2cCPxaz3abheUow oIaWJOO5O7a9WI451c736BpnDoiOB9/UTCPg8Fsy0oZ5KW46AUEIwc5eFiEjazsTwD2zdAdSq4WI 9SSBBpt5fWHbh0pvECmPObkl9wRm1d1u1WhkJ0crtqick48rNz/w6OQzDNJ0S55go/KT7zeHPKxo tGcVAuLdPxcNHd7qnR/mR4TPa7kICUkPCgpUieNvYbaTLVKlsqjjfeUpKBPmib5y9iawAS8sDNcy h1daDKBMOChJiC+4lNDnC/fvZZPkT4qpRPovVEPBwxsyRBs1pn3fRVjLhFuXbOdXgecPIIPxKL+d t+CC4nDOxFREjMNjzfo+BRUGhlD2s5j9dyTh5wQT37IBlRoXm+NUiR306bU9xh4BmqbWsXK6B7Il XPzZZc7wu+SwD31P3VdhWuidCwC5PV97odGrR31sT79nA6iM3DuNY+FLy0EkPnwjn9Jo6XZlsOta y6zYGcnwX+OoQ3kGoOzSnX3bSRyJoCNmxS6Zvvg2qV08HNjhr+gZJEzmxCDVhM5mBOilk5OL9qUa e1tkLmgT+n98ds6icxkcGIF8JGa0mpYiS+pl8kSjfF9yLLjwfYm0a/bU+Qr9GPnTZsBVoALjKeFB jzGeI1q5HLIJVwuugMVWEXKXppCZdzkBouOS6AnjXXUXdzm9GTqthrLlpeWFJ2YfYnmFMzURnVvv sVKA/BMoJdrtrOMxVEWxWwkkDCKrIieoILR7m4DRMDbwBCwZcvH9ORVWRwd5SO2lDvQxcibmSZ0k 8XBhWnfRdhs+ZsExUwuibdJeEjvCnNGrLO2TSm9IijuUucKfc37SV/jqoUHXUOr+236iPjJB54MV 3L920xXCIZpzN3W9T3p0WZFLnxq9PnnXIVgS2xWEm5GZpDtf6w/yNNNTdw2jUMtuBhLun/srt7lK pE7MQK56ap2aXVNLKGSDQh1LQ5/cOOhebv1kh31NUtqcL77DnwIjXEohbhbTtbQsFjUXHvt7HcU1 ycHYlznzW4uI9CUE46R9DHkCZEosnKagdsqwocReywAu+mkm6jgLPi/yIrmK3IVZBt4Jmt6VGiSm sETPU8zSMPbe66gS8EQuUzZzZfehVZczM08L48sGKo1pnA5WKnYs/pV8mE0cPWKCFsb2O3biBzHC wOkdGpi0ett211TsfxL3O/be3lYC1p2Za/kjYb9FrpGW3RdvYQ6b7XIBrtqkzO22xkPJE8rSF1Po 74xPuFWGr22s5Zz1GrxRSRPD6KsjoVIZ0xwL8Dc2KP/0U1JuCfNhiDPfnpbrxrV5QvwMTrtOdxKx vnndSFocxbnj8RNeq1jRCtgQgRF4WqfR7q5b9VDMKjDvuRyQBaF2mB7j0mkSALuH8NiXQzD559g1 dKG0+xOr0tc9c1SGTnzRwgXmhj7b64dOzkK1Fk6dE1dojepkKOWDjOqJdwpg6YVLHV7JDPXYo5Gh s8ZJ6ohX+78rGG7mYZfB2fk2QhCnBSaRVkpxG5zqHfBfMB2dNHZGNDU49XUKhVI2hOw2MslmC3f7 hcuEDwEpsIvFkmOfD+I2mTxGdMfhO9WwgVHLIzULRzFmAIOy7pY8PHd9PniopQSaBiK6Pmzcgd2R fF1/toUnsyILLff0Jy5m36xAy128iodJl8Yvd3REdYKvSFuKDhUfRRNgIV0KbSO7FIyhiULo63po UsOkHG6B0ap+8uolCd01vRbtdAbvbzl/ZGSxJoRqtMYoym5wLGYRZSMR0FiSWbnAcwqmagBGE0ZG E+n352lp8YVFoyVHa1yJCfg95znEuIkGEPHBjauJ4YyD6M5hlRzAKGpNf4O6O7wbG77mpPFYGMd4 h0gjzjU+FKEeqvjF0ZJY8JA9uRY7NZIxSXZ0bJ/cTX6rXS5Ruhpc7jD9Jne/GfFCnGeuyB3y+U+P 5o6OsbYDoNv/2kUsQITWtI0sUlM/O77UeF6f4zVmcW/rHJXZvVzzZJDjrx+/TYogEglb4gKBMCIF TAsvU+yMsZxlywjK8rUuvexyuPL33xF1IBSzc0/M3cFnF8Gh5fHbVkjNxOPFLt9M/AAUr/LlDPo8 ujqz6Cv+hax7XsAG0WAtFzob7SxwNQYvZ3ke5R7U/kFLEvCsmG6qJg9NwraZyMg3Rz7ZzLdC+crh E/n0C7GyjshCKMLDzGmtJuj9xr3rdhkeu9TRuiTKXPZUhhSSSpS1oI9o6gpIiWR8B/1biMb0f5BV an7hvjXDnqdO93HrbCVPTsFk4PJgw13k6UEd5etBaqYlfqHOW1890SH58p+LrNyPuGucq59W+4yR F1XJgFdlQw4ruvIrUbNI3ujKTuA0cpC6jjV5sJeRA6pxSgCb07CfF9bB3HgeqsV6D13Nsmdo0RAx /Iad53wAuimJPzOC42MtDb2gwS/Xp7DE1RWNqJffEwnIObui4pKKF1Gydfrnm8oacweSJyCxZhwF CW1k6GS2nsbIh95JQaqhFOGue5inNdebGNDxjqhvrhsACputXPaJCky6BSty9r6xqvRk2zV5W8No LxNm67iXDgx7dgtxGDfx7PKt6R0PYvvtFUB+JvG60kd6VaLnsOXBfSxt16CTMJvd43HSUbs71DLM JEikTTq1VVPJ4eP63ha5zY3cTeH1niAHlMg5e8f0PDu8yzlc8CzGH75PVhvfWPo8kjKLKWcuG5sx HieFY+Wn5+XLmc2kluhIfYR/u0PADmeHpaRkDY5F5M0JGIW5n9ZzEHGEZJFLpqVPi5/mHlT99GDy 54MZ/I1jHtw3dcTZe6l4GNvTT200q1n41wtCBbTCLV2J4CZEuaXQXeoLjnz014ekUpLCraIDxhvh w++7pVloNR7vTMi4rTjp3le/4N76f270H727KpeaQqHcELGnBAA2DbxGio0bB17b9enXwklkvDJd sQ4Va7j48+S/u08ZKglNGtOzmN4XcNj/9vptsu3bam5YZoSL1i/13uGaoVxqyag9FgaTUKLMNyOw /3KFv/TVDZ1ELF1OjC8/jVGl2yiY5p/JIXKCPBJjObgObpw75ITgg3ypUI6MvW8/ADQt4pcBeDpy 3i6rKIKrP9DZytKX8SQw9zxiDujdgN2ueYH4mp9HjHg2GfAxh/ows9DA8tF9Q38CcHA98J+20kr2 cowIfvXWuG+mI74dvW47kJ8+PyM2JrW0gyVBnALMOQqY7XhQTSOlKj1QM+E6ZI2fUOmEJd/l+7ri iR9wc+3ln8gAYqvSSTMKV8jVnDwfirPbag1gFvaxt31+tHC6HLlC5ACOFvmanYuHVxrogZYUZdYN 8TaScW2myxDM+cY8lxpCu28R78Rue2H4U/A/OafERZiIugoF2uk4pGR+9zdGBRFf3ZdMMl8U0FXl EjnSyEe69JuFuC/cZ97zGq6WGcSB32tJFOdgU/usEpkedbukM9JpCHi68IKr5T6Kv2MXA+nZc7OI siLTvCRiTWAYPMHeGjJhFpB39gaoHW7B/VGvSnUYthgIfy1rzXNAkmS2KdR9tbHllZuEYEzKejBg +9hmuSKnbakjtBmlnsvf/W8j5rQjNyF/AMoB2rDH0FumrSems9C/nNeJ9pV7XG3oVjhwX1n5O25e sYzkMadaKX4qSHkXyhZmaTnFz7AYfHmkHV2g9FO/RlXYO2boihDOuIWdyu8k3ErH1e21XIDSCAup U5kyfqF2ngwdGUwXPOxcuXOJc9bedzmyXdaejNfm1uiucWky0k+tYXUUHeXiUSWBqIoWH9429i1W 3pOyqmJY4kgEWgeIiyMnoGvSYTfBpnBfKEG594+eTvWmGbkmdh8m8I49a2MvvMxYqYL+uFscUXW9 DZdv5a4GAtzPzFvHJL/veTijyv7r91foEo0vcAlxbv80eytS+Gdgl8TrTuhYVktqt07RL8Rb+Thg S5A8rvrcGqWatD5aPvLVBsxuEP1KHRFfScuV48dwawG4lCQtLL+zcLKLOjDQ/mIxwBZihlH5+NDQ 8qVg9+purCf+/ZDVca3SPBRPlwG+3pUp+bARKJCJzVLRvrDNAxazO9k5Y9uhMPKvVGGx3wTnGpl9 2+DxmbX7U7kkQfUqf0oYCVSbp8GUr9LIZPxM4UGr3o2ZizEvWNqh9ZyrkbwV1wW/l9ydBtNhZUEG nwzntNWUqDR5S13GePRIinVyO7G/2F3S8gIOW7muP6uaP+quNFVgdLFQ90E7+sDCsVNAbrCIW7VT ffHTWwz8IqIlya4tihU78ciuHdYP1n+6V/VcF9hjcnhjLmWLgqZRsT5kkGp6m8b3V0aoeGIcZp3p qEi8h5Bz1n9ZhgB3QXxoDdX1YghhD03sjvHIB+IsCcm8yquS0cZhyk82xDFPvGcOQKAMuAKyFksK WiQvACUHoB54GiuV7p3Fnz6gQqdzGeUYi59DYCAFLGSnDMYOI1uDhOEiA+/7BoStNehmQoE6SxxH geJDysyGRA6UQAYJDJets7J/YGCL/1cFCyb4QEyfISrvC07WcmauZSaDnpZAx05s3wwHvEiakpOW olz3RxHDL17wqRCjLt/Yd+Lmf3SDofO/Wr/xVXNofZBEvQqfUuKdwB61rtGBrbCHeGBTD4L2l/0E qntgCkIm9foJ2XDbj0sm5VcbQqZaprT+uTOZVTVzSua1PBnPpZekKdQlt16Z/NXHwCzRwJWXv5Fr 1SCOF0dyqBWBSqZKGlpBoQatiCMYKLK3OZ+OKcc76Vm72nAxId4ramWtl+kRBpZqoDFaGtApeB/H /ohMV+tbFycYYZ/I2E8gN6+dCKOh+xEooRAx/bUD30Mb1ztoLURitdgpbuYKVa38UGO0zr94NYbZ YUJdpD8kSewTiFi/g/KrOSuPGAjMce5+lUbftJGXCaSyk9/tQmaw60FUXmXtnEH8uHkbFy++rbZS T9oBGsHRrSdDrKzDtrQ1HvaC63YsjupHQpXReQiJcN4Qjilzqi9hoJBwO2j26YQwEUJ69WstuChi Hx2m/TD1zEZ/2Ubdh/wRTdnTqRG8o15p0PaSWfji8NgcH4tlTOAcas5Io1LQl3IwCSuqaTOsPhF2 f7Ekuyx+6OpbwXrc4Et67N/LmAdhK3444iCNlXB3Bw2NyhaNLclF+lTmnK4sErfy/px2w5w2468S sL4ngGdinaU5AaztmAYp/tksH79Jn+VvXC9v3p9YF1bmHwXZDkYfH0AAR2EgcE/AuaB3NR6A5JNv poXlA/57ILT0PSg4c4mtFOz8EDVrGi7T8hHW8JPv2/alA/tDVB89qDpwmNY/2uJhewU7Lo1bB4tK M10MziTj8XUyPsBwTPRl9NU3TUXJEME4Y96mJ4EYLkQg7iFmfbUKfsYXlckJNiTwG2tna5C1Z5zl nqCTd+nR8bO+CE/oYS9sJIyBuAIdf7oc8JcPs67yY/KeFq8PJ2VhYSERomQ3Klz0Zw9TNE6dlCJo o6UOEfF+sPOPn/N0XUbg8oNUgxo3ZXW3XBpt/KvcJY/+V7xvSgmwXu/o2FPxHQPF5P/tgOEbBWDq GtTzQRVBhYyuNtK++CEyu3fkByXpybPRU8GgYIcPjKwL4i/MYXnC3iB7RI8HicGPURxFQ3Bj+g+Y PIg7jXTNuXheyE2zror2uukSwyJ50mh65DOKnIz14xuNm8BWS2G3OoI9XHsOnt70uSS6LZGlcgOj 2xCzlY1P/SWyw1YiW00qkhQGGL64W07h8uZhcjr80ueYcn/Oe6E1GOf5B4BifXn6eAcYjJwD5S+p rV0TPCvEJmHndvY1b6U01uYfRjpQJIYQp7XdzIv1mqwJsKKbWNo/ODthUydpgDVvZ23USmatHz/D qfFWCJxyDOJyywpDDAGAMA8R2n3O/PbGY5UPE6ELn4FiO2DZB5aneDTj0ctNUIe+R1AX7mxboKvl h2Cfes+TZ9xpaIsajqDoVI5K5KEHfW4TFVI1Tgl4eG90nRdZsuuYLgXJgWJk1i2SOHOmV1L3Hm4h hxKR+s1DLr04mDCs5HygxoW5u9V/74Kl2dc5AD3H8oBEvNODr/SeW0WfYutBEQhs/UzUz4I3bqwf rUSOnSYFWOoNMnIsea/v/Gs7cy2s/nctSATmjMqQinJXkTCNeGr6LSOS02gWPshY6nj4DCgUpi4t CqNYO886/NAborWZLHbIK683CyAM6qi6nx6reWr3+4b2Q09MYvf/NERMW8BKzmwFjzoq4OHGKa1p 8CKTGaoxQtC2bWy6wK5ErTXYw4GC3QCC1n9AGWLLrQTimyK0mCGL4imK7zxg0zyTuWhfT2qsID3w bNxtprItIPfSMhncdq0a8pRrif24KjBQqdbedqu9lCD8RnlyWV8ifoQCXNJ6NI+yg8IuvWvhcjr1 PTTRDusVj/D82ODKpI3Q636tu0pnTahu7gpAnTl07VlgrJ54bRVEdc+T984ZsxyKO7QU+1jdAAz5 vYu37mlKVR4hshSPB/9vmbUDcIlvgta7evQqBeGxVXrU4dliRFOCnSOFHiVvJdbEJZSxl6b0tpkA ZB0O/rSdEuOvZR105YFZGXullBwkg8lq0cmACQo5CAnXadt+TJdgNBtj25F0/TT2bcg2FsqoZuoE FQYLFGZMF0kseMmcYlxqGaGuujPPjgEF9Cb+zm6hcUM4pWfhU8/uL8eA1nK7XAvPOfILUZpa7Rb8 G2AnkNhlzJGsnU6VnYZabuMtKVdKOvfClLSteDWwIxEG9ECKAfdpZilPJOdHtH0dqNaZLH8VYZcX p9g4JTe57QjQcf3TzcDFbxNAbZjGiDw+YJObWzUUFbjF0YlkDrOQOU91gHy4cGSHOt7GRTE1Tlyb LKuf4ekPHIW7XDedaxif6O5wIkIC9I+9aOOQ+mQ57o5BW4ugQ5bru6YYSRQZiEvQgoQSsBaVcIdQ /SOX8JVwOYs5I4CFFTQIZ4Ifs3oSsE+VKdEHAJU3OAmm1sG2MvLyk/871OB0dlHFzC1X+vM/lQy5 DicK/5j3uCfXu6XuOKCUsJE+2wSYBO3gnxJ6Fg5l+V4SmVatBJjSzXq9U0w6d5u5v4V9U8ivCBpj 21NvA1zng2X1WiU82r7fLps8hMX1ZUoXFH9ar9gaNRuCe2QGBCRnE4TnhNgsePJw80+eD5+F2Xgt bp8By2s/tq3yiJEfJQhCvTWlrseyK595joNDcWrkn7pWMBwLL/6rDqb/fcDs9RJMxhPeCoit6MAf BTZ2E3zpFtBAtt+qGv7N8oC0NUp4sx+aTXjS54evDBNAeI1yko31Cd0Zu5lFg+tD95m5ZsFHgbkJ hBJf0jD7hAhMrdTHigvI4TCxLuKAGQIpZRYZaswY3VlniMbl03OzVQR6WDR980D8ioqiv3Sl1RZK x13fUf3AJoJCPFaNTDNKfNmQSz0yTwfF50Rje3EK9xdILNvnVt3LgBKgnUPc1oUUL797wGe22d0t ur9KVBmTA/eae/uOwi9HQuq+xatF66ZJzXqzMpAuA0ETwk2YX8nXMDe2g1TNiBk/cj8yoxOlSYok Yr65kiy2eyDltBdI7aN64yAmsXBl13zbNrB9NHIGA42FIaUU2yP+lB/d1AJnXQGPT18MflMoa+pg E6Qk3nSN6AeMTS9HVs0QPJTQqmfgNZhoKVbAEBAa8fqyS3j+4cv6leyUh7VkozWiV5pQtKWM8aTo lWEgP+i6Vl90yUzl12c9WShtjksIAbGWh/Ntt5bAWxcQmaet/2e2ZcaMG1z7y3KRucv73603/B9+ mnkhLDA7p57PO4JGkPaX47x+ROuxXPwNYuh47Bsp1uoGOaURfL+2CNs5xcqefQgTMBAA52ZMd+8q DpKhBA6o2wWkNd7t7MrSQh2bErmDRIA4RQ6jj5LW3rsZtfJGKVKGH3pX747VGya+FT6G/22bPt0o eit99QrlX/W5RdMK7RFwAi3OdJibrrEM5cXoRlbgd4AovDEIVe9DlUj9OyI6/HAV5LbMlKAth8lW 2K4UC/A6cHYl+xz6bzkT4qi9Zhc3pfffKeSs1ZINkz/RTVoh09c1ethilOHwnFTRxGIHk6QZJyIK tGCLXiJ60jggoEjJ5YOMo443rWuMfOZr+/IoEzmeT9Gii554m5CVXk1xNPG9FDtcw1j9SeUqg9Gw cqvuxL048rmoIggKYSZqhVJ6rnEAdWiHy7r+mpK6tH4CoU2eBNWiGsfbDd4YpqRqL5OaJwjTa534 2jBs7On2/BXQxB6BsiaoMxuuGjzD7NfKcxe74epfycRDwFhgJG0yJYDNTeterh0maJMwEbKH1FpE 9EvF9ZFJ/WK+HANhJTCTbJcJc5IqS6SXh9o22TPO0qgYo9WH5Po6gw7WT5GAyWfuqXllio3Yw6Jz f+zAh0qeB2OItq1GjdAmY9eSNFuVcHiUW10kE5JFpNLHswaFBnF+uWO3D1FNu6WOd4kKEXarjpUz +GTgdU/wJsqtBF4rCm0C6M1AHC3Ojs+4hS/9WsRjZcFfGPeQ2z8WV5YtZfH1XdTZiAXUSPW9zKb9 i0AnTX1DV3kYE6o5zaDY3UTAx3lajtq0y87POwFILSwh8sTbaSDIQOshgz69GfmTFsMlpvgHbvVj l4i+oaH+RPYxABd1pHd6BDUc/UiVD5Eip0jh0h6P/hSY1YE4aZOrrSi3vyVg5KSa8TjB3Cfhoiee 6+8zvNIBpRPpvDXzwTEOfKzFbnX5U27BX8Fs35eBM+9At8qkTqa4VH8UUhzNrpfDCUHtUqHzB4mo p4UE7eYx/DJysMyNpE3AtDz+JdZUgEYzOAlIpHxtUN660u34H5MMPg1/c95gExFlMySFbVRS8uQN bMrj50ccw9SPcL/MWyF2NcofusHlBhEC3Qk27dTInVO5OuVmcDMwC6nKFj09yO5KkZHGUOD3K3YW jYfFVNO2DWVSNALGteZNMBn4OTR+nIVW89/tC4ImBw5+nnaqoAn/baOO6IMohLKJer6/JrmBtbsS GmMqZUanGtzOL+xh2a+8v+H0iEJhEfAaYM3yKFEXKGYk/OFYNd4ozDzqdTgtVmtA+vg2/ij2/G92 9lE9RpvWsm1kQv+mgIF/C0aaQgoVCVAzAC1PWpV1/zdhsHyM+WROywHvzv/iCJKilcf/9aPQ7/QQ XNVF0hbWo90u8NFNPRyOS2kS3TnMasrhzHdNycyqfBEDeed+Ii4CR2KWayQNVRizmzRpE7r5uICG h69M2TZMT3al4Qs7aYHmSTzLpyVbZhUnEUsFWbpfIUHBXp3ap2hOw0VbTeQjiJ8QODSzR5crmAni kYnOqqJvzTskiSk1Z1g8rG5O2XnLJhbvoGDn6iFBRJxprtzgSc2daNlazeiN6GULM4iWcVkiad/7 t7V30KwpXp9DUASsURi4niSfKgbqjnWfPH9CRT492VDbZbX8BhuwvOOWgUoYpx1RXxqX0zCljMZh r5Q12N49U8jS3QFnabWZQJVL54W5A2g1XNwuR5455uCZaT/IGmeIAB3Yx9bJlyBGFhnC3ATUVLcX 6a/y1q8MSWqraBRI/mLSBQppPmrK6ty021hXjcTwsG2rkGcsFQQ8+XfZTQI4YwqwSYBjLQLXsyIH QaI9Z3qWX5hZtn1A6lW6RklyFYzfgh20myUO6RVP/Yrfc5PC3RGwGeZsLGwdsKnIpQBHztiClVNh ELahH4pSr7erl4H4jtM0CdAWXMQU5NBkKz5RfIVQbh1KVD99Msnd4WihxU7mxxBp82aReuo3/cCs egrdTiyH5znirV957nrqWvj3bsEdet2fgaUNu35Nimjwcbts2kWEkFA+dnE4ihEvsvItpDJuqCyK GPZ38yCDFsjX+KXD3YQYapfFDD5+ex01qK7wBVK5phGuV+pybWU5GZ8GR8SC8xm76e/La2CyOl8d bTpdy4U+Fs09yG6T2PMJkXkjtdU4Wl7UOugufSW2/1IozlFPVq7987FORxjJa+v8WhIoxzGdgE/v c8bLDrqhQrmmJC/rV9NvMGuQr3QbgfVZUrkHg11AGeNNHF79eokTtggwJjORngjmPlq+2ne7dSSO 31BSXJ07hznTJLbCAafwC47eEVTCXoVpI2ZheyXQdc3qDpE11PZ/ymYg8lDCXCPtujVXa72nR54o 1BiIJ7y/el5zgOfvz8wSw4xW+9G5UfdNv9MDhStH0EVIKIRYiabw1scaMnVhiwkf2Qhci14N/N0N QVEyO8ss2Rxfu6mHvGLGnJilzbfIOjgoGpKSJRARSeFUB9HXCzOS9s514wgiDy9O1hA6VBScI+nf ibNMcNB7LEU/mFL5i4Vy59WNqyNruvDEQWv+jeC4cC14/mPaHmDg0XAN5hgJTKUlCpB43IwOSkKr 6MlUbGCDpV5j0LYqZpG8u/hR+zJ5c+T5eoZf+8HfS2T6iqM4jXW/+zWXWnP0bMfPLEJtQbpAO0oI sH96G5wpBti/lUK5O1bV6aBztmmSoyXOetJE9j7usOtJzNH/tCFR3tUH9hKtOL/e4OsLcDW7rtK8 PGXyekg3UGRgqNTCx6mvSoXOvUbQAIwfmRgPRG1/S6ysk1KtkMyj5Tj8UjDWazC5JoY9qwT8jiYc Rl8wh4ftGbWCVY2iWJPRgubx914UkD2Hp4jQ2sa4YBZmbCjce5FFpGUREdpXZx+CqxN56JltZdAk q+lafDYPbKmXvXeVVhlnpw7Q6lifLCGRuYf1FURKJ7gmWke5/Mhi956VFWhbUQEU4v9By0tP3x1F iWPKnL7HwDZqIjP5GaMSCZnVsNpdykp6vbzhp0EYP/vpIzYvAxPgAmkCTg9m7gyhTcl8GZVQfupq S2IiF/nKbcd3xMFNTmeyHjV25ThB2ShloZFXSLgrCzDo4lM7g6ftD6kZwryHMg8fdDZvDTCJXzZC 1x4mZToAmH80bOo3frgpALlKr24UHFFnzrwQwW/9AM+t0/K5D8vyDEXYB2i8N5EcqfKbJA9iVKtg qyp4s84QDaX+/cNoLaDbdyU4Md1V0s2JoPl5W/dXDdYmnvQVzsDFIfaynZA/VDBxiVVgaYSeVP8v RTM2al+9GwU73mOE0E7TbBNk1Otuf6nHCQxaraUiqW76TLlQLFbqpTCKgE0Jf/nBSGPnGY7VLnjX CvC/hKka0nzhHAw8XDoqdHshrljoUHQgU1fN9MzmbYOjdx0qhs2REh3a2goWdHZx1zkm37CznsyY 17Fk2BYvkbNnxXN4gk33MJ5SS7v0XXM98xUOh3H0570G3k873mkOWMYBezlRV+q3SarBGnTpkqz4 9yvSy+PHJnyhO9FQdygrVHINObOQZXGz0UKIBdZOFXIdEOTntTdEY/XjWo9jpnnpp7ncbI9h7t4K ryOMq2I5i+ZA83HDiWFgUpIjrF0prYrto77Z+A84Xl0fnCs3CKf6YPQ/pFrxvjvUe1jPqfi0Nszn BQbfs8p+2pQ39YRNW/VDpPhs8YdHqcSJW8XzIL6DUjHh4PshbsANqYnfoxtOyhxtYf2d6jxdcADG C4rPlP1nmcXiAAPyjkbUZEiQ/Qd0xGMHmkXX2asECMr4W8wxxImg139/RH+617GVvVH+NXDGG763 1wtcOWgxqR4H0/Bke14nl5uiVrP3nwGpgBT/hjeLgCFCPjmBCbM8nAqW7UhvZqOA9srfZbRo6ZXq ipAm5FpW1qXQ2wJNUs9QOw0uDZaRKg2eh2Qd8U5X389xNpqf3ua1a1o5S7rmb5oz0aCeFtZevP59 y/Z9AudUHMhwrKhO6bTpDZWybUesUGQG4OXDLks7d8YPeABUTj0Y47h/2LMdSscZq36cwNo/tfys 6MRoieOokgin65IizhLM2Fz7Uq5MSXtXbhFB7YgMFhM0X7YJDkERiXgaBht/qHpT5CtkN3eSvRri vz9v5LA1Zn+qWhVbde5uaJvyGbBoHMKTjMtryRXw/gzc2Q23AVryBM26qUHFki4z1rkC8Uljl3J1 XYGVopAbXUe/AaOt12Sky+i9t/3a2gqxazGBR+LqnzwKa7MekNDxdO3H5YT7/Fkikczflqda/E2/ JTRtGeK7GPv++Qrip+M6qCXN5vt/Oc7YPSXIaQmo86SPmkUFH2SadxEfbZWNFZmQ99mu3rTtuqtN vngsLQgn8UI2Ht3T45ZBr4d91Acz4mqWOFbBraVxyHLk5UyVu2aiK3I8qjoeiEHoeztZwMr3c3pS 6R74BiL3Hwp7iqeKBqp5ONsF6SW9LyxgtR9TXfJ9l+hC9Wx8VLO3JC7eVuU4iG0uafG6KsrzFd4c WCZT4VPugX7TfiLL2iVynMS7QF+tBHkHN56thZ5Bgea5ehzwGou0FOiR76lfR+qvR6YRl36Z+bGx 1AZ/ecOtKmNX1Pk9H2QaWIhkGfxvfgElIddN9yyBV/VgKJO7NZmCalRdrKcymSG7KOY5HaVYpEgC ZM3ttimmmqXvhbPAqBTJZPccsJ53TUs8e6FTKPiS6RRnhbLzOLHDzb4UC8Xsvrxj8cprIUFtYbJa 92f2FLkoTgMG7G9ufWdFACmmX9gS5bU3I7kFZ0KlLQdGrp5NNRI11mtsf3/+9m5mcEK3Cnno6FvX 9sfC3jO49AZaWYyAeBUHfcUpVh6UDBPtYWhxONXPxOWjqgTmL0V9YxSIj2dABMlBC3sQ4rCCBWvI NdA7urBXmAjVawo6+nAMxrgfouiP8+GBuOzfG2yPIQAQZ1KFhMWp9rTk5vQLWR+V1d6tSU7HO41a AF+t0qbp5ddZ4bEcBldShAn2XaUNeFgQxx+XBuConJ1q9zoMECwgTd4OErKxNReLdClzF3Q36LId 4uSPKY9d6xLieoGp8U52bt3cxNvEEHiumF1UhvsHeimrJCfdsieyUzt/SlUeSI52eJEaSRz2HGei deu1ITrPG44DsZXlDkD5oHUZvIUHbtNUhXNny5Ex6GJgoQZoYd5ZPUx02ZnOe5SvRXsRvcTva1zU oIJNaJP9uqALZJMO3wDhhk1vFDv/5lDLxC7RX+rR/WYqIcqgCB4VXTPs6LV9MN9cj/iNUWmMaN5T IDiUX9PvcQ9+o8XHX83xy89PcHsl69v0zy63N/MebP2IdIZDOZrlJcJ02sxHk7u4OAeRMBSEFL5P 7sXuySbrt/+8AKwX9kIHGt4xpvmHa9L9XQGLTcd+Wm+l9ZUTWFMnjfEgnHbCAMD+ss/zRzV1Gtie n6XmbKhWLIGaoIGqoReNXEnG1zr6BchK8J3RdRLH1epExOBJMVb7pFwfGr3VmX4Sas0bTragp7Kt mLfD8zdWvCPB7PgXo5Ir6tYVpkgqiqI39xpw+8vCcZy2Z9N6tLTMDDoUepO4wTLuw1W8tlHLQAP4 CUhaFEF52l1sb/0UMCm7PyjCL+Ifd5KEAbdooWrckFs6YrOBAN7lIvt2y3o8nXNQ2cx7JyQZfg19 u/oOV0rIDvtAQwBiQC6hxBlqn7sK1ViYJR3l+oqSa5wqbuhUovrUOqPkDMLZkKOVhiRpvia7sHPv /PamgZf2sC8pG3fOj8FR8Qjut9AFWRD4aV74OtsoUlzg9KJXnBxkqjH+oZftHftglTeftUsH0o6A eo3kXcnDinpxKOnPSDjfTfmU6SNIv/UgnwrN2VLjATCDRphxt1hoykGCeDOqJ1qJp55QR3CJAbJN WIPcVVXvuhek2Acu59n61prEOHlywdTQlmfEaoPQLTGl3Z7i20ImOV3PoJRAM5P7Fzg9r6vhZyC+ KkaB80O+ODZH3ttOKfZ6Y0j0+WKBnXiHXpWnPBoaPioTKRG5soHAYE0vkFaxugmB6YhPyaKfDPNn qQOI85nrLP+zxzA26o8S7RLaZ9vcQwt6XltxKGdBBEYkhFwYlFP71Hxp53hHzBaaJhNT7rxoc+iJ 7QaBhG4DTaVlu/7GO5NgkTr94MnmrOfnc1MJathdlrOeLJKsM58BdfxGRLF1Q6bo5hYQaclrg2YB gVkhnxX0Brr/RSvKDuN0RtpSC7NwHLn0mo48NVAVtXvNvFIzba7IVNDopL12eqPVQh1Lm1cs1qv/ 62D75BxkBm7naRyoRZ6AIyQxRwcBe3VE0CtP6bh0nZR+Afmeln9/k4dg8RSvjCR8HujxLQ5hh6wE gE/QCMFIEYlTaAeB77lILUvSqP6p03UEV38nBZFyU85OZKor3l/6AKCn3rm6Kyp8Bq49+EnVWQdj zw1YjrujxnqoDMljAUvm2Zr2ToQSBilAnRejRw1t+GMTqv30bhvPMi9z8BEJ35WSBzpUWfljMBgl Fa+O56ZybaW2n6sKtRpwusu4fz2/ml4Nj78LFULNF6QzOb+enfD/ys+j6mUvUVgOePKxqTL/Nero dN2LeQwv4FzhjR2j+DMkUWC1dAGxq7QjR0lZNnHzUSawZFikJTOYVWS1LbhV+l2uWqC+1HzlYVvd /RrWEuMAFchKAADgdb7eyhtaNx0cNB4jwz+7B7Z1u/R7Q+xnifC/YY3v0uUcXaqIvHKxnSR70vOx +96M9auOR7OXL9GOC9eeCAY7D1mWnt1p5AUsHSla9Tdh0hzwBJdoj1+FCotYKYM79DTDcWKqeVGF dPT+yIPYcNmxBTyZ5rujd8jbv3uma8cgYfS9FxgQx01g4m/JvTrG9fAaNBJw3ZbjKQJHwDOziv1Z UYzWpC4pAOr1M/BdYhjetKdGezpijuJdv6LSz+nCK9U6DK0CJhhDHv2HzSw+Ctz10VnEm5A4Mlcp 6Zuwgw8wXh5hZ7Dou64TiKWqSq+guzM+QbzG+LXv4eplPzScZHZHx9WIDM33WGqirxQqqDuTSvDN 3JQm0s8pjRASiHHAWoffdNkhhdy1WGBvxERAbtD/38rp3YsVOq03on+7vF9EbAyN2HmXsjKS+0LN pdC/Q8RlME6X3WjMAte3xmBOSG9N9IC3bzOWnwbMIXcghuaNkVk7+yeNoHh54MT3a57mejKAgctY c/aP45ZbSLGvZ2/LrRLPuzk00qgSkklZYF1Eb7yM3xobSeLNtkM0wWEFR/4liW5Dl4lSMS/CBTvV 50g2cZDjdfYYLZNHno1j8Q7nZItoYfyDUUxUmn7v9Ie8M2fdDwEmXO1vpY3WH/PyVohKrQaS9J/f 0JFpyh4711CoeT8k414J1H+hqF+3i3oBnx0dHymUfjpdRYPrlamvSQglqzhIz3FDfs8B3LNCeLbq mO2YGskgzy6FiGlBhggQfMzRvXP7pkubuiISV6b9fkyXb+6YJJFgsJG5XjveFMes1+JDJ4Xuzd0o 0J0PtuSlKQi+uOe3kwDb7O/QnSAMC/WXu61klM2shUInUYpZkonFcpqHZwHtG5Maqmt2kQUHb3VF uvR16842jfQ9CWeYeLhOlSG3BTcQzCYybuAmc0UFD5NWRVWVmvt0KdTrGCoWIlOKSvcaBebXxcUQ 8gZfi7aj2i9ToVYnmVamFZyLcY0O5xpy9QIvKm9i+QPvbahxQdHBSMs6dI1YdnCYlUoy3CTbI7WS C6im6KLaTRpJUSAHZI3A5gKZDDY2WTTyqvyoXLpqpurhqbmMcNRuorXQsHhmOWG80+KPqA7dlahb ImRy60XatD4ba6GXKRGHmMzTtRKBOdQ2NjpG+bPFmZj7+b2OAzySoDIix5hyxUaKmrlJz2Ut+jbR wixE4m6X9gk70gQ+VM+Nuff9QDcQGRZPYOkEwi6Gbtivb7GwHZ8nIcBmhx63cDI17olvBPKoEux9 xHTIOPpNkuY5z4VB7mnMg3eiJSUZ7DLJFVkMdwxtTP1k7Ff04OBQLNndsScNYK84grB57/8Rit3d dO7drtmP5sBzbV4fapAlo4040mGzPMFE5nkzxBi9KGW2wgUqL767QRBbGXQhRH/fzf6WTQU99TB3 RVuMxYk/I1YpFDD+QkNJblUnY4gre4DOnhZXbbHkwGXaMC4dF8s+P098WBRGWfrZ5wFR++9JL3Dv JMMTt6wbEmrf2YW1wjFfoQ5SV1TiajAWfTanIy4QmSD6VK3lcbZnQfMjiLsysVRpimKE7NxUrZGk 7T7HePvnjmgd6BdiyMkA+yWyXoT35F9PH6J1cVZohYf+MhWyIsPA+ulgCMP5F9joX+VAhFg5UPah joMY+PKWG4NFq5n6nxhnxQNNOfeh5BXoGjwrRSj8kGkLRzePEL7/mQgrPQZk/pLfVp2/kgZtFl8Y dTxWYXYnWRMvUolSGMNCnyu8PP0sAciUK3E6ya10/ayTrUBh920vkoXqKwV4UOsrUsm6zj6CXZ4g V5VCkoDOLpLtu0wpo2w8mOtKTfMM1RB/BxZRPH6sL1JDtr/OJI6hcACXNsJgavpYOxdpE//o4xLL 8HYoUJnGHi9sx/aTOUyI/k58IxzJgyHdSx3biVhZchYZbXjFYFd29XZnzpntFztsijySnSZ6emwY 7i16E09QHspMtnqfoUBvrJxeDPGiOxjxbJ6WUmtWoN/+2nncqb9kK7CjsuUSld4gU0RJQKj9hx7V KAkaRdWdZaq6b8cydVtVI7Y8ZjLiGW3X3kwc+GU1HDyYppzlEtsux9u+WKnt/CO8sl5KdcogZgAf vl5wDevaI007HC/IhrU4hq6goWtjO8Em+QQ2aO0YjbvTdUYqaciOhtQbY2+mpNEa31+dfatVJE+2 cI9fbpy7bQR+Z94PhfTIye+r/l0Aj8iZa6LhEYzUco0+coTA0ZqpjX12Boqxhxmg7W3s19Imjmte A9R5mTKCghLg0O+1IHtjgrY0eBhA2H1cxqfC4tHobf4rZzOERQfCWh5UE/Gw3VO9ks33DdfW2nh8 alKcMq/7EeqnrcqwTfbuAlDXXOSRlqNkfmiwycTJSUPHrSBZcM0TaKf4vOHVZk1KnAaL+jEoIcIa YGXeWbPxQOVdRB12fyq3dp7jItN7jmaaY0y37Ofu42//Fp7wcExxZKjsxUwljjvZrJdtXiRRkwdk qULNtyoNJYzowTaE8GwEEvNvs17tCVoUBct82PaFtiapc2jQaGzruAeh1FdnSEAzSoYnZuIbUr5e uRNBAFa+LQ8vt7YCCbT/56F1ca6XUZVJGa/u3+lZfpgAgECMwd+QZ8p9mDGv/3KKLY2uqJro9VP3 VvYLTuz//LLhqdK4oD+ZCktYvXejgNbJODe82wbnAqyZjalUjhSIht8I1L9KSh6UxEOIymgGPK8C Ca8z+wCdI/PeZ9m+Q08IxNc7RC6v85J5VJI+FgfJvwF5OYU5zhjUSt/aWGLWF1+tDO4iToZBsNFg VXQqZeaEd0TqXGMBfL5SjVd5AAamDR84W2fdz/9mhzii1y8JxMn5dkI8Ekm8zE6cVx0tPxo5jRKi AlOOgAMGBYAqvBg4NMPGEtDZGvKcp8XSgZ9WM9N1Ft+w8Asg97/a1+Lzq+FHUBNFUtIQkCPHgQAE RSFU7w/tDwRuPw7dXUEIZRkVTvkiAxTfanI/CmK+rdczBROCUOMs5JAGNUgDC2J10Wo0CVLFyCvv 1DhzicpbtAdjAF3QpoUSW6ZC/ykzOkYcmQzVNvXJsJaxRX0K4DuxfUBziJTiD9sIDAUO0jXhQ1an Wkzq9R5gwUXy4aMHDQ7/az3uKNST4niZifCH1uBSO2kCKTT9eJDSHRvfGXpDYd/0ucnxlgpcfz5O t6d0irgRJybIHsWMfVq+Kk1p2kQmjr7DfSRXmKrOAAeGBzfe4cx/FVyk3tyO9w/q9ixz9uxbMEOa sA5EY/dqGvK14649V1d7l6lXqeFexTwHBv7JMtN1brpS85uFFs11PA87i3zlfFjGsXYn490QlrgS 23Rtr7k3T/JOgaF5NF5k9z+Otr1OBaH+PwXd0zbWYDMHTNkvcd18xEdcYLSl3X7dv/w6zwNBYyqh 4XMUcQjGXMLAVmaBgm8InQFGtPxPuudIe+M0jRubEJqVdtatxaluThuiTEXbgRu9RUY2J5bUehKQ Jzxdk/ByX6d+iCX4FGh9tn6mVe1NI4s+t1IIsyVP8OhgQ9gAwUt7bGDh4T1owS9tn49for3LVjuR UbpzqvRCMgdW9Fiuk04VrLwaBOJsqtOnkZs0FMFfiP23ppVetpFPKJ85do8sDHzXPVROsaR42P9Y 2kmo5DYhbDT6I12LZYTgDuLLKqKahdK40EDa5qL8ZjyarQ/KwO7DMcuk374W6+VGDPXU5ihsY7Pr rbv/0hqkTG42cGxZUnxoOmCZ3YL/50psuLgZbckqvCZ9DgwPvyYkp8Xrm1T5C9KPHPeRaAb2wqls G9vbHZuIdPp9ZSE3he4sqYqkxHX9QcAn0T1cv98sVRrmKS/aRRqHwjWiDloUc60ooWX6w1mXuBO9 fzuqa3xj8Ts3LSjvMmXHFYqH3xWBX78XBd0BV0yJUV53AZGrNQO41OxAMIGShtCVQvcgx+D0LVON KegSncaznRl2P70Nk32J+Oyvdnko0yRocNc5Dnr+kb5B+jqmr1Gt3mjnRcao4zBlvpluyPU7SBVZ uDrcwCRDJKeF+AZ2lyD8u/2MkGdDlEWdogEJvFiQCWg1lxjRMWyWvcL3o+aHQyrNM0+ITasl+sVI ub5OMyOPwhmCOjNFCaAilZ8h6/pfTkfdrstZl0BLobDxy5Jjla8m+MPfdn0sASCLsY+sJWOMCng0 kW0nGHGcWEAyNe8CNbu3wNpIM/V2bTzcRIKU874O2gmcONw2o9SCTR2eZGeDveqef0pXmo9BYY6B dgYbCe3EziYUUFbuEYJiHhAOjXZq34kYYLj7QS8qUmFMKpUIkpGtNZJweMqd/BLTqPOAW65dmzgr K+uLvgqQSq1wnd0wTAm15CZUXQlPxZaU90kWRWL3LAdMPjPASQMde/wZPLwKycfkyh8GkJAQpjcz IBnnjqyCvNwXv5aWKzCow7Sv1QX9y6pxHoPZ1g6zdQIp7cE6hQRDkp922l+SnOvCK1HHgIxJujZo wH9eaiqc1ZLMMVf2qadpo0DHhCi7EjujMUMx1n+XPj/Dp/Z42yQCwa6v5lABYoDy/6KZ0gtG0DWB 7KMUfggJmMPXp7IFqmk3vyaD6oaZHcT+RCMY31Skq3MKfFelgYphaw73cc1nS4BOooRASxKo2FbZ FNnMW446UoLR22oviGh54pyF1UoA/aKvs/BobVRthaw+J/+CtToC5SOKCX1jN3O68rpJ/QnL5eYx LWH7+Md7zvr9VJ9YKQ/ccSEDThpWRri3bTKRImIA39TN3VQiRjNL+82+FyHjqE4a53gjmaebNx0q u7022Q8/y5lv+zfwU7vmH6DWR42LP6xn2gVPYYRaHU2qEEZTVKa+zcm9eJZs1lxj7sXjDv8s0nrD 5hFUPj3WPcQOUASEE6ieBGQXM3qDm+/tWxFFjY34IXr5bk6hwtDGGuKyws3kw9/Sswc8XqoeJyej FWmYHcc/QFAqrawSDKfj5FnnmaDJk+vV+0zzL1cVj3pPtP1rE5bkmF9EZKFgWggvmeHtjI2YkQ5b GEvHpEAyGLDMAHvS9fUaDRHktfyiG0iYHuaW63Xs8sKCMMA0scgP+F9Q0lP5GQkEHMFhkKsbT9Hz T67uyN1UPKE0xFKhlLY17wjJrh5iuD1x9Ns/peZywfnQ6F1c9gqv45pB9aULYL+RTcCyL5fCK6lY +UO+kr7xU3rzQdHrcD7wgYXHaCv0utXNFnhNbEte3654AQpcHYTOFpIOX7GnZRYoKpUoV3k+TQNl 4ru/lgTTJupuF36FaUtg1EjMU8g6rByxZO+ByULtubqclgvM5b20CujWo2t1Cps+75x07+dHsCzJ 2PFL8BRDwBGuHmbVBknCQ/SOeRfe6KvlmzgUk9UmKHZpi62CKgafF1w8p2AH8FJRU5I25jkd47zK KYWUzwEXh1D5r+eYAocbqayHTOlfzWL0KucAP80ZchSelyCF/2I+wwTl3nXvB9YUK2v/mNuVCe0i kTaZ/QwYIzLSCttt7LP9ujCaQfeFcYpfiH90bry02pbFF02U4UcwWTLSS+E7alUdU1aTOxcW6IeW R+sM9IQgB1qwbo7/1IiyTasyfxnKvXckMVKVJJaZ3M47wsm4dLcl1lNSL7d082YLxpsyfNTTHXVS pDlhybaJAG0t5c0rxfVkBgTV/MGKx1QeBlbVWsM/lKaYj+FiNLtFIh4Bc1IAMp25LSfST73jusep O9qUVOQRQebI3WhCY4tCqZkpse9N5HC1wGDkLJy8isnsZCpKMiIywvYPHwPQXw2xgz4b5f5HFLrs xFV+bnX5YJqW/MXwKpfLX4KTgPDAp8YWXMfkktleXB2QfSGqFaEznA4roaCu0q4HImNY+4rU4kTC ztnSY11wZqZfcVJ+3mqAxb7u8O0imk3p8D+AKIiJkpirvJmjGxcz48NZ6mor7KdVW8OsB/JTPQsE 4bEWlzLNggri5wU+SVklTdFNttpOsNsaHp4ed28mDTPHeNPVC+OrLbi9UyE8M+Oojhi9W90aKO/p GfVDjSColHcLApTDQJxEON21Z1LrLTfndHOSHDVV08XFwFssagHuoXg0UyJXSsG7W1Krd04hPkKq +NcGEmiy9u6UGTW9RSCPvwMipcFx1yXSY+Th/gWX+anvN45UBhG1ZyF+WIT3oarWB3mxFx8mcEgT DoCuR2HwtlcAMjrVXd6WsmPK8zOpHsPzI8BO9cWzS3KRaYMGiKpT9ZU63X8SPigi/8Dpu8ArnRXj MWJyy/xGyQPtBjW6EnT9SU2zip0xuSFw6xCT3PbeaWtJu6TJGcttrGEw1BLRsKm8+QJWoFXd6NOa rd3CvZk2R8j4ldKDJr7/G6zsxNoL93tn//Eo7QUgtdVGqpNvW2WOKDwjIRw4D0xhwe5iFLR7OYJS /Lr2fa2C2vN6k7C+Xqch8Gtk2fpjNCj1inDAewXI0Zoh0HEXMHaBohegXVSKsc+eWFCr3vQFw3jh JC3DLuD/IJwdwYpBj2yD59P5PJTuGJD0CL71n/MC+rJbeKWg8CymwhH2m/ovs+25QNZiXBsiN4/0 6R05Ks4XXlawlS+P0AsOv8m+B3/91ZtP5qeubkUD3+/2YhXKXJrTtGq0d+LCW/R2E3jGd5KWhElR Kp5tE3JeDmBWK8irP1Jrp+SpDE05WuCWKOfjndX459CU1PmVENN6cimUZ24Q8R6RJLO0Lh4CAiSR 5nuybOl3rtyUxEcSEhDDYxALgQ4g7ehsyO51CrczPApm5xEqj2Rtdr4l8lJxtNE8s+koC+iOvYj8 ygWNUEtKZ3Mk+dKDSV9JlbmVdYbInBSszNZrJKWq5UzT95X0rZXVRvRes1f/Wn8paou7X06W+sTL nwb0TltpUEQpsX+qc9sDHogAN3MhRD/jJZxusedFBMPCx9YqZdlLNYJohjIErwXb1jbgvUhi3tP9 rUhtsGibkqfUDqpivBADpjnSQ0VLj6sgXXs9Th1wvzyJlRYfklkhvAw2QNQNIQ89qjBSVjli2mqe ABUR332a2ZRSYu2WEx+i+SDRBxEz56Z5PUsvCfkQ9pyGv+wepZGi/f0yd1pfnmbV88+i/5zGhxwp sALKQeRQBFO/8BCcziuV63M3Jje9xnKq/Ski6Xxt7jOa48+jteyDm21vFnZ9XMdEloUCFUZsbfqX Vnm4/ZXUpPBuT6usojZV5/bX+A82R2Mwkh0I8qgU95OCMs/ZPLsNOJPzSjuYOirdLRsBnL+5QEQf CaEDGPq2QYpoklCVEsHQ3NSM6wJrilk/VOKyXo/w7Awi8tRfbAeAV0WiC/31iMyA5jmNyBoq8c4p 09ogcjKBcIZWJGIm4z9t0nqUcqqP7IIkJcRoIbq7DFtOhfCscksPzGVMuryF9vhaOGQJ3OhDDxBz eXKvWkQYthpAzNVUc9t732D59fSgMXZeg8QUt/C5t6MhUaNNEwmOlBhuJbXOGDe22xgOHJzNgHIT J1usXMtqWs70JRsSDaCC0FYmmoc8+j4Qi+B9bfKbgvnWBpmPpx9AiI2/bOeQMRexW6RzAMQH19ES 8fgJ6Ej2WzBv+wWnKOBp4qLBPC96qqXDhFa74htvWNUz+9U+IEV25POVpyYrvNSq35X7DEMK0KYt fka8gy6Uqs9zR1uGhi19ByHVNhfKceV/ZmAGNxJW8bml7zdxzddjyrTS0Co/Cz4XB7FkycpT5FEl 6laZos300vErrUZZbTwY9QX2JLUPx8rkPpKcGhbnXi40ALJn/erQyrBxjDyV+iQIeUPg1bB1BdPl CvXIbuZP0+smYiawxSebpmWENCGaIkhlaC3bZvtDfEC6+6k9ju3/vKheOrj/Uho6mjDU/kwboA6Y iaCAPS3DwLzyYwoEX2/AHxhgSf6C7NXtS3uEIVsUZcVouHF3HEP8qqad+PsY3UXYmbYVRBVeu/nG /3x18bzYu0nq3z9h+hPHYOY5IHMIEpxb67aJr+Hllcj5GPIsd+yrxUecQj80EDoNrzDwSFFDZHTQ c0IS1iQya7VOZy7OLkv+KKC9hnQbXJA38bIjabUNTDdr5MbdfNVamvRIqU2HH2SQgA8sP3g49Ntr oDaLxKiTl34Ai1WtWdHUOGvJTx6wWTTNDQzi4j2HSi+1K9+bFkJoXW2bfx70JNq0ZhhKLUGsFua1 xFLNJGqRe253eMi0DV49CJad8GWnLvfE9P7aLLggwXJJFQPtNDyYAaxeOocu3FWDhiUDAmrUpiKG fPrTgkJLwl398BnPW3v5eGBKksyOOsn+FiONAJUOQ5BS+7iE1WUM+mH+ecufCzZzN9Ejrmg8iu0+ Xz+a8pKVE5ISUUqyMkhBe2ttoEISlztZyGxFVi4DEKT0Ne8Im7sV5E7Ydlx0GOdW2IZAoXsuDcEv zlsPAl2SOCV+1+qa7Iy7Fpp473f0uf50P6CzCODHTarOdUerNksJawvY/Wz5+TqeZJHCs+GNX7HB UIt15PcMqprNUls5LH/YhRjrladWfR7XEbwZzFUcu0J8Es964rXKP+DgwVfzoyWS5erKKpmaFLwe Bg5+irY9qmKZKaGQPW+P/p3aftYZuPbi7Fd0mMJzcUhNy2B9KxAwl6nYc8wTJBs8Hw4ZOehF6YSg ts6zRMNIVHxeQLxXAp4KHHxa3TbIqM349qAJAGtD8z0lU1N5xaLviL/zhHwDcaoG6D5f/d6Die51 3Eu1qOUdZiYxlBrR2E8ROqAaN3ACoDfs4LurUavMNLnKUcTgzY1ZLaRQdpI1lbCl4QnVeJ/EmVt9 d5gkMkFxBBfA9bNnvf5Y3SyrtREaUv19jgSCw3MhqtYZkUE9rLKJj0MOYBRzSkuFqgE/o/xwcySY 0zN51fAWrYS909e9X0HNbT9CL2FQ6SZY3W94VPH8Et/oeHR6UE5xNN4WAKhqcS7AV/g78xTt6EHg 1lq25tkEj0QihjWUhiP+wUqVRecb0Fmzfo6Cv01Zt+Q04RNrMtpI9QQhcegbPVATQNMz26d7HV3c mA6jz7q+n3vE3w5vc6B9HE9RtbSPHEspNQaK/AjltdHN2v5/vImiKPEdtJs80khZ+4YdHic4zUMj RLHVs5yOdW24GPRNy8HRLfJeSkA2xDdzBcJv6k23j40qxS5vNTOzcbWyMi7LDlXvELG2HlbbhJ83 0KJWXKOWm5qdDAbej+Qb5qyjTvmzGc1JBZA05kXmTf1TGlRKIkc2iSqV0/dBRGQ5rT9puswl/gwF uO2QK5SbWpCgHEVM3cLVX83Weilc7sUrDHRk6q6puH4u427eigQ+exgFjUpjF/BPhVcssCJJzUY/ CnVQc8kVm4zglu1BXcmw5qh0ZSXqrVlyXt0f8EgVet2HRoYAgubbTIw9THPYAxKqnEtjLoXiHD1g ZyVCjrlZxeVtC2Ag/4oi0cBDHvuGrpKHsC2bNk0autJdk4pECwC/f5gIQ3+L4v20vpLzl1N03eZt fQgNbuNNNFlE+06tW7rWjMO7P6tupyza6gZvlZ/hJjXNLwU7JqczJ0yrpA24pQTx0/9/rwOdkP0C kgedjnCwcHeYCIiwdPAXSzsbGKImx1phbJXce6OAX7geYlDNnJHb8A9kVlV15PWx4p+HPWt0zXM4 Nvzjfi/nOF/UPovBU/UPdKAtJdwjYOnk7sD/8OgqHFPyAQD2fzUKNWZoenp7bH+ywjTwAjLk+p1J nz7H6IU75wlaajlNTdB26Oq4YGu5DCr7ZxCHLy30AbpBNmq8v9GQeUNpbkZu2RHa501lxCyGtJE7 5y/5Pv0YY5+9J/C2rUO2WAVkNeQ4A+lDO2CIRS8LQwjLPDwD6ZXkV5Y6T8zGJ3TG+dt0pJIgbo8t eBUGgjf+qA42XPFRlWqGr9i3Ln8fvHK0m1Zo4S5u2ExpLiexA11eHdD/K3LoBuCRj7qxjWO3gutN TwYhp+71yGSn3ha0oydxT/Y/klsFxgBEo3RuCkdlmtdaUHSoZIuGpuJ9gQ8YHqmZ7ImSLtXRCVDy /fYg6vbgJzPbXh2vG6Jxoj2bBhWgFIga1sCTCITKOfojL34yfq750ebQKAR3WLBmlzNIp38SHk6B jefObsBl9ANVwMTIBcVX+103RUnuheKTsqUcqvBF8Xy7q23l0motzguz1CwjIhm5uj8Kt58k6bQf jun4AxOyWhDwbiRuDbIOI9ok4UErCLfgbdtdF3FxKfNc7PQ7UJoXU415WPkuZvrNZfDWfAuIi7p7 Rih8I+yWh3wX+ekIrljG4CAEgy4O7DpApL/zjrqtWIZ1EsoXfrD6UiAMw7n6nt6g+4Sz3VqMGiSO ZvGc9O5bEvVxjiZ1VBg4HyLWVT2QIzMq/nIW8aFn7ZZVPGEYwaljuXvbEoww5J4m2BwkAp+9vKI7 PMwKIMIta8Y8exqbOfdalmgPYVsjrQ8Tqm4mJDRfN1yhF+pOA61o1V8p+4GPr1V9TQGnGa9jfQGm ZBTnnDaO6xk89fXi3BPjri7JrZYWml2jWFk5LKJ485cxYqUaFt9r3XBdbuggEH381R0Tr4QRHeiA mzg+VIq1MxL4nn9DW3PMvAqhQhhffU4eVsIox65rJ0GgZfQMub1lrviPCLujpMfE8rd2WAsjwdE2 RwzUP4nsJw8PJAyiVknhAchxtk14wn3YnQY2xAoYIvfdPAEZFNRbAYYj6ngvbgBh9b5FPoRnBWim 55Myvjvue1+A3L4J9tbOFi1RYGsE0288MEYuLV5JU2tWkM6xe5seXaOVTpKL5qsYTZmw/8s+qKMJ 8JSByxxda1GIyuxOV24HXh6N/3hcH7OpG95NSonO8SEbavyuLsSmf0fVdBAztN42tPSEseNvcV4Z U8XZitZhMeg1IUThywQ4kJUsPH6003/IP93MYBK9oKqABoCwVMlF8WvTGRa5NWz+adCmiCnwyViE 7lY5cftYptQvpBLQss4Su9kzps4pbDHa6i8wPM+TuK7W/PF19n6XTS32qlhGtIviKl1P8rYOdrV2 RBWF7A9e3kU6s2Y0qshXVILpGg+g/ttjcGVvS8Up87GTo+pgxAuH0as19xLXwvfPCsuMJ4So33Gs RUfpPU0lmfE6I7GtNsylbYTL+FVbOW86A18j0C3q92clyvjf8l3qW7GqjaFXShT312W4o4ruXhlp tb9Fo90oNFJ7dSlCA4kzg1zCYYcebNlTB64oCNGkWsK7ngio0eu2VMrhrtOjh+/TqbjIe/KcbQsk kzIIwCVmwKwQ9G2b3ZpM4JksaGoAK+KYQH80UdH8uMd2kqfcYUcphejpesGatkQTUcu6m3euzg7l xKRPlFNi2iCHlSbZ6yHoFzyjeC/SCWcdvE4tA7YvMUUSQQhvUWzRfYCels1B+bmtWlxNY6M5PLD6 muq3XUm+3whwrKH9gE4728N4Lekj2bFUR+GYAwsH8Wd/0CIOHMPyNg0J9B+Pyoo673Wq6Rg4B6tl Hsd5dhyhKIvmdS3v1hC6GrWT01NELBmXQoNXKBpMVYfcmqm+xRc5AV/rm80OaeHcH2G2FK4fX4CZ bEFQ+lVOuRP1miFKbtLtS0XjfXod+uVDZ4hOhdc1JcnMW7DxSIwz8osrgGHhISZmCMQA+BGk6f6k M5HWeWkCluVKHyL58ljRtk3fCOUamQeodWNcBj8YmfEAjbMwUmX7yeeULgh2jTuj2wypTC2clq96 oh9oV7+TG1zhj+mOkfYxu3Ae6eS/ZXvM1KlSaTPViYvzTjHGZgDC6iZyD2pobjWW0ewDkByG1DHY kHZTHA/0gAAYDzuDVoxy4HjTKsStdItKiD50QDeJvHtEmPKl1YxW+VomvF9IX4rPmnsYfyRQR70R ZT+aVslowd2mWwPwonkGkdZbpafGU/jlhp6nue2EZNIqUcwvo0jx0L3ntpicWUOXYkML68pRNNp0 B59L9fSJ6ae7VuCDsoZi5ClUf3Bcs93sQ9ZHoPZbC0JL5NjsGelgKPyerscuQowecuEwlJi8BD4A WqyrllgtrTh9rpRaXYP0x4fwbwMhEgWAb8j3RxHtG7msFsfdTNaAe1CHcFeE/I9Y5n9DZU4peTTd XXxcYgUwMgftT3Uh5E9R0sTm+WnGJEzQB+ATwuWItX0F+V9h6mfvaY9jcKQKAN/4oCInVIXbsaO5 U3HYwGkTELt/c4COZ6lZ9zm5dhbje8XNNP/fEcVZMnnOk6LYXCFMUbVc3Nu28tEnv/5WjquE99sf mJFAdnjNWMkwcgIkhBIt91awLeE5tjvKvv5o8IqOipjwF/Gm6Xr8HlKuCh2+3pFIVzME9XSLg+V9 Qkeph0HaJm+1t4+U4i1BPqU8qyVMmsZPs3d0//kLJQUIEIZvP5KnfQ46N0UEMYDFAs8/O6APmDp3 BQJuNn5BLwm36YzjMkEkP2YC6xUwBs2Nm6EblnycZjvFR/V0GQwogq3xbTs4AemMD2rUm8o40FMP QH/L4omlvkOet48bLl7nUQQmqTCwo19E2rPhr4LTQ0T3LaSTsYHpRd23bwlS8BI1RIJUWpxyusgw R8n0yjM8odF6jzyEegAVMabORJlw00kDnhxrGpNjE4wtZht8JtFvyTaV0d88u9csI+aJvZ5e2Uwi YP2A77YJnBoheKD/DOrnpFlO8CKkRolHXdmOzUI40DIwKFsJfjl5rVWQNDLeUNQRv4zRQaBk9Ra/ qW6bNHP57k2kDmuDU0pGtIS6HLxCL3ngBVY9vqB2mBz0DJHjkGTDWtUfvdhUAROO5sUpJRmAHZ6+ eSRZOEuYZcAP/C+V5F159wbva7/3WlbXE4BLJsWZNn1dTiO2hxg2D9nRN5wnKEYs/0L246TP9H09 rn66p+Qm/pOxFWXD9Xgshd7f/Otpq+dGfT6Tu0ErU8kj8W01L3ItvKNBfyx4/MlW9yuGLgxZB5Gc /HpSQ2TNjGU2nXSKTx3EIXH0mm5/AV5CzZeEjhwOELvji6rmdT7wC0uedKAc4Q+OSiIRY7PGJe53 2VYOC5IkLHxJJbe2EqPWcIbezjOS8tq9H4meFPORvccAD8gA+yUNvmfgmI8i/CAgwdU1LdAHZUN7 OZG3zHd0pFRV4VfwlSj1YK8/YwdCxLeeH1YlhkGweHLHnT276KTARSyikZB3+Tv4trDv0vfZRYnz oGLIYCkJuU2vwvsVz1dWMRD5p4uENsh+R4wLaFgR6B44sYoIBTFqNoA042rbVC7MltUpz2205szr RF+RqwzRgOmAaKMHyvH4eH49s5oxk97oqhJoBdOnoxjGXOP/3A4t2h98Z89Ww+OHGHf48yxlKNAi VYjvkXhdHLOry3irrnWf28bAJPsMtSskceXDhBiMe60WHHHwtieRLWE/tVMf2KDtsW3m/035/gRd RjaRLXJc4OyCtdOwrl5zq9QZ0/2Tk03/Tgs+nNRcvnV25Tw7tKVsz6EsHSUXOSGUf3OehCzvcY+o 4RgbPsAsiJRyzbhE+aGldf74WbfiPUp1Qg5GhsXCWTLsPi1vLpZR9t7RvureIabpjVYous3EDRfQ 7MkFr4JJQN97rwb52oKavpE24kWXbsv6aL2TyitD78hTNL8r8z0fTknf2n6JtOqckL2N7YKaCYwv rWM9FQo0UcS8i3X/3C5v1J1iMn7H//Bva1kqf9CTSZwnGf0t5lph1/bGLQcPN6pMPGzGLZQLoSnM mf9KTeV/VNY2of9+lq/JoKHmtR/RE9XeybZuYEiRCUYoWxW5B5y8q2zSreUYrnpi7EmQ8tn34p2Z g+CWO0XiQwLJj2pFXAaDmm2jYCJg7awr5WdsdmTWAurLHW11YyWUzqG6/hryTgmc6/E5D20dv/VO dK00dBRBIpsXTKIUe93hrj7noRQkR1hg809WkFfJZ4oPigkSsLlyPXTmg2Eb8cwM5zbdJzn2KWiH akq2zJw+udWi81IihE2DDz8nrS/sf4qAH+vLahvETrb7JnATTr49l707vYDzrEqfhXAgUbOpYfbx GKPYlretQNOoIAhDhQY5dT0K+wMqLlYs4D74uYMSn0JhJzr1fyU0ciQVvieOEphvYJ1NfqlT5wMG EOSRO9n1rkmrdA20cDfl7gmmrH2OyXGIfiOn3uEh+NAe3Y4u+Lmo1Oo5CNYJwZAjDuMevwMOtydS dhYS2Gn0Rgwxw8mOm5LhjgBVAkH3iaU17mzqLcAExUguyXUOtp1Jc2D+0nlpELD8khVl5K3DZj0D Tk59llMJd/hkjndwoZEMuhpOA874u5exc4bFVNB6St1towDljuiGJgtMFbfUPgrQZGugPx5d6PQ6 9FOn5O40yX+J3HyvWnyjxOwaxYP7uBNz7Z39i2bMg7j6wJ6NcFL5sHP5mbrOTPy2/6e05f72jmNZ er5HVu70sVMbtyA9SNlvBsJ52du9Kl87ccDvJRAwlMKVRhk61WG4Z1H8Pj4lGPbd9eBtNfzrKonB ZxsF1MnGT6qbJajFo5rKSLzcWZdxO8yVPZHLlnTicyJciNogI/55nhzJfBHtO4/cX0P4mV6jhiM7 m1OWRhL5mjaQw0BX+zDlU82qp35BsL01bt6zxVm4uzl5cLY2UKRHQ0/tLj6NI9ZCIcsMoo3pMTZp XxLWeuOvzo8/OEEAu+1y1cCbe9qXzr7vwP0HzyQIzNcuVy+9PZGYsj5FIEZm4ptoAtvju+cdC9u7 0MR1OY+l7MPLxSBLV3DYCbAqbIGCWfooUSZ9Bgy7yOqdWa8DH+50nRRd43WNKa5qKFozM0fRB+7A RWB1UhKS7LFICnRibx8zfaMNae5Dt/LyKLwPJxmK9knyjzEiePUQg86/lnREpwqmz2erJK6jQhPc SSXDkfQVxHqp6PXnlH7frU1RCD6WpUVcmKcKh4CiKjoAHonewXDbQSlKRWwqUt3TPxVbRShU2bEc EbUkkWgJFUeMh079KmPlYEw1FKNcvm/2SKhVkLs7uQTjeVWmFXE5lxAh8mHxemhXwJ63ahOonst1 8rLV6LII/EkA5cqA7m0pKHU3kArMnErbWUCCi9ok6taMQxC+Uz2xFW0I53IwLI5xOa8XQe4a6938 F2nq4tcinUXT5HaPx9qygfYEGzN6YUEhc4DUQPAkV3eoC6Q9va7fgat+VaT4zA/2+paG5wI9j1xC 3WKM2yg+EM/wD6fG+sX3hlV594ZLehIGirzj05tnZS44TsKzkXo/pktA5o7kYwcYPN7nMTO7FA+P KRZcA0Sgo0mUBIxX27qTl/S5sWMDg1ro7TKnU6tj2gkf4iyBi6Cumh8eUnpoVFyXeDgJSvrVoMow DSUGSTqR+rnszAtVsNiQP0LQJ8Kt10NHEORlhokmQTQnIu5b3pg0AZqlT9PXb3fyxTvn5j7jcAgA t1HxB3O1dqGBphldmaoYhOmodoKy6YanzHRwT6eHPwBkir7vB7KWTE9m54fe3RKhqm+o9vZ2POix oAoaJ3H34FsMaWwwgd5tk9khSKzCFgdtvVcUrivJqROCZs1jcLdDgCewdRI6tGqFOrkogoaJ2VGI q0qikVhPhsjXx4h1+N4rJRjDn3hpNGLBE2J9iBi4xgL84dgdVYp/wLQoG97KOjZLkCPnc4bL7fQD szNwN1TzjSZfFvMKwde9EaILltFxiOlhn+48anx+VghJrmoJ5TjkRtt/5UFEijAh14Wx1xBJ8UTd 6qcMbWPY5TEOqf3/8jccEPHh3JF47gylhTo+AxwBlwKEOT457eTGc92yRDCsTi8zB52OnlLzHmva rgWllGX96qpkSc6zsz5uc2aUBHZgR83bjV6lQm9czPmh0yvHmwFICFWeD4CnCrEdlDqEcPXg41N9 Ea+v6Oz+nYUsDjbIP2pZMywj89cHDmAX/TwddkYKmysFjVDCcv4POtu6l2pTQCMLK4i5kfyteS0a KcLLWmfJqrrJBtJiA/E2j1Wr/2zIWiuHQke+nv+CbEdvqPyMM/iQA9RGse847411BBAgWFKnLd6S Gpt43YSYwVtsD3ovkRsnENibFCyIastMNqpfYRT7x9G7EceymM58AdUeUyokwJYnRLS4qS4nQ+q5 5N2GTF3ArGl+/jUYgugD6glxcJ36F+Yg7xxpAes35XqfCrAuflGuTRYUaeCu8NfvGZJPRwyK1jzH sofgQXxyz+zayI3npMElRiTpXmyAieDsU2+iRZq7TYldFL4dtmo+vkhTIr6x8TZAbHbqW10dK0HL yBrGA0Fj9bUHS+9+3BrgZizf9IllcqcdVT0Cs1nAaqgHwAb4LEU+twdBXrOZPgB+woIj2aAWvQse LV1uGT+CXm/NWWbtCsjdJafwJZ1W9SyjnbyiMUDNv0zjCQPOp6sLAH/6aVr4pOPHpWZP6H2oHhTz whsvqlBjOROK7SJwg/r6ELesTdqK6YG6utvEBnLi70VCtkeds17chWkWCbwZK7Uywb6LAAkxMXD+ CRXQjzkunRdTNeu5/bcLXt67Ob6PNKiTpLJMemnQ/83XC29Vpr9ihZSh11lzzeWKlb+EKrj14CST fO3bJmPfQV2xmI4UiX97E9fY4lWug1RPRvZwGBsI7UOLTHOpSDb99LAGZa/7oA7N9wRmcZrUfS19 +H0rP7KpeRmjoo900l25L0UxOJv5SY30ASpnOYcoYLIxr6vkCG7OQDXn2G2nE2gUNjguuGWecgVi EnpT64Fu88FYDj/HPtGZWifb4jun92BvCcGgDwZE7wcRUK8JHd4OXvpXUxdGmfZXBSgOmyZ0/JVz MzyPljtoZMZyIPvRh7unRCJQoBNBY3cPVFk61G4B6h0CEJ1mrKrPHtDGFQ/mB9UQcB0TbSk22cBZ VzOsNnuunFqkUJehN8PYXCNAKHKzogBtPOllQBQjcXl0Eyer1lz5BopTorPIM8ZKMhLMbUKiJQ0a UyezLT6QyVaiJaMAZzyiO0KwujeeeACVGuVibEgGr9eOYFyO2O9K+YkL9WenAxh9Q8mXRmTvg7Vg 4IhPG0wVQRUuk0+RgCP5oKzYziWJCXzU1IwNTWPgNl+En47YtrWhxsU3PkMKzXvJWiI2g/1WwE9P uJRU3nw4D0CH9wefVFJ5mc8n//qJTW8QsklyYab99MIB+nyX41keK6aNg3IYZG9Z6ME+qaKvG/xQ eD94T6Wy23eJs5H3Nuy3c3IP1b3qlEx4yMFW8o9FQvGSWLdyIxNQ5sjUufbBJp3nQ4gs9ynhx+Ph 1uqCUhKfMzOqyfmqcPHipBgh9vb6d+VLFcS42pzB3I8huIm9FkWWp5/qZ/SbS3NDSBUBFNRxtwT5 5I7KjiLFJgI+QBUAjr/LV/mwISAwD+3NMx6bN3uEEs75SP7V8JUEWNV/KqIikZ8ovNMV/qCTw7rU CMQO7lB/VQ8BwwWVw7hggZbjcMC/qQA+D0p8BM06NdsJWvj6lWEP6NqmKVwrD3bcHhmmiw3aFcKh cmPPxVJGiNXQUCNLnObQjbErrvzJirl/0u3BV6qMsPYjrCClS793XGnzOxTzYCjvMjiLvIU2uzCt fMLHrn9yReljyw3Lg+E+kBTdxJF5F76jU0NB7S7cZk2K7P/yzDUnWN+8dHKd3zb1fPxWqsWq/ZfN Co+TbRdfrLue7XVcv4/FqriqtrsqQu3jY6tRrObX06n6DTvlgpiRPyFB5PTqOVDXk+wBRIdSkAdQ m/5IyDkn6S08ZBlRmeVVdLm19tOGMR7k6cuA+7CheZXjtwsgCdckrqYcmyRkvaMvLZIpNXU6lmjb p7W4Sr8+WKk9tw5/uBDP6g0xjXmXoWV8vhvm8tRmjIXBl2Vc4Z65d3fpSXIRdLvUMHnSzp+T9aZR JCTYuJVo6qsPY1Rq2i4goURKxOtdCkv5ChyGalU3Sc/8eWtlmVZ17j0zS0047DeiyUoLqmXJIRVG GIxZDFhdEi1oqo3+6hcD7iTbzcqJ0HiWkE2x+9b2C10OKlzQEGbQA6VK/iYBc5Wcns/gY5uFQ3QO 7YQC4+X9aedbE2uN4d3wbCJqqe2eMtmg7055viftf0vPtmHk+0GTWJl5dmwGB1fSw5kGdmc1GeSy M9+8cpJpC8hhH6Pf67gqEjm2LzcBrB6xmoO/KD5a9KTWa5s/2xUGROE6V6IbrkX+nKlY2HmPDbDW nGQa9m2zE+0WSD1XJqIfPYO/EHp3v0qvbVgPb0bQQtExldBELjGUHYuue1vtDf4ziWu5y7/qde2/ VUBRrEak+krHSixWoZLzp8Dzqs4pVQ9CCjCir3wUs4g5vphX0JyIuXK7dSjpVeDyVc29ygyK5+wi 87rUC08+TyEsq0lr+d2aIF+8x18eSrWzK62d/iXTrR89iVcKAlzr3c8Rfyjf5VbsSBv5GY7xZjzF yse2KHVZlUIP0DCmAhDiyOD62OfOotOsP96bETrN09rzMJ/mHB6K+F1sRPVnA51zCyCBudawHnEn sUqtxAwFgYzW3D03TQWTweKLwnMqERkhmHQu3yPBnSUszJeAsIXadcROkx3OdnyhNlDhs0hOsGZ5 ih8Pay7uTpofL0Oh8CByizRT/qYFPsBpqZLW3DmdU8yh9Kdi6g2Iob4cckgGoOSDI9MBLavqDcLR nTa0hxNrjQyzeYsYm9NqJcINxp5jdvmuhoOosd4LGYtD2ByF11s2MEkzVJOhSuLdINHA29x4MMiD lSKKK9toe08rsV8H9F8QSDheIX3WxBkjrmnRdpena1adKTDZ4uzttcAEoLs67I/tlOFfgxludPqF EWgZozzvlo6/XxlTm0M73GdqEqJk3M/HYeiueS3kgzyaq3+mHUmJN/vKWobF5d+UTovSRgrdjDMd Y6aGVeKErDVKg2rZfCLRUuwCP2MK3BVcOHGS+6wuPctAQnePHhqzHvxcjl7GbSti/5Izh2UownY7 roInKuTXlMZUNM6HdUKYAo/0sH+1JKRi9rHOBA669ZTjnbYNxtFMYA2Ol8EHbOzC6+SSguZLjFk4 pHvrx6bAVFvpf6XEoa3ezfXhYTWh6qPPIoOXIP06vnCVTegu8+AE4Hk+t9wSHPgOz30/K7zNDXeb veSvSNPQ4BtJ42VM3MZSd2BRX+PB5jsiFxjiX4yHg0QkZG0jMLtyR7X9iTG6kb+/H/YyZSZS3IuE JyemeG131sRVKauBLW/kwXMr5+AvBv2zUZ22cP8RrkLNspou2Rox+m5EIWoVwNBtHktlSpN8gj5o tPrPio2nq+JP3aibIDBbS+hfcAECFzYZSVX7HCgzgBqebu7QkQJ1XKjkiNZtYx44nTnpSrAMUxc8 PkwXn4zy2of0RqFYsu6wVq1YUxcuP3xZqyLybqRVAgjWeNTPG0nX3QX+zSb9Bd8yYS6y6MAceIv8 0Ma7CXpfFH+psYZHBepXsw3evaST3mToRzGwsqflrUeKVBcY708KKneVGIFfWlteFaiJ2Z4Tw8+X R0T6s40f12uxzgxTuRR6dOqX8rNrODyiqfS8os0iz0J8LzZNxs0cD3H3XaBf7UMI5clIrk+4GXDR Etw1mUcnvlb6EXmieHaOzgD2rTrJCWtiyxPXzZVqBb4xuzEmDYcw6FJaKfo1i40IhAe2z3smzPSN MNmIzLdMU0qgzl1pghmfWaB3aaUjKOI0fbaETsHWxv7buz5YjNegrs7ZoMMYB+JVmgO1XqqH9/uR 78gors62U5/T8qk4WqJXiXvgbF8IMzL3CBHN/OXgNHhU06tVDHUBGHdOvKQkMA4ocJZznVNjOC5U oQy/faRQAeIIc9XoWdcmwL72SiLHczPgnT1GNK4gY/K5CTLpIL68tUq+mCNTQkS9W1wqgTJy9dIf rt0PQ7q42FdfQBmy6opB4i+LYOFMYeB8hw2K8PiW4bf4Jb/dgHGmX8UAv4EH+CilgvZxS9pfGBEb oZf1u4HlhMJyVB2W3nI9Ohis2Fk1l+FVKF5Y655+/2CCGOoBik96G+YGfEuBsynRuhhN0H8d02jH 8fhzDXccJ6FWVsGzZNeM0ceVMMvw6RX+TbVVHkC0igXAnnJqjr/caRM+QLV3uidJ/6j2VNlFf7OU yrmtto9FxwUG44L8V5Avh5Kwi9nsHKhW8fqDTm1Jilh+IqiQo2VaFS+tJOmtn0evImfB/hwrU4ul bZfz5Ca7db5C1uMbRnxwd3mh0dJzjpVsLQLT9zvd+n473s51voCiaqMnYRMT8Ctc83m5gGthESFV g04Je63yfA+Is7RTXn2s2I63WzhKHIQNUjOd0OOHlkeMqNJaj8L3FVWGR+3Xf54ju4zEiK4JbA5h b9+CQnNTJrMXE8ATUykxTPIbu4CLeZGY20NF3UVk0B86zbvYd1Go9L1rBukAxj7A1tRrHpsg7MDE iSbUNQIYNwKTfx/WQLpX+hsQXFLSXarx49jnFJAIBSOaEvYax0cfdP5NwwJdvYsILICcYrkbcLW+ j3oy2+t24J5aAamZLjHoqx/JCCE6OrIkpssmS8bWBYMvfWcIMnVKC4DKaSIZ0dUZfWiKKlA3qiie w8UuE8Bapv+rMBbrmw9J3ZWnlSCZ+ilhSAHjmgcqHcClrCXzvOvec8KUmD4ljKCSSoeU/YPRfWv+ ooW1nhDCIQyJdDiNzwjinvsnqJnIm+Pi7N2opTQB4XVelucyqB2yxnHqhIB88Rnc7RbaDiOUdH01 PPSs8tUC1mVpODw/fylXxwHwMTQHXSFai9MTPk0caI8RBLV80A+d5LEmxkU8LZuH/7r7Wyib6bsN E1nP0fYsj0uPYkI6ydtkAKAHHLuJcaWM+tSgIgVhHrWW9OO5S6IaEg8jVqUP1TbblXcOxECB/XlO pOsfrRukvec/LcykSIlK/8yuxVYl3TKwk1rqEJNZpcVdLGRnZWVjjAb+URQ5j6pARrz79z3KgdTT OKy0y39EDbT0T7D5Xm7nqrhOnHQK+IO0oNjn6RQro4u/OevAJvOeVmdqyzPM5C7N+PHvH9CZG/dD wEu4AeWjE+kFLQndh5osEY+YxZl+ajcasx7ovmF0ls0T2+EpsjKmqKNYVhVBgXO71Dxr5VevepLE VDM7oJGOI3w7OBoNwX/eiObwVB2qnR42Z2rA/u0/LA/ixDmJT5vKoNXY3W1gO8t14aenJjJVfj2p GR7W541a7Ut/vZ9RGBD1E6O0xKHmSVn4NPrVqJBYHpTVsHWlC0JaA0vJeZHoVkmqhtSRL+2KqKq6 V2xJEjl6ME2SbqOC4arB7qUEVCyx+NmKORR0hJ1wseqT69sc92/JsDxBofboLASpesQps1Pnq8Su 2Ey2fqyzNJKuUhpak/O8ec+EQj6Yho+gC/X9+/Zf9H3k1q1cTAn367DiI4leFgjOo2Y7YqJb1v1j baH+xSBjCR8zv79dfZRGKNujmSwuT+aDwPUZ3hAIGu7OOLIeHJAzibeTYw0v0oWCqmkrSF6y3s3u G+XTiEzBxqDjszmiZ5ilclpH8x/xPmC27q0OoVDUG56tQfT+v8pDmukK91y8yfJq+U6UUOADgBJN r+4h1VqdwuiExqjy1Tniz9/uwJGwQ/qlXralZ7gRpt21IYqEx9X54cnzACWtRsgYZn/5UtY2aXG7 wpxCz/3FwD95KV3fO+i2koLzMwbxAnrkNR8UkFe1HDRHEs/q+7TbtSu74pLeYGffhNNaz7lQQ3Yv V8vLTYvYhKzhhKrGFOLaOX9S1e42txKrHy/0jPUa/CXEmQz+xi/bXcR7l4YiclIGrZHrttny68N7 UUnMN1sgA2lQ/VKeKc3xjzZgmA3QD8bWmR8KHzdcG5erftiEZsPGi77Pkm5hXahAIWOtf2YtXPpK BvVGR9Qan5NhUA/Qn9TkSV4T3eyG15QyLDDPEolFok5d32ABRd95RFoZRPEw0C+a4ryaVtDU/0Sw ZfPnKwcYBApXw62uOqfli+S6lZpw/FHw0zHUPq4MRhZbKyIeaqBXXI5yQMOa4iJlUj0Khp0/nlfC YaSWk7OEVXKLTkgJ2YVS9+G5s5U2G8cBYaQPVpNzDwXS5pqj/P1tqHAInzcL8Rx8ijEQgRFMD5u1 6TuCUPx5zJzVghmYyN3tVEQDz68cmO1jDipFnWwElAYq5KpvqHtD43FpUds6pxd1yG9pgdWZWCgj //fqZxu9//v9B9x9c4BDdVilck0yF6rNGuvLSx4Ra+0PNVO9irjI0cKe7XBBoj0pS07DdwbtzIs2 VQWS0xJTlX6gh7SLoW7XmqfoctD4ezq349QcXlKl1o+M0FQNRrstIitERYznP8yRX2FREw/Hm+8E ZfiOLWAVBh9bRl2m63IFAoU8HiJtrrAtIA/C5zrzFQuB48BS/yKCutxzomykhlopBh+vDTJ+4cwC KQ1Im44BqK1GvyrNut5FeyT+iqDZ30WF1lCXgh2zpoCXs/+HubRCmGcK5sCjezQiPCIqEzG4MIZH SxFmvLELl2myd/oHaIhvAOl0ucJCdZ950GLIjkchu7IjV1PpXQcaOJRubEDnX+mOjESlSPvI+l64 tIbQ//NBtq2TMmg8XZ0714+ebcwMQfrOttc9lwM2rqc+nH5TRpKGuGqesmJVMU9VbNvraIslsxFQ 3EquZDjtAloSq5jh9jrcRmlmurXJ7isTeihxstWqXLR3s85r0GUyTrlS4QLO2bITYsT1whDAu6MQ sY9wKIwuZopRWe07J07g6N5lvjadEhEPhHqk1ekB6idwg55g5sMTZ9KpCEfjwqLkfn57gKXnNzuO BjfmNoleY9+yYoYJ3O8I45lcx2duAiOsA2Z1nqIRk942FcyVqtdDaE/3mBVf5wKgVArtTefgU99a M7Q72zXLq49CxHwitTchpt+Nd5AbB6KIlOVwiS68V+YKVOQcVFjtpGZvpkAXjCPp0k9TyJSqu7VW Cz0XT6faj5zlVoC7y56lZk7LzUV386GQQ0+b80Bf8B3UPqoug8Lg5tJT2AdVwHvfoGDKjxEmD4p3 F3z4whE+QYlSuWAVRijvwEYVmAIKV8yRf0UHkU1UosFxVvzyNKOJrjn6W3Gn3M5N5H5ifCGQmb0Y mWcfwqJZVcIF1QFQ7KVihEXXzXT75BBeL0jM+inZ+wi+/w/HvWooP4/NK8jkgTGjeDyNq0eaeeJy jGLvye5CtkEeg//OHUYSajbJhMUght2rQMxyNclnjnkcXnWop0xjQ3H47DEMOHOL7XkoPGc/WzY9 fWyXBlM8ztFGP5A/XzbHti2GfA/oOPGZV5FuSnSCOqi5dkmzckvfPI8caYpSe7x3p2HS8KclFhMh gvfEKrxaOAzjYernOSUnQrG+g75YXvivA+H07iu8gVYRgKMGy7SWsnG4Y+AhG6/PGCk9aZKZSjCG CGFUqlHPMDOl3mm+8gKel9VcmUEbiByjM2b8/Gw1OuOk1MD/opIGeT+mQ/DB3PN81rvtaKpIBCSc 9LOllOrEuwwVUdgomE41V14D2qIn/aPl2RQDP77p0xqCDvEXxRiXEtr+ubZGtQf41bEben6uz5BO mpgdwj/Uirm65p70ZxDbPRE7e0RJj7NQXObf6uByfuR1ptE9IQsbY8rdTaUsX4np8BpDKPPRzhEp Pdazuvt4mGohKpi8/WOTDCKu2FTh73mrMHCABKUCT9+/PP/2lpwJQDiqyPBh7SC772EgDSEdrUu1 9w04IY2qtPzSbWzqE+E0i4DPe6ngs1B27XrJ4f7YnlpTQ9zRS7PYn6I6Ro2HFqeN8Je10mBI2GYF OWtzUIgk0qf1PXO9lbRkiNe2SkKSl6tON8pCKmFA418rRbZc+jda7hpLUOdRtXPua6GBu9tYV+HV e1ia8bV40LVvS7xDuLM3Z56Z1bEwaQHe9gc0hqnIpzqfhLAg1FjuXEdQ7CAX0AiJym/ZkMFkoteS 68nmMoFRLHni10lzzwblWlS0shpB7kBjwx59W4BHNB4+Nq293oOMq02/RDOcVr1QiU6KV3mvtX3+ 0YBoqQlRAvdcY7d4Ea8OR8FrE81ySfqLyTIv0oLqDd9QCnXv5ZBvHuqvLNW/B4See/aSuvbMrpgA X0jWFt+e41LJWAx5H8A7LiUHMgg00Sslt1fOVXfggBcjqmaVKR5AmrC/jVKoAp6zinbBZyZ41VdY af3853rhgD8m1srIs6qSRm72L4YtPoo5RAC1RHFdXQ84rTmNJ0WyjJmvaRNDPzorp1K9WaWvihtO F326PfqjKJcKTFcAjkhGFd9r0V6Ba2QFdL0MYyN7lI8F5PgFYApkkGYYwt6bNTzYejp1lDmH8KFH +Mx+w17xnw9bmE86iFgRe1OOjPFWDp2SfgETBKGknOnST06JR0Xxk/QqWk2CnmMTWDZcwDzj4lgl ko1v3k185R42y4IB3UTsV74nItfKhlCvThqnznbaJjRUqjZmcCc1/G2uX7zFGQrUz4tIUGw0E0/6 cfW2cs8agJR9pnyXhTIDgw8giAsEaNXbUETE7pM5gsifaIujCQRZTacELXuAFpD1vuCZERBTHVr6 m5KNfGQ5e6AnnuYhcwMH53wYEgALv9y1+y3Vbna0RnfAUCK2GwqOjOdMP+ifa1L7K01WZAdYYUsw RLl2u/swP8Uf81xviKtGRGZTLtK7fQF5REKfX1pbnw9poUxNTeVnzH4Ckvg6hDZeOXPOfSuEXMs6 FuAmwDmQKeftsmJfEkcwAutbWadigH4umaWdHGJIyPy0X9hyJNduzaIOeMyHpYNhwkxFaAHh1t2v YNNHU//r0vbHa3DSxbc1t7F6q1pNO4Yo9cIiGOXAD7k6GCp4Ul06HYtjanWBYA9Wyl4xeM+ftGPG eSfhSEudQix2hRE/zRihQ+jFd4mmLcdTiGniCdszzeuxO58U/wXc2lixGAZbHwRJbQ4wr98uA/tw obP66GSyDdpOyoOarc5QuBSwxj2gFO8HTaZr3/fno3ducF6YiBmSZyMCJX6nYRgn1+sQt7t1SKTU GImCXLS23d1Gn/urHrCfksAxPSmRyQ7HC+k1dTVrjOVO8pxpfHKsIO/bq+63jj/ewM+Sw/hwAOnV SHbZazvLIHOQ+VqXYoWXXH1iD9AuEgrctLGhDixU3RZIWcymioYudQj7G4/aZoztPlC3TCrlV9e0 dOVqV07s9IR3Wy9AXdcfAfDlpvlSR/1IM7zm4p96LMRXz7cUVpINoi5mXtU5Eg7NzZcitQ9twOJ2 4FEVkBgZZS9G2y1qU7t+jwEZUG/bkaUZ4dihyYu+U5Ukhglcu+FK04MQwXrKB6x39KUlDJsGRxU3 zJPoiFGvY2OLL7045/yHkpN4/Ks00DiVG7/K1LdL8z2QXH2+VY/8f3yuYtvl7pO9ktTjfxAuPVZg G+4b2xc3hr7qwJiygsizqJDNH4kq6WA4iYvGp8tVRD5VdvzNkz9S8UNcKVme1tDeWCfXhFuemD+7 9y4YNy3kPnFktITGn0SFxYa3sp9vud1vMUR36sBpqwcjPGhsXkGSt5Mhr0rb82SBJZHaT6gB7ZoQ hZdt0bpxcoMg7sZwcDsRuy63XPYiacCqmWxWJqpoIvAFElKvTqfxYlbWaNFmQ19A4hiXeg4P95BS Vd+enZKVoV+glxq/H0TLhKqRVXFZIIY0R3PdhvB/T5rC9ADL4d1jmGivvbDq6QA5M+daUf8mDj2M X1znOXn2c8MSnsAdKwpbLvLaclEBQDnHvFrDTHmfGv6K/FdcDEerie5ahfTcNMnRa9FgevMYA/BT HUIsBEWwElHboN8onA+pT47+Cli97zGgnIPxoCbN2vANOpZOuIJQ34AtDiGTPm8LHCJq7UDMhndO MthfLrqV+WO2leIErLimQIPK2ybG5T0UIdlmAPINfQvYYhxjN18VJEfECOILeBFybGpok3JPpdJq HChK/UUWmv/jcFn5KlsvLUn+iELOqhx7QB/xqUQBRUxq5etDahvxbnrVNA2zj6KqfHnBYMbxpArg KVxRNO7WAHTWfdcwjtQixEJfJrpPU8SFrVc5cMURWwHR6em22YWENFccd1XRuuLpX/dJixFCpFuG /H08jgvYDAaA5msH6VCgzOrivKjQAjgv/xEeoaoOGJQ07DA0ZkGkmjRO68QhtjRtH9rXRzQKNr1F Ruei1Dw8Rh89ZFw8oR0BDPket6DexYTGXv42B6urSa6gWboGmxaW1AFxZjC9Xk63vnKH8YhaLwzY UYf8Ry74IPypmHyOwNY3yWzSfvuVLz8Mj2yt4a4NjqO+RDwVXX90LHacSzmSF8sosJod1i87UXfm UMm7/7PldWrDO3afQ7FvPVjyqhoTFf4M/8yHfttEHqvlwgp5O9WLJumS8yurqR9JKgzqq93XuniP upmoE8nuVOlA800/aq0nklldwVPijH5mqRm9LYFcZCcUd2Ge8G6S1sbC2O2uGPbdCAO5U7O8qKEL lxuegP0R1tc2YHlvNkZ2/Gt9ZVV8mVFvq07Q+teAabYIVOnejJn8Uog7X4v2X4MJf7eCFbgmssPw jkE88A/r00k9M/e70JT0qDMCLK3BgIMdQQZzfejnJ8q3lNr6nJ4HTYZYgyvV+D3z7LE4RKZ/yiB1 bTbBX3fP+hC0D+xbqtD1y3yakBAnVSNdlyMlXKhFP7Ac2Zwm6MxlRGW9RX50dCtXm5yZvRe1sXmY 1XtCY4E6AOIcJEeI7Hmk3Uu/yb3GnT3FgyZEp3NrP1eOxke/JWvIDVSL9I8NyXxOwscIcugyPYt7 ORdoDa1yvH+IxkhkmRzxZFoY4Qr/Hqi6VgA2tuGUttp2oU2EH4Ms/yKiRgZMAOXZunncKYhlEJBu 9J3Qr0WMi6uIhxlGV0gsxDNBWVwQkEt4fPalnyrmd3xKY01Zcvbrf25sb9vY1K6DBA/zzJuXLuoO 8+v9xMn7e9JAsTak016L6ZxGLXVlUNbz/B2t12JW4GgC5Q4f/QIQLSZ9fzVQmN4qBnq6IuJ10Lj2 nvdukfJVFRFxq9Mk5sl91MtdVFv3xOhfvE2ZHc8vNDCsNYVNYumx7phG/xGONlK8mxPOE6s8Cf7I PIScPOo5OGYVIBgFD6WD2p3TED9MCZd+P5tDGOLZ8cvk1rwYJH5mwcvzc6ZQpXFKncz//EMTU01n LMjnsCINvUnBN/ZS872v3SXqWP/ptQWaxdOEuRL5ISnlHHgOohdwbkj3Max5LRigqv+LrNSb0oZ9 +vmN6htcvA/tT5MrsMsB3Hy77zH/bARasNHPHzwrm0yTS8Hb7MZNVbbmZa+6l6ByObuFXNZYY57p C989PvfCcOxzEm+mAfxki+PvTIQPbEZYeBmVLR6xU+WZsaxQxfE6d/rbRqVzQjjG+Cbu4sC1j2gP RiJjYAfEkWcYXCV9tisTPBEXyOTeA9yghij5/KV6ggPEMNkQxpEf/n1T1RxY/EYDGcEOVISMqQyN icC+PE5jlXwbqA+o7D8h9BV7EWGBZJn5PQvkytKblzRsl2ba11CaJdeBUfcKiuJdNKqCOUW/pTpn WWCsd29p45R6ilC5VoY7FL+fePUzavsxoxEu69qv20Z1eMd8W3+yFsdYQtrzcNlpscO1wVFSQx3S UPFB96NAdR44b/S+lKOBEba2au/56M5vFoz9shjEg/YmsHVtXDB8iDBmS1Zwl479DvvF4aeNouGd ucipD5OL7B2I2rm+uGx43q8/3FlHIvkWxnmFiWvTLw62w5Wsl6bUXyb12BqZb6SH6M+5+rNr8c+/ Gn6YmyyX8o5PLC1u2/RDJ2QgBj1fAxWY6p1HRx1aLkaJHzTdZMV/qL5qBjq9qlBt2YBfcAJC70TC yKC2SsxHhCyGS4WLkyXl9C/Ch49r8nZ9XSddSGhJVDQWmAn2FsyaYYNMsKCVo2y95N1pDSfsXS4I XkqGQA7bJMYxaRwUrJGt9L40oy0Yv3FJ0OBXjMenw5S77yIqa7ZeBBKOFE+V+DEnw4fvqWNKfzuD WMu8MNbsCUDMAmFbTcrcCc6XZjH7+jJ2AAhr0YCVmlK7obIW3AX0dwZ2j6f5CSj2h8/OydbdMuGd QH7Nr/4GOMPwfF0PIyxA+yrPTrcqPK6jhQeYtHMgeiKMh21ROrIeMhdc0W3Q96whi6HBr0YQTYi6 vjGenurRELBSeur1NleXNhv4PJCLJ5rtre/qjHWDqOEhFd8e36p4sD1/l28CFCvkTHBdlIX0ANlJ KGdNXGzWHNmECxpZnAe/1Vpwr2OH+SLN58PtUUUQwrlTLo0sBzwCEc1PpeR+0gCQDbeZ9HUyCUmb Ne9eMJTMJ0p3V7IAHw7dGJ95tW0VKGFo2XDh8YJQLBJMwT8zyjTrmAOJuxIR1wDmTweLldQbcUiP igxrfWlgEEwVZJM7tGewy6cAmn233jVfGFixdnuqNZWWVBYtQLndn3DsZ+IUsfomt+T0cPNF/mFs wCd0ZXIl+60jEsvzjg7ATup5aOfCgmWspvJ9j1z549JdPSzjLX5LXalqjiktop73aIRQ8t61yV6t qfMmLA0tBrue7Tvb4X1R3H43HezKxsr4PlN2ExiD7Whsuvr6lWrwczdtvb6OaV0Feu6sNPEHNHWG ARyPZxxvSwlOMSvdpOLlAxgS9ok8cVSAAa/0oXDyBT24FTt1/YRgd9ZfoKAK1QdakL9AfUoA5A9Y E3r624yGZ2IEJAG9bOYlZrs7LCje4zfkH9b9DRx3fUv4BdxvmJjWsTqWIpVfa8Z5mRr8DrEENItV imI2ck7biFnKRixs8YhDjf0RSlx/JC4Zr1XqAxChsFaqbCb3KBa1qd9NOIpPCVgy4G5WUky9vjWr LPwOl3G75LA4c0mDhyLZkvT81+S/ydwHxZCfUIACDFhAweAnG9GnYiV0RvR68YSEN4x+zlghH/V3 ROHhcpPVssF6rtWD4wV4k0nU/6CNJkeGQ27dT3aQiZTSYTCT6e4GD/dfZU0qRneHPsfMBqZ31hst nkPJpzI0vk1n5WaZ407N1vLWZ+5ZgoQ9dtWT5e0g46/aPme+V2BvIuVhivHMy8m9NZB7hH+6cN+S tqn/t/wFV2Vw9Nt8Z7Wv/FhyMHkt3P1Mn7AhsbZ3UBTURR86aOsavpbuCGd7nIUH84wjhcOYmfLd 6cfjawtTc/2opVa55xByh2LWFAVKMHLmvzNvyC0U5G3GTD63xl8tKsR8hjwYguNcTC0kJAZTwkju 3KZRO+Be2djWmHwNJtV905vlyW5heIYDfJlK3qP6HpCf8d20zMxkRfZwRNAOQ2bWMUuX35lE+lZq KStsfa312qZntD4J/rwrxanHIhzCgLDzG6WwDND9R7sra66mpAyv/b1MLBnfehHVaZlfsfgWF3Pu 251BBewpwgrckIEobVBt03MO1LafnuDdrhYy8ifT3cwbtj0muoHvOavDIUcFgqASoHqZ0tUU1I4p zM57yNPTNZoSkc6RopOVeNH7Kk6mSI1gvmx4AO9Ac8hIXajKQEmXck9UwCNRWT6kVldbF6/WheCK rXn1QHdJ303lcUd/QYuDyg//E+3uQ2cROJv0Ys8/Z6UQguAKpSwsSv2qAIXurs7JxPw925aX02Av i/TpDyKoHE0szP6G/a113mpYPWTPE5oGWCNyu8D24XTqeJbO5dWI/AXqt3/hZ31zb2WSQxDHahNL Nucpk7i0FH3YN6G07CFuPsyLn/p9BMpnCSJn79N+dtlv3GAclV61uoYR10QqQrhNMfKy9VUPKHFU T4BTPiNumtICQiT0FucbhTv/jtTuB/73UjF0tuWIyzZfzv+GVDxFsFn4W5XTdqbogXIvIkyvuTe3 YVflndFuUqft6vJpGEQI+HbvfKQ4yOjTl1D8dboBlc2+R3/CjmkgajQkL4Y1z+kGH82spKbrsRrw P+aoJYIzhc9cQR2wk8BBBSQXTGngt4Vlj/I0amTftOHXEZ/SGf8pjT0rPNSU71gBCms3b5Hk9HoZ zkZQOc0itKfQ2D7ijnXfRj+Ogbi9Mt6/flYAY/FdNMYg0MmQ0de5FC+Jyy5Kfw0a+y4MJIYN3Mnu IhyiXLQIH/tFnqt7g4NHndn1hfKTUX/GHbBF2Dvv9iHbIcwROy95Ekej1n0z6NfQDDi9sPPwyyK5 PMMboztjthg7e+TTO6bz32H4vEQdAy2tEgFq4XTNTcH6mf1b2tb7pI+eKzrmKd9F6KhjKZXD5Td9 mgJlIzprsLx1BIe9eOq6J9VlTRCXTQ/QLiWRccC0qrCYnoqk/VUrZK/zMf+5gL5uxAysy2amOn9r yteOvXwgQM0rcBj/Lfi/aTlLlo0ERVKPT4vqrrjcmbqiCSVjUAzaUqJMobr20U12f6KK03zMOjaN zw5ShM7vNfV4VkuH31bhMIRRFYrD0qPcbZZuA7Pm/W2m2mSqz/jC5Dz2WcSbtlj3lSTfuL+g2ZkU /1NIlaoF5iz0kkC3BkHGRdO3LxXe8zzVFEwmXj0CzCS9abm66BcMmrqw+/1q6JNn2McEFDoC1Dd/ rOkpOLWGHoCLn9rbOcZWRDFqYF40/nHSwL/9oB7y7x7vQ5ogL5xamKJgCpjpXqQk8l7TPYI1z1pm y/RoSi8A6LjfhTfGEexBZTu33Bz8Y4lM/PHJSiJnzgRFcTtYbJwt+SfZdaMaqqtulpswhfU39N9l SGbHNJWyvsUVY32uUX+tWiZvHnbaMI/fTZSGl27IDqJv/jr0EYvwJTjExdlErwb8+rhB0+IuOTKM c9Xzo4ClsH0xW1tNvFp+JsYGankDh2Iak3b7LnI2UsWdaQ8eFuKxJHyG702X9u4kJ/uJRnD4dKox uHx/6EI3z1MnNZ1RlmOOkEdGB4G7Dy6t6uv+gV3q19LiekCrRvt0xUJ1+EfId06Jc9UzfMsM41u5 5LJLnmuY2p+ycv2doQzqwy31ia+9O109wlItrCURiaCPPdyKmzJ0Bw4/nVe8nPZvxbvmD7Y20Pof 6C2jXEe9AHymb2TkS7WMx/u9WSUahvZgtFNhZTjsBNNDw/WvlnBt2Iu6oi4H8oq/4FTyF2SElxcd Ai4lUeDKP9PNKpZSL7mSeZZ/ES6Dy4VJm9OlBHEKutRtu1rqr36bQz6CbdDosb9A5yxlz4ZM+YV8 lZuXQE59eYPR+771vAtxd4OO978SwBGJniWQcd8VfWdZYHtgixZdyMmsgStb62DsLOmAyxc0hRwo zP6GUXmAcOBPm8oiPf/D/jxSiGmnBzxETv29SutplJ+rl3WFO2NICsNx8Z1qH+8x6IR+MJsmQ/qY U8sEy2GfWlaz9jIB6FGKpum1LkdOGDFxxkyXh7uEpSh6gexHQCjKBSUNp1FoalheVXNB7i06n9FQ mxMYljByzkKuopeuHGuR21HcOdn92Uu1Fv+fDq9cogbNhCsbGyEwdJcS1Yx6Wilp+m//GnajrbLl QDhGdALpKTVlucoqzk8ikzlDVLOPB6Cga3nqp3cNDgtDJ5D5Ywz3oTVvPNPlbCaFkUdsQpfsGNKd 6yAR6SOmgYIEA8Ehkzo3NrElWIfsqXuCk9WRRnwTGSVkXVlCcEMigdxKmBJIylesTRQVIrmmZsqR R/JL4pBVdkkwS4btyseq0nXZVUj9jfZXcvNAfIF8Mhsd6otHr40q77YJ/i9K4V8vEbI9YQtcM23s qwExs0B4qzY+RzlYTi2KKakY7Lkg1vxUqbYF7RLd2EdzbiavfaLWt/d0WJMlyVRySi0wdSSP0+ej o0uE4jOrUxADxxt7GXrGdNSeNHEtGyhhS0eflm4kiabmXtbfcCfDkQLbvt+ilyn47YTMR3u/tKBY Ynx/AzS+Wzs/E8wLVKEyiWulyeTMjiTi4h/9DBY8bp1rxyhq9toG89g6C/QfqMf94aQ+FeOzTuxV +GVo8txk2TfYwGfKBN9YGGNePqWGqlh4QmduEHjC+BUmebouvwfyISxjSgrcWVw5+WEnnAmY7WlG 1aXyOMGA18xUyd7OIYrL6idmcxiT6lZAjwvQ4LoUC30ATDolna1dl+B05xXjS7KmP8DkD91Owyi4 7Iq2yWi0t7jZA3TXGed6MokmciXWmVOMWnVdtrSkU+JRvHDyvgUOFQtvW3kqMDINYO0It/mExakj 82Y9WeSJs122HKXd0wt4Soqfx86Ak7xDW39yywdXPfUn5On3O38+s1ktzlx7iHp0Tw5qZaz9qNWD muAflol4xIbLD8LOjkZTurjoOhRGw52PPiugbEM8h3xcIE41mW/ZCX+YVEbUH9QK8scMiYscvjiW 8rzw7FRFFnslRUb5ynFb0/hpEaaIjUsvY2WGYnLBwinB+JmYdUQMUBbxGTdB04dUCLXSw3Hd7+a9 wmaBZPJQgg10GJfoiXS3KbHqzKQ04n6TcR+t5Ztqi5357m/gQB2yjrE6tontXmeZNzHfqMcrm5EP zdmk1t46ZyTmiuvb18wX6FYLrcYdY8dkQ+9ga1SyqgDoKN9Z56B6zZnCxusxzGPa95tkkYbvph59 XpTz5PL6dadEkNjDwFt01V6lpGhW7cekcKAeuEdDYgC7xcypjr9J3XdPVLce6VL9Q74mdtfwnuza y9ifGTvRhppGMli46tFKhIYR6vJvQNT2bq87klcJLaUDzmZWZhYL8bbG+VHDg/APFUJQSkukHOOx 6HtjY6fT/YFFD2v1nxkuaShiC9isCEnNzy6/FXUHF0WWnOfFOFXndwDwGKyvNHlhymC0j9AvXlzD UcIHG6Or/BfH0vtJpazBA8pbAfBplw70BOwXMjXNyBTLcGUWx66ZyQlJF5ATPC9SI6vxTs26ONgE YDaQrNejUD4OYnvphH01qBE/+u7f3j4AAyK1wpSxea55KWRsB4G2RLgPxtdL3yyP8iHFAtDtkzNE ur3EUuBzZFGfVB/MFUMlTtGJySxYu1NB+tU/MYp0J5TXVgGZ6Fjm9hnAA90MDt3CXlBVDL7Y46MC ecV4NSo2rDVeYU7uHJeCq4DTuPJf2QK+iVWfourEWs7r0UVvxu3513Am157bZt4SGmbYmBytUevO rz55pxxZkZl4IbkvqFOkfLZPcMLP8d0MhfTsYglkabzZX9hRcbFyqL6iArh5JWVbVdwmHNOkQuca CZgXflWdzkFVg9Pz1Z7lcnqdUdXVbnMwZtEqh9TJSC5KkKYjbsB0HB1wOvHOaaHukWrHoERxg9rJ CSDBmlMgY7AxKWfRed6iQ1h5SOQHUICc2SKl3AjGBF/aZ5g3rgeFsybQNzLVDVVxCTtXtPOF9ax0 IEV79Yp9Feql43KP2DlpF7PVDT1VHIOelQbCKHL0q8DBvWZfwVtF/PIEgEturBVMZ1ZHU+QFG5W3 U9giPWTHU5PCfGrNhgXvf9w5QhtZL8MAXVmZ+6M24ydzUraBRwRl1y0WsMdAwd71Sii43r/gyFFk fPhH4n0QF04O3ciyZhuItR5UQwiYpmurB4zoIOucwRrrrQI2of2VVmGSbGJIsQrz2V56mbgeBdy8 sD793RFnPABoe/Y5i6L4q7MVgoGzPpDVOVg3eYhl/6QQuhuywe3Ssek0fKpTfi2vOlyDtHYg+sHz 9srm4ifeWRXOkDYZEo9wzhs4EfXIknRPobXKsZJdrIpQmTCxY5LsGNcN+9GpgfqMcSUgqQ8pC8Tr zbe0XN+4hi+swT37GoxeIpPUG8Qo9W+lUrKmiB+pLGwlhY7GuTx9hnNF9XJFtY0ADecBPViDYFpz X78HBoiqZ9J8ibCtUqCqr6/HXU/G1nhmZxHiba9rvx20XrSnRsci0Os1AGMzMfSStQt82MQI9rWY J0aP4sajVzk+/LdDen41WAMEzw8+BM02DGRKiGqlZpaIPFO3IgbM7hTnn65vPST7ehO3nujYfAbk lU+AI4+iVTn3b47spQgDzzDqr5la24BxY1hYnJYJCHkFBRO4zcGPD9qUy/skZjaHfzs4hBQKlAql 8qIg+7/fm8oDKAF170UMpsyeiGY4eeTu9ZI07+c/H0lZTMFTnhoeLTPOthlMvcMCj6GGV0fT3b6i n0mpNAz35bCQoesX4mfW4NnF6LApXOV4sl4IqEGxgtjfqZnBwSrODIvB8sp3qK1H+rNEPbOymLdZ I1FIsIhhuMWxG65i8/YIPJY3cWpRyhOQX6hAGa5loyF2NpqzrBJxYfzvtSO1paqJtkZ1UlwEYawT OehOENx2Jhwd9qFcHF5RRe4lZvKBXUxCux+4JgHJpuvThpj2fu7Vw5VzsumjK3c9DtjQyMh6LwAp 8rt7YpUbKJwWzmuX2SfpsGNTSkwJGdSZs4mfuh68kCzQbhRpgtNUzlQtAP1DfJ/fvGnHD8zcpE4V H5KhXnVwKYG3YWSoFI3IfIzON4Xm9q6RHKKpeSeWecmTlysQjidy18V0kZXnfzWToCz2eq4z4NfO dlLUdQ9lLQ0+kt9It4ihV2aNgcSR760bBRPYzZQcJ/TcwN0iP+h1CJQrHqp0zhl6+e3FPeAx8yDw 7CMwv+VzUIiwsIREO/AsIAIIbEe7jxDopVBFm/KOUfZ8MGJpm/siO66XgEfjRVrOwzuVlVrOOy8M 8I9XqPK2eg/TjQCZ/Hmhw2ZBSR/MrqNg1BKFIw9igICLjnv2BK6YqMjq/FhfH+VNSy0DOCBWfipD UpbKlbG4F6NRqEtCyRfZnCmW7Z8SQpaGbAgB1y51G0upWOaXTY2j+GcegfPbjB4lUo+B+T+eVzhr kYp3QsNnAkjzKlTA1BxTd4xgK0X15EA/Ql7gkviQpP4eZ9bF58bnWInzQRVXEDoTAaxtFejkDV4q a2aD8IK9w8DrediV6UzNHQlIUSrDNR6YGGgpX+ZAuxaiVELmkzI3cLuMdfus6EeluGjQ8lE7IaGz dupd9u/hkuaoiuOQA6wddI/5Yk8VkWtWfPv2In8F0TCfcy1+vu2Ac0bOMR/3SSOuUUk4CEQSrX/k O61pVsFJu6rEla5cCiCLrewJTmqjJhYBTM3cbMs4nJxSG+eUxcKtFbg4eGTmYKqM5EoVOW4eUx8z teJWHxXkZg0pHmSB5nU7NiEHV0uTgzXapsUZyvA1e+/o18TzHXVnzTfQN/XhlhP7JVHn27nrmP9o M0Y2QsrQwdiR0xNchmVY7zDwSA1jwk55i2zi0B5aQZlv1oUgVISQLzcMjhZC2XltSnhgOya8VW+5 GNGF4tCv1nWSdqjNlND6c5gs54g26MSacCai/15mpCuYdb6vF05HuZM/vs0H9ncbankNI/rvwZvs kjUwmEphPsEd3ColgtXfEzykzUsgdb3ynQnb+J8tL3b/dpAh1o53q5Q5xo0iAq+c+x7FWQHgAr0x MmYOhgQnMY6ox7GzxfEoviUuqq6BL5w9MEUt78ISMDe4R2yFsQHg5BblqYlVmbsA2o+ZYMAQE4fb dIBqmTsUMPV0S4W0eycZr+ey2Yj742yLbma9fTB79fRGKjWcpVXYhLKkxW725GlOTcbX9ujLbM5O sCx0v4/ydVQji+SMEYTB7drtz4+TKc7vukQPEfR4nLjpg6lbLnDcampiMnECa6+qTO2shmCgd9pD oISfbN/rZdI3HMF7U03K/x2JtiHtWPNvD0VA+SSTbLzrBKM0UnsBaR6f/wFcDB0kXLLh7fgZ/hbq 2G0mqFeFCKBqGyWp+EsXoDdnN5DuFDa+C/xKJPC0fcRI0eslgXh2t3GWgX4IDPjF62QSmGLvz0XC aJNrxEp4TP+cv5pQUCTBeaGcVcB5K8Z9mjSKgblVTwDXsoM9CEXV82gG30UYvcu1yWaObMLq6NXI SIGr/5UaEmuhVuCSVUMFFm3ydnmOZDC/92DubHLf2eCw5O7VHUKJ475CtCGGLyd05rukyiWsAadp PEdHU6VcLkuiHDGQcoahftS8qWyhWQvIE2rGMGGlNUvbzxy5zpzQ/oGaGHtNMbC0FmREobeyVTX2 wArR0uRPKb69qzMPad32nyJJeNvkYoyvMczwqARBN2Va2xBCYjQjmIdXUBmYC26GWsOOc3F1ijW5 CPu9Wd1kZNU0UO9iI9QBcSlJIzFPIwUY1g6F7Q1XeACuHE5FB55Mtu/iRqBVvcSPXsvPTEA+Xu8c dmED3r3c3SkWSDv4TBS0YG/fq44LEaDpRQTkezK0LxJ0DElXBVEdHRXI6rM7ghBco5RVu2jvjiSS ZFEzL1Lxn9+xVpzvbMmZoXZNUPfyFS01ERDtBnB+g63qYs0hScurdH/+OxCbXovxItmgB92aIw5C iAZ/HIIobotCoQla6El3RcxpwlMr1sJ++umJr5dJn+sV1OUMLr/xifKmvZGYFNUd6uP8lys/uhEw +hEmhT1YxBxLcv8TNN/Qbef1g6gnDF3pW7eak+Q5uOxJtTnb5+yDL800ee1hXSIlmpFNaJX2M4ey QP5e8h9tBBigFBWxJEz9lcX3CNbvnfUB/f3hUSWKWgLLmFi+uuV22IfFISmxqCWU2e3AriSCtMkD 8tApD5gVi9qOnT25hUHuu0DCJ1hgYOMBor78dYn5aJYGMZ9LZA3HW8FlJYAhcsS0A1QjShFStY8R VFdBxliZpebrlVW7HKfYsgYUICxCDAG8K/KRnV42c0rbzd7ucqKPU2Ro7E8cANgTq1KghZHotNI5 Dl+CQ3kt8ZOUJotwA18gpeEJGWxGONayoTlAhQ1Ja9tRybV6d63PNUIBxGjldkevKKnHPktO+YXp nlitOmZG0f9u1nAhlcq3v4zuF7Ac1nJjD5ZDV7no4jLHHcInecTVGQON9KGXOYczKtohBlhwmiVm +An/FSvv7pkD+qf099EY8B9EBz0cXWkkovTu9cRR2mtCBstSsakUE3ziVcjrAgMOk7pVbHfh0BoE gJ/Rm91i5ev5X7FuQASpib2gqNmkMYCigXqA9/uPRv63Uufyo2LMiZ9xP6v4YJdoEzaj35CJD0m/ wO1+SYtahpoybj1w3v+vLDDKO/OeBe5yf7A3Po4g8CprL2Ru49D+gM6i0xYaf4/Gnp9FqJo6FVYy x6zbWdT8jrtlOtRR+CTqjiVex6TccR1pxCS0wHlKSFTnuq1iveQjNue4GKzQxRxhmJUavtAhPgNI 1qTHacQV2TBRe4FX5FAoe8RfezFqMZSg2Yl6m8uSKMgV22VD8noh3tETVT4d+3AJGP6VLitcuYZ0 RR+dXVgV1S8QaUBGvpXIqAY3Kbl64e4qGVco0vKjAecLBLOwB0jo4qcrCWxARui5wYRtsxFubTm5 Z5HqOhRX9COF0URja2ewBSq0NibL/jtV/DbFhsxe27SNqOSNSLTG9/C9yX3NDKE6fQfrr3LgVguK N8OFsZT2kCUwfKNO4uhuGYH23MBVr70LiqZLpJWfb87FaNisZvS69ed7erefsxy9UrVvJq/YO/dx rSoJp6IeBwdQfWN3Sr8j9oq57qgV5V7zjs5udS8YyGVkSQH84aAdYGPl/6oANCVC6KS2QrZ9oxz9 KWiHrpMEQTnTcHc1w21ljQwsizuC8gZaDHYY9wv5H4yXVdeEh5GnKQdqM5BP6ogBJIE/dFPMf/4t wxUQFHO0GEbITYvBwnTynjVDCyFlD+pdDsu/NUKeVmbhPZsT1zCuoeuof5X72hRnRRSTd0JpVA7E Xnn3sqY4iaAR0P7sljBJJamO4+9Tz+rI7TQs7r+fDMHpwrfZQhth1zmsXAzvDOYEtRW2kodTFYTW SRnqUKF9d8jx8FDYebUYA+3IoqcVIzJAhRc2olaGXbCh94dIasVjR+BMHnLeGb1uBb55Tj6Q89jC VfS9DE5g93aC2vEZmS1m0NtaE7gte0ZvqCqsCv1idQ5Sfzmfk23/GCU2MJlLZHRy9XCY9VL9U8kc O3LiWjzBL3JiDWRn3iVg/k9229CxUoSlkdwzePriY2w2hVu5IZnH/KCNY6ff3yHoJNAZ8txjVqrk vHa1978lRTrI0q4nEVnq82lWyuJYCe0STtpmTBBilkJRckQcKs916OsA6rc/8IVGTAbNR5AGkDGD FqdFFNr+cKqed4NX4Wo2Owd3LOhERWxbnczS4I4FM1aSKO6xNa36BrqzQOjAbcIq+ikDIFIGdJac 620VJQmvdBILFJaI8he6rrT6B+t3ydfV1y465GgxkR0X29Gnbfxx+Wneeij0/5GgRuoDWSpXuCG9 YG+QVGYJps7v/bwwdJuxiwfVlB97fRWb5C5m2cFVTcFDD9C+CekYpuLVGNY1DuR7BfL+EoYqc3Fn gOIm7yKy8m4xFv1/Nu4RlQD18pt9zr9KDfKIRcnT8DSDeAyqBr8LzYfOkdZ8XKoehDNVtML2J/03 ONLf3RvUKmLARH1wNYcTr5rg3O3ZwDmr2TPXrUeogazhyk1vtCmedfU7TGKG+5n/cpkmFmKa1TEj /MWInCQNqxMRmajLQyvvA6Y/rwd4Bj0Q0awUvC2BnU8Aq67Ko97JSmin9bEOsb6yYbdzb9kQBRxG x30bwjhOevBojTqvWx1kqDxS4lCUol2w/pdZ+RVVmGo0Zy+KdGAIKVpdiWVGDlhgMUZy051Uqsli nlEV0pnyg8f/v9iSApw4aHB/XGAOHW85zneFXuhj/ZwjTFCizycHb89S+Tqafxm1dnGJ+uUCOSjl gwPcW1pNMEdrIb/FOCrUD929nxWS2WRF+c0CMqcIg6wo2Ypk2EAR71XE4SuEqTf3Vc2sy/OoNldP SYlTGilC4cFLqo4SMG0JUBvMSh9qbEyCO+wVZsd3t6IJhm2afTyuoxLYqJdqSMFeurgIK/PdeKDq A921YJ3PmLh6MH7UNxl/BvhTFO/a+C+ciZjhQJtdRROvI+Qzvvh9gYsCNcmSty9iQ5qRfPbsKcvg tl1EZhTQvhz7T687dj9HtG3H94jnqh8mAd98Wdylze6tcsUvt1+PDgOjZBQI7udc/FPiISD95wCD 9bWRudveS/lmCUJZN+6lYp4+5sy4egaaDmFjpPCOYre4MsSPMTcfouURFqG25jWFWlXfDD+yGU+P jQDugWCYMk3Pe1vN6LbvFDlZlQTMab31Ko2ZXo9gTzFwxI0SVCyBkV4Z7LJtAkaOc1XgdLqnxNYm z1tGy2QMrznf0V36XhDn75Wo1y2J+a9Fvg/+sKdgV0y7iAdRPpzoln2vybZ3XIF6CSNUieQ+75kQ E/WHDeEblMtCVehOf31m+c5980bYRfYlsI4mheVz/daJXZGSU6z0txv2Zjp9Lv5IRk09PX51nex4 yCWZ4o7Ra80DyLhWmT+ZP7WX+GWurhL/E9J2o9WYvmKgnlUQdcq4EZ8ZQK5kXHvZAYEtBEy69zL8 PHM1e11hzTU91rFwo+8zO8qI42zB3S+ySWMjJ2TbfePV5tKACqls8BBQm5GrFFzMLaGdkSn+QCRg VfDyqt2NC6Yn2igxqXVGTLAuLb20jLBP+tRrh7FqhuTbji5RURoTZtvy/hjyE5JynwikXEh97thG r0LEzwmQnwsDUMmltH0BXCNxPjtymw5xCemkkY6r8oWWQY+wj/bcJTsO9xUKjFlO89gcrLo/Ax1x 6A4nH0c4Wr20ZXEKtUpEjDqWuWMn3rDLCZrqqggqkm4Xq0/ShnOs1F9uiJSXpaiSNJpmL9t62kJh oK33ZkFeNeLgPOzOB3eIWf8cbdtx542/v/haOWcQH5Gtt96J4skpgFqLw59bhL4ZetcUXl/9jaoe AUsTYKluHoGuqrrLGoqw8J6FjdbhYDOlwtgohJh9JpHSEYxYLTLfGqTVHzvB5Gv7yeIQFM7FVMdo pH/LkZMi6FxtBDcSWDQEZ9xUhs4JZR1Cb0JKpcJzMwPgT0VbYXxSlhGuub6GaGcY0x2oO5++k8lT RHFd5CA2gAHc9bHfxq/bpLYeyrOuWmghDRnnOqg3rNlL3AbDVmrIcPcNKPTTrhB4+hMBPphXkQlM uOX8wV3KhYnbQH1vixcAx5wt9/Aeh3SSNaExSDYGMU7kJqxnuLV9FQi4dJOUdAVDgmLxjx0H2SHp lFo2SgXJGCy+R5XvvrTMTDr43sKT6cI3Dv4DjBkSgz46apEjVRERN9z0wrprjlL1F8HMQZm9u8Dp 0uIM9nh8Ru4hFos3bl07ZYe0H8pmUlvSSZ6LPYTr15pyuMuXVKQMO1ksn+QkJJpCe1WD+jLvZZq9 5HD6pZUq28qKb34GQOdNX/Ns1uHRt3z/OKKNS8CZcSFoUotZR35olPXa24kcJfJJMJVw0AcEe5ho Qr9AVejjftHMir8dDlfcGy56kih+zGgtjiONrVWpZlV5aicxVjGWPdIZlq3GcVO0Zl7KMzI0tzQ+ 4/Wih4xlx+B5B+ElmDzvrCaRF90OBrEy5AHsfyRD2Bjqn1/zC5J49jyJ+ngpOpCP4PB8r37VSkee S8WoXHXZtYuOl22R/LNOt4h0UqKX0DU1lNEu7WQGAOpoJ/umjlKvfO8HI6ufm72yZycgnB2ZXldZ J1rwGb4BnfHtKG2bozGUOhLElLi2wQh8G5WjmxRMAOfKNSlCpzfo8JU/hFkELZGAJaVH2DlGX4zU qicHmTsHjdu902hVvLdJtL3+xREnvMU2RMA6Iymk9jAmtPHFFK8UODQgwFGFDKtlf1BGlaJhkNCA 6me2GipX+m2wpB3mKCYmg74dHpmOxgU5FxoEqj9oEGbzVgeLy/nXa0PTkRpd47ZPZ6JCi3akDHmT l9I9Do6yuEUGRM5dVb/fmwMgxxcuoECDtOkQ4/uQzUwm6xO61GqKtygBMslYGNM4gZCRXysvzTO3 CpTJ9Q4FUy334VlJf4KdA3/UDzgdqd7NcnBaNQ3Oyl+9SsZOkHeBksUhX/JEILvZiX9v9QSle8lT 2HvCFNVzGtzDo6oxATRoxHFcTVKopwYpyyT3TTshD+OOAol5d58IeXuzBGp2tUayqy5ANGVSwFZy qz1zqrf/NkOetKlcgi/PdLamzWERY7JfjOgi5H0msDiPoO/GcboDkwH2XICvk5K0OSiqsKjsNzt3 XByr/dyqjkpnchvM5XeeBt14COWGva1/wGq4KhSBk/VUMIFvpShf+IbkNpxWnwa/lPRy61xJ7+9Q V3MS3UIO3QG+XXDkuyO/3UIvqUdxbEvEhWQbPv4p7GVFSQFgKH+HJPU+NwTo+YtFcjyNKHedzl7t OwP2JEhGoowwTAZF4tylCS+WCjRj28baqvE9/bsKzBOtbfRUJ+5SMU1EiUOCuajypDKiPqW2uwuK +M+8zZfvHkFG+ej1ozbySN5PdrSIQydut3nzxLGLxSsg4ouYtTRQjA+/+I+48j6IjHQw/GGZDnKI eodjy1VTXPFtLTCqgAW8XtWdwVOO5IWh5yo8fDbhvS3gl37Sv18DeYJFB1wi5BSQpAAuat7ztdTO GIbLV+bks2ZKXCDms8BCB1K2gq0JPZIjz2AZvZNfCVLHNhuLxF6+jtWhRzjswAitVberRoN9WdG6 +YJY0+NdCnehbcHM8eIuMtne7Vx7Z8Lb5g+cb3pSZA4onyBiglie5uJduk4x9R0NDtvFAm4+usN+ pnPbLN1NDe8ayEEI6N9irQlqTAXeLUKBCHCtaKSLLv55rjTb+E4cUPE4UYV86xKxjcEkWMbTdUPg Tip0N1KJDY7a0BUjzYoMJ67mwWokLjxSFSXdrB3QT9DiTArJwsIDa9lMp0OJtJm6PTWwJW3ZQFgr 8cukOkdYTxtz0FYUx3l/Q1s6qF1ySPo9Fh+weG5+Lg+bXNi3rW6vyOKrGF9GURoFkwAXIgy1eLDD tzXYkRJegbbrerlZ1s6D3dyArAzO1ZoP1avsMgjdEPzG0yzLVLMVshQV3xem8WqrdweD3FCO/Pr9 f5kkUpgSG9bhWazUVzlNdaGPQmbbNb8C1BX+fi1hs/P0Z0Lqpi3k3qDFQQOIgXnxk/e8xWv8JcTR dqOOTJEVcGSeT2C2bSFsXENACv/zevMXtxNIU4l3OTX2dGY2+v3fZJ5cLrusjVwTIFEm5fQCij7v bJnjvIh56Pp6hKe13IM+ZTgQAx6HPJJLOeBeIi2oV+BCDpgyFQt51SWhbuPA19OatokzC5quLkyQ mBUVLp3u507maaBPtS4ZX//wJqibuL4FBeAJGOJKIjxoLG90CAGjMktbSUZR0TWuQEsWbVZPFzmr m6W6PoDpbn7/VGrb4n8jehQldSJeOmuXqplhmJ2oTp++1JhVBh6ibfPWuW9GS6mzVOTLiKSp051A oGBXECIjzoDQYdrh7GSNiV7aXBAnhZ+y0JOT3hBqRBq47RA/Lksgkqs0mnLbbkd6bwXM7RO34kMu aCLqgQmORvdIWFe2Vgw0a34vQxiURvMTEe0azZfzX+gNnKZ2i3jNsNvayYbH0pKNB5O3kWrCi6MH 97Sw4SZJd7VVlE5HemS08mrN+++MakwmYlSwRC1Ag1kkElUiZ2KqBsbmMXJh8PLASrsqzS/iPbvZ IJvkab7CNAEHt9YuAr5RtBFKMOyC304Y3DnZO/mfo5NtW2GVaRAhxKPBZgrlAbj4cufbRJI0LJpU Y2Ji0UQY+6IHN+FrZMxpKXzCBTTufS+PfupRNmWFfLi7utXs5JlNcwiXygeL9yoEZccSL6NrhxoN FF0IoRsZZ3Abekhc5wKHBja9F5D2wM0RnBge+lpvX/aqYp7j5aPGAFR/AVaNkHik0Fma+bF/fARk Kbv2WHAEm4lh4ESWtSebXyQltjcGv5KOwTnKkuQ8FSq6bd2WEAAB9Jih+cWkf1fbzswOkQe0XK/O UpUR6FTchS5rXNwJwx4xtQCJ+x/cDqen3Qv14pdjVSnny5EKT9b0MCaVjxN8zt6I13N7jKCDAh5t gaSLpqFg9TigOnAmNiaAskvZHAbPhAE6ZgOQy2l0JAnH+Y9VMA6Yuq2ovCEvq5GtR5bMEAWbST2h SV277jHU3SrZsfOjbVfxXymywb5WfTvdqh9CL689EpMOY6GDg8mMMDj+Hfi0mjA8/V0k6/2yCV+R 2GoJoZNa7BkKUMQhUezqUJO4Fh9TE2lFC+2j4YFE/lb2D5OrfC9rLZXSeLG2yR097VCytm88IJdX GyVj6+eQBZs1dDmEBAkHLS1OlR9qUjzz5yfTYcKjKbwQ2wgDJ/tJ7kdlJ0yXhgCMN4LqBeb3NbHC AHoKl40FMXDE99XjxBcC3jLJujirD+CEBSJ5ntbb2Qd3p4PJlSAoEk5BHvTvYoq/gfBjvkPa7dif TElzwxwKe+Ifc3MGQJ7VuKrQkutaMZrYgDibyjF7cNktlMktwSSoul7gxQgxFVE6nmY3DO2OLSIi BHIuwG4tCUdz1XlNPsN+aka8FKYawc4VfJJQZKjwbGAxVzq+OXO01vFV+pD65TklB06mr+pNZZBs Ug5bSviTxtbIP88zIiBMi7L+7dfnl8Y+411qJMtV4hvQOkzLxLbJnYVqyCkSzWrWbLbdiO2maoZB oSdOMt6bWbA2kDH7kG0Tl1ZAtFytCtJjUTbJQNVvULiQrS57PgWR43uS3lt1l2UYR6VB0YCx5KtL wHKsqPwiHKuVHE/n3OP5qCXPk7ocujQdacC8AFYGpj3cnB25vEExczJO5dHDOAxYc5ED0mtGV1rK e9gisLw/2i4E1yGs+kNmU6jv33ULjgcqYUbef4hgcZ6kmnF83BTk/xdW98fkmWngXJeGu/BHjV8v J0ZWU50nY5TSPuw4J+dTeI57l++v4HIEr5AII3fNgWpzEje8Qc703JfWvs+Mruh7Z2fkWH8rF7bM yoF88PDF+xxnaqsaNeLRgs1EaPXHLQFU+uWLShoWHrfC8HSsJst6sfG1hwSWsWdBYXdN2BPCQsOf KJqovGBUwqjV6kMOcb9i+YCZnI0r9bEEuQKHRTjXiVBsaJfhzY9biEEczIDFepV0WoVdI9znrv/K SFyw2Iwli+UfMqXYMpliVKaZtYkBSyprFsGfP0/4b7gR1kJQDyul/tKomSyLqlqqNsDLZBdiWGZI D/YZOmTyyQKS1FXAU37vsIZieTMTzStpiiKiK8i8N+jceF6/naaqJtZa4KntJKrspCC1xIpSm8cN Uu1etmG1itjqsgmJCIC5V2xM/skMxHMDL4UchmQVdcsx+rkLV0aclM2K281RxOkDEFgUx2ZYkFAP KmM/BBeI7ZpRTq3hGTftlprmpah1KXNHJfe18lRdLGBTjfFgMFJavDsYkpE144JQiiRDPVH0QfZ5 uXDSKbmGB+L9rGb51tTdy8ujOg6HoRQx6sMMxCIAFiwjLE0tU1es/erQFoUrt7JD/NwpvBrPwVtS WiumuFKgO1xjCtgZKZIr2rIQKRTeKb17R7+12etPBlzXxBbbCsBGd7yU04z8/RvfDMDJ0Un6OHp5 JEloNkphpRhyXxRm++3n/taZ886EfRDevTxscemlbznVvIYxeARWqd7VBNLVkIl8XjlPrsGl08G/ GDOm92XARXdf/Xsdg75ndfsgJNYNEe6F4etsWlUS8tDfJ+8/D/ZYMI7HEVY1N1iwLUyhyqsFyqK8 dSlJrfVT7VfGkqQSrOJAjA66aGeWIrnvH4OdrmvunzBqZ2MmClHPMdeab5abOvaF2bhp8VhjjcNX Y4uQzm0V+IwRamWkBF0+BZK/MtB46w3yG+kirJ8iykCOHjplp8/BPUNSaMWZ21ewVvL29EVckeCK cNXCXdluTKZauGhXQ15mNGBatnnbjwD7g+BRVStvmglZk582gmmsYGVluIC765BeqyjUPgqJ4+yJ lcCjeP6MPdC4UYBi8eODNC5Nb51GfggCxYWwCmWSy6O9HLg4S2UM54jaGgol0mTEYU42BC67iUPI 5hdE7iGMG5I3qHbpFk7iypq4MNpiRKwQF++/TG0O0YGWwV6YjyosiKmLevPbyYP6RkpNCh1PtICg syuC7ePTmxJLwG5Pno9A9NaqLVVxBOuzuGAVEG8DYvsV3Yz9vb+80sHgYLTkg8ux/Dw+xaKhqlp0 0rBSGR2/9VaWx/WKdx0tvzUQH7iv9QzG5uJondmsQhUapbW7dzPvzi7Bj1r+Qs/0uPU7iujNQ8xp VqEwuaPaNJP3YSx+qlvVX3N6eytnKL1oKyxJcpxlDmmmJd8S168sOdRugdYpyetNC0rCq06VDqXr D9pTJ6slwNlrfXRHc47Idnjqv4MidNgufYAPEFwnMLwDYFbQNVVuLGFC2Cwed5byN8QEsrPvTDRg 8qWU8rtGSa3UzoF8Y58xsvwjVouyh2XjEgLb2/2zbRNZwl6pRVYumNzN/pB6IdYMDa43FQ2iC7k3 9af7QlA77B9pDb6G+0IFt5sMTyppaLL1dx3OlbdVYSfeGiUl2o50681l9p+/YXMxK4ZXric4V2oy Lmn5A5iXVeCHJGCuw8bQsFgd4PR9jihgw9YHo2RkGgbvH0GqKvD9VuV4zlfXxdQz4n2Q3YtPRf4X OUAH1xGoGtW+WbgNOceMyjGMyBNtGR8QbcqRv2nA983mm5nIp0mOhHnmOHl1aRNysurPkBQQvTyd 0vk6/iN7ZiSfmRGOwdAlLcYZOgATpG9XW6HOzq8drmfFDuKEVb28UXsGftxzIpe21/OYrYO6Hmzr 3PQuKSvvuP+GgAXgy6SAIPSg/KU1o2P2vf0rDcGDnj8mnWKd40mzc5ff+QekWHss3hF7PBEfPVey snD+SEgJ6D5XXhk5DVW95b3CCXDylmFU8c3RKjK3YZZUKKqocrld1b+7qWxI8tT529j08jPdhWNg Cbfk0CDnZ7qSw3jI8+AnJ+QyB+WYIEnTPslR18AqJ/CWtbmoUhmBwZyPKLvrbyKLbWxqiG8kvf7e q6qsU/maR5hQzBKSncx0ERvfE5H1zEO00JbUIxXOrcuVRQBD28GuVISwOxZ4lH/fxv7aom6WRP89 tm/iCNvVaI5RX5iFVpQg+r0IqaVdin5l9WKWj5oezt7l5mrq/tU9INpa8NQz3kAoJudUntNAb4kg KyLyMms0p/onPmp6XmGxALOmdgCI9cd/IBjNgxB+nBnticlatl++SCb5qiRRWWdvf91k+dFglNgU OY8rltHpUFq5hC8Cp2+rU0kiASMrLNVb4hOAZAKgjgumjl1bfc4E1njWfKD0ORxQTmWXzPRMyewJ UjHQBh/THth7OawXyzhv5PhQr6oWkfu5nzaVWfqROvOioIFWdf81sbGQbI49SSpSpNO4ZAiyZWdY 4bqlv18ZYGcKXP4jLBiTuSKhfEEhmCFkWD27jFAjHvdYgK69hDS7h3TUxsf2JlqNTGLlw7Kx7XdV hwJ6dQQNR5h/t+LQmTJ+8neLips+CGUyacXM8KDlD0MDOhHkNMXvPZszSQg0TQ6HHQkNO2p61BIz sFxzqDLanGLo/oU++DQa2/j3eP9LtvNfujktrdlMWlefDITI/qU+hbT6MRFaqMM96xhuD5HasUy5 VDR2+l5tGG33DwrN70DXN4Cbklbg261jU57qLhqRN4nIx2fU9EEDKRI9CBFEXYvwc5oZ6TIFou/T igFyZKSJIzwKMZA1NSEpaStmQlThRYQ7p5Oxp2EE4xHfFs81SjhNzDT4/8L5g4mv9P1zdcPUavHx BnlSoblOKBYx4X+flPPmuWigpmxifhZ0YiqPKsFFSnMqSCJbJs4ohhK28njFs3qSg1SzGcgLA3Hf xIK9vgFOMmeBVjsbeyPLzIRpclLIPYGF5StnVHKXQj02vfPMOnKwzdr7a/kaD2RRUGqRSPAtXWnm V0PY5+tDtOyLwVkCCL9OdHn6Z4Lqvc12/1HVh4cX0eYMuU1ykbDwhG58hNB8EjyPVJ81oCX+i5SQ npg4qmiDvhj00Id9gIs5wmxoOph51snJUW9XiDcsGlgw33F8Uiqnc20zViEp3fusAcR7uFMs9FQV GQjYOrUiCSVCHhz+WQ8NpzfZLxnlSeAaRFRYC6bDJVcle6UFWFMyPFQ2/Qiq55I9f4WGVHG/S0+A P7E8jAx3aM1Pj1mZm2Y28kaSgHjiwbLrr7lHROzPNvjB4Kg0T2v5kEsJAhLBgMCL/s0rasWbQbZ4 xoq+zXMiIWhBBbAvsDuxl0TceP5u/Yu2WkvVS5bZe985JOBxpersHR6gAeJ3xYo1B9E3bDDr7ipA b7Oa8qmxyBqgFlfLon/ixGBrmAxBCZ7ogGzFrjN6PYsuI60dZHutg17hjTsRs0AZmLeOvUaPPH2z xygvfbQY5k3aHSBBEMsh9kT6ZA2QXmM0qG17jJXaFypnZCfF6tQhqLLTTIr2COMDO4/E1o0pIFPU 9H0hV1as2XQVGOQHBEgMHmUa0T0GvzN2rGbKXM2GLiFCxxGYJAJiIoNsuD4OZiDYMzv43KgORyQ3 IGGp/7QPY2J2qxnoKBNnWgzKnEF6/AefgcRx5ec5UMZqQR2LcVqlFX6UIUjl0mS3gJMRvm9hFs7N oaewULujwgmEDfNTSO6naFhcHFyWx31d78RjKMQcPzAvQ5ZP9olA7vbmvaa7Uw6gAvRpAegOlu+g hqY5we92xErf/IBOj8khtYDsx8SUbzDKAY7AILINvmc8tN5rsNneatYNmheYuU6JTb8nKPuJtP9n 3bFiqB6OZ9RF0ZfCM+IprKdcjfRZlzp2cTu6O53cfjnMmbabns206cwbEl+e8NHKC/UkpoJzFiJX wDnwCLppsHjqe2XVCcr8bmWfs+9lMkfPzkqT4MjYO+w/AHcqXmvrwSfnYjMXin2rk+IDP6L+qHyy fLvZ9DL7rp2TWQJA6WynBTyLcYapNlJQlLyxfs+6Uf9oziO00QyD7NHVOx1pKRRFndP1sTYQsWn8 ExaYnr3BNG/YsFi6tMNfY0PBf9jzZq4TLov1AuB7On1dcWwVKbumWtJO1zzCUuJ2Wyl/5LcdrTXg iOhv2Tshg0lgzJtAV2TD4px8iU8MAhzUmTTMvH+cBfsJ6lCj32xi/kjBaukV08FYWGizpgc0bTXu OGfoQYL7nBcvCbTGboVbucKCiUPffQR7jRH4PExvpPEsCIbL/dTS3BqdZU1j4xsHfcFnurBw2ZAt T0EzB3KjXw4ORvOunHWQmpH9/LMips/Ba6rOp0lPSEeVbl62BSJWxhvgXdWty3lDwk6MPmOlU5pf sUYsFy0vv4x0GsabRIBhmCu/OPfxUdNpYRFr4fwA1gba1BmaNLFoXqxCONJ/NbbixB0y8EkfPWQ2 Oi7P2KXRbyNoa1dQdS11iH/diw9j/qLHlvnMciUk2MEeiRnSfYcrx5/qYgtJKLWEXzCImrBYoHpG 3XkCI+c+HAiL2U6tFx/O/aoVK9kI5fUPoSrVfewy7DyvDQJAtwr/ipT+0jS7vk8fks+dJqO2QMRN GqTSKcJ2kYEFT6i9RG+3SjzxQqeiEn0shsOjanjUqhmdiyfnJkcfp8kkd/E7wp2lohqQMrE9tASj XydaSaT6qVuzJtw1cIixUPMdd5f1tRq3HTSj80b3vqncT1FfpKTkOHKT/Tj4Qi8CLf81PndQiTNw QDTuoTcclBnzSi5gnTi9/4uwwTvM2cTdoIGEYwKYwZ0t5tHvFv72b0pbncqhjJLhWmP9X4tlu3a4 gVyV7QGqkHk4xZ2t3emXtZaEuJS68gIQIy0PI+kruQ7MM2xuWkUUAuH5dXjNeD/pC3A+GLs42u+1 mjiCKsdNO4HSy71XZreGKduV45/7hzospmc51tcWOlVDwWRay6DIjXm6nSuV4USGmafRCssRU6CK 7q0fpJ6d1z3NkwE0f4EY/FO93Pu7WOs4QIk89eqFXN2Ux4e08/kWSOdpeIYxZnlgoKaBoXcdKd2V 4fBdg35D6b0SMwuH8HpagOKwjEUWbAnSl8fclhaf+yVuqijNckgkkLWO07oTJST1adD48VOIeMDH t6D5v8H8OoSIbrmBd1x2RdxIfs8iB5NjxFWI4XZ7CdTRxdr0tPofuFNGKxUX2aDz7cfnOTNbWf1q SBnCS4KQXIB2J3Thx99jFwYw7d4sBXLDoZAHRjNv5FtUSm2Jb0tyXNcFCRaHDBF54nl0MqmXS2Sy kuMg0xEpvFJG5qzo9sYjaEyJa9KkkwLBOs35Ga8LmbvhCv+aQtdH6GzCLK46nPv2zxY7Y7cfsSZE bVtUo6cquQcDeoF/MXP6p+sEEFiRuIVf1H6sSjnXEoUTeCGx/X3vLh622J63yU1V50N9nrLfkCAk JXq6cH6iXozmRIZbnnrtE4CJSxkextVJfdEx6uac63MWnAgnxnfT7WPqJ+TGoHzmVZ8VnGTum4Rz V3g3rEu7BBptycrM7V8TyFBwZA8ulnB+lrsY8kaurY5pJfqNxr61LEj3CAR0NhwbBfLJ3yZ6Tv8D xQpMMGqajUgd+JbiTeuXpaqpFjKP7FK+VYVO8hvWdV+z+E9pFy4GnfrLkXgkfaMB57Vq85K4GNev 5xu5rYATlbMceRmZ5L8nlKrk9tHebh/A21Uxa4VdS4oZiURGMpIH2BpSTzejwYgshKGo9c8qgpo8 9ujPogz08ITCNjYdYBxDy7Vk0A5GdGCR0horCKEolA8G2uxFXkoJaQZTrJWgg/4cm5mGr6uX1r6q P3I/7mDilcT62+p6g1iyEfhvcVL5CcIBsMwbVIRdCvgt2oOAIF3RZOmogYk3Z/FQFbC6e5bpgING AVgFLP4wSsEE7Y0PgF7dGRZDnfiJK/Iuc5Q5zweY46R8oy9iaBkzx55DupkWhkif+xzAgw09hrQV kC/atKjWuzSKhtNZrZw0iJiDCZanHM0EzqV5DrexbXbdJd7qdVaeLv4pmCR2JofnEBtZOp2Dr2+m fTCVvJQr9Q7kTQ621v8leZR/NLbt9V2MJ/8Amx5x9fdotcO9RSolBYF3HERRRrb3THxXPfp/55BH cegiyB7sFR35YRX1oW3gjN4z7mO2nFlqI8mVf47BYt1MfelboR15gfmdeg8B8KoIGUkCw2BuEeIq rrllaesBLVfWpVtdgKqqt9e9f0lhxR4sLsXs1OkRNWsLDDWvyPIvzAV2id7jB8hElNDkLqWChGC9 iMX1xNEdsD825/H1vlHRDamQH+8dp1zWMska3EasZEKVmPUxLSgC4WQorRG5TavBwY8fb5X7qYoA RcvDhBYDZPBQhKx6BIK+Yd5a0CRDis/yb3l+OSWkOGd0pjNRcumwAfh3btGfmkxG4Jp3kHx1Nqfu R5DLFa++I9zE0L07eyGZw80FsfvJXz3WdiwQnN49HX2UyNJ+KdqcOTDaTZzBylZPSMjRNklVMqrS AJEabj32esOrDFni4moqy2sH0aXUVZTwSqE1hyDQWM3P72UbRLNuyJ5LxeJf6HI71waeZK4JOQ30 Lwd2ns/VfeyFSuIhKxumWwZXKg6vJoSmUHw06Simf5nt7xHv6qaw59yE8IAFqqeERqJNvucQtZCl ySV8njm4d+oF4e6Xm6GY2K0HUTFbEUA3oEf0Y4BOIgRWCJI59kcBzQH78At0A2U92F07wxW5G0b+ /+lBNOSVqUz3iiUO+UL4djzDjdzDHONbDzdG+AU/gLDzjA0NIfuhErJnPEpWqu29qWTtoHY0jA/l rG5lFdqMj5uA8N/e3tlIBl/qCuv3lSOyXo9REK8BD+0ohaIv+J87GRyqR1VsYe2l4Lu5khZCvDp0 68Py9476bX7McJ+vpMS2rjmju6q0aflp0w8tzN008RMPxspWrgSyAJQZ/nKJY1kWHF5j/8TrhNOQ THZIaYvnAaDlcm04XX+fBySGwk6cQGZpOZFsr/55b+atiaBazSyC10ojvdU6sWk+FaLY1FdCv8ej tGjEtv3PQcsLkdmLKEq5vADTX6Nhv9EjPFyxrPpxFih4BwG5pwNr3GEY0TjciomjZi4vPg9NboMw F+f4G5Ey6YeeGamp9qiFBhJoMGbAv5MngsvRlCuDYAumFifmrPd/vzoMF0lfgE3d/AjtR4O61g3l OxDMplCLJkKrkHE54bPGyioreuqicvfEgY/OG9DHN3rPS2Zwz38m5D+781q2ewfmDdbblThfFxBI HpJL42fzBZBUlPyOJdTv6hKI6n9jJ5XhaMybj24QnKI/QhRYdVs2reAoWXj1ZFL+8cJxg/LKE5V0 fLzu/XHmObfooIqK36BK2npmgSrx5HL8n7mkB4dePc/pw2lSaVihyiNpfRdu3KBm7rxC1ExCzwoA b4Kk/BvLi11sbEsYMaJo7X5t1BOvEupKihOXV2WjHn95Qsyy8Kp8KEVwMZSQk38oqFRnV84g8C/G bK5MjaDvbxRycjhcpQCu9WFoxo0yXWHxy+Dyc16uR49tuhiickmdkF0TKhuFpzXI6JUA5RKJPzWc ygz4kjMj0PEVkeVYCDW3yoKxrkYLY8ysD7at3x1uB22gPmkY/GqsewAjX6BJk21ZrWHfJEEFLLml +T+Vo2iAlEnCct+bYlZ37IUVrXAvMXQL+UCzNy0qPq9Ct9rdSiM5bgjuWXlCZe80qaqWuhjPWrVd OPMZhnDar+VXhb4anFM8hQBQUIsNwM4jvp0CuTAjQ2pGyBEcplLHbfjB2b5j0IlPqPWPcrvcFmRK OdP85mpGOTCw551JtthP8mw8S/mpVirY1JfbaNCjKP0r2R4RV7ATfRXs4+dDhKuVMF9D42iCWOfm GkU8mi66DQ+3mZYeSVdOflCzhcFI+0gVR2Flw0PaE27MuzJbrAI6l+cYlGjMUfldAikon6gAv7s1 JW8W27npp/WRe2ItNRlJd8Un55VNqD7/eoWT2vMFWJFrT6t85qJGBoLhLxzjxwNriFGIFR0LG23z TZwGeDV7gx7jXInM/kVGGIaFoNmufoRCV0r31qRuUuNVnkR4gFlsAbKiAeEnka+bdg9Y0P2iogXZ YfnJ+HK0IDwTHFc37m/R7G9B/HFQuTwDBCxKX8vSqrFfacLMwn8qzgZd/QqG/l4wxqOqS3C436SR YAad2OpyUwBSKXy2uu9bxCvpRqUr0h8Y4PDX1Pei5yVJh67nmHEkTcJj/IsErx/a4K8a96iApLES Dty8Q/pklU6Uim3Vf0TGl5+QI0KrcOWKiePWT6Gd16JyG5CyohBItSVdsaCO5m9VMYZRLGZgnylH 2w3JXrOO2317GtY7uJZbX5kk1hYDjDYa91QoZwe4ZL82I9WaaQ34tN08R+FDKjdTmNf0yng2u4Bk NEVv5q9eti4FEMvqPXG0GwsibHApqFBFPnX56Xudh9ZgHJVAuXvHWJ99ZcdZweUEFvab14APiWFr a0R/Gl5SmTb+DNKD4sn0rhiAoOHYa1ISpzRtIxCKBz7c3aC3ZwEmCKHqUxnvb0sbt2s6AktF7+Uy qAlQVzRrHIvsioHleCbgoCWc59UWThnz+DtHvmCrgr5ie4ZB4HSa1yeDzjvK8dJT3Ejkc33WD2xi WJlchNTUeuLYymYZehtp6QcyW0fNCn4VDp8pgwpwYFcaMgyHsoDe5B5kIpeeHtTwEgWFXMKVD88H vcMyRpQy3f16ZnHKHKWlyaL73MV79UTG64TZHDN8s8Cg1j+T0qPn0uCZPH/AqBfcBhAAyJ8eM4gG Elut3+uEi+Fnc0MR7l+wq+o820a33gBSuAlQk/LEDPrijpH86MTVo5bIlPFIII5sLqv8jv+vrMqM Rq4kLJGaoh3qCoM17zW75kUVvMQbcLCJKuP3SoD16daJrUCPPaXa+AFr7cQ2z3QG7KaIkjNoPamW 4bcYlJK1XWA9V9NkZhqQ04vAQdg3VH9KCtzUn+zR5uWclbY/U2RAX6JOR58qub+vh00BfIbFh+kv RvGloijGH0caIgUn1cDZRbjTqG8ZnioB/vjFy2dXpW2iBTw2Izm68pDqoFmUV9j4Xz3VExPKmF7m jTOMrtvRPUCndkfZvdfQvnZo8CEN7t+YJbus6E6A4ixQn5fBLtotnIAd1/jsRF2NJQ4huY3v5q3x 8iTwrWAqTFL0G/8BIr4R6eHQojC4Nf/t6I67qMPzFKG+QqpmGG79mIS2gcfzns43cn6EsreK1HKI Xp2bZoZnzc4ubRUv4E8DCRslWObgiqzKkWYZAnLZ2k9gUQKvZpN7NSBf0O4BO5JmKPeV5xOJV+oj p3ZfyxNIkCItv1JSaRBPMrARFNJHEcWXY7q6bK+o97UTfbl8fyldniFmSsiDhTLirgAZcLBTkMLX 13kyCVhMQKid+gmwBLiLmnxDFBfdyqt3UPatsaQ08q52/DyKNHxZU/BcqCBlWhf0AQa/ME0/xZUA wNytHcqsVtgo41YyLXz6z8mqgOioGyg3zXbVxAyb7qY8VR9YxSvdLkVx4Q+vTEKBQKdI/UwWJOip WwagkwqcqJFUz0bp19u3YrQeGnWXhlpIfT4eFq8elSXx5lWXj+jiMMQDhIJeRqoz1aVR5wsbSdqb IHWbv7XUpKGxktzI/qC2BxE0n7rLNiwvzBi3OI0Wk2b/eZWE3Ihz8wGa2gSnDJ4hOAJ2mnS84JEN ibEeWLeIWQTTL9rd7sABjfajopnsFb1nmmWky4POdKkImeT111jWynitcWsfmCX5ucQl7hUi7eXi n1KhZHg32s8eH6d1vSXQ+u3pYXrQnuvr0IK0qaJOaubTCBt7LHNbSG1+fq/H20idZa199PW8aR5O BUpeSI0IQAfXdv9JNxr5SD6IUL7Y/6aDIbaMnw/B0V5X5Y0t7YbsHNekBD0Qk66Nm5Or36lnzDD2 1tHbUZxwoyFUmnj3I/HN7RXPz+Yc6v7k7UGUzjiqzZ/qqh9cSO28Kc5DvTBgQyNths97mEMycIlm l9H2+sOGaW7J9om44QBpsJknT5Ibv9ZABvz31YsmgnpjRab+1BUSoOigay2ezH/eejWwX1bGghZG 1c7V4rk457QMw9ZNsEjQSJDaaF+eOdPXSod6oQo3kYEl87zWK5vN7pUP7J/C5r7B/liN93gMSfWC R4uxttmyRW/GtPmJkTehhGugZdSn/aOKu/zT8SN0fKg3RFRx8VhNjO01LoS4ahY2hqQfkozE9GzB ZV92TShsKLQdtiVgkN/VC+ict7OIGR3K/g1SMCAvChsmoE4AyPf0/H/uVGa20jB6brL80cLgibFF luNDLryjvSRriufVwiVaDkZJEjX8dGw0EufhlLfaQA6D33Bur/2V6haBe2vDzkukKfjL76CdO8yX 2iNRdS8+76E99ceba6aUXNH4JhzD1PzekSghjQ9/ldhRfLD+Wtjbl9BIiQiQAAMQBigSiedRAvwn dA55WpQ3fvWy0ZKS01mR6vJ/HFtnWVtfHGQTsp8GdDibivie7jgeCJYYV3K25c9LhfHxRpUug/ru J7/ydwpjwLqJcs9RMM8Sis8M70FgBoZ8BQFimnbodd3yrplqFMz3IfvlCEo8Ipd0Ti7SzcogQjl5 XtMu9RTerBx0qmnAn67/qj8ZL1Xv8jkLuN4mo9YK63D3aoddTpV2XQYoeLICc6jBdW52RviubpaS qfz2zBSRQQqe7Ff3LFWDMqlx7YMGt9NAA187LCmsIbitTSdgr+YfvfTjaklKgowWz/BsNyJYmNEp ywk2kTkz8DnJ/mhSJffCqoEZYg/f0ZtIL/Cp58HFZ4WNVKIyn2lQ2kDZJME7AWe7c/vfDYw9YToR bHD/7MjW6JBHmDZaVjzfeVJ5MBN9TjTFxc5vXaFpvTlFsmZ1VXoG9wLMIUHnvkl8N2D/kVZvKLnf 52j0A0uPRB8QZNdIMKcEb3L8Pg44UN0Ys0B1V7zmaR9SQnOQx2JEenmYQ0hGO26HSylJB+aEu4A9 3Uo1oo/hRtOWhAZBn3cYBH2o93/RCUeCuWycJFjF7PKz3RUjEYsYSMUpXx+YoRgki8gRQ1nJLq2+ Ep81aWUr6DN6l7qShdR2G1B4FfbjoqfJzDpymrKgmdFK3ODF7+MoX7mDc5FNj3dWlrPBMlTxdShD WJ50EI8r2dfC6LYaC587wu1mWZhjQHuVta1Y+Nk8ek5Z1prBxHLUBzO34+lWTpS2Ca+MZV6Rz/kV 67INFeTmt1IFt0p+/m1D98Z+EwKtx56QiA2lEnn25jT+1GdQsas3tstUjIGKM4c/1vsNyzaeF5D2 Pg61FC9SLa4GX6VyT6gtMwl6mBc4ScT9ymyfKGkwQou/ZOokD/anDOPkQmibX9iwKbrx+46hWNcb oJscEIOsAgonxX3Eq5E3I0larmR/H1ST9RowZzRI2nBW5EYlcTiHTsleQi5zXK7wnsYOxo4M+QG1 E1206ynMb/HrNXMivUziS+i3hJijn9z62kXpnoiLyzYtj8+yilhihgmQX/r/SUl9mn5B9KmLEWuu C17JSHcl3er3j6Ne9uSAjO1iMxqBi4gOzUvRD54nPhMDYjXGR2Nzoo9JYDQqqT6h28O3SJ4ZWz7M 4+kvekaRfvPtOf7d+s9Ezib0ufc4TUvFWHhu1yZGf6i54DzTsCSmr+6UX/sMEkz2phev512GebLF 6GYFyKtwjwS9TyAbi2Wkmhi96fc0mArFGIkRfzqq0/jU91p5m2y+Hj7X1pGqXTG3Qki43rFHNtOU INtFHd8TJiYPf3jEV33e8OI4KVemr/jgrCNpMJQMEiGcCzxRRlHFHRGYZsNd09fnwxN2Fgc6pQLF rGPMCe+lrPPAiDD4otZZTv+DJbFm13z76KXy+LQlJZlTFVSn2ixtcCRNtbkIPu5L3ySqKDHrHO7Z LSAkWwOyeb1N71vIgNjd81ppK5G2O+molmF+lp68QLzopSfdVDpArSwRLn7kVODPMpT88yZBW9E2 YtClkbmSwreEBswfxpistjI73xi/dmNjfYCDGKXvD5jfNK8ULtfCgu8WO8G6dF46itx/j88ga2qh Vs7+Gxwqw8jVZX3vZi1QGHt1yWD8GNpArtv7i7Ly7lnM3lePcLCxWa4yzUiUgJTPlYRvVO/bt7Ol Om4++bhcUwKhOweoHHGbzOLqqkMXDfh5q7p2byESgjm62vCGTbUHDsVEA8i+1ARZEhEhG7X/gyAT iHCZCC9iIhVd325SA8E2nBiRVemAF2XJWfe+m145s9JTgCKgKcvV8jzNdVzCItWOISuMJkgFpy2a Mb/IS4yUuWVoLO/2/w2L4HAXhTZj6ODYFgnRPfaa3KGFE6WdCaDPq+ZmfyTSieQ/3Si/74tN36yP WJkQvhsTnOtpJzvWNWADmBQxoYM4YfDtyUww+muai4sB1PJ9WEs5vmI2rjCdwzAs111ihy0PMB9q GrbKcle7qgymhL75ijYd1WJQOf2JzJGsK3HiHdGRHFS0mmfAO8KZYqIVAGlFGZkmv5zslDVvjcSc aftBBpEc5w/z1T5T1BXZ5M/0gRtsjEqYsswD7q9gCmgFzfv1E4xydxfy5DeIZSbCvNpQYl0g/3pM WoWz5kCTr+K+7g+uaTGZBdB+M0ESUuoher8j7uxXfIs1ISea2zBHHHMHRGN3rvmdszJ56mt4LV9F vH6VpD37CSpFLhG29AEGNOlWGXFpaaG3X6Pd4+xK6Vvks1/2Nf0Me/ugUNAan1j8KwVhkSQtcEcS PlQlVDv6eT1wPdDEUuRFczEe5swN1g/qdU+zTnN7mxZILrHQiUj81U2drvda560iLn1aXWwPB8bP Xyon9O01nZpqCY4pwtBanbc44msdiUXO6A9RIcWSDXpg4bh1MdbFfQjsutTBdxgJvb324mp99cgD 1VXumcIniqzWjSBwS11Or17GEM8v4vPXsT5LkBI8vQyXTqYdYPFG3kJaLljWud5HWH+1p4+ljhND rcvQjJtaFW71z6XY/rBohuPsyvGZPCVWKIyOip2Cy/sZFDFw/IPMS5UjCP7uj2GEXQzGTx9enShD itsIi4EGzXSFS/p0S1X4bKgvlwD0Uy9UgzVw3gVJPkpMIsoes9BFEztglAgOUelSwdFHUsnDqpHk eUg5qmNZA8myZUQO21MZQ2/Ehw+qGZ66xetLk3CZI7bQhlltNgvMyohDv8QS+O0lxkMYiyxf0/2x Okx1x8lJvez77i9mbQ2XWopEb81NWzlEA2glUYfCFjohIMbpeUrrBxQpyLCMumy7UKvv0j8yd+iR eOWGthcpnwL4Lt50CdxK+z+uhzefzmDPgC2grR2gxFzyzCY5750fKv63mipIelRatH0V3lGpEztm 86IUAIa7KDTymIAP5lIuzQWfTiob5E+byMadt/IX0/x/4rXYeI2GMfP5FlHE+p1Izn1fWnvxygJK 45TaP5VFwjdCawajoHfMeA1JsMByMpxDpHTkPL96fRO50r8sVBGb5sKZGdpb7ZJPC8D5vtqVNWIc wQHpInwjpnz1VIcFOuJNfhKpAfRfY9Jt0K2xC+k1doAqigCOWurVmvVJ3+pzwU+HpRmiJBMPEIFt FunY1m1kTg1gDIPqw0j6IiH3QNEIR3yAENEhTn9T0+KfNVtEifPNL15+xiiTS+Lcogpv83UxELTq c6XK+uGpBUpdL63WBJPHdfCJCiLmD8TZoJK/V0EQp21tmn2pLjzwFrpHsM6+LOl3r5oWklBiX4D6 rVX9aDtq3GyKP+R6S21pPyFb6oTBuhXn3w29qFGgKnIQHSkDRm/vmKdZ8EYQqZP9knETsQywI/bo xydKU1Rs9DvexrAIwSfrMN+HBeVt51ZvCzO1PzSs21Bkb09yVLqdz36crWHHTXrzH+Yb3by37smA BcmQC5DtWfRjuEsRnkIehEuqmIYa+lP/BpuMjgvWFLw9xjvBd34I3iiuGn2aimlvHZC7Tmzeni43 toZUMiUhQhSkme4SKJkZvS7zRdYHxpvos4QpolBZSxhgTd1YbUZ424odBKqix1yJNjfXWytnr536 sW1oMR4OpHbl6OX1Ir+s2pX01aATtobu3bfzLdRuiVd5w3eMleYzthL47MXbyujg9ueN9YmUUkxx XDtCiyHN4mDEl7i7Y7Ae1NgyRI//OtVWm9FRsJf8h3MPc4yCE4RBtXS7b2H+kQ53b2kiWs2b+Hrl Yvxl5808UAamXV4rHp046uJe+XrvKwJO9emWGckC0qTAmvKaC7o0j0+vw5Qk6wzDBoDcGd/pachA +Pe16GL81V/8BBiyLK4SoJsa5o6fhooyBLSWW3e9fmXgI9bqP8BjWruzoQYhKyQCPHC49tKervht wkrsmcR0vXrAKS59VA31Y+GpoMVQthV1UOJ04tZSp3GmvLsZoLoiwnhz218aIjaap58s0Av9Cr8e nzaNL678+LHcUemq81I7tlDug6tO4EXCTHJuPdBd/1eq8himZDTvs0YhYU6cbeePjy6ZctMg2ZoG wxIaYwf2vyYRmDmNI91U7NfXpBjWysIK67xUZHeDWCePBVkWxl/7IsPMXSGpfxgL+7kylNhZ0UUE mFNHO9WmAbCtBWiydjQ7aDSMf8kMVKCY9DAA6vZjoPYWK22+GBjEnhwMjt0JK9yb8hr8bmQJwFPq 6rDYMFrPIW+94hWKFkJ1OdptneQCNwkKfm6jPAjhhxldmvbFU59piGeXKjEDjJVq4K0ApQPU2oK6 i6TV9hSPyIikco9Rgoqn0HoPpo7w1rvdx/+h5lD9XRgd9b3PoMsVmthoQ/QzA7lRnn2JoAOhOSFP CyAlTGjy6s1EbOC28me0F3aOorkGVcVpmMi9RhnLLSe0Hzd2Q0i3tGWHcU4V4qU8AtGl6+OmmQjz J6vawTxGDGaDx+Te5goYiwGm25w0OKuiWueY3II2b6+rc4VR5AEaHQrk6MneVL6gMaaQ+mmgphM4 oRXOnsYgsFuJoXJtEwKp1tSypFboh9gphve4hpMT6J0r3NalTMg50cfPQ41XZAGZck/wwpfePYK2 mQB3YZ4HkE092GmcdShHsDP/MNqj3uBSn0SF6JlbW9AdXt4EXvoD56I8LrJ9j454sOYGYiCa46/o iKS4wXCTkh/JdcQZhLstLxKzl8D7C02jjCgPNodRwK6fcFScXNYgRO28LEftw670o3w+wYeZcifD nxEcgQZqvfBxi+v56LtxnFBsVEvvvwr2W84jXTCQKmBMhgCOCJKT3zYm7inSfJtmKx4C8FIl3eK+ OwmOGlOupZJZNxcq2T/fQ7c+YSkA1z5ZyvoapTvuIu9zM5tRJnvSPRlX//7WkiBNWW52CqOB6NS5 0ujKZ4WqAsETPJgnWck91Zz6HunGhWBrR6zoodXNdYTk5kpVkqvaCpumpswvmEoo37ROHGXgdyqZ CIxEcPQfo0WNrOiz086QILsitU4EaufRX6HwLmPMzXiWZ/Tr5DMazvJKOFBVc4CTAdT8e2REMOZe 9W67TFZsib/MGkfp0q46BpJ8SRm2Lrf8Pf5qkVxV8UdgTFx/CXaX4FYDmJWreJXIryeP3/QRUY5P 4UjgXdpz/m2Z1OqgI0T2F8Hbb6+wslX6/6oUKjDq/0QMlUlIlBDDsNqVQDZEFVx1gLnqabcJAzXb 54Icf1xn1OhDQ+KyKFK2L2dyKabjq8aXX0t0GpaG5RoHiC5IZCoP8DEzfcgPMXrnM7TiydKuhuuG oIUqKpY9lw0HsL1pLfzoA5bA7WH24ciLFAlUGqI4bd6H3uovr5nriK4G7Zc31GDMnVSlUWhhphGT UFNepgy4LHvmax+lejHK0tIo0yKsRlDh9TDCcSewVvmJnyAjsYZ0U09AC2VdVhZAOn452jmwNUnW 6dCR+b5qQncmNXFE7sDX8cjIr66oZwcbUjcTxgA87WP7rcwR3+rw7/3Szfx1bq772TSNOaB/MNGi HrqxWbQ+yAm5cE2T/Yo3kWXBpTEyswhpFqu0nJiLTnvjcGqN7cRN2MYvzSNx/NKqjQTNWHDCNExm 4cYIQ4M/FJyY7H0A8nVnbMbF5v2W3nkh2C1shoqFmjKr3q64Yzy7I+ZE89bCZtKH6bu/3b5FqwGe vdqzbFhUObHcYylrzvOPzNcUA3VQ8kQQ/1NybLcDW1+zb/RMWzyqoidWYPYyux+s/dsNQ+oejbXC +nwEazEfysv/t4HESu/auDsoJbqFUEeiOR1Tg9f2bnK2/zu2CN+fWXhdeFzeHolPOA8ktDEtHQSB U5su52rl/BGxjLTnwEtrF/TQnEqbfd+6MejOxap2dXTCzBmgMXk2sn0HOQ1QZKBh2QzTe5t3EAxr pFRuMMWj4VMFoMyzVUM9flg4hYMZ2RJG1A4xkhRTHFUeK9XH/orLCMJ3dAsj8sAGvHbpc4ct/Rme DozfiFa8htI5AZvA2Jkg1E28qKW0Sq3yVgEXTCZOp0CrwUkLjNFVlMFGxj2HecgLPzpTNk9WvJIx sW7d7e+8WnKvsnisSZKygGwXXC+HBXSceNM3gRBOcaNHBiY63o0tCQH7pIP+GEwxGPwg7GUU6Tit w11J0nF4FcZ3Al1jkLS6+GOxtcWdMZlxSqjofvqE6LnfWuQ2D6ALMN7IwPlR/qu3rfcFOw/30gfI PQfG0XjC24SplaLfRWRzRuZ4DhYuP/qIJaS3tFHsAJm/BpYjVbTTrMj+tg0Dkv7m2+kJFKy2tkDo 9wSmJgHiGjVj6qa79CCaxKOGYbIlf/AgY1aPFgtOhrPskFK3NRVHJx8Ks7xCULOFTfovnVIiiEQL bRAhr5ksgNV5gkLOAY9TYU6LQeyVsURuKfpr69/UYf4jZTkPDp7egaditHcqBbjJoR0NOREJ2Sgt hNoKL1xdKa8InMq4wPMHmE4dLC119fmcwVNLQ3b52BDNBSBdPPwFNrlONUsdjOoApphqHBnWbgML gH5vvqW2WbeH6nA7I1aqcFrBaXQiZsq0mat5nVh9kiLor1Xknff7SQ99sggqi/xga9L8nDCqggdO vYGx0FQH0U/M2LKxrPqzvPyRbJD9Qltgxwzl1cSa9UhaszEMDdY5qzqESTxOEgpjWNJrYhIUX+Vq zoLWY/sRW94XtFw6zucmxz4envqLm7qoGiVbVAlPfTIyhlJLfVvoaHrIQPFuooziLunWfmzSInYw wDD7NRjR9KmVzCNdhsPvDcNpNBsMeLGLnCfStJs/mNJed/UnD2Z43gS7lzDD5R511zGH6XUZ2Smh LKvCevJv7LS51hP2S3eHnCde5wkrx0MchCathUvFO+H7LwB4yWT6xdRjWmNPuTRHwutgZWDX9BD2 wS4H0eD6TlBmr0yE4f9s0ich/FzQNrAQ8bBoWh/ixLGFV7Wgd/OANmgyB4a8xlzvvBMcO37iGDCY X/DKP/IxwYVLde9KTxl2HtxCA4zcwxrI4tNgEsiulKvGVN3DOyzKbaz8Mn3nD0DqZDEDjIfO/Ibg BsUCedVTW13eONMdL1Y3ufk5wudYYcvh0uojkLGoSxRsXsq5QKPpoACs+zR2i5/OBOZfW/WxeFbN ReaKMv1ykmfsxE0jSHv2CChwlwEcWfKOdmZyh8HMKA0SACSbvC3+PzhnD487tfAREKWTnBppUO+9 sTVwJoit7QRwV/TcPCsY9b7r4VTgOzGF/Ge1i6CStsVIP7WcxVOMSufa8XJC7kzl3dS3ALbdbVfe fCL4XhqNca72wcR50Ow7slGdqAAInM+lURNb5DCoDXZCw+W/5M/KbWdMPgRlXi5zGmqxB7nWoMRO vzvSkvmb8Q2HejV6yxnS6c/1EUe6yGdDiBCSvhBkGdMNwx4BSO1YmKJQV9XGKtnY17W58LBrGMOt zKSzxUY5YfCZOmhjvR95ISVh9yzr+rQdfInwN8CxoSf2e63fhRqWQxFrcqhi7kr+iKpV5nwMFNSA 45V+aHGb8TKT9MutfrmD+QckbKaWzGwScwKUFRJa21D2dde6zuSoMi4MWgat+z0Ds1gw1ELRy+b0 vZbn/4DmSOwx3Ihrbd6Tp1suc1axyb9TbQvAAgNPEG6PD5vvxdLwfQujAXT9RqAH4mJv7Sm7lYtV b1pvTJ6VAQzyvY2+ZuoYq3LBNFMmQzNIbQHcmdAl9eDO4tlqi2qnvkgJA3+2nlI+qj4w70uyKLot UyHknOe2jtyqw0KBRt+Lx85i6Q4q4poqiem+a+gKYjGeUQ2nG5Nea104a9ZvP2Yhagd1kCyw97M5 FHogl0joM1goWr35K0C5ACKqZ4f6UwLBfETXzSooUJc1Nr8GNgxTwLiPgInvCC0kwcspT30EPGXK ZXx12hAQldQVbQkU7rpjHT6+Q/7BMyO3Gz9PqDnNgZ13sYdI33GDtrTZiLHIDt9kxfCt/QFdUnfm 0APi1iWzPSV35zKW0aa9eZzQarLySbWrLq0gG1DQoDsKOAIv8A8hNuomcG1NBWRR95M/0177xP/K BjuXJ8JXJj95RfW6NJi+TmWNtH0rbuDGV39Na4ppaoDh2gKiikrLg44iItbJ6rT1HIzJaAQibuKR f/mC2FQE8uNDFNKVcsHraFH2ZT6EVRE3zlOglHR05NlM4Ri09NXPThaqOJSFJtgNmJWa7kO3xUXX PabgqTQioNz/uWIPUlqR1D6f183O86IJLZnCfB7iwrCJVAnk9II0unoCGrT8zLiLNQrF2tvv/bww 82tahFkh+f8MVlf1oGJa7dvwrIxHC4Mlo+MFNNYpshuxSuHXqTKoCwLENMCj78VlKt1ylHN5R3ch 2XSFtIiQBJjvCnYglH02Jd6KeMAKTciUBzhpyFft3EweFdol2mccItxZjcK/xBzpfNeCxgmkvj8E ZzoGe5kFTs31ecjMJn81SI69l0k4b/pXcFXa68sBPr1wXKn8bBw5JL3J3lT5DNM0HIhlf1GeFdY6 L+fWwHoWHOxPwQJP9HaG6KHmxptO/9sGoqXCMIh61bRbJyb5nHYX3AufYHWIre7CXALMhoWPhtKz gWU9wqfuc3WgjoI7egdqP0ZeNK/yLIjjnZ01EHqjJD2wHxJ0MBaA2MThQFUenY8SafNInpaq85oX aHt/x1vh2gAKCq4MD9JmqehzzuY0JKfkutOjNfNDec/olWPqy6X4kcgxxgmhvoTCq/WZA+4wh7cN F5GFwtHubevOn9YwFBX45hNi7GKXo36kwGfkQGRFwksYyEMMzXXWCZbZpe2w+GT6TpxluA9W3zfY 2hpoYb6ZYDKOpP1EwIAC7hoztCoPIBy8K+BJfxaLF2MGtXS0tDIgWx83njFOEqHAdJ0x2852z6uZ L7fdhfLSLjXRXU+uVoGcHIUtNSdMtk467FPqp2Da8XO+ZC8DFsZmQEr94M7Oig+07bHn2SEq+5iF WTLei+WMIVwfPrYDN0Ycy7L+ocuMtgtGOC6fXwIr/hh+/sgHXI0P0wGauneVGtql9fZCIgu0fyEI ENZ/DhW4/QZRXFYKi9u+b7ECbuGnQFj94sS0YxCosuD1nZlWu1gMjeRVQNEJ6uM7ZtjZ6/MQTeqe mM2K2bQM1wBdqkNMOvQ0cqRzYdXk6pgnzFdIqS2JJg54/KY6hHgaVqxi9fbGaer38Z5NGcGwKzE3 MLAL9Ynru/zXbl8M4jP2Gn01l/gfs6A6LWMzUm4H80FvX7P6tiPLtoArp5YHERmR1lU5aXRPZHf4 TC7ObtJmGtqnuftdsIf+OsWDHjDhlKIBUwCVnlBPbdK3n1uUQyD/eRWLAMVYgeIKtFoqR2+gwa4w eUaMYb3WodMMJPTU0j2qQLjoPk+BVoepzbCGZaQFEjTctUaVEsSO3+R1HhXS1HoAPaCOeeaEH71F a3jo3fSnDypin6zIfDoHLNQea9q6PfIGgcrfAFlV1uSqOo+tzImr6Sj8yg8WC8xJ8uPxkF6iFb7/ V62ERsdSpJ4FEGp9S4jvEwQkKYwZYoxAUpxX4BlTs3gVGZ9eJcwLkpZAz11lW+s82eEcLG6w7lPz BVFWY4y77wnGRZSCKhoQLYRe8lrYfOqzlFqHXJEypgTzm9UnLyWjmzE+Uc7e20p6H5FPzvw7CNMT ZHjvah8I2QMe1IAGI/NDubwuKN5+Wba+ffkW/7syxZC9ylqph43Qzk09HXlDk9vQEzVKLXEYD3n3 5RMCfwvyCj6si4J9wZYtzCaQxw2CupfDryO2UuBSOid/A2irRKcQkIGIinVF/sRIlRl5yWPBdb3U gs/iEEFuLmjMt4Hg07s8fsnNuOgSpmMUOq/IshO0lNimzDfYvrP8pHcmiJI3as3YSTMZXhcNV/St 2C+9Abk7NLFlEy3jhYSn8wz0GHp+DS6lgVpknSMlt7V9RH0/SMDxHtd8L/B2fWquE4vf2H0h6hbL YcZq57HmECj/MC9Eoi+UUDQo6e88R7Rh22jgasrSaFm3jm1dlQL54tKdceACpSF/KkQ4aKhcyGP+ Y0DRoT4cn0rMhvVusVzKsxiIlZPP28MHAyoy3Kz+jKDRpBlEQ2icF6wGVKsHN4rjkAu4NCj5DDYX MwQqRwM6YafeEn8EeWxKN5/+gowPwD8YbfUI96XtuZXH+XaSEMftFnrV2aH8BDjSr8GjIss+/TeC r5lh8VqAQ8qE18SowCQLySXGUxj3sC0MbeL7RLydJ8wmTcZxYT1CuEnSJbEWRr3nuPbQbQPn5LkY VnzawSzpBpFllME6/5ryHnXX7soxAeLEYRkLzayvZ7lGZrUe3rh2UJDbRsUsEIYIjcJJZ0q5vbBR Jcjh/U0/xOVL/azRKateNToSfICah28rDOPCNYkRtJyoiZzSXky6aClCfKrsMML8VupQ99ybd4io g7S81OGXjEI0zf3ZW2nhvaSWqcRudcM1mcZ64TCR1/4sufZExBYj2CeIckgQFakHygP61He+BGHv NYVFKKI1zmuSyrsb4yHAb/MoWKsyY/nzTQcYTytsYCTiErf3ahHCMCxgj8w40Lhigi9xTNpcTI9p C3rtfOUYvznZ1mspdUmh7m8TMg7e7tbg03Dp9Cyct3XMkyrigN8pqrJdgEAPG5+0szS+zuwMgJr5 bBBVCpEThHi7Xj7pEiXqzwmrcg4bZLw1BEhA+CJJ71o3qaz0F0zAyRidE10I63BtaYk9uHhw0GqJ /94L1i60jQzM0/3bDdSNXpNOMcIeTTGCzwLKJNFRPttYW8dL0AieDo9Q252QrUy7U8aN/fqVPEZk eemhtDq/qinko4q5yS122gYXMdL1bSLha/FPs2O+hIhNyaSvvDW2uKSl3m6hYjJw4ztDHAGJd/8R /SColOUG1P1wz9IN34LnLtHJzF7qDn7y+l11/AUCozgCvwKqQLbunf57+kAwasZJaE3J/oSmRml9 MbqhG9Kay4+dWAKBWaM+/HstXaErIwjVoTojlt+M1aAHpNAE8mNJ528jqFzijGyHrRVSNEUl8Uy/ heMK/r8U6tvD5TECOoq5TDNficPwrTZqAE4URIsMTzfSyZ/YyzsqrsPHe2/R7brhH2DeWKEZe1a6 sJWynu/7GSWr890hodq59laqqeSTmUgyq8L54NdhKWTfCShqWojB0XpOhWr4UYnlS/eWhS6nJzFf gvedhXUJwwhAb5fPOuOFpomOVSIJz3SHUB5gwi13gNgWtmz7q2zmbad7AjpfC+wDZI79PTw717Hr mgUDuZRdQOVFFuBWFMwnAjZVcd16RdfZma4NEo1jWh6227vrvh95es+NJbwAIYM6RlTPS/nhVXlk IUwStRVyI9+/vdi5p+fFMakfBfljfASVm8uLM2i3XqYzGNkZoyRDlBcF0ywHp2PvH0O8KJY7aU3M 9oFqbwPc85EfVlN2iC0w4x3sLBC1G4oNTpt3RsYKM8h2nt2K7UNJBGESo+vd6O/ADjMnp9CAKY8H m8fS/ita6sx/0loRhSgWpB99dtTjXDmJdHwiuSMeeAmzonqZl0CpiBUuIcTjg56+6vRi6/OhGu5s O7V6a0VgN834aDeYSujU5XUpsrQG94WAlj/PyAhGKiZ3zODUucyr/EjGnGZ2TE110Cs8PEd/Rj7r 9XgHV6yKL5ZDxYnTnih7cHCwjhE6sKr4VoExgVFUtJX9f378xyxcNUTT9kn2p0OA2KzfMtkRA9pq iHKbtRGYXiNOuX9IpgDGpWMZ4wZMs7+lpx+IdUI5DwKaU8uWk9GsWKnX00GaE1fHVYgqS5TxTwhO 2IwyxMtvmUtb1ThygwR00bA9JY/IyUd6kFR0/RY6xc0ABColfqKV3UCJGE23N/4MDifs1Lt+0Ua+ ptpRu+el9Tx0tIli9Z1j/l6pw1KIBtyDQVAgiVK+Wv++zQgZ5FGpGfR/y4ShHE8i60uf2IbjXvGC DHgfQb5OHfS4lyzWHLW6Mre9UZMI0Ck7bfqDUhEGHc+/5PR9ff358wyIyhpcUgorbzvqy2hMfSC4 QN79BKyiHBvprJ1SB55Wh4PQUnhDWyPlhm2OBFl+z5/AdvIM4kHlajxMPR4K0cLq5FzJa/KB57TT FQNYX22VSasUNie1z9hmW0NQo9DWLFtNVONj/Mh7mYnWnob7QiT4mqIoDvu3HH77UKA7eybvfYkZ d++Df/F18ShbfugIvLDx4jj/175S0lpQaz1JJh1n6bCZxIFkmuNia+WEpaH7IBrJeygZuungW8z6 LQiImK35kMSCnocdYpwwsbAdiU4dpygZZFxie1UBk9WEaNpid/zLfW6iAqDQ8aOcI7aSQjp7XoEa i2OZRldVIFA05YLOVN3xPDFoLLcqHr8UJitE4Bco76aJvL0sOw8JN+G2bnUYekmdYDS2RaouxZO7 RWy+Sulx7+RkxrSi+bkDyQRclK3vNh3D9d6hTHxbw1fjjsQP8JYClmppeYgcswTRZuRI/0vJvBFg ZfGDibx9fNgn40yuOaRvASbhqP8RAWd/WY+np0sczfzNvm3KGt+8bZU2R1UDiF5VYi1Q0l4w9KN0 7NgTqHeBn9C/0LihqyziQKxfbQfr9936cLmli4ZQui/JTqF4arC2HtpHBFFxbvZgSrt87iQyis1d lm9zWpi+t5/+2eBlZ981UfNNnP2VTDmavp74HS8Fvz7fUokIWlCcojEfm9FBvFOA2OpB8Fzl+YHV hH+g6mHiWjLa3h5t3Hk+z+BiAudjZ2+/ONuv3WEiO/EKpZ7bL1FuFtMBIEo29K7T3jWTgxZPUiL0 yxsBu1Zo+dZ/8u4S1RBCNzOBFY3PulOdSOm3eH6CWZiaBlBj3sIRX5dyYDxXN/v79cXjhD9NAxI4 k+yv8lZbF4+x9seZiYaPnwmOuGqRr6aDqd6LK+KjqVGtOdc69VpHW4BtMacr/QaQbuvWgTKkL4wJ CO6eyBEV9y62b1QtKY88HGa5IZud/I4LHElaMTDCyzAtKLGqJO+FV3gFH2d2UFc08hpgjKn6mQNp /coFbEs60jLGSOpbi0PUWKVtGW+LdZQtlAy+v32FwSivFC66CBZbyHY6+rtdyYlZHEh31Yo9Q+tL gq7mdDrZaE/18e+FvrWq/HM9m+tLU+GpCA7h9TUT4Osiq6nyZRz+KEnCuuT/cfe/ahiUC60hAQRW KDrK3yCWZ9HfA33FrmRykUSqGqkYe26G8Oi5uitYdpjGIxDTP81PlYKK6mTpdJMJ20SyZpgKo+oz PrAp1FuzAp02yaXDAlWHoYi5sNskiU3o/JEYPHjDqd+wrnpHQaiOeSjUUSGEqG5+gelqvfSSWEcb 9R9qV/xikeJtxFnX6qibxF2cH/laIZqhN+bNnM5oU33PP7YMPqBjcUxNIYxl4Mpw6a6AFbxCYNMe h62o8nqbdo1iJktGprCwRKS9SVIRNFEa2L76R9VgaGkVI4luAqm/lTm1WCNFsBUCP5OrPXcUNLl3 TOFVmZ/pLPjWoIaE7OJEI8KMTapXLdyLaCy60PlFK/l7l89+9yb4Fra/KwKKkKqHhliGPitXHMqI PvSuLllKxyI/HQf/y3dJhC57lXb3XSWH5O+sT5p6+ffRHga2XBpdiQmARMK8IaSm2U+87LvtqWz3 kkeXp/HXerKaJfYf+/ZQY803RV+Iopft2vf6+Ar2/4/ziYhF83G5utnYfJgutu2LZFhoEEybjzaf F3VYF4X5e8CHO+mFg9KxDeDh5CmRYAaKBkTYZxgf+uhL1gEGuvtbCmja73kbAK040IgaUZtWn4OL CqzcHHOzb7LDj6RY1TPzINMLXgSc8erwZViM1LVCJU2H22hayPYjEHDOyLsoCvOok3f3G4/qwfHK CExH6IKE7+plWHFaEF7xppdNsO1K8orJzz8jpVWy205QwtS6YxSPL57JRP+pnzRNM0FDZtNPIjQF f9BzPuXw5tEAz1YYD8ihFqmnC2UEzRm33yU01y6gBRlUTCT8gCxug4DLmFfHd0GuSD353JR+/IW0 8pJgZwc5iNCMRpvIX1zaSZoAezTYCCkYSgozt1FozhM7A08m4xGzh6UErA/MgczCSVRgQ+k5CW1S Bqh+OPdGLcT2/+JJYRZTh7GHiRrQhvYPH3Fst7XuN/QpR9N5uWerp9/pB6G9tFH7FjME2ooWDmhz 8tByj6BgpCCMgys3SFSwQ7enIRstOAI4gMrMv5vmdnDgfTwtH2w7u1ZWYOWEp4T4DZmCArNC2bwt FRFy9nnL+WcFxSKyxxxJuD5xWpApJa+BRJWyjLMOHIFBIHZ27wzkTdGqCfvvCTw++MvVrySzQi4Q 7q53MOnyyEWiDCl/08AvYt3X8RCVpgNkYgSAmBi6Olx/Yi+o37zfm03dl/kEn6nGy4JMstMZ9AK6 F2DXhlP3sIGJxYXhOMPitlV5bZLhOz8E4He7fipmZFYhex/DQUBF9+pb6X0uPLqVRG4N22gO9hRu /NeppvBOLpBxeh/H36yxu0lw5tuCFHPkfVHoqZPvtsMUlRemJmvjcagJqckqD+h9eyl52PiZBCq2 7+TBuTjEMR5ugjXGj/KWDrMuaLva1DpqyuvIdCExAIkvwnftqDFy283nO/z/1T1g6VgDjHBJkU9p UVCPvwSW2/LEc9YAR5a5nPt16QAmHGakrKD+VR+/6Og5XKdw6rVcr5MGG9ArjFAeeqC7kv2Cvqt6 JbaSJ+JaAMhsShshu7nzXWdQI8GxOYDoMSkvJlddotMPdYW0UK22AuTmtaB57g2zByLGLgm4H6pP qTeOAx7BqVM2yWlnizc3PmrCEqiNsYqSCHgHaLml0Sd2q1BXOKtc85mA5U6W1WNDPQdmtr8TnI5W MrPnCtzT0f9gsIWi+l4Wkgy6Ze3pi5zZoOBV5lPzXvKQ5rt+pmBD2ig15WEHs7NfY2LkaQyC0IU5 Vkx0FtF+Y8/PHx7rd+kmWiLYwgFUaE6tJ/qBLVlZ1qTtX7BX51VLyHxRHSIvfSPu17Fehk60/sR1 7yZG2HECuEuDDRIQ49AfU5jVCQZQAlHdJuOYpI/PSEjGltDIjrcK8W9RwoirknIy3jJYGpTn3m/Z K434AqpoAfiA7M+1zLuMSWw9nWmnedeTJiZzi32ir2HiRolSvpmRLXSUX1CX3tz0RgDxI3ajBtjW fNdqxz/ea12qVKh9fgBkRJYZXYR8Gh91SlK42u8pdnCnSSN864o2pogwh0kH4vKOpen4DAHDwJ0X fP3Br/XWSlnM4Tz1Gf7HQoRGn0qKrFPtLrXl4DcHY30kepBj75NRdDQPN7hm9aVG/xewVwEx12dn GuYu665MnOKZEA+V9ZaYIMal3b4jWveZJO3aHZWrnVr4cerQ6WiE9LKozV8XBvu13DcbLAnmXxh+ 6SQ5aghwCJIKZPngOhEN6xlPGqEwtZxCtMQoqjw3ZnOQdwEzSCdSXGO63yyB5QVpcMFnieIaNjSc AlVvSBkD0MSvDc9OQLdREYYr1ebH4vBCCer9nM6Nntsyh+jv8eVGFUyZidPQniXNyFJqc4sA7oc4 vdnUbJImqEzxRFKgtXA0EyNyak13+da5kOrYFa7amxYKa6UZG4d/zHwGrcm0TYSTK372/V9dkEoZ nFkjt+78D0aVfC7YkFeRhT8S0T0DU0HiDmYIwvh+Epo4bRowOXOHq9LgY5H8eSiVnswOcF2Wfpjk 3cM3tLL25XTxsYI0IcIBULdvYsTu5rfSguWNH8gJ5koZXOBkW3q6hemas5fNQS/xhHHiEMnex8s1 YVWbmyy6hh1AFd/Y78kBsWnIFZBUr6s0UaQbyEGXkHYUpGC1i92wDOxYqS0hhWotuwDC5hChqNP5 slryKpB3R7Uhr5/Z3Q+DB9g3TDVRbdrUuOD60LkUsWjJgJmKUC5aCmrU2jE5oBmuHT4AzuruOr4O m4DbPXH9+hj9SAef6TnMtaTgzm8zcGUv4mdCiBFx/2regaZ6MyADYehKbv/XUiC/CtwFKgXx76W9 8nAcoPf4OZ4M3ySPB+fu1XIA6gAd+SRqCFlckljT3KeS9zqJQgiunHprdt57IedxRwvdujfjX8kX XtdyEls1w3QlVzX5GbVjx2fymmV9xNctd8rm0OGAWP44ou/XV5qLrVTegTudbWbSLc0VNRmmS2OB 2++UvlCotsrMTjuXhREqu2+uge9fScqH3eQZp0ggABvM4j5jEoSualhrqrHofRWR9lXa06rpHO0W 4UxH34eTRaRnT0rhlE7jfwWhyphLmDuJuhrDNk4uWl+XtuUw8eTuudCpqYRQPOOoWoYYsMoHzmBB j4eyxV538O+FGA5Vv9HeOE0nf6WfJ6LT3/3AXFeCsRoxiPKTBWhmmZ4iQLnq9wWP/YFwpbs1AH+X cctpssr+W9GUJ3msTzCBzW1uCDmearydU+HfBw5EK3qfCLbXUp9FxaUJTgm5XK+VhnqxeOF3i6w6 GKo9woA6SUJ1kB2oaEk2u7C5/fzS0yGzqsnWoD0EL/iP+F2ClkIk3SWfcjdWkBfoYeD/OU9526EG Ym5EuZsenLw00wZdrthAYqRWKkak+fhqD1Ek+Qsov9KdfNW1Q+OfyzWxi1cZfiA540/t4c6zEljd SqIYfvDWLUZJoeZs5ORswmMCzjtZy3bhL8jhguzHILg0egQ3bcSHRFjmymnJKx9jkzOuYdF5DcoR S2aLE8InjHlE0FNEINA9zsLQ8MGlYofx2R+ZN6qDEObHv8+I+Q6Go8UtuiehzdIy7Xi0voIrA10o k5t0YzKkD3cK9Xm4oac4JJW1X8AWb0TfFN929U5Sd2Ka1MwEEWsJjE087BB6Lrh8fkvrmBCagvke Cx/eTxAmvrsEDR8aJt7XbjfqtyMFLYueWn2GFWWyLWlIhq82uzb2th8fZGyqGvK6Q+K+8mM1yst+ UQkxaWtPbk/EyKn7g4sOda2yZqEV/GdZAr1X/k5UHcfZjTgR5POeqG5Kx87pr0lwYLH6qdJhrtLN 6KnsACm/HfFfJ5aMpjB83kp7H/cGf01J4HR5BjYwAntMBDrPLiWvzPKruWo2/QXlyHbjkW0vLkSR Y5UrrzlX1zs3NqJh/R6O60n+ZoLms3evjK00gvH+Z67hr2OXb2lxvA3zrB9OD7yP9cMdjp5vMGxq q3ljblGQoE4RU+pi+nc52auv2LpBCEo6EoQvo5m3PBe3eN344+CRDATX6C0s/Jr1qI+Cyamkj17d hMoNt0KrHDBnX5Gk4AqOw65fSl//jTUMmrGy4lLPS8K/c8xbobwE/2P9SnMBbEQgH0b0KQFfMQIZ jLFcMUgoOfBbMMT6U0deWhXU/na6+tpVA6hO+iNk5/VHIyIw2NFaypSjryNW04x1mSeTq80RrQR/ TG+8CfvMN2Xod6f3oqB4DK3KBDBl3goRHsp/UFJSF5ePYNJctfAaHEgpFhE8CAh9Fqit+1cllR15 ZhiFDz+CQMY2m5Gec26/KEHpPBx9GLYPWXVQ+oMd4eUg8hT9OQq+SFbuUKl+iyoFdLBj2Of8+mat gWr5Xg4n7lG9o78+KJ93OAvjCu4w0GT7mFgiOgp2hgGDASiARuFdlIWUBmEJL7sBnktCm98ms0VG 1Jz+7PlnhzF2QwqdEU7dM5zB4SweKzB+w/oU6FuhhUreDn3pK0ndieV+OK3axaItYLIh/pLkEzP0 sXhDVvAsnIn1kBwfMPz06kC3kc0Bn5+1lLrqtS9hrThcOaytphAChCwOHqOx7L7P0gV3BYvNV8uR pMSycZhtp9LnJ8N4r7XDfWC/9G9F0WpKhFfagYPkW+hQR/NTF32+0a4WP/2se9sxk5VPj9y1E1yI eHMj+r90jxZaSD1YEx2vgROc9y5DlHMk+rlTzKg1/lHbMljgpvvGm6zePzf+dHiu8CLx6/+TDb3x Xi/csZEQ4mbhqS4hU2Uf2tRXwnEtj0r5aLULvOKi58oHHpvyewIBmdTAcVbhG52ek2sRuJ5uWkWP eLLehRVBmvouHlVfQKHsaDqf6OOayF2JxEa/CKpheG/WlN7BhjZX487nHuKToacx9nyRbw53X5He +eYX/1shSNoA0gUXLrALWjCAkHNuN5lJDhHx6tnk6xXqeH+bHtOXqahCjVH55nUDs1d1w0WXGhbc QMXtHBUJfh+Gcx2exywUuYJEn7Jtq9lGskib24EAYeNVwXt9HsvNn80PwwdcctnDPs/Xji53vqoe xO9CD6+TRTtBQZY91R/hTPoMyNJmpE0DLdKDyh5vAJWVRxvdqJ5Y9ipfJ4h49GR4k06e70X5TW3I APQ2sN6WhlMX1luRnjpQepLUgp/IHKJ+7xCxE/vJroIvTzZoFWyWAnctHWP8ifCiKugcVh3DuS+y FtscejU7bx1GVgSDZyXe6tSzGvnooW0751AtQX/zzNZtJVXxcANpbSWJCtfTXR5ssdkx1fIKg1ii OzaZp5jUPBlhZmeQ/HSZuNliHbp3MNTs3S+pyLduBz+/AXTkafpyDxGIGY06wDlQlXc7+NHpwGcW F6nHzB5Fr+5fHB3X3124HZiLWKsJApN+kGCziKu/1lj9g6oR/jAqN5hgLvwqMRBjRUkLbyPu3/hi n3RMkQnORPFOugMZMFRuc0fgl5GDTlrO19yHWsIvv42YxdAsggZ6+2hor15vbOgXcbOaNQZxiG5K lwtnLg0ATolxVBwT+kVzLHyBqYx4mEBehHJEA4Qx+u13ZUO8BrB1Ldk6C8E/ToKdcACATv5AGVe7 ylmKTF7QqTc4kvmISbbKPu7IOENPq9SGLkoKeAMPdwM0nC0D8m+6Tm3IkmWXzdByzvRMTV3t2977 YVDxuMka6XYHEef00c5ep8xw2hXWxoJHjQ2pvrGA5BH1ugm0Cxsn0lYUl5eA6s+T9ialGMjQDN20 eNevWvifdNKCvu5yhaj17jloKwkUKHdLefV2HXDMcmpwN0+TmKRsJXaheFGOUTTEaSDNjt5b0B2L K71s27xGPBuij8Vy4uuZ0K7/xqr9QKQMMsIFA1h4IeSnT6/dvQTL5Hd24ufaN8pQ9Sp14NBOpBmX FvOYLkNi4bLQJNi0TY84gCgESSCXOD9ot5ZKl9MyuwX85nWv22pUgh15Nevr4g9LjrBkq1AJ9+L7 P0/2gBZrwX+M8Jfd3ANgQy4UhMD/PaE9RnuIYoZy+S0SO9vsqwYqJlkKZmGe4wC3wm+6ncJyzw5K f4/iDKO8V5Xg8t77lq/Tj8aWVRfBCYYPsPXJC3chNkKNItzAshL1SEFtUOZgmAiuocEoFPPBY8Oj OAKfKe3ViCFjZr+3KoJ5+/qA6yiuXt4nhly7H/WNrEt0pD8ildYrWzZUa2uRvONU4hBUcYSsmNFZ A3hWKvOVy5kYSEwCVAjBN6V76zA6y6ikPoVZvWvCwgTg/r3p4ppfYs0cg73FosAxR925dJIF1feY Fj/0zgI+kQBi7KgFY5wCn1SQ3V/Am4hT7NzY1Nz3gJGv14xcerI2gWuKYLUwwfLvNInAKLySrpql H4Kk5tfhdrqe3eqqUpatWk7/1HHrZGv9npsphFdopyqCSjNQybJ6Jomya1Br+ELQ/slDSCGDG7iJ hhECi4WlCUdyFyWhOawxTvoYTB3nrjDwvk03t8ALVyu6R8mcMfCtF4Ny1KSga73HEN0sH+nLKkDT hvyXHBDl7EV3hx4z+0sas97Q9C4iYH6I1zKCh3qemEL1buelwLZ0HlL7d0To3wZnn52ig4IU80du skONJOKZ2q6/fQc6KYBLPdeiXO7oVclvcfuZEX/HQrFqusFB7UimMreNasBvi4EY9itWl+q3tNy1 GL0WcyQLfTf/E18Onx264PSDWPT/Agbntgx8xZwJwWRrEXgzOHHpqxkFBE6MWqpdU+G+3aomuxSg GsUTgoP5k3xdsf8Ak9zo9LRLXv4eAcELgwrR5vmyzuv4bkJtejbcw7WFOQIvdWOTW5iawlHmW4J4 svK1ij/ufIWDrHqBzZW+3oaMX5A6UfcH+WFuuf7/VmhO/N/+2rKJc2WILNGaR0j1M2NqqFf2jvUO FQzoOgujW5CKTV86QXHBBoUknSMnVyeUxwFYSjyGJOXovDwp0rQIjnVnuf7iYHl+PLX0IQ9TJwAl sX4YtW0Zl8Pz0ROMBjMBl31f8zORoPxf4ZAkRQn2OiEqcZJJZkSwsOsj8fqgfuzH5ydnyLOX+HyW e/NVRjq+6HJl+4AK3PWW1BcNY5Xf6Opm47Gltnvjmf1vElWGsB7q6ns/h2dBQxXlvNqG0bQa2XR0 b9XuBllrpM154s/sDIHDAQq6o2f0B+KSIxPhzZvJXF0laZAtdBy7acyQFaNjDu+9QiJeT2rBg6Vu ieSN0mf9DLR628lZbDR/qC2ReVZzPO/GvrPdfLBEh96YAWxuPCM4Sknz3Ed5khzTx406S72BiBDx L75WMhmPp+N6oZrDZKwIA4BC+m9/pq5u+e5xXHiybEIMxro/7jQDxsQ+bJilFADE7ckIFGM0giP+ c1PJcOiAKOqhvCc2SJ3lUFEM70JKPNpyB4EdSeiGDtGQCBNTH1UnAiM2mdzjpN+huB0xKPMIcE9B ao8I/ANnw4I8WxAbfT44XMAk17y3HvN3jMhiBRr2OB4Q4FLwb+Ox8kHJy66I1ZHBqLVNr++S+emr rM48JvZPIpxAamoLVI+ps26Ot/oRICvHdH9S3oMQnRCJLax6Ox8OCrHOBLszW3tvRG/4s4W3mUJ+ DOTUIrqsJP18EOssXf6j51VUmZxGJxRpCjCed9BpJPIp3n5Fwriv5CNE1nT2FWitm+hVrgjd8Nib RhlU+jeCYg84DoDqGppHhzu3m1ipiVAFMFnGT1k2dgyI2x5584lHHO/dad09XoGpkUalIkSJUyk0 +SgYFmoHefFInJcS2NNrRXTUzLb2vm0k+X9Zg8C+n5WOszGWZqW78PcPxSEH4T2IcgZa0GRKhLRL qVQ9LNOQ4AzzsH31HpnwANHa7i4HKNR+04mN4s1FS0CHATkntld0+nlvBVEX2e2maEEqtkrwO5KX +n+pYWgtp9FnGLQHfV7S/OTMVBN4jmUyot5sGllzm8Wt9Ckc6aKIi/y+n8lyjvU7pFGCieSgwr+S evWHn54KKtxEIYkgM9sC5YqxV0iNcfi56f5rEWf6If2aRB98pA6KXg45eCfV0sXISFGGMh5VRU2V aEugVXyvshQrAbdTkGXDlW2HUkAVjTWEe3p6zU4FeEtRmPoxpUjOD70f/y96Qo1nXrG76dTvuRPZ 1qZWxFkdNtzLIQ/KAkmIgDWsDdYi9d3TyxC/yrQ0fsCcX/rXLKF6cwrKK9NV6ul4GqCZclNXqWA8 E281AfyHw43NtCpxJFVKykSUi/VzbMPizvrluEEJb2++CohlWFtTq3rie07U94kLLi4WwIdPJnmk /qCv0PerxDWgAZ/l67VUUhYVH71BPaM0I/Tgevuuyi5pGCpCRj/dKtwre+68MEg6CRxO5Q/xj+So fun90SiXHUbZNalqmX/3i96JclB+N5/18k5vj8FGqTnfHna1A6NjygpRO3TZ0l/kXVh3DSCBQ3N+ 3xH6d92cO9wfNdfU5cbeZxD4bdyJz3X4EMk5Y20i4Ttz61+vV5eY3N/4FcofKC3nUgMBT7+0RxtZ UA/BtT7wEBZEPZqYlJMOa1AS50IDjHIswn3jIaGh1ss1ZoW+CKE2DHJ9P2k8Mqe0P+bizcs7TQW3 0vlFKh++02UoYCBzmz3Qg0jxXprHN6DQg1pRQ8h7OqsU6olE+v+mY2SMjRqTGu/eez9y24HKe3dv nStxMBLNe+l9zPWSNQQn1B8PYpsq6fCyHwSVVeWhlTgFlAV/zK/jqV5E8mtGv3WdzEhN7XXg860v uJKyJaN5cQqEVMpbeHNXoACoqx0qILBtUOhOQIrGHTz+fcNfl839VV/s/EY4ewO8Hfeg/ej9PclP UD4Ovha3p95ynL8pNCD4elQPEliKr/ooL2XEKlZvrLib7mGyjHp22u0+wtZk1vcBxc4In3ruejxD dBaeBh+uJhg/mbNv3yGBLrN6qQDhUBu0N9PJWcyH4WVw2eU6lvVADd5X4oXNSfLn9FSySIepmOC7 WlFQGit91YhiIir1RlLWC/AiL92yL2jn+tr0f4uHFq6jmZoeaFyTACs3RD2he7c/u1z/cAJzt6VJ ZGEEWagNHUYP+KZzCw3qyjx4R+1opQWmivtv5tNfu6vXof+IwaaB+Gb8wSVjLGqGRIz6lYkoB+pP 11JYom0h3+3KDT077J1FUoUQEZen5wj6JrnG86ZDce0ZSqwzke5wdKzcxKdtbxrC3QIYi1KqkfCt QIJNbD/74enijlDi8OWylztscbk3IlQbSmdQcJsUfv6mD+ovO82H2fbd8Y2idDTP6okXjD+AUA8H SunWByzs4NdZq8zQTp1epysby7Igk6EsP4TMMflTja2woIuVDtdir1jRaswr+AR3HSLhFD5/LYN0 Z1Dn+iymwFF47Ls2tNMIcSpeZIcq5HIV+XkmQDw4gcUXzn7Fce3swoesJrzYFfLygc45AVxuL+z8 HTR3/i1wSzwFYShLKSDbVQNwhuwSK2+UCYo46Zahe7mtoddtQ6k5brX00BfeOHV17jcG6Qa7gMdp +Yr7uwuRjTK4pULugfT+fWMnzrjOjGJg+vPttbhMGLG7xRsqYBAzk8ZrQAJhZKWVnBhbb3gz+LYj rL66xI5RGAFr92FRPrTqWR5/IAZ0QYEX/RpsNsgz9XQbUVWfksZvnKmYwbPsRlb5s36owyd7sUYN UHA6hz6ud1/Uj7h+v8qmfYS81rIoX0HbXC/dI8F4wPYFbd6cURj5qaRqTYTIfsFV3xKAFCSGTJWB vP4tzPnQwwhFdn7Kk/yzNa6NwIVGmepFrMHOBCWI5hor/UClxaV9MAvSYerbwVxP+gEvzE5R8TK2 9fKX7/zO5/dSSqwgnmtutchUAQcMuf5e2+u47WVCtyaJr4xoRLEaiDDJfHwChnagG9MCpwnc3Jt+ FgrRJoFSwG2yHHxMC6Jz9PfgFpUAOafSY94k/PXdVZDjR29/6WLIpepQXk2sSuHwleY+btDU1heb EyhKdzg2rePEzM6ugZ5F44B3Pq6NqQ0pUCOFCMoyMuJ6qlHYZtvNWRF3Vcp5TfKQSNyfsaBZLnYA HSXzuCUZkSQN0oT284yVd7dqZAMzYHRTH8U0Zlbp721jEjUHmE5oJy/fXu94iba9K9faF4Je37pP wj1bp+hydra7liTiFlwD6SWhuMRfH4/UD36G8QTZyMknXENh5QHKysXGuQ3BMj0mnRCtBBqgpToR AqZ+JLpU4xpsloVWnhgskNNxpLsfndjhPc1vWB7VCttizmnRA52VMS/L8gRpiwo4wOa3aQhkXE7i cvlw+bGkKX9f2r75pYvJ/yt9xRjSfA1xPGjgtUWxpv6oUymeXb+V1i7/L/aa2hu4XZbNm6LPylUM 3VhJ8FAvhzU3V+EmvBF0/+p4GMZ6HabCoDkOP7sAV1BTIjqhxXIiBUcGGG+W9qy/Zkuy4ijhKp1c vVYhK71clyX9plspkXjR0du2NWbwke+atyUkcAosR+jqie9eWyGtvQykhPSCUYQa7vsiGnv1DFyp QV/w8OG0OFu1X9ZZM82hIjB2oyWNY5zZDt+wOD/VdsoSJhRS7xxkNiB6LSO8Vj2vTp+R5NWS9JRJ IJ4/tlwDmiaszz2dpUX0Q9HI6yhOl+Cjxeu2qq8+JuM+PopK2P0fZ8zU32Ok60pPooqQXcsfECKl 9Iq5urIzSFqzcwcONXEOngwmUuaxOVjFIXJDxNBEtP4Ae3GghskbcJbvKhGuxVZN9eAp9mAAQ6Sn mWd2I5k1oDIC8U8e4je0b8r6zHPNbjEE6UnHeMOHhu5lctdmiCuby53YYX4PvgMkkwGhlqVXzf09 UMqb0eTgdc6p+RnvENsOydjcY7X/F5HQ7WgvNarsXFlzfUiRTO90wzjF7BkmMCq2tXRizosL2yCV oF+XQPQoXLa3XnJPsiLgU2/1EPadBY+QRphUf9wSPViVTFrfP40FXebIQsi8SMyzMP8f2Wo1BjtR vHoLoXW9oDU9BkW+5oNak+VQbmdxtOQXTxHKhStgu+gzY1WwshFbhxyUOY12NSMXE4gQl4SqPors KxAFEerZsRkU1Pia0D9GS3wD1vPRbENkI2c8SygLaU8KXeM1WZbkC0EW1nxL+mIaS9W9JUcNqTMb bmY4fQFq9HXmPEJFJrhb2XR92zR5RMF8ypWWigSRjJv91TJtCDSKlzggXy7OqGLaeLE6e08ESJE2 Tcb/cgR72hmZXrsje7QiT/MNbKg1D8Qt6KxMNZshZ+VjitwuL3pmCKOC9/1KrSC23GJvDWh56ppt fZNouP9pYkEonUVukU49mX4G9ZJiMdP2rJnI+2qSYL1HG5Rpyhfeqxt9/P6K185hRYxExGcunhXZ hJasFBQNWzk3G/zL7iC27tPY1XXec8zNEkZYRvrOCBu7T+uEhqxLIbwr+EW9ByLcISQc/db5kNf9 IaHh6EaJWJY6kLGkQPEtFJbxDlFO5F9ZZUb4vOuZdbg06UMkXISiCQdPoLRSYqlES1vW3tjXG0rm xJnxjwCM2f0Yx6Vn/f4GdoHikshg8Y4fnfDLJhaSc2PM0VfhetY1w356dBf0vI4rfgqILwnrBvjv b48E9jdKF7QTuC0ET2At9MewQgVUV6WobLOZV0rjSug6HEoQOsU+bJ6+Kfq2b7EzwqBTW1f6XxFg Q9G4aKr0GmFJsbETmTjLNuoZl/WPqSjDFT4r69Fqx5IszfEovy0jpJSb1aPuvE2w59EcdjH64pwI Xq1XaKvhWDiRPJ8vmHAabd83oMUPM0syMVF5jA9nRtN+ivVFKPKg6HJMbox+XsZtCfNVcdEPQKaH p8WhMjAtZUgtbpTAl/9CudkPeDjxfNpmmdbywStxoXF0OLA5nQp4FJDvkckGQcE91gwOrkcYaA9r ffKey3cwEBq2bqiZzIXg0MPX+/08wdeElW0e7mTwzcLOFPTfRt0XjFHHEb9qcSQxc81oPxaLpzpM qwRuFqA8CDaWWgjDP5JbIbkGp3qaXppWq9xXlKXNZ3Q5XVTy4emY11d7igVffH0oaKEeJXCiA1LE Zu9HGUaE3wEKsBPPILI4t/SWRiiMr1yGdh6sqgIXe6AHs4MkOFDvhOwloNcqn7zzgEgB5jLuhT+G c2CUMfhDrWR/Lxdcvoo0ZVYfISHaytoMfpHzCVblaBX5Td2HmGwJ6tiPyY9tuvTLDC07TJ+7+UMW OOsScLO5wCmWXyI+JXoOhsMhzvI7xARB2eEaM9MQfm3J58RxmGVuZkS3Rf5C+cA9KHtYuBkUU7NK zU72n8yfX9Xp5OpaR58nuOcyizH6PzA57d82Wu7Q5zWImXLzDp6NcQ2UAqgrfk42oXzdHPnWmnH1 1AZGhj6nK1ciBgcCzbVexbaz/0Xsjn697fBqZwFjQlbS+vA5EZqz7nbPpdKMOdBeJyLCYWNrzYfr R2ajIMe/7ok1L3M6rDKOwlzsvjPLn6tLon40qyF89SMMswGFKQSTmfKdwSMYoBn8ko0HICrqbmfX WlllBc73O7lEnF6lMf687vcujMXqlqHxP7kRouN9Pk79FhNmxRl4TLfzuUD2aV0wYnvnjpIXlIRi kPseaTLFp0/6Lz9OwEw25aZE3k5ABGN6CuYRFfWLgOxtxeUpvCAXZIww9jzAYSEn5w+u7XA6+8cD wMCyeKKUTmBcaUsUjkj1MGdnCvPllL9e8xCgldntwYUllNZkHCWgmCqfE2vcaT9pqa/bLY/1/2oh aG8NXtQpN637o//k/yZFTH1p/hb5rqFIyxgKzelchX7daneqwLpsg9GJO52Qflfo/4b4xOFWhzhB sOjuScnzcRN0FEUJYiUQiODGJoGMhL5yn6YfCHXrUF/jru9yI6VRXk2xuwyAzzJce7MnmtAX1vhn Amtiux62hJbig050bEOx/wlaglpB8sNSxZFAVsff77qPpndsGX4wkoy2gbayJcwQIjVhA8XmdmiT eM7gX9qdwhRtLSXDl/+fVSR1rCyG7eIKGkKGZAIluXND+j79PymbMk/WwukK9Y4YVQ8A1pCy3Hdv AF5IxS2qQH/WARzs9ytqKAA8/c2iFqvoHUaRA3QDR/3Jk027IM4yHdPhO0HKfkJyFNeH4LzLdgFo bplxIiufx1G7OSZiwkh/DSEIZ1LqXkQ1XtWpTPivEaomw8U4O5gJGJSShDsNJCWvnLG+FoxRz+5h Qbo3P1EOqaDZUQhl6pl1mL5gRUP/uCCdoRivV6aY7WR4nqdUWc9dqIC7btE4Ef4JIlfQPTBgEN5p qpR81Ue00pps19ZlOs6YU04l9ypiWUfiRCfWNLCv6Ie4/ygl6hKdJfjs3WAqHo9Jp7d+OI42CyLP 3oUhKLOrnJoOHmgeGxfL7ARV++bC91Ty1YCfV0Q+yLERW5BdtJ3tRjxAL61acgGvz9jBkmoT0oYX Qe5UTwU9vLolSg71ilJAX9F0iLLvNpPBnUzUNM0GboT8dCo/2+jJxPwWH0MrovQ/ru7XqdQoAeD1 dAn9tqLDpYtk+rTKp4Y72DDz3BSUyJVVab+LnW1AdXSx9bxwESt4+qWHYSzGamnzzG4A2QNpm6K1 enZOihbmjtLz2AbjTM2V7wijOfpC3w6QPRLdWHo5/5BOFYny7jD+RqkoyVu+GOCdSs+9K047yp9c /Hl041X8ZICMXiE6FkHS5LLLml7Wt9WiFVv4ZDmR9vKG5ZdRe766pm2Z7z7alOTvMvF12UQ/Pe0a VKR8R+Z4a8RN+Cn/HlaocD7WfuK8sd1Ox/WG4iMOOFggpfkxXC1ILvaP5OUyT+WylJZw/3Zdawp2 wsAUAdMMjODz9mcb5xYHOdypNGJ4r1SkqVE15AzawzIqvR9NlXRw5sDzVocCNgGrRVdY9wH7+2S+ cOVYpOJMoK45Jb1opJw5aKncpIzEtguR0lVbUtui1Idlph2Nja4rwe5Tohy5AFnvQAwtkt3dcsbS L4FJbh/xPTFOG0xdDLrS+aeD6SA18xniVrX5krSQNW/qjRkjPN6f0vcCTjhpJCdvO52kdLoxE2v5 JWH442PKKqlJq0X2gUkuxzu0NkkLULI6Rus9EMQjhLGFoFpKZt6Z1hy1+Tv8W6SpWlYh0rSzI3MP v63Cxw4imgC7P99MuRlvw430qbxrzf2cexDqbiagnBkF+2Zx0AFizqhf8unKNFk425fVDOatdDLt hcsphJ+vQ3/eRIgupgFF+br8anCrFDIX8G0t9XNSYeSECIQ+PXvFgisO97kT2gEIRi3sB9XdgseM ak5I2keFNQLYYZK7+xa5piLlOb30rVhQyOjCNvsNq0syHqm9NUafBI07sfFHhKiErzx8Ei0uPu7N EoO6cGkFaiMmyB3kPpcr/uydCfNu88qP9xZozHrVG7NQrNkqv3QDUw3jCBPVvmrw0+2/6B+/hBhd g8bNRLOnKfVZoI5opZkYU0cBbrQ+4yyHzjV+rc+WiMMVU9cqjkfAdKgRFlXg/Tyewf/37ZibKYBW sSHWLKyQIOzr/TwntjVeR3iLKRDSZN7xj9z4nKSTm2sXs1Y1miTspLdhuRCwi2Sy+D4GR9mIvwCy v0BtlXQMNpXVcdHv+iVewHKNJofxbvm4l6qbOdz7R80pRTfVEbsMkuNCK4oLGnebAZx9UqE7CoEG 0hePD5JJoQod0l/lQ5h/ffLlqzHPdNe1hA36KitvoaHobFH3MPdb+2YGV4dRPWz6rWPwiRjwoyUN CKh/lc9S84gHw1a0LpVS/1TICFip6HNTYS41o6k22W7xik/dewSXXmRFC7wst9jzCk3JFgF/ML8a tEI5bY4eH+NtIts8v8J70M2aByvCsYiXNoyHa2VO80wzaQyMisuuPXc28TYpnVCrs5XxKa4xVAjE LWExiyqjSfMBQwM0TYCgeUczi+JNPtYJdsP7IvM6V1/ULQDt1Kr9vp/a4d3T9xpu2NTngB/48vn3 aRDA2lFv0dC90hA2WkrqqtytfrVdO7C5/XBpZNdZsNBcKZFZzLFYP1u5+67FaWi+pawGzDOc/3GV l8VMNAcnjBjlkyqEIm+fwtJIGLjpYL7EPPhRj/FgkyIwE0O1/WkKetGLkXxn+6x43Yeeak9rkjJ0 vEvFLbXRRC3dSticJN3IX2D1+IQl2SeLbPbl/HED3vGnfA7mq5rppehx6wGUFLVH/F3ccoqjBV8E 4D7W9aADgyIUlpKL/R64DYBc/3iDYPVmL2yOK/fAbedsfIka7KrN8mPGiat60bkYbbeR5QtASKhn eT1LVroBd9XUC7OMF5sOzSgW+9Cpbd7baYNRfAtMAE7VVDMIv6Br6qqeHUBzWwxL1JlMcJQmjERx UmhzUustrP/9LVxGU+TvFlc7KDIU9YrEhQ/64HIWSAx2hdkZn8rWNTKJlUY9CrQpDOnb+RjeBNBA t7poYD2xC/Ie9UKN1XxinIMa7GAyMGN21nwWKlDAyMMKyYkGoo9Q5coo5uFb6P2K1U6hNXBL4qc6 YUsweWSEjmlcLHmVghXbSNpeQZkzH+q4Ey9NlUFRUUJXTYEG85rlJXjSD633cZ4bszeE2QiXCzuh R/iqmqRCTtZtpFG+5PVQ3QDur/XcKheI4Oo/ctG3wEBqVyXsMKRrRO0de6qHBWN1omQVajBpHYuY RnWnxTADu1uNZ3IoUUzuEB8n0SC2M2mGZeIcQ+ekelPbvUmBNKSPAtZtXk73TbH1pzak+1OX2WqO TBz7mVn8Az0x/rqU6+nlgHOBmwWGeZpfO5SbVOm3OvZOOIkqz8/cCwn4eb2+zuDE+s/2LZtf9PKj IVnftxq+Jn0qr40QG65JJ8Qp33BMkBlnIyDW1HDoZuMoAu5W2FCY2oWnhqZV3eB2PNMHfJxPJeUz rAtks8YFj+0RILH0XAvJJ8DmlsaVSBUhUMg/1IxevHjE2wdAu3fUdmc7zLbQSRWoOdsl1MZ9h5nR Rsw/GviDoV9wNa8pQytbrKPHWLyiFPc10S3v1ALYn1UgZoWmD6eeGM1xVaiFFO2cEGrTPZEvv2kc R3iTLxrxaVTWXnGOFxLDeaWL/f/AuINVwrPK7gV5//p+0t6BMEFg6j0MdofIdPACbb7YYfUoOm1L /L6Z3eE5T4+NBmGSfM4NfKEVrkpmcsEGNA/Hmx8Alk0sZOPEU/tcJE2IPW8ds+pwtAi7/P1UTPiz g7rNbxrKL+I/j+9TRofY7u7Ed5+xbIQY8x5lvBClQoOJ3/KCaraGyPeb7mdaj2xf3RU7AFt/q2Zl u2nSbHAhtGptu08khREvWZJ3Tbq1qxScqEF7CAXOv1wYmevQ08IHFRbJOf1Fe0n/X7f+O6DJUlfb bzFHf+GaAWc0+09qvtNe+bBoo7B/a/KZ+zqdCkLD+0s4h1fpWIpF/3AfcdtfaX99GQVaLWDTgbzS QimMSOVkzzGebUW7uPWdjWP0kcB+zAEgpdltM3gnZcgp2F6AIKsTMYyHa6ZiPIU8t5FD6yU+DOSB QztTejEs00xEyUa58wnG7anbsw4GgegKXPMgBenIszly5MIdj+LLLEaP/PPf7k2m6/qbaKOTLGNc FnLyaMcCSPMDQRQWlUQ4PiWb3PRjxEAOLKDJqq16mbnfSLRNn7ebRk2K+Wdx/ZfKqMWLqZUFn/1V BxTs6i4NWFyIvms+c96mUpd0qWFGPlddnkRmbSjFs8xb3+3ZzwF2Tx3iVNiPXp1DNZIeOocFykJh 2fAOA6T5npjuL5NKfRH+WXvUx9AF0IdY3+Hu/C9YdBsFqkEu+a9gotecW+JRYlweUweGTcNVAC8I B2EboSo2gdW+Q1Hos6hN7l8lKZabylC0HYYK465a46TW8j8tksRfFcsOmRTtAT1zFBi2JGv51AsC VTxnGbv1P7drnerE8Pnu6P/WLnGyvIWXMkJAoXugF+YiS0dhz/t8/+3f+lBpY/g2284NZMKuoyAp 7YODGdfqvQ7X5EUvuUkcFRfwQ3Hx+m1DGbiOdY+S2XYpfoes1Rj0yFzjzWEfikRbvfTm6Jguz2NQ wPl9vFDpR7OQE63OMqf6QU8q6i+bUoDjS/JV18kGl2ia5022qRRQ58WQ5G1+zcmPUMMa8jOR+DpB T1Ra8t1cM5Tzx2z0CcOQENQNvCr1Lb/2b7btr1nCv9pTFq7Qjq3ZBq/SmezeEf7vKGu3EoDNqUe7 1VZKD11iwcCXuaM3tmziQP4LtCqdYekcYcxhJtYY2O1J/u3GXZeTN51moIW0GKhYjDlP5zj07xl2 NV3wm8gkuYiGfAJleJVekhHvt9lRVdOivdTY5PkxNOwxGdfOBUtP0NCScnQUpN1uVNDZq575gLlQ fQLm/8buanEf/wq22tbk+4bB9FMmyMFm9C3MU6rufVfScM/fwdHhNNX5BRugDKhztATUpZPtq5PF XJoVQSrAVnTmugEuj2BFZTWmLpYQWC1Gh1zPNj6Br1oZ3l1GyOc1l3QzdBnggyDs96fFLiL7A6Ls hXAw9rd2885N9YO/7/ZUcmx2yE7VaBggspO+MJ7S9xYbGxpeAY7JpeaPTxzSPaH09S94TknC9Twn R+/xZLX8LfC3Xf2wiNXK6IARtgA3FLiu8sX/h7WqnXD6PZE91uVXfvoy+WR7FEn+kQgv0gZizmbu wcDCaoc87mcuO0Y6i8sfE97wIglB1gzJahJEycl9GrPJq1p3B3osi/37YLZySF27IjXIzyWvo5qC JqHUWFCjXmOASLsKz1UrkJCHdkPwDQ+58u1NdGc0Fjw9kcBmLvAC2PfceAtHQxPGCpTg1e2yhwcd vKaBhi4XLXr67nqYfaHOVkP+gMQywvzUZeeDwewlMX7mAY5ZRWIxL7TyMoJnfv/LrYl8TfG799dB +Fl+bdRy4mt1S7ASQ+dBqdw2+hdvOgbLB0dfUmwW0OzajRVaXJdnAGXz/5bzL8X8JSTrC1IJi8kg psaFE9pgplcSq7l2IpS3Qlc0/yz5BqREFaIN44q8sgE6rBnKyX6ZkrdBeetpz5f4fkwE6EDdCsH4 SstBqrZYno+s81qvdJaFrY0aX32jhx82JyJRrWPy+C9MB8fzYBv1oqtXXGMxsRwt/X6cn2hogncT 8b8l4mX+eAbjeb4tDzdbv0jCqtz52oSwFOygqci/SBgs4j2Nv2uGITYl7vZvoxHseMWYrppIjy2G vZOf8DaKpztpUnw+GtuZiqQp8kXVIKEwxk+DFvS6yRqh0s0k3VMOlKo03EoTRqE5h2mYUKIWdfun rUHB/HSLCuW9vF+XDhY/joiy46osSqiDVA/iDr+JQuRsSOTFLBu5BJsqtmNAlR6dKdTbyhkPKAzp SJmruTjcLbKVSzwXClgXb0EPQA9+puaOb9ZhGmf815RURuPD8OZqOyIuI1ZflqPrKU+HYDXJajUc mAzMtKb5MSUo1qjRmVq+hi7YzeSMMlXaP+RlMMPW/XrXyw00n/CBtVC3TEHsSgG8unujgpunl/x+ LS1AK0sezuEZSSIDikUY5OsK+LK4rNk46EjxVWuPK1cQIipk0pmEqc85yWXwmL5zX5fG2tzT6Icb KDSENFTS/Ue+N04JKxJnrzI2xlWEouTp2owzkq22tcncC80onR2QQJVHr4LKhe5TKDAxKuoA7xcU Kdx2NLJ6Ga+b2A/w2Icu7WAFHLJbcgu7EGnWKGb5DPH3jaHtUisSMKVXGAgH/AQPkfF8SQ0Y2tW5 cCRGI1YWzVF7DBMUT5oNm7AXpJpZFrCkcWuptXcuxWjZJo+GhPDFK/tS3Gr9sA5D4Bh4HQaT8M6T s8OcP9IUIa6N13WGlXQQ9PMaCwLPqQuySSQgE8lkupP/wOoErxxlhES8YSZTfNCKifw/gi1rGnJo yGg8aZUQGlidmZ1y9jl7pgqIEi+bGydcCMm8V4bxmDPg45D8nq1ZJ4R4iEgH6Z4CW3+NPkNNGbJJ eexjg+wlXiueRNRqot5q1HQrfWOg48DVKlWjZezQ9zjfDEwPwhIhLl0k4w1zt4MYQHVKH12psqZ9 v6D/rTiHTp495hjrNNDNXDfFWlyS0jyL9NVUeQSTi8WF75IEClFpQPxcEaOKtpLwnMzW7wpLyVZ6 W+UoU9xr+enSNZJDQceupdbJc6zkUc0VYMQQ5WH3GG4Xau1EQ701oBzgbzJ1q4/KElpK7SJQm8hO idF/uwrFzuxaytaM23yvDR0OHRzE5eWb/VJyweBq2KExFQjs0YUFG90biFFYMq/pewJb+EVfkRwA lhftaGYPDpWYXlmsdXvcuawg84bi8Czh3Sbist2RQ65kXWpTJGxHYqP1S/iGK+LNIMSy1E7vE2oK wDvd1VUvczNNOxLaI/t/1wbp+Dqny2Ju0kptIdu2CDs2YI+M88mbdepbFdPSWXLOUcII7n6hyss4 5abl7v7s3QH1ZiOYqW0p5NHMu84PGv0B8IeFsKiCz5i4RV3SOen1e+otCngKcpYcdzdQ9lBFMhnv PlWMfVJ0UmhZNsLqGOjR/zZSYJaZuXBMnRefp605qpk6fmwRsl7HgbFyWRSGsIRWmBipD+3PIIkw +ygz60VBZhTMrLbm4ubl8sKX2zgnaiBAPtxGH3ZWIL68Fc9Rk7V7s7xOZNi/joo3EyTUsMfweAaL 1nJdgjf1LEuqdVU+KBnBmByGErirFUHLBO7WWwPD4gezyPppX1b8g7JYJpGMDSxOhoC4sd4Q6qwo 02IIAJ7rKXq7X2AVHdImR0ZTjVUFnIibne4yreKR44/cOp70IehzvcAg3ajMIYNP5hAIFVr5CXmM b4Tv6AFqNIqNfrzs9fpTuXhFhhjpr9ooe91Fr+0r4FZ0MBJt69zdHHRxlCSU/A4/cSjiGZZXPNDi 691Pu4CKZfS+TOrmG/LJo622pCTE8sExcBU2JPc0LKrAtERk7jn/gTngS1ORvS2ftgQq8vlGzmQh B4yu4ZSG96GMbbH7nEB0hQBQj4fZbweU9k5vlFNuZVJqTp9eTwQ/cz0TShFPTRBr71sWRLPOi3RM umvsp0ZiR7uje9qvvEciKg206TzS/VAispc57CeVlc/xT5xWvKExFN5zGBrSO0hFhLxQgLIYvLT5 fkQ514IsZ1QJLKA51c8qUEIseTRJod7rEVWBxhPKTCSlRaTipSToiWRDk8FZyvdXCM1AmFAclqwN S1ZEElKezii96EC0V21/C94l2u6t2MC6YBKKP5zayQBLGV1UUjwsg2OFRHvQ3blK4+SXmIy+fodT dpO1dOYBywMZYjxFXXaNB65xm0v0xnkCv1DRZG9G0CsE25v8N5OnXbMIj1PpeHz01Tp0czi2L5FM tsk6FVIXo74NsdgoGBUYZby6+38ive6n3j9taAY+RBsrv0KAqMZHyyZPcRMherQmdeYmdda7a/8M BOOhuW9HXbrS4KmDwQqFKejm0kYBAPLD2jxl6KkqNK82b6shyBkHm598CEzd2dH6jCQcWE36KT5U QfoM+vPLKq/Z6HxjKHvHIl4+oCymhhT+GqTIwo0Pq8BDlZxW7TQFTkf4OkUZOCt3olBniFsry5Pd dbh6SLGq9946cFvR01X2O4xI/nXko/N93zznUdneFpNri7GM72xVIBqHBtU0F/0Yw2xB+MdZ5e4L aDbvKf0AyuEvzmJSbs1fyCLVdbKol9bM1fZ/+A4xdUuCM5O6UQNKl+LBjIOY6l+ijyDFQMdLHDGL LBh24swfTa27qR+tkcBMy4bAVSE0AeZl4butNtXttCZAB9ISAtFm6o+AkeVC7gTKcNb+BcI05N5z MYO+8sWCwaul0yEmR6uld2iDWHJv8WrefkPNt5Q+L3uqD27ZbKJd6AMoSY+c3pkjMbOPSXSn5pq+ uNmcVo+uVyMr+8KeXX4JYpVCtkN+GaTRMFXpcS/ePcZEyuf4oyBl0VIgIqPg7XYcj4iZVsBVH0SR WHNDjlMQcwAka6tK8NRV8Ns+7VYrULkqLJwvCu4GZjPnmoijybS7dBzY8+QIQLHVseRKpU6hriXH RIP5Ti7VzD1b8afc3KTdfswXgRDunlhy5wrATE47efSTMX8HiA73qwEE9hdH77KD0iAua/DeyCPX mYniXp7QZnF8nOYzktqIoMr2tT/ky6dHCWWvysl4n93QIxQLv8r04CIuzX7qHyQ5GhAPYg9q4jYQ JgVubts1ArQ1v0mqcASC5kS56+cQ5ZZf1HYpQfIxykPT56p75onSobKq/+H0lfWvaYDzA8S1UQh2 Cgqhjkw4ygwytFX1c0I8AJMceJBgrqgO+St/mnqy5JYfaDaUsHj42ZWv5eWDfFheqdqcJ5A7eHcN okX2UZ5rCefHuYbqjzZcJpAbAtLHUNlPEeUPDRH5lE4ySMoLKPMpo/SJakPeoaBacjhZFx2Wf4zj Fto2brgjCCil5R1zF7z8i5fu2hUl5REqdySNoY/WSCEVbe01NAEYQOJ1eLT36BaNHKu8DAevEZC8 SOaDozrAM9l+T7TX0Kgi4D3MfA/jEIodL1BscNxq7IhOIHXIc3DwNfR4C7OoiwzPpDvvoMb7aYPx 8uf7vpHJYWAsnDI1hWKhwZIsAJ7p3o6pDObaNRgNdcvHZWpTspWce67IEqhE6ZWoOOEjcbQswBbW Ldjapc/gNBWjW9ScCRKr/Q8liTnyuwpWkeCydn38xi1WUs+Ml8Dsv9gwB2zV5YUTa7uRjlOfHXTw qoz6zWsyMz2ShIgZB4jDxG4UVF4mUzdlVvXvPKqOHPMLF6rBQo5DgScQ3xhWOAPqQW+uh6KiVfbA NUb+gpiTdxCf/87uKLEOOTbSKxukaRtCu3hFLjzuelEZmGP1ANl58u6zsqVfhkk6pEBM9yUKmQ6Y SPGQz0CcsjFzUderW3ACeDIVOJQWdpccDU2TOEd1fT0kLtKXjJn5XGT5w1LSX9jicT2oPDncmwBn 8THCL1A1Yqi09qLSoow8JUBH2W/SiG1GsZPB/Cpf3O78BJnioYvrIAJtxgR3hfiAN/bVUtopp7yI RsmgTbUAD8goXLxbm3wgEsvemlE8L1xeR1H30bspsAxGnIhgV68whuIQOB7Nuv/2dpYUTPPhBH0s mGWZ1DI9N3n4tB7TI0r39C4SPRuJs9iDc9HiN6IqgbhE584CL47SQ9K9HClNkeSFkMiQ5uRF/bFl CTmw8xxaqPcSrrTBCu4vWltfOoRF0+S5W5SXPPyh1A7L/AeWTQruXaOHEymi6HSvFiDl+zpf+scP b+/Mr3NDIEb5gLnq1MvGBPNbtc2jHqUydV9BfE+/luVV4QH6nitLM3HL6Izp+aevC8frAxu5KupV lh3dgRuaExXRe3TZH1yNGl27vtvZHgKfOkrk5y1rHQlborZF524i01fdOEHUW4S/ADcVy6CF83wN SC9dBYCFmGJIwItPLhE0RKsbRjb1w3iq5rxUXsu26sRqwQDLH5LLlLow/C2cga+HIw4QaJJb+xBP 3SepwvDosRj0hB8Ln8qCrV9AKF/pXE1iuKNng4/VdAT37H8MRR0xqQKlJWLmGNNy3DUd4cs54oY3 FQQz3xuydpFiIMgBd8HlbJ6I1c1GVmqocfb3ORnxc3eZv1/kFRIagiYHWXw+o6IRne1R0Be3eg+q 4ja4zSBBIxHUBTowGD6cy1ACGgujDbD6pAbsKPGTEolJai+bFYbabtAaEY/lwo9hT7/MWFCdD5yG sxu/pjuN7XBdINYD0orQOiIk0EVg2NbyZ5AaCiAa1gfOYQdxC/kYQ6Bz9j8HmpU6EcERMF7J0SxL N7z1Adi6C0FBBkYWz7XBhEa8kBctCregsDvCvImpJgTs09HSP9h4Q02GxIIKpN8wgg2NbaKNenHs GdJyBFCZqN7GrpDD6zjUXcPGQo+7/IdxYs9IXhwbvh3qlWHa0xRhuFIkyB2H5ZNXD9/jItL3P9rK He3fMZMhB9g4z1dDan/LdSd8ZnvEC5lb0IJIWZptdnAVTJD8cQKVB5qMRUQyjLNEfcaT9SafIn2E Fiv4ca1ztWCgR6HRhYQcOKNZoLshynGkbQUETkryyjuZG5UqTzP7k3bAzpA9Ra0WPuUH5WHyQ67Y ikZTno2pkuLXOlu6svFDktxVBBkN+hehI52FcYcVlKPbXsUWC5tWl76jSgZtCCvB8zKjjXQX5SWG SfMWxwyTeAQJtGojp9uXyYYK9NWi5aJ1AJDzBFzLbZvoqWMQBkng8MocLQ0NJLZLybkgJUXkAt6S QTZZlnhSyPuQQ0iIbaOM08XVelVzSBJXggMMiKaQKS3D9Mx4ylUVGjD1ztjvqAkSix1Le/oXxcDg 2hGX0djZ/SbJjq9bkKDuewhqhuRdWmXsPHAQYR5XHYfl1u6svqAJcq25s8lGmTwSxVdRC9j8UGw4 cZZCEy+8yopRmMbOvcfdifOIic/fFjX4JIbNf6EnhTKM4iptRkvTSzUg7PNIvidRwsyOO7SXy19r /jEW6Ydtw57FaWC51NxbowwpHR3yhku5Cckf7A9ZtN2KQulpFj30C/YL/Hd86hkZkjUNKvwGrfIk uIu69rfXQw9hz5nDTZzh9YXdcGMnTLkJRum1T3RfM9VBrme9Oep7vZzj8W/CI/umgyTGIL6i8gIC jUM+S+IiVMG8WLcUAIjdVSXMoHxgm4GoIrFjcL9GqUlpaNQuDz3ajo7PqM7PUT1Scgfpn6HPltCS WtH6UcctN6tc3t20hw36fPIMVj/68jGCoGrysNzAjnbZHqqosulQ8V66AYFCObk1yoe8vx0jkbAt FwgRjm+TK4LkNgHhpArizmvamiExBgq5GrSWDLIaJb4onkx2rL96ATNnf6zjn0JdtrxEqNhS7deS e05nc1/taAdmjCG7dfXv+i07glgAWRITI9TPeM1m/TJB3tDv223XIG+PSlLYxL7G9+6yCZbERAQw flS6X3P9DwYeoPHbMp4AVintm0NDqxXYMKcMwrLvnISn1TGjQU0j4p9Shz9xhUxcgeZeFArMXGbO IRULYcrkC256oQ9dsiZ7Cq3zxfuMJPZX1lKSH5Ohn5ojt+sXUVK2AGQgRKBzo9K0/ECRrLF245T0 ffZ1sCNxNzSHPxtVAjwy3Brh6QLneMfoDiilGloeFTeYPsTPC1Q+LrgtFw+ixoIDsLnquNIVEN/N 7UCXnve7OcccAyBdq1RH/fnm2YeolpFTDkqxA3tZUFEzKcNcSXvcGJ8arSHC3ZLZuw49s9FWSD/e deza7y4eoPUZZBaBrwM4VRDObjHhAgx+yerw/cm0myX81XNnAdIsqaoIla5VIf3fm9+KHUhndRXK 47Y8nFMDX5P7XjX+r+Z7G9ktLgtilQCn+lWaFgi2PW+b4D/2yWXVSjWb0lVDuzlgnsXm6XN+JV72 xM7razv8vJpe6i9Cua7oTVqAi5w9KmMlZ+kKLmqHgCcQ4VZUCOELzkRP5herMdFGKsMil/iggy+C 0HZjSMUepWE4hW4tGob1/quy9CqRmNB0hUkB1hue9byV2BtCyo98pD7AU4za/Rx++H9jJCZZVoc1 HZzkiN3Z9o9iwxFwcV5V99qsRcMzWxowaoyZWIKU6wyv5AFG5ALDxRg3Q+9jBdVjd2NFxD2SMmp4 q4eiAIO/4NF4yNhcBAOCffnTdtI1ITaCtRpj9WoEOpdYTu8kJE6CTNJck/cc1Zmr/91Acilypqs5 xB4hEcaX6umzuoisBeZn4fpPNF7F8aSNKjZjtsKuKlEsBbgDP9iipdfi1jJhNII7G2+9R5Y8I9rO 8c6qgObPQfrgcFc/Aqw/tSc0mgNMgUDUrgKrH7IXr7nOXwnvnhCWsC4gNHNDg2issZFDHYlYZ9PP 6gWbwoWLNFvMhLIzxTf3D6o7CAG1403G6CPDaDD8RBKGKfQOKojdQvmkxlgR2DX8k5N5xb4DrXhf aUf8DMjNoL7N+L88gF/zO2f/kdMCTDcbf7eZ+BY5HJqPui+RK1tbbEH74wF04KqfIO0f28W1dK/I uGhAofEuNIEtVMLQQNZ8fVUCOEaO7DKyqd3XBmNkRACRmozBDGRsPokZKgQj2Faw+xZy0oup4YL6 MRvENte6+FJPABYjq50wfX7gjQSuhMEr3H25sNj1qm+n0KsqDwPaX+aAoM596HwOnAAG6SGpWIPy 2fAnD8+FQ2KLVs7M1RMbZSWq85n/3BehaKXd++ev+4hnFiMLrntQ4qiSecYJgsdHHH2uD5LLI4xa EngEgX3T+EfutEOr/1sVyPOmH9UH7FFRCUlBg1IkyLIygYdCNstPzlU0b/aH6rV2Jpv8dgOedfzQ E4s0eqOqyhTnGXhxqYsMuegUQXN2/6TxMHBqaVLlqw4IFIlDDKMakHZTWYcRzCFgFk9XKu1xVH95 bFNhmKzWZ+f/9mLD9rRs7PENV4byKp3bYJd7IjmItvHFjXlr978QownkkpgvD+yiNiAvpX1nY8cm RfuPdG+/8qBaU0uLwXA6sw1mA62kK5pc259FspiCS2yreo362uW8ivwlNz9YGKKEbAd5fHpySltD KwkN0Pl9EegTy/g/LBphGXZD7JOGkk8GsC3OCOg7BJC5KF+rIMEIvHAfKRpXCVsBKTuALPfaZiAJ M8Ts8/IO7ErPYQDo+oHhBypcFkHySpthPgVKq3KKni9Mig5rJ8xICubLM9F5h9yJGGyh9WBXgSk4 3h3xPXyRpCCFHZDn6tVQ9L2+4YZjVsUJLA4GQEijk0oQ3dt4ZOCD7hALjhp/xbmeytgsiz3Tw1oq ppHatQ9WucvqYYcAxe3yR7pQEWGGRt0nSYC94QQAkHpOurBatNmOAnFR8BXVX+18SffDA9Z+P+4c g/0QaBXmo0D2NhR4t8MVG6NRDEUUfxO46j7dDLDaGFuQgXM0khMlUuFFTSOd2zVfDzpwqrMNaqbR QlKt7a5UtSNpiIEC/hw0bQYEp8LX3kb72enXMmErHbmKfnbbLJIOkP6ABYzokHUUUsuQAqBzvtAR tM8vmTeE2bdKuGGpSOF5iZKfGQLOQjzXcqkV39xgF+TTi7VgB3aAmyoS44scwwi0C3ufwqlSuZwh r31LsGOX2WH8j7dOm0hmaU7JE+2NLuKqcjDokfXvMDH5E4lOAinF67z96a6Q8g5bJxwNm/EKcru6 GxYEPoJZCKa5ncMYonAMso1sGc1UJvG0Sl0uXAZSzodZI3ndyGqSPM7yvX0lwbGTjCcK2OjPIZJh AdDzgO5Q5p3VRloVSvQ8HceeOsI9TO5uUHtAgBlONAQ2sBw8ZPbWJf5Wf27jPFMpgUpVOnTOQlMp 5FuJiZaV9xDqcLHIqxEuVYKhuiy0EhxJAxd7+FkX7e9pto2bPAhmbrURLtnrCAbP7CU93lTYbP2I DarYzehyAXGiuYywMbsKIzJJc+3c1wPUadwo8fIvRPcy+oCGeKS5zNmIb+tO9BHXOpVjjDKEKsqX Mjy/yJ6hUMqbvt5r1y6a9IReBGPYLI67xDqql59uxfqj4p8+t185odYfDgMW/+2T98unulTSJceu IViNaMl6ZbFPcqYGxD6BNdAYLDKZ4LYxc/BYVX8JHeWEkOrtgZ8YJ5sJXVWxWRjqfYAfAw2JtHVu pS2pDozV35GkZhB0aBTf1UmzzAaMpiGQOysrzUtND/JQtjA2f5zvUEcyR9DJ4zZXyJ5dR9ivhnhK FVfWwvx5QuP6Je1lVzvwwjocv25gL0NUcxSDcnwc7A0FpVZ2XJ+d8hYVp6jfDEGYNJJe3kpGi1mo wpLau0cQ/QCKQKSw2E/zO8aCNDN9PeNqINkWhDQ0wDPYCzjw2UGJ/QxHB0F9z8l2EfQjSH7wShP1 Pe4EcQJY5itFiyP4sQRtRi5hseuDdZsxiA0FmDApQrz+oNkXjBSgtXmChNNO1N8bMzhozq4HmfJX WCzPbz71dSA26cMMNOH3rgfq5bIVEutIIUG1Iwb5n5foEaLg7NDgA/8aw2KOT/katjl3lij3UBEY 68bPgio6pvFSLsHTj+29CGWr8rAyUwrVN/Fu41QPJdCUVsDDNCVPOkq2Ml/p4EvpC46cvxjIxGdU ALdSM6QDzHB8Fh5J539rGXUFqk94nFfC9fSN+auQSgaY0SsmMtSDJuVpvLNInWSsl1rUoQNTyLJM b6gtEkHSdm2Ar7LOPeDBCiG6yFUas/DK2qcv+c411qfE72iuIUMJy6s3Rir6Pvb4XJu5J29bqanE I/FYkpz4N9G+ZH/fowWU9jN0DcZG5mOI5mTwJqdTRqfEchcs9SU0CLS/WJHaPD76Ui7EEeN56sEN ldHGlIeq1STV/jsdldzxsUsYjRbrNnzHTR7eQc+uef6V0qklaQia1vvk4CMjCFh2jhWK08BN/TW5 Vruh+C1kJzzhgJN36qv72FTXon7L96P5cxmIjSsfv+jZMBIFrANPLThSUqIbUY0YsPewLw5Em4d9 L27pvl6wE2dsGYXbPFyY0yRKw0Iycf23yWHqPXYgSoty9puXzatHmVA8MgDQexuYViimD4fhg4Td 1PR1wk/QGBVT1RBBhmZma2zYHk+9uKQP41iZrGSFbdwrLkoCIHMs5MVZU/jjSVG+2l0g5itRMCHs K/ESbVULap6riWcsggXseFRYRkjJueOTih3uSdP/fdWUBr5TXUVApjNT+IfeEVBGjABpgkQhjYOC Bv9XwI7KLHZyqWhAAj72ZI3Yzpg/ctHIdc3xgFWy9TYuKwk0MzloSPYfZLeXBrHhDVaPFG+Z4QPs oVGfWXkLGmL4ZbAvKuGBCilMxZau7MTXmdU5zXOxE0CbHtH6R7ofD9LkGMwMGTWYOaDT9ZH58/yv s5EvHkndh933n8Sl1WKdZK2UFquT16fstGUL9WD9Ga45/AL0xy+Y/Dgsw1Y+vJMBfYAeBsGY4QAt /7svVEy0ifKyDDVVVS1UTJE/vYO/jz2jkq2Dsb32USB0HeNIa//+9ngKDpLZVHANzgMI86C9OvPM KOsOXnkKxz708UO1+X5ZJTKV93+mGDKSDA3s0qRM0g0lM6TEZx0SIIzWKqlpLixP9D/sm24q4z0I 1H5C7EM5OsJtByDR31eu8DNcn08DLvpW1A99ELUa3Eue/gUngEQy7dpJzn7FnYCBb2cvfDTfWscQ xI5LTKNGhLxXo+v7F6bjH3GfU/0Qgc3Nga3gpxxmrkqXc+uNhcdMROUTUVRRUPZVewFOb/g8y5aV WnTriIm3TDxOmEIV+gcQf4SpRUwZhQjPHN6G40F0WwP4RP0cpSS+L1YrpmhXsM2insmbhEDNGiMO K6csOH9dxGCrpPlKkbaiWl6jt9PmzIB9PjbRQXBFtULQVIgMcqCwWGXGKoqRZHj1WzyiNRGt+yT+ eKu9BpY367JLCTL2SRdI6tYXmtu0HuHGgjoXvxmqnkd08jAGkhGKwUlpQDn6dDyfpBY91Wfq1QbG O0mAdpEo0NBt/D7z0+uNVE4mzMjQOgOXyHB4zkpb+2P7FUoDjjFu7blZ8I3sWpZ3sRw3NNSK44wt rqAhz91VKT9Wm2UDpX+/bwAEcfDtoiSoO1XRIAUeFXx+9GGV6gJwYnUSMGgwnAAsYwS9zLH1Gh9M DRoKstwA7eS5yB3T4Bwrhld9JYxCHLrItlIM75/45Vfh+Fd/J62V3QI0HEe+OrrCuxpRfS6m7ey2 lBdMQmzbZc5CXZdMz+5PcqUmg5eNZCBRMZCS08kIoQY0d2/RBlLAKEcFMLRhwOmEiybh34731dck esUU0USmVZBLiC7RH2/StD8ByiHh3/tsCydUtVv3swQYdPAF+UVxiQ1eSZtA422Cyz+1Ma3u5Seh 6sde5poLjUShUle6GuSXpsCq21phEg31V+TF7zoBsyryNXjSNodYM0Pzg0EYDI3ggKrdDkW7f9Om DJ7JJiubpcZ24Or5MK9L1jiXmZtI+Q3KItSmHm6POwIBhSJe4y+bapQAhZJNTd7fCeITmDLND4Zp AVMVv4s5cGC2P3EgxOYUYC5lqrYvgOV3YavgAtx175V6Ulg4lRHeBICwzJoSfOKUB83fxuSGftog oxS8dKILvCxi5UCKd8JfaXMivpl7G1gq96ZPsaJD6uKmeToSLUxtTMlacNRbLeBP/3+fiSyir5Mu l9WzASltns5X08f5k8V8kC42A4Ao7KjQ23afCi5uMS9j2U/mOy0ktreEQzjRzHTQYNXB+MibV954 Os8vxY43LZ3kJGRDIjb6S2JhDMXV0ZyOI1lSxRnegFuG/DZUs8rZeCjpexIE7lZmTnZ/NjzaZagb xkekcvZKMFIBuQtzILEf1icSsnzqX3RaX9YfCcNhJhjQxr6dBlYXLHfqzEG8kSm4Wz7lbqiqC4ce wNuzt3kGKu8EO76k6jezU/Jw1VxmQaEtqsJ6RikKz57Tb7056PV6W7VMxBIsXlx7OLZ8mEESLDFD kUlbIvadw4mLYpUWvNd6GlzODVYBz9MfaZN30EtffIrlrea5gPfmqpNHNvu20/2A6DD4H+PBSuzu yrwmdm0ghVX+NBj9S3Aj8k1m9aTd0/RTSOETJfdeHM666oSDIh9jNS/LZTeeSDgOHfC4oC5ToLQU Da24awIBrdjhWrnE7B0wwjVUi0bMKvhU4QsVhimh5e9lXB2ipHn8576eOSsXsHi5G8zSOU+Ytkt2 KY0XyHDEhZcFWnOwNj6Ji9UIclcRoh94CGdpjI5xSZujegmeZEqhF1Fv7K6Imen1ucm6/H3fk0aP DrmTtqSNpea6l8MvvQkLBmNZUaH33xXmxNyrnxC0qyxvKhXNYj9dCgDuOBpSWNx5V/ETUZ97vL4s sSF0I23eflsgB1+4KVmc+6L1lJzj+PTYmWd/kTgm5LRwxG+wakBb0jRHB2H4h9xlGbxBhQodLkdb LNskZGP38Hs5CMOyqC+yw778IP71gyl5DnI7UEw/Ba/SRaF5F9vVTrFKVeDuVMtMB0JjpRd0+YWB FdZudIUUJz6WgeBk80XTcVMuPMIs5qNbjwCPC4x0ftcTBnAmJ7ELjUT/04RWjuNmQJB6h5xt1hSz qjyCstlCM/mVpzZRq0/8h+V8ckFK09LxAi6EX0RKWV0ZuQhrvwCIxhXJj9M8TOaDsSV8LmgV3Fuo q7+GlVzAFOeyjIEE58KfigvxeITAZYwCYLB1cCaE5OjSrnaZ3Wu8557K95mcE8wazrKN6qTshC1p asx9RQD+aj1sJRNT44HsDX8bNy1XXUlacV5ZropqTqsbFsct1QqdcygUGwyGKzr49U2BRcJ02XhC pI4k9x9tCC4A6fStOJQWZc6SHHee2WXnfdeVDUvlMR1mnKtNVwcCgDussdZTAwz57Teo7Q2bdKqJ e9u47JOn1T1Sbq8d+o8RYqsRoBT0RjuMqWlWOquii/6g2jXiYuGy1NpYLaJskMlfj95UlvSQPa9q hPZmKmEwtpSL9B0dQsq5gHGBfDhbYJEbxWPjYqSP2h2+rhmG9exS3BQ7RBKLIsiZo/pAOlaRqZJB tM3zGLc8wqrU8orb7lk5+xBZrqGnn7xF5X8txMpu6WmqFVPRLa/9OxE7rctGUj4YCgwPsDmpWipa 6/LuC3H050HU2AAYFIxtkRmxXTCFpWon8wXiIWZs26Pi07cZX372PDqwwasc1Mk2hJGSzueVCUzS SiufEHzSOpKO9+mxsZTJ0L0jTFm4wN/7xbh1JWpWnQ3XlM5igWMRdkM5JNJ6YGFgs5sp1DM8gk0r MjbLNRNTNCzR5DwO+xkby2TTIW4p5aOMwDM47vVLdtEbzAC4T4IYL322l2j3f1JYZP9r5L0txEQH /rwDC7/lfN159mzk2+j4B3XoNtWRxeQ0N34iykKyqiPc/zgmpWaZY1ivIbtmIPv+/dJ0pVejUGa0 RZpGWhX9q7sRzmBK6r8Lxc2Jmfeo7+5lcPNB8iHNThMOAFxm5bsFrm0bahJo60ao2wO8Y3jOCHeq wVOgyjWXDfjn5thipdL8dx7EvxDhJw/f9wOADKbynZAMXgfiGERqWTjkMU3bZhJ6EZorwVgVG4Bl 0gPIpQY4fLu6Rwa1jtMeNfCVxkkkpYMCxp1Mm2U/uxv6e3U6SMXU+ifFaLMPrPyiLjOPTJyjQs3r ggMivRy9MPRDGfKXqMM6+Neo/8TRrHyJOxpyo3qP0BU185+D1osF3mzgxCWkqgQ1Xw6j5XKWw/Jh Y/cfz2k1wDSs+tpNu1f2qMJ1oT2jw+UFigsGWIULKRBQxWZFAsVD1iIlx/plTrNcaVFYISjrVOt4 07yTvWkmf19CFaDgBEVeo+6n1qRySij17dBnka2aHZVSPkh0AvdzFoO1zfZZJNm9aNZmvMb68I5m L1gj3ujjZdcnwZIsZGsoIFKRuoHZTmENCWYgBTVpqAHOK5Tzp/s6VWWhemE+ivxUiDiUMUgjV+nA xg497Ak5d88p8jWI0yj0CuAPDgSr2pK8Mfhqb/0cGB/JJXamNQl3ekUMaTYTIqFlewY0/OXSWMe8 smsw/zH59FMU0oDWqZoZgzEQ52hrXm7wPiTO9CwBeL2FqjodFREO1eEKiQVbg+gCGANFuG2tXGdS betlcglF4+LRvUxWx4yZqUDV7Ua/0Zq0XjWNBQrhfCF4W4kJS30wpoB50dwz3apjTTOGqEuPHZfF Sg/XLCz+KRO5jK1fXumtoc1rwbZ7BDX+cvYFyzFOzYq7FCNP0oLUGZa9QH1Ko+OpGM6K9HjfwuTL GnatelRp57siP9I0OAohbS6qYY+nLzXLMyugYLnuxQw8n86pVtjnGEk/1pnT0clxc1pqjzPAmPj5 AYVOJGDY/CuvGUN8qJFaB1J5ZbKwGcazO0tXi1dA53EPmiuq9Sx395PmxW+YUT3Ms5qc6i5gGscI KntOevU+XAQ7m+qgCg6M9w487hWJXLfWVa7AMDnU1HchezUNEEdguSc/LTYF9wrUqby419g1tMpM mAxIufuVmp39fZC8UDtvzhlnvOmNrq0i/mf1SGvDAtQ/BqgMmO3xyiNK/p4JR6oCKf7eltQV+JSM iQKoqh/GlErB0HUs7/HTYoWj5vnD26hDjzUHtvSpbTw0UFDnWCe9nDogNbxVnDdo+KRM3rMC5zL0 bxexz8rINf7VhI8h0Jj4fADUHffctBIo96WTMyNzQhxp1n0XPiEorxOr3VFnBTesqygXBvr6w+3C lNnyW0+QuVyhj4okKQKv5RbjA+u37apzKuZdVYpoMoe4778YOvZIy+BkbkgLHW2aX/4eU5bPd6ON TI46uyITHraS+zWyXMFhFKaZUbFoT0H8m5WfsBgG4XguBRKcZ0NLPAEwDhCeBmOjZZ+rMAEX7MPl Keg75lrgsa/iquNW6d1dNT0lrItG1n3d8OHMoHGptyB7CXEInQypDrw+n0ktPKd0mJlTMEv2BpFJ ucjEF5C0g+ZXRtTBxcG8KnFtjS+vOWjlmCvP8aDZz3MgWQuIlP8BhsdISeiBrjU409BDQ4rhnQ5w XCObxAbCtwkII1VQtcgiJHZ1S+FIjaH6OEjlTsgXkvtVLwoIdvXfWTo6ezdOrxtqAEWG0nifGCG0 fFFUnlmY6dNbKUlr0vkly93LiyD5GnsY2nIl37dl2Jf/3h+kh9+imfawgJoxcPAxwmT2xqSP4wtD v76+or97f11yyUW7v+PXNL7C6OmSkJhmMWTRFUy6M99N5nWtbZnxqUE5CoKKMD86L5f0v1WgnY6l XNMVWHIXH/Q2wLltT+5I2qxeYqN51heYbGi/tXKn/HCRBGbxIxoY6eMCL81OBr76LPmUD1SIk+GI 0sO77ZvYM956XRASr4ES+vfaQGcIPzFC0RMEF1Du6PJEDZ2/Z52AMQVb4RxwGa/Ji5OzzrsCu1p+ A8rv65nZfHWZAv7o3CrEmCSG+Z2s8bKLx3IsgkZOWDlyA0tu06EH8MaqryhkQhRQoxBKn8a2QYYb mL0GFSd1okwtguebpVheG9wFOx3AvRR6yyVQK174ZnWDkeRSp77eOJBl7ToSbnAmYIDFLoP0zFdI 2v3wUNVnFcx6Zp3roEFVNGlUM88pkq8a7u4LOch5d2CezqXIm0812mslds/ilAzPAYo1YQSHcW8C uQmdq/IGO1qtOFT6xeNdQG4BHIgrNcrL+h77WsXv1y8k9y7PQlU2L5RYSD9xbSHgeKmjpuEOjFTF rJCdLo5u47rbekRXg+Y/vZ7cohJQzUuOHO8MzZc3fdN09PJoFXTWkGWVrww+9tOfhp6hQYGJXA1L LJB/zxaWRDEZW6jySLdO+2ua6N27/C93h+SD6wbrtYDeRp8AnTaFbJ5c0H+LnwqIm4gnCShwzOLC NSIcmXCJq4sOeZ0x4dStPmjFpSrCvmnvKeD9SkKioFHJKJJ3VNZ28HgTT8dzv44AqlfFH/oCePo2 ZsxMfMsuu6joBgLeOz+zSRg3eKXwYlKJdea2mDfnKmYvAJ72a26/yZe0geGju32vqR5O2hkDgeZh nCeoaAlmVxzMwF/X+4Q4p2gjiV8OpkgFvfcfmFJwbhHjQZDghS80vpHmWj4A8L02QeiCPyl/sE4h rWRSLT+zppOlIH2wjjwWT1mrCVaOXPpfgUhUC2wq7qQmScjb2gR4ctNF/XlNIkVCmk87Sk3MecII Qbl2gnrDDWePx5px7sxfjUc0Jhgxx/W3Gjs++le1pSBDAvbqL3mOe7hjlR9XyAQVHZCcsXTF3zH2 bDm3onMT3het99anL6SmbS6EqN+vYJ0A9X8jFDXg2ej51o1kJ6Bbgxt0mpkVJs+izML4fop6+P/t 8ITY9zTSGMeBt1ERKrJlIjYY3oLJmdP1VqaY8UH+6uNJaSIT96AGnv0CMiDd/qkPiOsTMGfvkR8H M2aDCBmiKnX+jRWWvWeeueo2LP/yjSy9ZMZawtpWMImmGvntFRi49V+JsFkCx7dJje2uWnLSt9j8 jnHajfc634DxhTMuhBwNgpOzeMBzvCMcjDyjuNk+mw2SiHdqDIeOVJIUdmoSbjL9RaJXW8U+DT5T SFL5nSDUrBdVD1T8qpx18LFkMl1Iq8bHkob0k3R7FU05XC3DMMQmmZbN3U2gLvWxCtofTsHXHxhp 0YgsVgRWzEbMHxYg8cUsTFVNQa2QZ9dRkuYZicuC04BT+JVstxmMcOfX6wWfTxBXcVNFjIk6WqEC jDQ04QWgY6TI19J2/e++JZGWWFOzUY7CTfyNl9eGsuYHKN7cV48ybGZoqbwWAq8689HCyO1plyNT bPsQcgpbfCPAGfo2EdSbD9S2a///Z8YSKLdr3NpapYSd7XGgyY4rBYmYq48cQaZ+L9kPLibSeEiC EHfOkjB/wDPfI0gmI3KtUG51VOHswHcf0ty8XVxehX7WI0x81JfnhKip8qjyCYlztaN2XyP9WmNr IP8IMYqYLm1s8P3VWgYU4UKPCaPwV635REU/GYYvaiVr/P75xl8cYzdk9R+4g3GIZ9ROpROm/k8x 9Ubp7cHqHGl26QzSnl+tKsp56ElXlS8SGP6puZ4DUZ0hwTFElchh15sDrw2h3sTxVKPzaOTr2dcL C7ctvEgIIRTOTi18mzwMEdF6ZD2y9SxH18ba1aZip7UsQ/FVNYS8qY48bgMxYEpgh7mfq2rw5Ao1 P08tLl+bBYUrqZ0RxsSvH3OOn5jdMBMSHD++qgIkeZwJ24pQ+pDZjlo1uPTFAR3COHZxyaKFPNwb z5KOfAyfERmzOeL6IYFcoPTU6jl0HLciPeXJah1rwikWg+80lE9vC9erj6O7lIxgDJRarLLdCcjW SPxIe4C+f2Gh+AJtZwYxW2VAnjvb/9OU3Fqvu5hhM9IrEF5C4vejEHZfJpHHIjlfuCIjsBokB5oX K7iGQ9GJSy3/xqTd83WUDoJammUZUkJhBYptIY4YnBOVdveiSIicstzFQuXm2a2JL+pu4xUlXQ4a 7LlDoGkQxL/YPW7CJAvbuJPXIgheSCmdi9CRZ3lID//zfRRqN7x1CXo9KSfhXoeNIjEJOBBkbD5g 1g0XbDOnJOQgR/WtTZuhpaQ4b+ypg7Fj3r5oIT2OhAqzvRjovsb/bQNVeKMF+eY8xB4K213R2zop tVsLA+3gwoq1IDSR4QbdKdmxbKBCL3OccopmJcY+PSuJ0F236Agp7Mg9CuR20but8xA9pCXXMV0v OLseo02agXDHUneidEBN1Ut+SUQTaQCwPd4sQMxW3gkcjDR8bfDaHLo6h3/bc3y0FYiN5gEMBnT/ IbxbRL6xX/RlfT4t5YqN2HvO6yPsqfKldnCFChIX/mJ0M/xceb6Fx5oDFSKzx/cqxYHxpr7LfiuN UKFpwXWS8xVks2jvj2oOUmpWT5pZWyToQ0UWV7Hb38bsJSycSZw80pgbp0RldOlj/bz7W+1EB4xN 7pQaSUmV/03UGFCY2Za6rg9cScMQRKD/48PtNj6Y94zmSrYEfVtds9js+6s5fV/KaFxl6bJ2HfiO kHbdg+tke67YaNpg2otmPtYM6cL1B1hS7nnozPej5zOztdlNd69cIAU85JoNrKcfZw7/DGbn4IOC qyusNejSEd9oyg9mrmxUhyGeymORnuP5cp0FmTEpQSX4H7Eqiz2lpGvoj/6yY+8DQ8mOuIKYmosF Pl5xWFHgn4FOg18c38t6zlS+kNCWImW/ujWllpELowKlSCnHLUEkacZfvXp4/rGnurN/ZzdnJbVa zyA4v0LROjlFXzgrXQOeatHO79BX608e+/r8t+XaneB86rllpdLN7P5WhlEoFoqtJaSvnnOjpd4Z lDFUBowbEQHftaMYHfbnYjQQTH1R1fO1kxxKckaZtVUabr98lXRZTwBNPV+GTrsvAqAurOuMW6wm UMaXmMGK4f7RnKL4mPDjZtiikYfIrv4O7ck+9kOT4BArxjAHa2VdHuKFr753oh/Ji7o5kuTK80cj OTzX8VzvRV3gL9DezCpxRAAdmiioMMCOjqzxKOdD48HkkQKlqZJ5bT3sNk1KCV09juSNwA4Uc1B5 Fl61E5F4NT8di7qknkb6LsrMG/dzjfx8WeLI5ousioEkeSawjGCx5urA9DaXtrWRU2W0OKXVImB0 DK/p2i4fGm+8LXm2fxN7wF6qqNuLVC8/gGMPaCtrsdLw4NjAz1t4YZyN0oschN0WrXgncksStEb4 q2gJwjGWFNVqstARZJYCOQs1Josljq7QnWKTHZnlldyts4lzshd9jTGMi187zSIUCNM5e1hvS1Lu 0HWMFoBAAqvFrk4xiEVp9/oZo/t7aQPP+0/w3e9MVyIk+/H9j1S/BXlkvuP1RJY0QUoELxNOBFCA i9G6beaAPQyQW8mmtqSASfMivi8aNPWmLV7Ka5X5kF8EzPcR/pxs7muCzWrNkVBiEe+lq/80Rize 8wdRoP6uTBERSZP5ovmK4fK2wPmWNccxXzYZUgPjxHdQy555Qh5tv15Ebt0OernjPKG/c3ZcQhEk ySZqYwmQlpCB26cOdsoXP9YM+RtLsu+O83t//mvDf7BJHJnezKkjYFa6rg4InCyiCqPD07nb8JdJ xUbda1918gjCkh5/ZmVPmHKWuw8FR3ScfG6WJwV7+ZpG5SXzy3J81R/ptJSAk2tz53lMTfpuRtTv 0LRHpCcZ8x0jDNMRqrVCx32gAdLafvuob9pqFzRMqM9Z/vNfZjR8bpy5A+W+16kcVSNYFzyAOCFQ sQHiQ6ONgzmeZZevbyO5Oovv4qv7RUgAcs4/iEwRvEfg0K8ZOJUBsFZKtpuFayfjCayGktIDh+2V ErUQho/2zldvt9dLBovEcADBd8n6sHJviGar0iZv4CYRaE3dTqYF/P5//O6nfojVobUTYvOh7e6B 0dYBr0xj/+N7V7V6Ehcm2R6retmKkkVFXm0FtEYGyFCIhiWiegjrAfhgyHI9mOBtSVAP2KJpM/qk wxvuGjRuNIhvjVSWUfo1LjEOboWCx4km+fvGZYnnQPvWse2cDZFRswBr3FZiEav9ezuW4/eEMHAd ZYXrIPqQWJFgD0ACoXs4JYXga8J5QegZzNmJ0QmwOZD1eKMGygUayVO99lY92TqH4kXo61MPDXua SACz7kugKB6yTLz9he4IaHcgoJ5f2JqAUryjU7dcg9jf1kmF/30UUjSMwjm5qPl6CWLMaD/jhhOr WCqDrSRe4LBQWlltrKeLHdGxmIwWDgL/1J0FWMVofBIlZqbFsQ7UEK4Pn8BXGQ0h/q2UDoLI/U4u RtjCaj27YUSbcK7+JMCDiCRoQ8LMbtvzh0Nu43oNdBMo0j+MHW9izoLYZDM9NGjg72aMQlH4WMqR +QLV5jL3HoxefKHZlAIFfjQ0j5PMDCU42FcwGTbqc9aVz1QEpeL2sAQcNmrP6Dn0jR1fvMSK4K1e KKMtw08Ixv3DC/nht3i1BceqKxcUwVXP7N120zEzebxT/5A0XPxk4OA0Z6JxsXu6s9XThTJvlsKH XU1U/bRuhm5+maVXixYlMa/BAXBxP5Q1ZmJGB8dZ0pKDd1lzJnmbA7nrI8Nq4G5cIwuZOO4lTwIb 7haaR2FqqqjOFQnnsppKRAIBzMelsbnQAsJOYQ68GF6WI3lOeIKcQTjftwFjfmLijTW57j5A9t5s sx127KrS8crOyb9uZILE2zBGVwHMHOlDESxxW2OTIR+LfNN7GUtLXT5xQfYz/9lJfAFiCq2vQixB qw8h1FMQawoVTfjYmxTBEqHl4W34/Ckva8GUQK2NdO5ucfETMsEU4q7J+UAz68flSmTHFMHE1oub uXBCFKA0L1HGiaHZwvR+lGZ6f1ZL+O2RlRB5bK3FqvaMyzp3pCifFihRlzVem3qTZesBAKIE3r+l lJrpz3pjBpNOdMJJsxtHiwNXwMS/68HJGzh4d1tJXTEIyWtLvimxAWsZC+r6qLWVCsO+2ymI3Y3y uBjzf/KAdEYDBGmlyQ7EqIBzDwZ+RaBG7L7cx1A6qGbP5d0tKoWk0/9UvFBhAQOUXoMsRhyIbKXM 4KwvNwtymdEHhbESQSfNv5esLKsKoJdcdcbMTif2OCe7Pcrn9ErEI/cFSB5OSu2Y2sLhPpmSUP1Z nPSp7vJtZmXSSqVylBhnirU+AToPkIO8f65a8oNozZOUxbLwDOkjGFrZPRtfgFc2LSDpSWS00CHO 0LmLlTS+4a07IDRUQD/qaNW4WmcFswII/kyGfxt4F9dB31cyGUTm8At966GreOtne9dfYqR/0jb9 3600xWt1rM/+vchuVTvwNXRXzY4nQnvi8Gl9ZtNZyiskPsh8IVmXUiG0lz7GyazakapUT7ewqXJH rA3l+6qBpKEJNJPA1aS/ZO94qvoQRlpiUTpg5sklpvpXh7vnfwVWW+/xdYjNEppzXJUmZIO12Ajo 56OQJ08exlZ6gyMW4fT8syLT8FAS0f8c+ykdmu2VoFJko3FFPvOux8GYqNdaYrGej0/Bw1+k1w7q M7dhepikRuI4yoFhqgKmHlqw9jNSSG+uRsVnBnEqViaK7T/No+N74LTTiu0JzQzQRwmqZNi7Q+6O dmnr8gc8aqjbtaDf56TpmJuezqEDeykav/PF1T9XaIdzUw6A9EPnQznL5qI8nVOdF2VmilURX4eI 7H3+olfqrsshKme9S2/kSkyOirEARCnazzbj3T/9JzkiHNopp16/O/qeW8g2jX++u0T4r40Ks9qU rV1gbiA8k2yNRNhFvacJ39rwFXTazPPtGsp8mncBawQ/+qjuwKTlDF66ZfH7z/wHPvyYl/AXszHY bmBw9AuWsKuz/4ZaZxjHsgSsRSfG8wv4LvXXhB7c2Qw4WMaUtB3d06mW0sp8nq1Myp/YKvLZDLnF lIn2Sj9w6lQCqF6pbo8RK8RuOVABQ2DJIJIpnU8tDK3kjevtaLjG6ePSkzuMmpx3hmamn+KkV7H8 zlN9i3TL8kANNIji0eT5/StZS2D3e4B9yDRj4Ck1NhApYJId8G2cyh8oAobECXkKXHRq/p00vioQ zyVkFuXVrgJp5fNwY+qbhQ74ZafgAVQ0iCjPlR/TZHKWnHnyPI4jMAQJyHoNSZAKyltGGLqANfSU hK49KMfMLxGpOIHY7POGawmYE+3ET3tGAhuSTROPVQDVxawNai1Cg3wG+xY49AEfsnOupmnF2Syv t72o4K6zDM5NQqcsEhezQQ1r2JvwxgonYnNOJQNl7z97nvjk8nBHIrgBMjoOuIrSueW+SE278oz8 LAuMC3tyGxbKhcU7IQBDWdWpuDR3/wlVDFEnQK4PWw6YOdD5PFKN0/JwGKhlxxhXTbb6G4n4oPUW C3kGmuyRsENRAW9lmkb2QMeLIH/uKkYNAgAkxnmnT3t/UIHn4YKqShLPP4aYS4Jj3RMEz8mfigky a9X8Kr6eEzha/dYuEwwVEXs99K5mjLYdM9w/GJurpY6xYld13lc+Xm0L9JbtUwayC/giyKwymbfi JrK9NcqcWcnOhJ3BD09o+WKQ8MfBNB18XmHSRUJBdNWBfEoh8V5gdd7D0rCFU+Li3o4eJUz92ZoI guIfpX8ptUJybcmXDlEj8uPw5m8E/56tD4c4ZVqEsO61iQreItj7DCifQi+I3cyhPYCf6wyXHFHe pADg8pNnEMS2LznBVNw1FQz14Sr3l2XLWQACI2SWgB5FWrGjx4C7rLDbPJlYBN1C+12wj9cl8Rkd WalwfosbKsfhhrqnLJfDFMJuZrP4rgOdPfQmqIAiafqXNH6d82aWtJBj3e9SlRB6SRlzpedld1GE rqG505RqalWrLgkTLYK45bimrd8hPlMFZpus/LH+ffMLfmg60CHu9ltrt26sE2jNkFgIfSwT9scE nRRiUTmHRSQrnhN7MCp1+C7EzOJli9FoRjwxvfUeE2444SHSOMiNCxVwkyl8PidXicPJ32StPM73 c8e4/ivASzjCG86byFsdMci0K3fDED7+r80C9GnY84Oe2Cvj/9EhzL1rCmzs1+YRc2VaWcdLbTXe eYoadgsUAqw1EgAzwaz/Hs09UnmMSVCFmjJTCWSRy95XohQ2y4/y2xICol3i45UglDZRVW0sa8qF BENK3Jl7KkqdwwV2WT9zZ0pybE3zcNOT+cCBCtfsSwVq1DterLKag0diEqHZKOFQM6iU1X/toBfw CTf0LSud/boVsdS2V2v6pKm04o9LjwKF2M3oHBK979nkRpZdC7L4zHEqx2MwFlqrAaFzPN7I48lM 4OsfeBccK+UpPj0WXy+46jmC/bCni4rpWmXMYJhZYZbQfeGicOcxZUPMxmZSN5Cplw3A/vpH2STj Nfetr+7OGn9HzKdPnDUikCNNObJN3MmpeM0Q1wSV8Os4MyVTZlECU5AL06I6cu0w3nn0/bN5aisH /Qx9kAg/K14efyE8xHTX5aWnfbNQbmMVYSdM6d3/6rtqCUC6eYLbEnweBg9eD0jyyH0hgPv4Nfuy pUyNq26Q5VO5GCW8Tv52eKN5/7Y6n5wzG5+C81bo0+Kb/z49kt+1CP/Y+M5O4WDtRmgjNoAiGI8x JJjzY6vC5auQhbXLBAbHM7uYwtl6iN5EiULCUkNUtNIdYZHVS4fBlYiATOymjWbGqTHEXY5uEC8K QMphHtYbXjaJWeg7lxecd5RlLPb1ml6byZRoQy92SAt11C8FsYKlaedGvazXCkqmTPnNgtnyHyA7 nUANtwO+cwWp3HKdMjZ9tLkyDVadFC5i2aP8Pz/z/8nURKUyNkg8FvNxDj6t1y5QdQYiesqzOP2x 8gbPzou4sVmq9dr4iWoYgNU5zhja9pyxLyI3rIwLTFFf3E85ZijQeifpkliZwtUJu+VGHf2Z6T/+ qGgI7Os0PFt0TDJWhVXu78zbKwL9tKrlK3rptPSjBmXDpKgCbWnsw2HCl6k0WW/Zdc5OcHsTWm07 FYkv3rUqgMJ4lfN5z8CZOwai5SlGZxxpk2FAx14P8cfPn53yascsoxm6bQuxwbdZo5Kq50AgGjVG E7q7UqJEiSYxBfhANoNUBRy6ZBpbHwcHuS8U4bFXLsMotWkHClzRaXxFtiDMUmYrjhOGGIvZGQrP Np2OmsS8Ur+ScVgqLwiis8DPGtLdqX/2QcuO+6rwS1/GjMY/GNPQwRQ3uwGy3bkTWpQpHJy46XcQ NcflKlaQEdx9k6t/33bim4X7DORcV5SyHwYudB1ltEn3dAKqekuGDdLHt84RdveNdRrVN10RjZzq sIRWMZg645qOB67hZdFFk8qyydfzvzizRYGVABNyTm2lt1mDITToWQqxR+0Y4axrB1eo2aZmV3xu 3s8SR+szFiDDC11JvLs3Q6P0ndJnQtcGNgbXR9A0S7y5cjlkHiOkEGo3RC+sLUtQM4detB1Y46Aj vrjpOt0qQTTm9L/1L8Gdxs/9VzsLrUf/MsLAcO6jDQBLDK25sxm9283oWkxAVmjSzQPhTdCi80zk PgKrTdgBU3StnV3yJzR03P+AfoZeOQyqDDXf8MK+mvLy88CDLqpcnYs0YYzDju9DjkfT6h56npAp cgwonK25cQ05N0fFDMOa4QLCFICHgRTivGofUpDiLTKq1eqE42pDlF9WbxYVj4PRfH9jIa4uc1jx vB9IyHLZfS9PpolrCFvfEA+UNobWgRr8euk5VK3AVaM6cDqOGbgebqmtpnHo/lEMqFSpGeLuGNen UkjFt5ZzxcYYz26mdLahJmf0nNIzPKfHWXow7JG748gJfN7VLwrSMSdnsPVxg+FpKomyMFBOXV8L bUpJqfKeu7bcvWvnUBqO72+dRT5OfCGzggKGX/GVsn1LRCMj/hpb+TVF/g6r5SmnCPW2eaJ3ZQbF J4vUwPgffR422urW0dyqG0EzUEWeXsMM75IR99X6FGqXlqw9SOS2fFNew5hHtnIQ63H+7h6LBnt+ 2TtMmGhA+m/gG460n7YMFDgN0YqIrW/8oWE82ARZTcTrPSwZy2cxIl+kFdnhCotx9RHuTl1vzNeo zdtxr7VTVxnzJDjRwDWn+O8vSTQRvrJrBwNOdGoHWucVRss6N4kBPbFBimVRYPvhkbVOAB7s1HYC p1HIJ2nKmOyEOlkunkA0npUgJdWV/OtnDfgSp1Ta1Dr0GTPn+O2DRy183MB6dAwzIlK1RRMJkUQ2 SrgDxAek+styUJ56gc69gOQ0fljSNhThQZGUWGR6i6SveRQV4AJmpBLkLx6nFKHHTRBLX6k94DVx kg6vmCnJe/Q+g9Jxv4dxtIyZEdmY2SYlqHJ5KBUsktrxTqsZxPVO9nqTOzTCy9JnIR+SHx6N7iIX 1Fgx+pNmEl9+iEEsI/lz8qhETdM84+VnU9wEpbc7uHB19rbGc+g0n5rD9PjfF1UVbfSNXIwncA9y zC9J5+LRlq0S85bSMTEOVe9/V6SrKB3KYfobt6Lt+dhkDXlh5joBmMhnNym5U5IKWz9JQxIYyQDN gB4ce88qnIi/WKcpS2NnHEFVapIuQ3g9X7y+FYwmu/yHOJeFJKE7iWFpBObmG4IbtrCGT431qswL Sly9DIxTapSBOQZwrUCpFvH9wCq787ppj5w+vCIA9hYL4ANiYUlkcv/Hv3YVhIWSickLuj+51zoG tAntnJ50BAZfM8QGkCbY2WDnurSbrP5OodT6OjSEWJrKMc8S+AAtsLyH+Hk4JrMIcIJOwTyf2tYs eHS1BZk06POVTKJv69qjcXdVssvUvVYDwN9Eh9bpg07VpHcXveAFUC19y9vmRXOE1TXxOjuzYDN2 B1TeDIVszvBerrR7FgN8/2bwwuWAuvEgVNEJhF3gez8rpzg5cqkNVD5p+5szxAzPL3rjUqCYzV8b BkwKsNtMNWsdnLpnYjJ18sPaVzVkFVSWMfi7duvQB1XXEUPLks/c0J33pOoygcTvz/nIqE790m50 /HPlImU9xPDowkKsDG+0prTXhXt7I8iMihLWXvzfsp37eQdZYFeUegGpMB6vXv0kc02CfUCMD8fp QiiVmyH4Jxz9S60cRrs0HPT+eeVM6u2lcdan+TWqYvoGjlM4w6ZwuGNvCvFYyYsY4GlVze+Fglk9 t2zBbgMzAtQQkOcz6mKvRLkQuKRSR6WOyZYNJigObuBUrgmL1UuA2RkWtjcJdbHnf7Rm22oUM0bl bdjnQ4VzYTx7/6BEsK6PIGOZbdePjwj1qpZJqnoKEs3CPBgPyi3EdqX5zkrgDFktPYHf1b5YVOW2 VtRSQfFpB7XuTSoWsDwSheE2Ag51/uaz92Ysaua8WCjaT/vfneZL9D5X4YHpHtw3BBIMgYE7/wtL V/n7/+B2GX0nM+rswbyzjOGa1gXo2itpFUxmLYqEFO7fkuwtMBasARkfI8LiAxuvUbjJn+yrbweu 3VojJqzElsnEcTQhP4Y9GXjextNwTywODctb7aNzBUqwRJETCeyHJB6cuSolmaYfQhy6pE1c0gSC UxQbvIBlxAptNKdvIjL2+4MB/3ERnz8MZodDrfCyeuqz0YV8DDTT0xs2S5MUaUsAOwWf9e2+A7aM S+EsarlTYFcVeT1w1P7MREeVQEVw5mBXictsetSGRGTQ5AJmFfdqucF6W9etz7WpJU+z8n63Zt8V l3WjKOkynMlU7c5uqknUK36AGCsTdP+B5hpR3YPSL5JsU9sp74vZ/+WzDVnE74brtQVyzqcqaJh+ 4A9I51EcEr/qX0wxZWM055IwMLCZX73ramsdOguK1kgYuunqOd/JbzOBC5YgNvAazitgtrk/Ev8V FermG2gs4B8GXCcZ2oQV6ku1lhm2ASxuP2GKmVyDJJbHTc/fHwryBSYe3ZDnSOHxRxkc3Ub/Ud+A CTVxQolKnEKqDgh8+YA6zGGIovvCQq+qqL6Rv7TsOaMOv3K38ZqZ72+85/5HSC9LM6+n801lVPi9 9A9Y6X5mNULg0DzrAjQ6aevD2MZ9433GarTq6WcG1KYfJMAwZhrAQNO5092YTrTavob+BzTO4zYA cwvQVaxZAlFdPID2ho7k1yVPfMRWjGaoO4O13ugH5BZL1iUydjCmz3nsi1niopApvlfyUDH9AqMN PLo06RQFuH0FjNoHH89Oy41rTGHLuT4yJ1pF0uMV5LePHZ+j8hglb3UovdrwIC8xE+Z+plAEn7kh GZKZpndi+lM1PRGn50RLxEz2yzbKM6wjzpfEFX9ej/kYcOt8XFhtMsAxVGZufpH1+bwqwl09GOek OzgYIQqbUW+aGDr6l5GtH8ZExS7FZTYzwXulU50WwVqP3f0apNuseKouMOqdCS4Il7YAF68HdfFx 50KszOxlGgXWv81p01Bn532HjCModv1akcgp7yXCuu3bXGPnEY/ybCOxmZpykCCdtm+A1MW64nr4 2QBNOs1T1KHJH/oPgBuoOhX1RfCC0ljxs7aDCetK86JVUkhFrQl//aYJWjDMcy4SOsntfn764T3W Uf92+ZmEUgeeuyzlQm8J9o77aHDoVwwhpT5onkhRgBaHkOd4YqFNdhT20pa3moVu7gCKloNxb9DT fV2gsCQ+UNPSgdNKCw1g8t2aD6FZuA7k0ZXDZWYA+2CmR8GuyojF+0saTSI+SgzALCPwL3f8jCrf UorrBoS59BmjB7zrONlSBhJPX2Q6BaBnoMU3tq3KBw+BoZqF8rJHoTSVRrvG/ZPOLhjx+TDIj6jM yQmbC/2PV7HEdLSDGYviRFxEm7mLPfSCLRb2Jx/TQU5L6G+uno6RXXe05TLl8Gl7N76q5aoBEQ6E p3kFfILNfOCMzicKtY7bX3AUKdbz+6TNJ6sI2iGuuUPE6HytoxKLo0hDd+JCbd+D5TOlgR3WB+xl G3zCZ7caChFDxaP52mztWzQDeJeiM8899Mzih2YEiMPQc3rbyWj3dkd+fR+CdjZccPhnanLAwUyv 1KDgNUDFIpQGTELryuvJp59BgI2QDXkZnAoEbNuVs9VT8Fw2jOZmZo+RCtyYURq5j83KFKKC7NAw eKRnoB7cmefNMPNfi4TG3btXd85O4wHEpRgjRGMyIB4rS23WrgbWZ6NvTb+QGhcwGp3bKHqzprXb h1EzE1msVuTOiz9aQkAFogfNqcdcIuzgZRyV2iHojV5idHqgiwayyUhEUYgaC1V1zfizCOgvhAZa fDVob6brVCqg/NGH50Ie7wszzSQPX6M3XuZVV2mfHtFTvktOgakDOXDErFqDWQH5RR1+kR3vmmEx fd+0Dd4EWJnoOghTuArESqss6+hpWLlGAFqNck6UnvbFcsfeym/02TbkBAhJggfl0zLn4+UnrpcK 83PyiV8gkXjd6VfWCL4EM/qlbKa72heKcivgiYCDejm/DJqqQ/1ORH1ZgiGpVlhgFEt53lBMijHg z6X+v0UE9gkzMG16g+6M3Goc0/humVVdB1G4kA16Q3otZq45TU7/QaAIKQUOmI/ET7LfKpCPwZuj kki+o2jjQGk9LBnBiEbi2pOaPcwUVYOfOiokcNFhUm7c5iN7Oali80t0/1BfVFO5jXGDoSPBdQGF VzZO6L/k8ZxMyNErrFTeUKx2fWDtlzunBMW9sn4qL0YQ2gfJY+wzl+CaHp4nTSvnx3ako+Jaat// NWdbCln2W5daWMjvnFs0tenZizL2yf+0ybWhy4GYUskN9nJRb3dvNBTnIPUcYbV3VYe4P1I43zdo vLNvbw06A3YoZZqoqpebfjROOuW3dOt4f+kavZ9F3FU/mmN+27LEPO3DS32S94cTDYh1/uG3zRIV pP7F6YqD7PJ0ZQCjFeGgec7lY8mzCNCpz9e3h5Vxg/mhbm5blgS3NHim9M2C5jEsxPujpocGSp8k UKiT0uytibbAx/u0uzvGlsSyYfQzAdOhZ3vE8f+ad9dgsAGRrB/q7oCFFndGvZgbI/xByhef7awI 5ToE4MGs/Xzm3UbgnT8UCyLjkJq6oLGP0hAq5IOv/mAmDbJ8XDkMCoME0jSxceR5Id45w6fRLmvX XPe37zPPSj/an78a7/nlOKhVHYEsEA61pYWg996LE4riefX4pknGbelxLBD3yv2c4UGyIaRL7zHP CcEomBtdtXUth7Jngc6suPljGStD2vvVKBmSZIKYDRN/jXzhUXpkq/PnfBCyXEo3FNNu9ceO+J9c SVKNQv3ARikQsOmQN8IPAGS/DT+qtfRXhVB+PrC+XL7pVuozV3pZhyqW1ipCrISfv5zs/+pDciJP i6Cv/Rgg4fwYddfww0sl3FXtFo3A+6WHbSI2AglJ23tpgkJ3PR2/fVHUVqdVfmNubAb3LlUTxQSO ECZv2x0v05MpoAdDovwuL1cOxKiuNfuT9l/s3T+Two8d7IIlQ7Vwz/WeBA4Q17nOkXUi2EG6Oj/i 8B6q1GHeoujJJuGVwJLa9cp8ElSlOhVhveKbfPqMUElYSi1h9R7bqORBiPjn/iA7sQP1/IR+kl1B jtqWhLv+tu67JEinGRVSqNieC7xA7lqax6WFOvwX3ELoqevHId/03LIMLIX54LljIt4ybzCLREl2 yhWS5DFz2h8D1CPd1QaHi1o4HvRm5vNSSaiPDQKH6taAGCuc2wXRY98G3wJo/W/M769z4y9r4iYV 38j5IC6dGsAJ5u7wp803U6Wvd2nAyG0CBloDYgnhNsCjTF55fiPP6uJYRejYDawE/fYsUe8CGSQL pFi80UmFF7rOInZd0N2n2uyuH23KgOte3jYiC9B93ZTYqvFLLfLtejJLyNN9trKUm/7c4aGIogwp gQCW6M2mSp9hR5o7qdBJPAPJcxd8VgWjrJHduxrqO46r5wv6/ZdGfftrEXpsUFj6ArpVBDmx8nS2 kk3Mytqm50Ju1pOT1AlujHZSN37FujJ0dB0kL0biXoCum8B2Qo63XNfUFdDGsVfCL1schCswtEcM J3B17DNeyEpJ+Yy9Cuy/Y0jhFzNS9FXOSTEhKA1bAHkwWHKBHeRDO6dVM2Hghzed+aSxawwDRd/l NEtC2DUbcAt3ivMoqX1ZHCumvKQiHqMB2BIAdohAyEgp/fy15JioLmchO5Ytdsy7J5GVTK/ypFOQ hJKpB4ObHRwf0lxVIflgBgaNosdDfK7fUKHhOtnno/pu2FOXNCE4MuhCkhOAQYHNd5B82xIttSWd bZFd44Dfz59n3yscrlT6wbWN1V6mc0xmqMH+GU4XaGd1TG+wG1A4r1t5GtCePFeHcDxdwMfy6m4V lIGwHCMs7VRZwNdxr54HJHydyaYGyn9ykBA/uft3Yr6sx1/LeHdSUfLXt45sG6QiUBQjn71IBuFZ xUiCFfZAK+X5fc+SNcVKunuxlafarP3i46jmW0ZiDKiBgGYeqScXi4dGn9RDchfSOt3Ks4lfqFCz 3RWG31QyXbIrbg6/vSIzM5pS03eccKH+VB9pnUPnvSh6EF+cdLjXQFCq2g399Id1f9Yk2d7X1edK C2FI9gh+ZDSCOItg0V/G9goNtWyiZcYCOgENccC8lWbi6sHVpPOYpZtWriON861JIfXJxTUXnB6v 2VW99iQNHQfjeswHNcY8xPvk9mz3C6Ppyg7zXvDEddrD331kB8j6AV0fJIh1+vwgkhrL3AhfV45o nHcqjQAMPj6L5OaKFRVj5cWpxxRTP9LkdrzG6rZUN4z3isxk7Fts1WitqGQsaRne/J9aY/+y4tIn vu0uo/KiJPMoj9nKbTWSbfLUeoplemqiIlGuC2QVNFHl/Dw/SK0bp2dVtLRgnpTh0cWQ4bVTEqED V2Wi9icpRiWl1EcLnqirWLaXpnI+BlmveGLt7lhAkIjNf0aBQZDzFEZbrDccdEP7hjjndD5SuVN9 mqKALsNzVZFgZ3OWai896CVYele9hq5jllAUC0K/x1Eykaz5IBB+UQc+r4qSETspFA14DE6b5liI K/FcI5auq2o32HwQirJmkLSYMTG6KCJuK7wmo3mJqVpOYGYN7/syAnmgJWD+ZnkUHffJnJbdlhy4 cqhFp83nX4S1MMcsxkOtiuHmpzd2vLQPmclZCe5tViF5dcgmNrveJAv9kvjIIeqGphgro5/oxpLu WX0LAhlLldXDXMqLVV4Uf66z+b8uTrHGaINHyo8fGN2o9kNozrB3of1+MeOFl1KkTiBF0fjSBZZc d4dV4CZyWB8XYnKw/mHSkKtjNiINDbGTZaFYmmA1P8bJNvqxU0qu9wJpxVFzsA6L9fIqXum0aXx8 pMw4Z62lxcb933yuIdEchkHbSsa0/1bB/2x4zIVvfGmT5+Oj1a5R5kRQwRwfcLz+gBAIemav2rVp mcZWd8e1qTQyz4En55tDNIFl7yFuyFfibGR/e2nTf4rzgbHWpcn1DBQMtu1yp8NkbNSqLLqggX6i XPhWLpOa7cc/Mbzf5fCeWshbhpou/ueedzLtmGvodLBGonvXWLC2hDkKR9asfwwDneMBNtP0crEj CbeQ9yq8pEsOVGKMNMzVKJCTTAkLS4xOBg4PMMdccHyiunblo5mFgdP/mp/2/VU/5chaWMjG8Sqw BI32wQeJZbV/TtSFQZ0DzYGExeAmLqQu9flx5s2W32zY0fe0Y+6w9rck1wRJ3mFzJ8zBxgt5yibN bTzIF7kx6ZeQGk+2xZK6NaEOO/cT2e3lnlHPe/mr4aX+4Yv3QbLX47s7+NpeX8b9aV2HYbUOwjyf uoKVPCfGb/wHR9awLbeVUrU14vsyBR/UrTIxmWn8kvDPwm8/Y1qsf2ZoHr4hdknxVSkrOEHJmEhk +PlOm1EmPmPfs3krtZ65gyrHVerT25p9+EVHQxGTsBch8bGDJxATqVN6QVxNenKVN1SlJYnitBEk R+/DIWbu01Lw5atVVMrDFiIAHIG1VNxewwtNLrbmzHwkeTWVoLEIyocfvE3p2dYthbfVoiNAaRDT Iva0HwcG1A10vK21Fj5awKwScXFqdMBnlMtxaQMzSx1J46+G9Wa25NvCGxhvCPzqKLw0FbEnAhwX SeIKn5PKUixgB5gUi/w6TlobAZZ49yx2a98qCknNVZQZMMcwKlJdkpXBXwHCLOMXoNPHLHKBgacQ lVjWynVQ+UMR9QJSwPs62V3mOER/v4jhmo5+GWUm43/MPc1AaxdiZp9uFlib0VunhxjUb+dgeHlE A+484kC3XHzxErzu5WF2LVyxcZIA2wDJBrtigOt5tiywjrDQtG1H0SpbXxq8Oo0Qsu6Zx3+1A3AA In548nMtU/6qxIzL+DOgah0mFBN1TZB/BaRwLFf+Z7RGYbBHoBCZydrxsKwEBocsglsyJvpFCbXL o/hz85D+qrgF7zzSqOdWhpH2V454PnwTsdK6ZstunUOJjc3fkBLAjHVA4zaJHg+AxC1r2gSiaOEV t3qEzrevZlVQ1rlhXTMVPUCyalHScdlIKiKZCgA6329jeIseR/Yc6cQcmrVeVglNKoFJxNoJl43n 7iT57a+VEvslcZNNGNpXPZqNVPtQ2XzQRLDrIEOob+3bkHCpvXcE+Gkext9kjdTLzETOWWMBmGH/ fxAESyx08Yg8ojub6N7TsjVVOXjKlix5sQaGg7UI8V3OOIiP/FF5TRe/AsHbTD9JfGYF39mLNaEF 9ARD+xEvDyVTJ6B9a1yWy6jZ8fzIC9OPcfsIpdPAG0775l/QwmBPtWOMgmYvS4bbCxosKyTg8Xf0 r57mIrzDr4CrNonEs1sSgAJOUljlQ+NGLiCfR5SGdblRw+hIbaCwiDaR9XgrqX5fkfjIYuCzAbvJ vk8sp4RTjXJWeaNGJh5awRX0eN9wxpCXaQFpErMpww0aGd1sNGhyB60+fssD0a+FUh4NGX+Qwvta oFEkA/kLvO8YcC3Vc8kFLZ52EPpHLxJPFQvpZXCchkvj8VZtoEIb5KHeGsTSsxyhC6T7RiI9sRtW 0MNmR5QQt/+pq+dCEPgCF42ECIjPOLR2zfCqKvbWr175EFcJC47gn0Vvb5vR4ARAsEo5V1+9fesk NSVw5r1z4iMc7TrkjEdK9rjzjPKQMLTr6anWrhYESuECfmUvNTKq+5rnwC4QC1uLTTIQyBGSeIsp UO0UAAdJDfQMUNs02CwF+nZKeIWyhG+vtq3DX3blIZ8UCs1BvtcjcHGVtVf/7oJ64hvY3GB8gFLg tVa19qz4gh6pnL4NpbQUzEf7yHOhbCnQN/8j41fI2zPriEoAqUKKghGZS/tFUDqlJUhVjYRA6YlR YsP+G4mowfVRritW4Fyq428IXAllkJU+DY9sV4otzgCJhR0vw65KjafeEuCXSo+zudwpOep+7xgl RezDgu3rlMfE3Suqoa0rSNykgjCWiMoaFfJnESDabduuHQOQKLni/+rP0j3x97uXApryd8d+2372 NRsPUvXj6dkA3NEHIMjukGN32Hm7v/4PF0ztkc92ne0e7Nn6r5/FbqT5USa1oJM8PmYUFX+bGe4O Y+3adIgh0w5WxGCesQJCPzVajiDPba78tFRZYF4w/k7FoXZzEY29g21tjQ6/ClMYVFXDtgeor8dV iX4qeIJNm64kZph98EiZMQTI1xMcMNN2o+0Im8Mrxud6fq3AFiUIcoaEF+xBj2ZrFhRryje/mxTl wmiu477AoMuzb51q6Dy1vGUNORF5LJABtaKqOPt3Tj2WAQrUUZO4dFK8V1/y/XgoJ3jR/az69x6T RiqX+vrs5KVf3+c2P9nq08aidiRwBbAIaUKhm4OtPh0B3eyHJnvSUYhnusb/2sPZUKn0KHVVFPiw 54cR/v9t3AwNjcgF/poAt78dFJVzEYnywUEWAWycfuGgEtjjECEYkHQxLRdi2stFsvFJrmlQ3Owd FAKAuuPga8z9d2JeRUaeXOC0MqNPfcMIvUpGlUhvbB8urpPkw0zS1hPEtXaX6MLPdDf3kEH+g72+ ywXLLemIIGmLuYx29GnXDZ7sBKheo26BA7OVAq7MvG6UuDaNjgHyza4JE7KUhkRlUrXgeQkk8A5d frL7OLlRBNP8uyKdcZmwpk40JPIQnbft7OKBYU2tOQFOTz61Fq5nOYbAk9joezDmwaHMMOywpWzE 6orp3iNKAgB+Tmcc4vI9dKGG9mlFbuO+ADU4lfViylVuTadJNEllO9qZSLji+j/wR7W3J1nwFoj4 yWLhREHdPc+0d3XLQfUKapp4XTLZMo1WuCwdQjqi6j3UW7Ncj3TDpT/AqjhVBULR+Eg9kOkZuMK5 HwFtSb4/1/5ZAP10Vo+7H5AOr8/6/TD02awH9qghwNrRBdVKTR/WkpCPvcnvf/420/yj9S4qei4K KYr102bFfkFt5otfKf2kObazshqIfP6qb4OCwckWAY7su/jtfZyjsj57IFf1rW3cI3+m1UefDEvn A97oAJh9RsdgQ71B4BY8S+nz7SvCV8qpdcwZ9Crw2D7Rh0o+ur7WaMJJgK31SryPOYaHwGnBq0ct 49fE+f+TA79HdeSOySvtfxe0Zy0US0+8frx2xL6/lP/avCBSfS2ta30XQAjqqtjrU6yGPwX2GYDZ VvxPrzPn8m1bcPuXv+udgz7YykecJ/iZQNZxdxItgDfQz7cDs0d8PkhoOCsSzeu6qyGwEKfrchTq UAnma8zVvKazJ7xTU3Wuqg2toTGC6BI9ZEpyYV+Tj75gPOL6nX9gHahHfRX7UlO9oimocPnmHL5n VLyxAb7xz651v5/s8t27Ip8VX45w9ji/CAOwjaBlH1L/RChqXWi+ljCj/C2ijZuI9cmgNGZvn8vu 6T0oS3tBG1I3ElYDYz0rkPqz4T3jXgYo9VPAWoTZnWjkObZBGMsrsgLdRlw8IE1Dp+OKtzFh4re6 iMNFcr9mmjf5HY2aOE1q7RqMMKn1J3EXP4EY++EEinpzKN3aT8C1ZLgZVRO9NiJddpcxwqXdKvZ+ 2MesFBWzjtVNQ1qz4j8i0fecjAAA9We3mXTehn2pCL7c7q++2uVpU8dYQpmyvcE4qFLJnYMwb1hj 2KtZTkpWpWavNUHVo1GDPgBg0OZ6JsC+k/VGCx8TqjuNEDUUAZZtjEmE9+k0XKjYeRnLRwn4pREJ ElucLeGH+aZfRfzxIHcaYg2ALexm7ciK0Z6k8Tvyk8rijPj7DewnZDmtmpnqNX43d4WbNmoVbX3z oYP9uI3KZn98ULF5asgJT3GYzrn7CVCp/urRgu2hLCzw87MLm2S8mTrG4q7Cf3z1Ts23A2psGvHI PWfxVbdsm18rsjkhHWBW+d7wvyrw/jaHtGn43m/iMjq/tQsIRKV+gZyTtJ8gTo5x8oTx/u5DNRpK XzI+tfkdmdlg+fLkeGaiKKnuKaLjG5DiT6ot3uDfIyfGpOagMZDK8xmfQ3qvx6tApkoorXqSaVbf p+Td0i3a7PzrMz2/dSyAeDp1wJZmq8ok7FKuUxOKS+2N4JADp/RX2GYhats9s+BygXAqlmFtwH4y pbRu4YpAJ0osPb9dMKZXJNlPXxgRIwlTzo7OwLmOTIgVSQRFqltzMpk1nmD+QROddku58mE26H3a YPyqSwJnGQFwy9I7HgFo9vsrlPs/dmshV5NoUitoFDByG8zesw51h7A9Lweg0LtKXKnHWhaFtOdF kUPcpinGQhM2T4s3AB+wCRKIDWriHu2GGdaz65jVvjfhr9w2T+8z5zpXvyoU1woCfHDRQHOJBkEW cu9A9EAzcI3PqnQkIto0590iFblTbKwwPB0pEr0O6E46ck8g4S1Qhv4vAYVPwpsY1Yt/Yc+POncq Ud5Ziy8iSgtFez/7LQgxZjJo5iqylH2Zxtrre35ldh6VjCJcjZ4IPXG+AtBmRNJfHtVf+lPMyPfK pmiVhoUE2dCad+ZtOsctjabH5lukiwnyuAYPLXBBGpvBPAsAiJZF7eiiV7BK10P9PjKKqEaINIe9 MrWCfRkfySKt4FlKHp6v1WNKTSXTlYAxTO8R/0ReiaoLwuoPhZ1xA5zl+CECqqXmh0ZsZt21fPmy HXCKyMWIgsHsdRIVIE4P9lCkbCyhgpPh2LaY6xp5nsyyWTCHuC6Us9SI+543VjVWuzilhu0EcKvy xpLMtu1HY0lAz4EyzdmOj42Ca9RLOWYalh8Ua2W+7tZbebtmPqI0wu4dmJkIT1ds9HJhIAB8GMPF 9IrIIanw69OqPKHx2gcnV+/dgJ81aJn9t4OAq/fqmNBx/1a5VuM2Ie9iFAFwrjc8YMrOkh/M86Cf lChVMOCFlZG06HnVFgPi8s3t5Rf05B+6lZNnA4lvkdUfaozlXBdwVSQNEVrUutIG8qg7+V0MtL9d R7ecCp71lFFbFmkzaVF8b4NUhRxX37/r97ZSfGxJYXs6ZdncZV3W8MzpuGRD85CaIwydjEHsZgZB IOuWkKT1iTbJD45vkqhg2GwxW8H2d4D0N64zUZN0aiKSoCfrhnTrBICcn2P5FP56h8zi9IlyClgN nw33xGPt+3KHqwDfNt5xwcbbToxNpvQGQuI2/hENUpHdJJYBnQcm4vVACPQg0WmW9KPO+fnGBnJP n7G5iiVr6TYu8MAhtT6EEbYOCzx31hG60NDNVxkHEqGh2YTIFXR2ReygkbjFOOd/KT6Rd+hlHcRZ 5Bb8u9kMiGoJ27oRCWqnN5sZ55LXQ55VMR2ogFAayawy/27byG8gafIGhC2OAyiJTrGAByTFQkMB 4eH32jtm+iBFY9y7iPogiSQxlpaj/DqDQ+spwOA3RT3QCpQQIE+rvo03feA5OShME0xHeDrvFVKA xbSnP71qb3kYKQ5BEijagCn5qFKdeLQaVKJZAIrT6yBAOQK9pE2wiY9rrp56h87o4o9p4ZXPOmYS 6vd5YuXDU27SqQqvNhIZ/YIielJjIOtEY2hWwiXbaoi3ylit5JFs6SS4v+WSj/1Sfn6TAGJEnZOc 4CD9nnsH7p+8VhbDvkz7Ac2ngU9pscWXWRjW3awMbNeyj+g3o7FSaw6CZVcIl+dkG3Tbb6M250P+ HbQu+B3k++L9c9XsI4DqnWoht0BRzToR9ZAsSHq+Mbb+rWRf3c9L51qAgb3XZ9FjFdDDIeVGjT9Q 1EQiyQ9EZ/BsvV8j7yH1y9rEAr6YtEax4fdI0iywdbZuM8YB/uZx3zGS5eYIw8qs3HjFYcJR0ybd Vubs+To7CvwxQqAyzTHHOlIPxZvByfH2RgQG4K/p8kdqYUOuHf/eiY+Vb19sic1VwQU5/ImwCIFm ZWNHVN50J3jhfd0B5gdrrGcjlZR1yBcU75MFG7nCRL+H6UYV6pqFt/V5Mb/OJsBGyPYkcV6i/sPp NssZePnRZl+XGoEYMALqcizNoy1g+8gKrBmODVZhNRyWXSUck8xllsowv3GA4XnnO7T5N0eQ36T9 3E+yWYYJmBS49BbPxw/KSc28IzN4pRVmRH6Kg5YKdrRj0p/f/o7Yf/6vqr1Qq4CoeVku+tTLkO0i yCqdr54wb28knEWrCxAaCEz/Wj1gLZsmxqKAVwq2u8n2Vncd7bacOo3vlNtaSx8wkLkImU+xFPeq fW5UIwjwBMsTbHAa9ADn6IbTH5ivZi8sRbQPw12Nd6VsetQcT0/VfztB1FCYEAr3xelE0myPLnEL gzGUXS6hI+kEFHRUn30gHkOYGvDtX4cduebwBYf2CdfMEVGOuLreKdeGnY301VQlwUWJ9jqL6Iq8 GW2xfZx8RBCvIq3SnTdn3l6QREnNylTF3lGys3ZtcjFOfiSlbcsZwSnzITCpgOt7zDE0veybsMNK U1LNwlGL26CupCMXexCwj7Cl3y5ZKo1ei65hTwYwyVFcvWPMaYOR5SbXXFLdcTZlYf/cR330RFr6 3/9Viy4H1GgnKwSGJ2sHxA2jhux7m696Xqq/rcdsNMAUn99aUAM9JjELPoCVhJ11q7DlH9xl/wY0 JPxdtUT4I/Vespz6+4+ItMzYRwRHUlISHg85fGjIveJoxwCNCkBsM4TXp0sppIJmeGtkbLQ9Z1UG OjhUO5NSjsqijOzONuwdLAxMWNW8kRb2p6a+ASMoBNj5R6jbDI4C2Vaugg9s8ktxoBvoQFhNrxN3 r87zREZlp3PdFs7W0j9M9l85XNKHqGZQskqfoXg+SkAoS2wQy/yrfyafXW5KWXvXR7B6CORNr0au X6vnOPsZPgkR6Q9vWzPUpLBG9MPNJdusUAqbDEovfSbPLsFyPuTLAk9f5qJZGIa5qjWsPNyBBNN8 CbxGdkD28W0pKBfMz5GLKp+wgn2r3kymnHC47H8eUOGsuxIfmS9ypZNeipR43sUwcH6RIawK/2ku pPyLUwHlYUMgxSLijxObQ4x3yARzif8lLbaj1O8d6jlbcWlYEGKcgitlkJm810AYKCWG46VK3Qqr TXzDUr+603Fga7qhJ9U0SHLcb5Y0uaBVQOLarRghrag4q1JI5wSTWzmV/v2IViOG5BAAbrqCEKGJ TPIKUO4XOt9zoZMfSRKL+1EVKCs0SnhA5b2lUKfZYG2J/ehQJlsO79EIBLnYS+GfCQFHmfR8Y/cB MtKzsENCO5a8+lEbZiyLV/q7cLW1kDLkCsyNN0vXav6P7CFo/dV+FmeAbLJ2DgR75X8LE+A7589F 1fxoo3bLg5JJmGSSI/BljEb6NO10272a0bx3ok+Ch0ZWTLT2rF80uaOTg7ksGWJILQg2VQqJPMLm TA4SJlFepQpA2K5xpi4+okP7ZxggHPOMDl2J1/jCkodKbWBQa+udSlU6GbGsjWLjSvo47lVszT32 vZklbMlLvEsNWiGwizSmhlPlWvXdZWOqXlT7bVeRvZmbSb75/wZaQ7RhetqJRScfc9oAOFIl4Wsb QyqsvrLMrT8+9Daw7wQLt2bDO0PqXA9xLI7PXphuf4YrprSWFz9vYfBIUQKX2xUDDksjVQ8TulsQ uXBf9AVwjcxAUDyYh8GFBHDmfy+IHo7Ooe+np9plM6umZ/ZswscaTzYrzJ8g6lzqPAU6BpbztUa8 hvJuS+alLzzTd9gRzKi2n333g9HLKTcst1DEtWFLWLdyvu+7PWdhzkGxCRQnCVjmdV+97Sw3mnIS QgeLL9HKa6jqa9BajqcGRranNKGKyvdo/L7/JVsGjOoKUuycqFTzv9Iu7uVgKnNyccmfWQQ6G6fR hGWkuGQVr8vUQbhXfkGNJcNNp1ubtAVR1xTIwHQLbfd+sjuOFezn4eocMK6B2Rn9RmEp0YL6osE1 cIHBC81LKQ3ivbnVchz24mtaS5r28tWkrZaar5grUxl2w5xNjRDUtzcNRY/X2sc3IAjQQxsGD2Hz IVbqSIylmKl99zlxqcN14VkBR1e+MKu1u+t69+c1Kl9UaADuqq+W2Z4ax/wEUFcQjExUy+nSkiHA A39BvzPRuVRWeCcY+FU+Tia5PtY10vhAqRsihYVom2agfWa7SuRxqeE1f007WMR92ARDi9hfqQnB eE7Chk45U77dSd7s86E2NuesR4A6uz0kQsaLYUNN0TNbdbg++VAqNbu4yA09D7jkp1ozs37PInC3 fGpWYvIfCTYTAMmZoNV9DdhJG4Iuk4i2OBVEsOSdoviT2yk8Sj++zwBvAMvAqx4YxBsFNQXIdl8M RK6T3KH3YFtojKuYFjd5kWq0+bkzp9OoMnaBynE/JcC7zU8pud6TAhgeaWD/64HctIjWXn0WDkKb rpof0knAv/mDDKi0U+XNQuGU1sy/kUk6x/MjSqvVL9/FBz8hpbI1B0GzpWVzmLny3lzAsaRGcdHD KVq4zesxolLZKsszZQKsz2H9L3+LYE3y7Cn/jdkIVHzevsLW6Sfk69CP8Tb3gadqHLbj93XDVitu rAu919tpvQftI7/Hns+Db6cDK3ES6/fjc4j7qsoP3GZbb3INpLDtZM282wT545SCom0i69gc6KAx wLM2oQpvcpqTjrtS8QdfukIrwkkq+hphjemJjh+cm3EwemOsW020jxuY1jt0hgMfKT0MO4S43zLX Xo1N5c+OoN5PJfgj2jzTBMHqGuFNq/WpSd07nB9l3tVgcEWv0WZG2qEfHFvqHppUISwrMZpPN1P4 Qx/vONFOVuLubnBrG0vFKUFqkpb3T23BiXElJ1hX/5x0IG+WZeg74CHD2Iu2eGIyh4fqdoghrKQV SqbmyoEWsFK/FX2/mMnx4R4BC8+pctoS8VEMA2QYf9Pu/7IQiXZunnaSqHnVbjypDN7/0shNWhnc iiqrtmIgS6wBC9xvlctFDaA89OoHM2eO8/TOe6ysVXVsohTU5iz43qG7JoBo8jJ0Xl2iubqmA+rl IQBSw3IdC/cudmBoI9OpxQv4/PVqDSuqnWFIj/6YI7YoZBm3uhJcVDQY3L/gtqomEMW7B+rvZNON FIqqHQk5AF73sBgwSGnTr1qXT/EvdHWYk/U4mkrklGM2BMkLgdRgilYJs67SOvyruMUxMXCyajDW nkRM2fzhBnSEaTKoxzjduhn4L+yJ/fph/Wt0jaMSbGDUB3GMScGEEroFyezqFL+vC7JERgdm0bmO OAwf+k1SpLKMn+dy03ljN3OifCdvz8x4JKcBcwlFMvTFt0Ypwe405lFev/Zty0mb9wAQb4rRyV7s wQjufcaOBDv2KtSHUv8rnZjvFgokUZeYYuReDzHY8a4eGH2WE9/SIjVclKkHS2CLJfrHsET19b+o LPKM6uZNc+BppETQnxrKbQLcLaJ99OX67KbjBUsdVFmzfNPY/z5lu40MOsiBxOkYGWroEn5z6gso t3I67LaT3Cm1qL9jTzRptFiAZyxscSELAF/AAm+5lP1Su1A31fYbdEh19gC0tXfH7l+iZywUR2PZ ecywfqYuXkND+BABpyX39R0UyTx6oJ4JTdlJ+QztM200G4nYHPB1trqijqeCVLZwP813/MFeQQCE C8j2kcign/LjzL0VHo/Ch/0HVVmJEFDalaaXM452Zo/u7Cf4YJbzYT3SKEaGSePtXcRrajJ1qc/G HJP7syDMxF4kqdXCb6ENW1dxRqEjCmiV+QF6/Tpqlsqn7yIbFjDDn8NZUlpIR/JjFQIwoNCDA1rh q6htLTo+YpM/yK7eLkblfrzcHb6vFaT+Ia3yJG3iU32TgjBuVv/t1blZY1y0hJ7rtdZhUAkzhw1g 34atl0BNKTP0H/dgY2k2dxMHK9ShLrscDhXo8XIksf3274sIvn0P7Znlov3iAAfdTlVgVJdZYbdp 0e0qHaEnRT8oMSwqBs4iv2nkiFOzWfAnc8foilscqLoVoIA+G35cS/WOqQ3cfHHdw6lUefryspcg aUa0XLQF3Izz8XmaCXb70+Qug/DvUBzhpjkiMXMKRncXtkLTw3x8O3CxOYdhnb4FB3BX77Bt46BZ tTkbtvNZbTpVB5mBtlamIR9AcTy8JKuawGyljyGgnU6CAUrTmWeMQMg/cbNNEFhRYJUL5I1M1yM2 0823ZPprWec5NAoGBSE7DumBAuEjR9VGnCNnIYKM1hjpp1bKYKT8+I0U4mPAKSMpd4T6RrqhkQMA XyQJTtbud5KNJGCB8u5KFOGOeHee3HbxjdpT6DpNWzx+lBtydw4uf8Bw2nTeuCucGYNvboX4W4ut 42mv9YfJOMbtjq2opiy6iNC6wKIocINRcqrfvHZLmY+we9QI3KO13z5oIPkxtASTJbx5zO0oByK4 VlCSG45sk1H9eJs+dtDNBHFdKcLitc8V7vlPMs6DePItdlr3elAB1aEdXn56/URP1RDN0qFANjD5 wJ3YAJ+F3GzlLmjLbkzYza2ay5CEpxu0PB5qefXsWyxSQwgTl1DZ3yi705M4raKYMLUsHk9/Uuaa aMa2LMfNxeOjsLiwYhIZeZGs8+vMhUjWrCUNANnf9gz4fVHx9jhAs4UMfhHualrsbiUnVNv8C6DI b7OkqqIuqGsCmeiEdiDQ33a1jKY6cCUbR9fZTiVma+VTKV0XpbeolOiyDolfQpfKHHcJ4nmonE4V PGr2LMcrlHVLZoqRh7Y6VcKvt0tooP5HTOTRlQHMIJR7JMxhLoafZP69rQHt2p9AR9+WU9SZvfLm af8YBsxb/mNH7/I9ajg7+qdnLLy66CEoJbzkjKuuptv2XESXQGAQXV+MxK00MA2aM3b6DQhOOlC6 Shy+4JmFoNQ4yo+OdmXlGsvMLE2V0Y/hiLGqha+MP+fznm1n/G2qnZ8F/OXE28fMEhaV8BGmTGKZ b2Dkp4U52WhbuuJNmgy5EgZSuVxo2RT9fJQKHAcuwAqoJzELwacf7mHKjquKSiuOxRgYJohCUNAd ug9gdralOujU5vb3rP6WbonmS/pcpUn+kEaVPVTZ8pTF3Aten4C9WLLY5aboDaONy1R7l69ilug1 7je/yEMYTjAMkEGBNoScwm8aHvBpTRx72xIz04t60ofJCWYJXLN9ciZwY22v8jo2dv0JdnSBhYl3 fMj8OjuWw4t/acQVxfrwVb07pQM8CXLpIWjB/5M2b5zq7gxA0PgtoNfGRgs/sgmbSjk0BwDvO+3y XLz63AlSfQ4ULmOz7DE1PHF7YZE2xOlDb2xE9/1n/+nMD0XxkRnyS/Q8YG739swkjBty6AoyOYgD 1NgGZMiZdGH63qvQ8U8ErRO3AidBtJyr0WjFfnDAC33J5TFfmQPkIJp8AfyUcH1XvNmv7Lo40+fh ry+zp7neyhoY9Q59hrQrZSwNpZUgWOnQBC7swUHz6rTxA2I3Gr2VtcjAgnWcKcGsdmG+w5xG3Cg+ Vb9eUopt+uAb9C14sxjpt6e9oGnt1nEyUp72x+/QJgIfcDfknWHqrNjLNvloLjifXQvj/rRXJRQz UABm1Q03i0jDr5WvaE9ajb/CjkSoyEASWeALGRSSTSl+ErZBneAyj/MRf5Xz3XKSZ78zzSWwolE+ ZjFSeJvIh9JCukWemECINa4I9A6j708pnizO2pXo5GcHaTDrjrQ5ZeGm9ft96vJ1rUhNMjZDXUv/ G3uKMaQ+1SAaZ7N+BrI2alTN57TKVmUcIJk2N2nJmPFFLfgoduqA7vPc5mpyumAt7EU6cc5y8X67 AG0QEQU4AomxfMoPlXrexsIcHf4imozqaEHmngxfsUVRwoQ+MS3BeGz4b3BriD7NPRdip+PwoEFF mKoZWFZgKsU5qMm/DzzdmndpIaNdcn5qrfuuKv9mqN0foavRoX1j2eoTVqrfBuo1YUDjH4b4Ye8w kjzTXhEFy9pzvQI3YegHVsVl8j9EJHIC8sp5LiTHI8QLCza38xOm0god4ktBli1rFd/VvQhrh9e6 on7JWu32Wy/lrzyakKNEN3Vi5lYhn9wjKaJNJQX5NUDaBibnYKm1ARo5Q9ePj3y6NwP7SRb9NG8c 3C1cCo4DQXzL+QHNvPK7cBVgo8ZNyKivjgIB7MVl3kMIu1y/W46tuz8IkD1YyIqP/EMtiN8kZcAS CO7seNX3boP0a1XqLMwISb67E9YcEYTKYFoJoAMH5kkfsHITzGfeJM/ZVA0Fv1T+kFlPv1Z+DgAN 9dwgZPPJrNYLcEVWIOUb4RpSwMh+hUmrEziluwp6QtCA8kNl7Nmh8xcoxydPSGTtyHYTTSmTOkK9 Gp5oEtdLPYgLNTkGy62mF6mPgjzfCA00aFZQPj39G9bZ6OhCKT5wkoZdHFA8qjX1WaorJ15oTdww Dramr3fAvv4rV2p8fAcmeti4jc20HCk9fuIw3P9TeUtO/dTjlDI6QDtsk8HDq1R4JPN5J/Tkm4XI F5d311VLDmb0mQJMaX0bV7uF6OaEJhgFoaoe/32C25WEXPHaN1JG9kata8jhRcgdlg3Uapvi1Kaa i17YHUjRRqvFPRY9WQ4Jy9+rTUim49LTZR7zmjVpUUeb7a/PN+dcFmmrbxdSt1s8XXZ50guOzJb2 KypAHi+RkIGDKyh03/aXkKjFxpsodXlo+WyJe+etVfNQ+P7aauLmuwMCxHieoPBZTRNlaynJJu7P Ry3UwwnmpAn0yqsqTVRctkDvOGI9kQIRlUEo1L3wQ6ZGBUzZ3IlIbIjx8BCZE2GMQN5Mf7kaWdro icSTBNoW/9k5JHBE/J6sSqwIGyMmgq5lV/tRHTUpH72bQFqBIQQMyxtR1s8xZ7fkUFx/lEkDRkab +IM54lIjJp6Al7is8bDxeyNqoPZsBXGZ++bS8kLgNC2lr/HiL/NfqYWMHo5rqI7oj5LweHZ7b+ne 1HDNNztxIu+jOZylp8YwKGz+DHDPM1Ij5lqQffhkPE3vxzO+eCtbu8ZkDOaIcpcQsVWKyTkSe0e+ d60KLjfq2uD9AZcTnT2qbmz8APjU7S7I6jBqkp0vHdsQ6FP/T4zEgiqebmBo56hi9Esd85KQ26M3 BS3xldw9OhZibQJ1YmaeATUI1I5KaI8E4S8SZaNmyHO6Yyc7RBE9r3Vgq+m3ozOfMImbvlePskCC QKVnk2wybV8E1JlCicTes5m4+Ju38pWnbapAlae8eJlJqxZ5xEB3NKJBqLYekGVaNwXR4G7bcStU /Dzy8A4HcO6Rm+zo2Ox9X5ITdtHO7+X9wIzIGS9+X/qrZ9gaNuvMaMPlJIoH73gBpCIiqCLqSi5a 001G3asaOK97eTDE8+aUnrjs1A1MpS1XfP6fRv4DR/iqBqZwwFZEx3XUB+YAf/4eIWdHC/l1orZi hFgb3JEuNLkuUR9D4BoH/LuFP8+9QBu2EgoEHP1cO6cwASaaaIudI4nTQmTJVPQXZCY/P+DVZ+uW homxmGOQy8HIWoxwkbpfJA3kyqxx5dJnBZQmW7sU0aFQZFJEnBjVw5rdBV0qrxj3dm1CD5uaIbS6 5QBgA8B87exsvY3W73+96ovVmcAAg1SJukek1wBc51+MDJeYRLd5wI9Iw1ilPfzSsR2leSDSd7kh E5Xw+DohSCwy+bZnECUP3nSstoar+tsvaWUNTM4CeZ7nbj2j/yaLKnltvYcTrkNBcHuNUW2n3DWh 4jkYmaqdh4RkM2BmPyzOcRY8yyMsA6UQG15is9XZ3HfFN5+IoP7VkC0FXMZQZBf5xYUgLjn8SNUN WyUkpnmOfQpoe3KhQ0XaJ+SjYiOaqcwHShX2YW3vtIL0r2G4ZY77mw7U3GVzFOtGwxEuFZtBhVH4 DN9iCl4YBnHYsPJpu4ge9/IDKvkUS8w2nB8bcdJUeaEH988NmqwJPl1wy/rPPJau2gpHuj3JIcIs 3py8vWuuaAt/EFMrCPOlbYkq42VZSG3cQqdE7Jr0kjhkcwcnuKaqeeXRZc05U+ghojqbVSTt6OZQ 8Add07h+KLsDdxj4NAhHqHfbPUE5OGcfGE5w6FVihuUikwbs1L7o8nO6jcNXrzhq4aj5ZYCF4VLR Y2+Lv73G9K8JOhd7k4e74rp+Eoe0moVRhDNwg6K6bvJjsKbjI/M6L16wBhVIJFCEWNBY0YPEJxgy 1DmEesdBdQyEfSWNzWLb3lQEtIvRmMV4Two/pFbkQ/oLLMwPocsvOiQmh5qLMa3r0tmuXksGzfYE m/5lhxOu8iZreWbiZJzK0o5A6Fa305Q+SCr3vlZ/jU+SKyQZkBet4PPqLnbsmEDfMKVMXqW4muL4 q0AqADNy30lD89H3gy1IRb0vRa0q0/ef7J3nL7lTXfG/afIvPZ9qvF8vBCfwuyB/NV4JC7bY+deB z+Y80wNXNi8/PqJUigHGmcsMUAJvI86Gb6L8fhzxFuodH1ZUhv4kbLHvrtu15MhSPAGbaubVNLjY chTv2si/Mpb17YywXTkAPzY9cb3/lpY01y0foaBBnhs4swwpWjSVY8h0HoobbC0I+xqWFEu/v3A5 TxPk3SwBvukJXdtVOd8dYGH3mCdPJ0ZNlZzuvneYjY+USf0FM36dHRDEiLC26749ZWoSlBOPA/Hs 8yUOkeuSsYIjwnqioGtJURMQNniJjc9ggqUNvad91dXAHdwiOetnhbcuYADSWSjZvaAUpC+6OAik lYRTe7olNqQuxOGA29eLJkd83jg9IQEFX+LLZip/yyQWwrVs8nPJdZl4HLdk4gCDOWQTZOTVJYNw Yhd4a1/LjpeifFdJ1UGSLvs8GVtCcinxTOzd4c1r9r+GtbOO2zUDOLCh7WZBwD8tn9Tl1bP8RDYp o/0F1SQfY3VfBpEw+D8+zZyasGSjg8PRoKZKgUm+Byy+BZFvpciUeEuKu4hOETwHLNevEu4s9UvW Uwu2YSyTnY5b2MwSkAwmCRLz/IpnHSJeYIBMAod8gVYe4FCYfAm49q8pPiZlCvb3a4yNdNYVZ6VZ zLDbOy1e8SZvplgnE3Jz+NRkprZm9+WMKnKL2JZL+o8hNzc0Sk3E3ngrIfKo+GiEphM5rJZ37RS4 5g7+gIcDgl9QhcNUDW8ks4PSP60rv8zwN8PxNt8jNMZvL7xkSefuIJIi8hKPFzbAOUH1KxRlM5pD C51xFr0rMEcYar/3CD/LG5jQG3Ar/V3noESAbHyCDgfFCNX6c1nnMACQF7vg7VuxkB6wgDud+EIn t8ZR39voLMpdyLcR6KfO2tPBnCCtnjvwi8AA9FIdXGPs2gMqXfmvRCn9qZyKXRebUgVs9IUpXiYS tx7Kp5cA9MfJMJVcV1YjaDvatIVsqaa0NFlT+SqWA5C430R5WrRewFjABRGTgWq+sATIUqtFLXa8 zEGByoCT3/CTjZHEeFniycwigzSE/HYlUpLOIgMB+OY6i0r12f9H2WjIww7pLKlZ/ofTgOfdDFQo OIcOxNcR0xaPrEy8J6YzZFIq7rMvnrUlxTwfFdcG4JQ7lyAf2V5PLb7pDTRPiP3uusyXXy72KnWo sS4WJ41Cx3ZRl+/xCijlhE4Z6HC574EHFxoA0+6cQcaGnL9D+PVE4E2/xmXDgVbdLx+Q7nug/LE/ c11fSRNYmJQDlINYOYuvqrzI04MMQBx1N2LDU23xN/B7oplfzWbBWycM0lovb+CDPA8P6uHHo+Fk zZGmPGOjPRuPs4ohtGGjdRrKJfQZJHFbFOw3pGKEhEZocwGdUGM0793V3tllVVwVOWrrQIhlhnHX bgsWfbnetK+8n+i4OptoAmIp0pHrrVW5vqbYfsR4Yw28FgrfXxqSbHH4qAv1Nxx7t5M3mQqlq4DU xUQUmdclxYDNIDDrvZXeXRfRaK74TIP1UWS+vZpqkNWDFlfzT8mBfYFjIkuy/Fnjk22X25o1Bew9 K3J1lmOmijZomZHPvHZPRLHf8ZWsVhtVk0uu7zN3fLLD2CR6MT/vE+r3nzU3S9tohB0b1bcSAC1R CVmqg23pm4vgPMuqRcXXWLMmjrP6VspNtlT35LwkCRxRM6PTP4e1EdPegKGAuB/uv5owazuZBtvA NClrTu71pV8BHQ6ngiAnypCeKA02jVJ+hfap7k87X3yisJKMnnwHf0y4HHJQ/ZJ8FPOVHOpgd8LS qb4XJ+WZYNidbdpBDqyJp7g25BMFXe6bRxCmgpWKYoeNIXdPcLmpud9DDWTPkbZqS/jPpH3q58R9 bO8xHk+aw4ASELlHswHn5078jOsg3hREodLQE+lJqLi4ohbgvcjk4k7r9RaaxGUCqq1H5lqJNU0q t/dAaGp7PvI9z2v4UukF/d1hT4BEdotcKrV8Rm0XJHydeWgHJwC/184eu5xh62EpVobHtdvZ6L5W Gsx2CJgR44ajgtZWlgplgsBdqtMxdWW9L9eIMVdm41TPf2CEf7fqvvGv6y5udJfFSS/Wv/xtDGVZ zC4ZNVdHuSUuBmjPFvY2dmnle68fnXILXrXvC3UFzIDHAuV/RNd6PqfWeHpZHY/TO1egl1f8sBBQ vAN16bVaHgy96fqe0q9xh+RqGKkTzcKQcYc32XIrQhP4CeonX+xl026L6H1gx3L3H2Iyj4D1od2H xQJwdF2UtWg/H85FvqLpvcgrt9GpHciNMwYXMUVE/NjIDZdSn0R9/fs+KX8puK8Ug193Y+UrK1f/ DyiFXkXpKaGJSOTrn+U+bGI6TRm3QWLMjLYJwI3/Z6V7Z3kj1JUuDn+DT3yqNQx9gZTsfQ1KDMe4 xQVKFk/VA3W7NiQAkcnyzYGQfPXxN/cN/5jgc9xFsyFGeLYUW6bZPzYrydqWEoOE2vXytlvRcKR0 kLODOVfJSd7U7/EHh20UqUyRyvOaqzv+W/J2HsjdRceT3B1kVR4h1GbWToeUzXSVQKtLuPyGFByU Q18gvSvIXoTAEEmabD0AsvjlXjE6C/x92gNCtva+/vX2DOig8Latf/9mIk3r4kca0KdOWZ2rZHg2 wqD9ImphAidF1MuwkJvRayoaEsPvImMODDsIkmW6sZr9R9ZX+OGyWvrMpBjfRWciIZk51g027viw RuH5VHiklXY7CYXfZ2xycngem5dMEQhaJ54ji6vW4eIqtk1x+MygmAdPH8K06Q3FH6VdBZmUYgSc m0Asau4cxWGDFS/57V/rQwY+PWN7vm76A6HFp30eW93VVBDd+hwI+rfq9AemAAkDJOgiCzj/xICf Tfgm9A7016kqGb+0LDxnOdO4+JoDEu3CVdOOUZsFi3Zg0uVZb82WLOH5cZBP/8OR7GR8E2vpofkZ GjjbknA1Eazci9uQaQcVNmlIaawrBv6fzFuBsPKaNDHVeCAgJmmDercEzSJR0LzY+D1IItQGUh+s 0Jl6mXORi6ofEmP5GhhqAkEZI/vF4gWrbS8TUD6d6CPunmwfdmlavHDiJiTI7zhfTfmVfpaCMQMP qqYBZZsM+bXWX1Kk3KKIc7KLXjVRXsKg82IBgIUlIBAovAaCk9akxADyaTcC1ZpDYNfcUbxAsk9+ JzhVasu8sjpvmhmJ0c/4tbnh44p4oNKgEREdJEzKg2mNWezCR6twq24sAfR2OhE2yZK564EjqDjS jhOD3sMfs6UY0Wm0eIcc6+ZsKe/PW7RnUG3iFgMS/EzifIOlDWGCpj7VHrXXqKxHkS1TyZ68uF5P VNXCs/NFcmmXU+zHjeBMeOYGIKTjDDF+asa2KNOT1ktdPD7WSEwj/mOyYC+zxCIxipzMb/UAj6q1 23vjSSZH3RF0usyt/NHWK7WcWshohbhpdARGYYNPYdWIptePfUC1DwMwEiTzVIsxgYM77rmzM9bj TeFG1KV8+snTRukWubBHD+cpplR045jyLY1tPURPlDRBgRyxL1uJvZDd/WKO01ah1baq1sxwPNK6 QVe799UeyD53P5hV48zFq8Rnsk+IIgAwzloCXWzK/0bO+JKweLw4FUsYFhZd1IBz+8sSfSyBsk/b mpkS6O3uUnuh4rNb6yJ6S0WOlqvLRNCTfOyMJzHYBGB6U3wW7t65nOdseY39h9ursy9MWh3QYMWD RIfTOLvSWyyeTW0vLERcdgOUO58RRUzsgRv463mDSE9B4LYzgZt6GttWVuiYWqjK1KHiTofVlnzh uPj1kgFsfOYfT2/g+qKVZrOFjnlxADqhhVA5mITMW2uvYR2zReW0rYAaWRT4xEqvrfBaNujHTQk/ PnC4NU4+ddXUKbuenj1b/FekWH6JPkKwVauoW4VlYa/l+Si4ZlmojdyQCGKNfhSYrT1icmA04Nck EjuOl6hO7Viu51DXKZjsBWgEOfZD0jCoPCjMyJuvJBMqD0AJwP1SaCs1gJfTLhrML6h/EkNqsGO2 0o0t9SnpV59SoIp4/X0Gg8oI52QZSDhWjFI7jF1i7wsWxjkVbJqIlOj4qfW4rXwGNP7woPiRi2Je 7rM3Mha6ui6QoZh1KMhyI9eZS7zaSWrvXncoDOaSef5GN9J419j3Edjy9II2fOGh+M4vf28k0znH hfcQHFqXqveCX1gS1BoKPKu7Irh9mtY1hm/tlN2Cz3eSNkYAXOHNd3dY9WbCWUBLo7K07reJrirq 5vhAHL/zfRGfPfXJJ8N5nAc4gEyoxPyeRrQhWMSqoaVJQ2FyQZlTgxF5T0nCZkwHrWYcO3lKRKax S+zwNQ0AgxS61dZ0iU621l14uwbivHj4n6rN6nzZeVva36aHTK/OnRWTbhsYlPvxuj3uPjMSFXeT GgJbFOHAa/W579rWVNv8avd1XVIn2gtVrK8LovJEz2CwmH1dJBvRpw7I6PSjc6aMuYoEwFwYEHCS Wt8k26e8L1W8+cX3Y5eGQJ56VHoMS/ejngK/rWn4MSMUEMgx9VQeTnJQBbQ1ZLCdO+B8ZpvE6TyE 0aCrcauH9dXs84OhpWJEy5x7FFl8pBlDTssh8uxAfDm+WxmUr/IWYEuB6+8Ylg50Vy1aBVsr1js2 Cv1X9TuaUzcm0AYfbBgn/qHQUw6kn0c0dcP/cY9sfIog4j3FElJc4gVXFcRjjN+kYAT9sPLk4jCE +hkyox7nDYbK/Tgr6TJcpIY7sjsUGHyOTPBxAk9B2wnSFnmAvC0j+zXbghQwcbOxFu23Z+x3oeax 3JSnzZCd183B0971US6noCPrfB4HgznxAxiRxqptsksM+zSnBDsKWq00jzk/gV9JCqmZl935EEyA utDfGw5Y/EsWYAKEwq0FrBgBSTWRY/QrDsOxYhMmP+XABgHtq7jO/cf13lqepqsJRIXhh9T3nYXF DA5uBXA+UPICQ2aYs2Z2p88UjfPJLPXAkKH7BQklVg56ONYr+NcawKr0buVaGv9LHQou6SJFJ8Uj G3ojD1nBA5NqC6ssWKQMMO48umlg8qClLLzUrp3Fa+NCneNnjXaDwayqXlfsvL4elD4vdntZ/Mcd VgfGZBytNA8JvPXz9TA8POU5fT6eh1SJagPjss4+au1/EK9wC1lx6jw3pKcXaEPiUKgWYXaPZYsf 4cc7/imE9oVWZ5kKStjTntiFrgoNK4Y8uInsUhOTEx/SkvsxNfVdwtIhl24B40RxcK0fxoHgHSY4 ifbCys2zNzYgOnZbkvJJDwxjwl9IxPE8xKx4XbxTW2qm1sxCZnB0ww13d3Q0ZZU2eL2EGUbqC+SK Sv1K9g2HIM6PnEYtrRUutuGNpp1u7fr/8d3IJ7Dmfzk5boCXlbz+BKH24pzfFg4pX2pYDcfdRRtS kKGakOM+EfVShVKFZ4FMC9OazcmOxhFFCQaEGRb7VL58ArhYb49NZdD80vWf5foZydtwS5dYA7bQ SWaJL3QNmcjFkQt1djk80TZ+K3wSZScPBBTpazpzg6CkATVnT+NT3tPfvSpXXjQPY5FExT+ZrOsh RqhYI8W7gRV9pisamlHN6dgwCOwVLtbqUgTfNOnVYqdfH5cOtke7EMlkYU7mXrz5x7dzjTJE2Lrj ImJXciaBUQeCe3onjs046J8tL2/FW7dCugQRqp6WQsNAOzv+9S5oSW4aaFdc1yKvJa9e1ct1EQFn aqXgwKJeyZmYYf8Z+D1zIPSVleI2Dv/TXlbLf8VVnyXFow5u6hQZyyUE8/I+GtifZd9aoyM90cWG /Pbux/O4+N/GCq9Gwj+2Xx+L4tNs/4RwxTCmpKrohkHPlhukqT1ahHDGVrywTwrwPae6s0pKHhgz Dpcwhz0Xpnq1J6zEMj8eIFCTq5q4H902aBWNVWJCE1ez9KPjjDqTkokiagYIx7fXXnNppMuoMcue TxkCHhP35vxjnp2co7BwG54oH7fq3QGozu6oyh/vVbS32T0J7Gnn0A5agNQmCQt6/qGHtITsEJFh 4kQX5IpXjxAM4hbd0HUMbz0vzxRPIyG/fD54i1MANrF4+zRoRbKpA1hnbLomt2mRhvGLhoDOOxwH 06Ffxk6KcyTIM3Hqg9sBCU7ByIjQrbFrfBLutL4uEfF0S6qSsjs8aAm06EdirMZzBPhp+f8BSFnF 6GoJd0u4WYRFmSgxMviC692qqjE46mP14ch9nO5GFv6uXPo9BWxPuPJXs65U/OM7RZlwSjghRhKk TRfvZDLYo9T0fo0Zd8Ad1uuW+GY0gKZUO0A8pxVnhMoE+gl7dp5EZMfgWTPVcCn2TBTx9aHg1kTc G3bFAiF4UrJS6FbC0u6ZcHTAwg41lRBmdvk5LKH9W+e+svZRfCNjqb9kEdKCF8iy01maFeqJx/Ra lg/jUK9vPZ969XtrJgSHVGqGYbiEYLtoGMJZYo5A2rK2R4CJUq3MuraVi0pYfdAJ9aYOItXKrGUb wcliPpnrpUJh+zAWczKX56JZa2q1BBRsJUnXZtkj3Iica7xm82bMBH2xMVNdsVD0S+Li2p3UVVSC wOCgJhAgOYutVe/H7RikdMUP2O3LwHXwiv8GDdH0MmdqUsljvF6HntmabG4EjKs3sC2F37DkbLIU SLaJi/IinG1E4rZCGo4/7dMR+BpUCz+bVdCzDfZZuWPGwSLnK3A63iweYUxU4E9H47JtjVh2u+Af 9PLARnIJ5yRkm7v+1XWBZLTT/JTkmC/lxVkVHxTj90R3QTXIIhM9CSRp8kd+qmGngnHP6q/Cn7h7 8TokL5p6Uvj8E3Gqgo+gsFJ7Y0RZNAo1hvhrt/lkJsUrkxwzfkVfL9Oz3W7Nghs4ilDu4Bwek7EI AgIJifgMkC6hZrBogEMQcnD7dYTCiO0tyvcjFICQNjlN1vZ75f5eYQ5pw7NhSxWV5CnjnQI+rydl rmxKAAV6SBjlmUhLxNh2cdKZfe6wcBzEfRvxIDQRZrSWUNydmrVtKkkQhcn+iOUkD4zknJdv759A Ca2wRT4g4s1yxf2U5MDTazvBRtrSbAwxf/5nscDOY3QuzMKHyffC4axmoVb0Ja+2SUyz/NmH60xA N7CLk12aXv6+iqMixKPwmLyWFxzNehSTRkCCxLi1hkvOmqPhf5k9L36vK+X9A5p0ALWaqrZtkE4E dy0VvOk7bMjIDf2gV+AL4cwHqNx5CKHG9B93MGJpOjFysRwAyCna14W5K5a2oSxNAVzEI2Mlo7Ta hXXjCWeLfouphrBw4MCD/cW3UaheDsSnhJJTaG1VMFBi1CReWPHgucs+GAyvtsjl5KFb/16CI15Y 5g1rsUvAoeQfrO3p1pt6PNEJ/QGXkwwwrqjU/jBuDerLgza3qE9TOD5eS14fcym27Q6giXWVHTfp PDUzAloK13mVQc0V+ArPKaImHqWukthlDukK50eelJD3NWj4VesEoyTfuTYSwjq4gqGToiOObVnJ RuGmfp8tjS+gcQWJKfyEXhewgUXViseexnamBBjuGxhj8KxSgJR8GuuuId9x6S9s9oGIctC1FdaW NbEnevx0hE58B5X3U5h1o2ohEkUJmm1PyKf6waSIGnU4zX01RYFuaTTGxgSuehHNwZcKFDyJkLKS aF8RnunCw6zj+id05jBU78g7GmUmxLr/1KMvlFF6Whef+Zv47sDWTKUg6ssc0kUE2igqN4MpFuZo dVm2OMJunIEjddCa4PnyzUK+pytGZP/pr8VdRy6e3ZzXGIL+hdCCo4v4xWOFONZ03akO9M9tD9xH mFwd+XBnthhvlBiZ7i3zl++gN+PI0Q+zYfDipcoWb1MS+3yozz+tPqkNlE+xaYb+VxU+Nv70otp9 /sRrf9/qutssxYtnFqRz1Dw8P1Owgyrv9xuBFbEAYqTW/EYZxclBvfjbWXBpXV57fgdY4LT2Eb9Z ALrjakikpzaqY2IOmfORAJPPN7h2N209i2sXjjAS9fKJ+E506HEs5KTgkN7Ke+AYI27qcKtfllNu ZmKCMufN9qIppodqzmjFrqn8qrfcD02jJ48yOFmOIKOH2IYTxxHDtUfRJ3Hbcx6u6COKt23RfA6I r04prPxMRzsVj9sPk9rjysLiIcoyWcDy9FAQTD2AuntECUWGnQ4UVj2BZtbePgWASFWnVKfNmdZG luDQe2GZ6IrkcTGoe4AidwVpjD49AmA431msXy1VF83uiW5nt7zF2HQM69Gwq8RlEfzwL3+2sjUO f+HOv5AY4ea8ISZhN8D1DuXJkeaCg739t4Q58nGgv1+Cla6X8wAwMMiqzkU76STjN8JQkgVSludu Cv0KDxwIFQ7+zI6nyL2LxDnXTVET9p+O9J1eYdu2H8uGSNSpT2QwZLnCPfaqdEJUcQ76hVBHXORz o+W9dK5JXceKhZbkmOEZQVnmKuKxOFwoIhW56RP2rVsRLV3qM/5Ym3MvLt/EZHazEzz5LfLQgn1E bksfpUC4wQm41ovxm3hQ8fHfhG0wjL5W5iw6x4+7oHjZ9xRSCHikGb2m0ug/9Grs3Hys9Uz9R4IF t4e2i3wQOL/vb9TkaEBe2tjEwAGUL4UOGisp8GgW3lQcrOmUyru1Bi4/bf3dmV1t4cGgiCT2Drho EiW1KHLH/XPllVEqHp6koPh9me0DQcR1/DxtnH/dhSHqaNOCvnq/deXAVsjwfyBc1ZW2KZz1SWb0 77yYV9Lb+E90RsgIF5GPlE4TH4DP18UJ35fMkMn3unLHcKNUhBFfFMFTW2iuiqzz0Fc0gBxRtL87 /BP3cZ2OL+Mz7Q3j/Kw1TjzZeaRsFJjDqmjBkwAS9ks1s1F+32TIk03UMZ50PQOM0kleP5vgYqM2 8VU2g8psdH1hPsYggGJoW1mNCrQbY4pr68qm37376LB090sgyyyG2RYIRFhGHE3nC/UFtbQiB/N2 Ii/wBepTFhKYtf1uvn9tFXpdzCXS0NjghtLPDUxCNcQsLOo8VAbFNf2bKDuW9kDHXt6CAfw1lXtL /DW/2C2CMuaCC917Heh+pAw2GmIqu+0m9W31viXqqWtVJDds18ixOd3rQOZ+rNB7uTiovDFawOk2 Xu7fhjvhO5gGmOeeObLRxOizSvxG/JNAB8nWlgBprEbyjm1xRwrydNJvBDvHbsq3wdFAbyoBGpvU UnX7N4Z/4RTne59Vhv/+z/tW2TEAGRLEB8ea1BCam0bUEvIc/P9LWB7+oBHBFBnaQBvDZUOVrFVJ iX3pTMD6bqpy+YVhsf+nWH6G3+DsCXvqVkCSisoCFlq/uQUPfQy3pPfmdmtOCgqKDvuz1/EbCieR IHgWhYiZokunCCr8omBw9UzJkUwTtti+oPcRf7GlkwXFazj1V4lEagEs5oUJGbKB2G+kY9I5p1Iv SVwL6jJmPrFhk6ql+k6qm8InBYAvVGPzpvm9KiCR8deU0ozypK+D0xp09HI4pMIimrNCLhmn/4fw ssW2oSU7qJiF+zTTmjUySKM+6S7f+AvGzrR6e/TsvCh2aYFrzomKPuP8lnIQrrPlsJT+Tk5Bi5wr 1nTz+dHwr2+MDgGHxso5/dljv5sh2PYQOOBFqeBlMtLrv773yXWmtQJlgj5sutI57spX6A+vlahu gkBfiK9tnlBwvXH/VdIPrNgUdEQf5cTEBB0/An8qrM+EqkqSwXWFH+HAcVgL5iiJMyive1IM7Tb3 IKWvmioR8Lc5nXX9X8PbcafksGpT8ZXLD7NCpOVNsRR+kSdGSDaBqziYEidyio4mmttR5/34ZNoV XwbpJj8p+TPXRg5oTCojH8TfpxF9WSX2wA+YfxqVarQzG95Nd++diyyfC1H4Rp7CbI4MLtwGv4+0 DNPLo41KO7ZhcnAvdyFPyEt18xP6LAhsaIMLGXlXX3hZ8MH5b4AhOMFK7y5kASvgfC0+7AdOco4Q 71buN9nWaHNkxKaDR3UsscoTllNSK6B9mzkA3ydaOxjMTDv5Qh1mzaE+Om98fBIFJ+LrGjZXt7Cg JoZKMabTqwOUn652+Bs4b+szXjt2wE/XWds7N4+usieYZdyky8DmaMpdOCEjZwALu9o4AMitQEy0 Aj+OBZXmnzy/jgE/gDmvM8GqKPQPINwBv86Y6xgnSTFZYFQ2rihIdBgrJn38l0+kl6nCAbUAjJBU IWopQck++cvUM0HCfoHmiKzHISjJ24I83Vjf0vhZZGK3WUlFMDcE8/J1zdZxdhzLq2irLIjzIIj4 GA1/d9A+4YfpSK6SZSVZA7X4Fwhan06quO29gQ3uq2JXurXPSh9WYoWj4oF3amjC/7o5Jrue/kNp KEfx9osPsoFXF7XX42RlmURJiTujRj4rehrvSjJcQIGd9T65G0BkGSeGD+5d9QcqfeRx4F0TCPHV USvskJlOBisiUF0pQgPrNxJhAxIuCVd5Dy7Xp9I8JbwPmg5m4PTaRFQCf7u769FmvFgoy3Cp7mkw Dfk8Hzn4QNBckeXkgpAPfZ91SSKfUBSWXUlKe7fNz8q2ZeybjuAReORUYj+hore+K0fxyl7WiFux v1JqttSeA8VlFAjaPbKRoa9WZA+Y0N3PN0V8PUFzFeJZ0hMIemttRKiCBo0m0XjdG5D96tX11di3 OW1GJXCfVTu3WqrASGF1a4nQbzp36U7Fdt9mKlkLpP60yLghZS+7MvrZUVY/mnmc/t6ftUgjqQnz wRN8Hjop5oW2ZdqphosLp2mYgdJnQLf23vv1Nd8OtiEwVdSrXUR7e8I78rFPgBCZvw0mki+whAVi 2SLiyBT2uXFwx4/fUBOJnixFu+ODWsBUo0cG4K40V9Fqax2T9PNtTusop0FEWhWjUz7XiY3V+Cjx kVDHjRUVVpSYVWFDI2YEsGaC8f3YVyJxDe54Lfko1Nz6emC64SEQrqpLH83GKJFEyqCcQKg0ozsA T8KFnjRs7U+3uQFDYawS4XA6Y8Dcgv1Z1WC8Ww2NbmegWr3Oyt33WLvfY+Z7iKzgjS82gYHKEJXe fRL3Fb10yUUdodxXRu4g1nYzKMgTS9+uAt964P06xMsLN0OLQIxfFZdgDF+TK+yd5ns22vKR6gm2 cwRI6ZDwhZWr6SKH9NGnNRm+EmX8p8+7eGBgkSaQruxMR8krwgeu7shZJ7FMjYH/luA9kMfFk9iF CKZaHKX1xrLSUGg7sjWnq2GdYh6lEOFH0dWfZyvbMReFoitpWITwndUY9mG+WdBdpxkb+8/gD7og DY80AMegbWv91F8kaaLXvhrdMLZG4trvAdLtaKVRMbow0XhRq3t1giOWtoiyEUUCqcYdHhDp+Orj mooayIW+VnS4fkMOKur2AGQa3t3/rkwTgdU4jm0ewnkAyq+L2324ZkNsmdEWZzpD3B0m3PNbtvUI WF916vmgy7xLz2RRyledFOjXDGSwcDLWAvx2qpJia8aHr7bS7YK7g4kUup80tdipxWtBKFl5Ic7J /VPIkbEjWNTHZMkSgj/2GIQvULwvWqVnlzHFSnY6urT4SsnHhM1l/lHOVVHiax+7GM3t5yZ+l8ff /BWf/rBJDlB5x8HJk+8aHGbRypqTmoVMaKckJ9xzkMqd0BC4k0zIL79q+CFFCjvx6t6nL6SmvJUA FYy8hzzUbbVx9QdN3Y2qcrY2sE4qQFrnSxyX8+jTWD4gOPY1TUwQzJpYSi15z9NecJfaWAl8kkPk Ne55NlSNFTxkD7JM4FTBX/Le8af8jVSkVq2icuHRjvbTeLEHlLEqqW4HTXFc+WAE/W7u7ZO0recB i4TTrwtjjZ49jlK3fNWxcNSu3MYm/rmxdTQFwcX0f+7Vz4VGlC2gL+TCta7TKUDgEL09usbDTSap 4xyDEGFDgO7ZhXkh5cvkSV3tu8kePdD/ILHm12UYAWTsrNeaUJm54J7QqbDiHhFtVYxYKYNKr8ka 5yqvXhMKY4+hpqntE+jSjsqLKVVQoGFqjVsDQ9le+I0Zbx0qlyUzosIwqoHc3EefSRco+Egepx1B 1/4cO9XwPTYXBTYEdPI4v58vazqcdjABV0ehNq8VSBdNXmrP1sdVlgEzBZGhyW7lUVtmzCcD0c9H rRnzTiVAuWk82QyY3XXeU5YQqh9TwGVOq3haDVeid7LkrLcuiLUb5mGtLQvC8/sKb6kviK/slhuX ACjSmDD7fLOmhNCGE4sXs8C5o+xrHCoMc8NtLVol3KpsJQarhsqLXJpnxaLScuo2v9HQjEYnpEKh GtL1lXqs9oNYq4j40dJJZqN5DATd+g813odKaHzhXnE2X4dpcAODtmpHdVMQHcEuyRpUxY/hJHYA B8LsmC307lgEwIwc7JECNhlJR9gcuQbgdt5wT5Q8MASB6XHuEFgBogNANDGLK9tkQE8fRL2Wq1uv Rlob18OPmeyetmtTV2/jYJDgA5y4Qfk3hu23cBnxphrk0LAVN40qA8QcUJDrEzu+M6dIUzPNT5lF tgujwJ1+wLt+/u4uUQXT7SMK2LXXzWw7U7EIKgj+0VHRGgSMPVwn3lre0T7w320O/zzv+vdjTzl7 0/1Kjd771agQlD79PGwGMc4p9IpWHiK71iYm02g1W7tK8pBHI8DZPFhMklRyXVhMwvsI6AjDEL+v XLv/qroOzyvMPU3kHx+mO8A4pHStO4vWXpCVIkHTUBWFEEwOflTuL6KUYTX+YRhmIBC2SL6LmEam M0AmPPhPFICgCiHEZ1UE231Pi+W2MmFfT72zBMm/57Ma4OBvVbrMA8xhqwYAw7p8SFWA6TLUNzN/ 7T68d4ZUPfTO5zcxJTHWlo+gKEFNUmEIwTFWh75aOnF57DWc9MDGmCLL5qAKSJKMOovoVJuQyAid KZ4lIFq9UWfJb7nYC/JUadObE1e7DxjI2xcq+sGWazKPMkDUntuDiNnW4JIIo+BWEgFSsc/CD8fT V8BaY/HqzwdH5x7NyUw84XV02bd88TeHaWDB3PGQvSvX0hSNzVsAZ/koHmjUN03rHsCjgVXVahXc 3DTh/QyDp/JUZ0q6qp9BSx3maeHHh/OGtvverc9U9QM2v7HXGcA7QBsUy0RGrpvckjpyAK9d1GyL tzsAsM8p1kjoGAOWd1WsS4RvSl79PSbLa/+JNlpo/P+ZhsqkOUuMvaFMNZwP17Yqu8PLnaIpRrpT Pup7ZEfoGm2y0sqkRijd0c5A75Iljw4KStziIxStKtF+AK6hBU+tV9HJ7ps0XeSDd0mE0LMFIQ+N EUJWYZkP2UBQbg1eWQRUef3ul8TCHZOlrknoGHF5M4OPN86WB72Yx2G9dzVHoiz2GOWw5+h0bv4G WZMMUd01u8oXySRgZXb4T96gKMBkBBd9Sr3meFNEMAiLA0TsPsqkoHgkoms81nEoF9EjtWaAzg+Q f8BpfJhBSCyG6swiMFJs05ZlSQ+Ri42+uZ3jl+SWhlcJX+C4cmFPeh5RShimpImsCwUAkkv9eiJI a/1DhFuqonDByEiuecKDCP0QZDBG5fzQjnTN9zXwU3pEiglKv1Sgo1PJPlQZN+AhwKvWenqYeoZK CU6Ugr/3QsEc1KptfLejWGCsPeE2uqxTN+WauzVCaxJs/q16CSZ7qbiTPkBkqXZUkSQvodzeUqpt UDJTe6v5How0oATXTWVaGkMMJTz+7QNvxp/MnlHrn9+4nXZFBYMfF9hsFsZwBh9GimpcmhmRGfLe E64eDLCjzQ+OMccsXkh1A1PBB3A4iPEW9HZ/1S5iNFaDo4WY9/hQMJi+T+DNEALZH8kMkRHA77CE 5eriL4Qx3nSkEUf2dgZ6Kh+ctAA3ARn1ZsfUEHCQiHfvdg8h5SdIHplMWdhEYWOxFa/N+G/FA04+ imN5JTQa2dpXgu7wl90Z3yJsk746qJa+NVaAMgzZWlPstVbxq9eqTfcqDyKghPqB6eI0DCevxigs rWaVf5O8oytAyj0BfBfCcH8PTrqbFJ8wDtEtpUojKtPbiiGNA7h2c3pl7nV0p7tRzmYfW1eFL/Hs 4aevT5+vykGFwsz8IU47gaBJK3qjS45Lrsr6hCQffVk6+C/neurrGyMz9drjljgfxQdHjuu5o9ep sumtHUfFIfG7GW9NNUF0M7R+w8nOCtDWBt3Xz1Q2nV0J3+8E9qpEST60B8zhrvr0Mq46AafMD9ip y9RKkv2KsepCDM5pJdL7KE84tpUz/rwP2768wrkYp+3nUu86ZqQjCLx1XGVjB7MjWp0kbQ7xGEcO SaO8rDACWvopYnihKNpx4EXYXOzeeMGRt5aNadZwOWf7/pQemHlwDgIj+Eu9LRhrnYoA2aHzQpFs bDO9zBsjcNTRKmgPj1vW5RucA5T5hd3uA7RQejEyu3QPflvPa7KrobAdJ93xb4vXD7y19aOVidwX ranLFJzLyUNa55ocVwfJvin/Oo/P+//3GhwiZ0j1NzvJCjnU8K0egpb3qHXsZMuOWrM1YIp61Fql zvAcLs9n7iXtm71Fkb2/bZ75Hqtnc/hKWxjZvahhRIBcABdGQ1MQwhrg840/iOW9yJdADOiUt70G rrpeHWHW987kgTqiRdqnyAasDboi/sAw/0YI8Xto0H9gqQYxjmPWvbNY0Qbvwytl7s0AP2TIgplN km26cabZwOcjZkYs3eeRfVqguxvXKI1/0MkHATR9CMW8/DgvRqP1bViugVTCcalxR/Ow9GgXz/mO HNzmDWE6I+TNZDTTGFQzdDMLtqg21EV1/nJS7i898++qjbeSx2w2Usu+lqvQE7G9RGz0uMeGkn4Z RIbQGylzFNGPzGJVIOHBWxRjyPXnJWLGcpvlcHv4VH1J76UBLpSau7LXyNZloyg6sodHcP7w+z2k Gc7soc1F8LeeDX9GwStQuliomYjk8y6+D3NOC7lmVibfod7PQb/uvmik6zT3qlExMOjPlOPSQ17Q tYZB8hdJT05Za1geUP1W75/auhl2VYkXLhi00+W6VLhcFmTtLooDJrvTgAdlr7D6+xnOgTkIvwwb tnkJ+W1EH7uAjwLjQfN43re1Wvz/6UcIDJlm5GSIAHuPNLxqZg7TaAhJEm8gonJcsWTxPxwgmuTV lvY/AZT0JYfX2VzejFR28aWT5gY+MZ5jrRGE6UYDrvLEbAtfXjd+YH8gmAB0djh4GiuA/kIz9P95 07c7Wu2ZJsCcGDf8Qpj3M7c8dIdVcz33eVaLceJGQjblhxpEWMAHjUzpBNn7j8C+MMH+6IjrEn7W p6H3hFqRDR6cr3/RRZbhU5OGxGa6GtgUp70f+cYw9kntr0Db+0c5sPMXnx2RLTfKaLXeWdM2RdCm H5kmH5EdBNisKynHjFVCxDHo4E9ub+TDE1QJi3pWoRWdVZFYS4WfCDi88JHAriNuh9szfSocq4uM AcnYOkZQOUr1q+ITLNXomHEPIeVKgKzdduLpSIuZnpX7gcLJrws7r/TqqC8PsOop9K8N8ZHexvZx 92Q430yOjmntr7mqdm7z/lFkKc4V1keMEB/pEy38UZXiIZjlfMUtea1rP/L0ZIPv+l1fr7H5VYr3 avhVyI/sWathXw21nF/ykeY141CvZL2Y1EI9gkbwYsEYabbdECWX0JKp/AEdIBlWk9hhLYKmIS54 jVbSLl1jNdYSVuIAbIHA4NEvDkS8OcT4GcZF8M2o+sueNyzT95SRO4KQOsRPItjSBZgygWlAgb5Y 1gl9q/bWJSuGN/QGPspAAFzMN1gErnk+a8NIe+zlRj/nQT5OIveYw8aN3l/w2IwpSHUpxl1iIwQ1 WkqR5kHw6rRydGD1JflDRGNH6vdIMVIriOJky3ZKhrMrcG1QORQa6UxrMv9FOCwGQpITneh/CZR9 O+Y/4jS3xyY14aq69J3opn8y0+xsI8cDgjal5epRl504Sy2wjLV+P5KuLGaQInPkUilxV8HF1Q65 tf5T8+JrBSSSvrofvr79CAG1/VFQuAht0YaLB9VETKcL5xyBR16oG30eTLDfXlv5R3ROD2GGXOes tA2o5Oh+ATR1cr1ckHjXuwSymKjEGcK3d7eFW53cKqQBTNs2igRYji6ub89b6zbAccMXJpwpfEmw ws2sO5h3cO9fEn02Wu56IWG0JInKYUyc5zyAgJ6+lLhieamW7HojDd2wi6IE/r3relRQXPpwMqX4 PbBu71Ta7/XZnoGlHHMgEqwA0Oc97vOdnzUSMmvK+lP0H2CnSXmpkXYr1atITM2u+HZdVtOwkKls CW0NUszOwMX0MQ8g4nhmABRLnP29cWD2e0Yuedlz4n2igKds0prtGBMnj/NRMYlDGMGklRrKuRwY 9YsLMhN3Si7ooVWYTbmkzBGTK3a5qC1AAPlLdVxdOOrsilOyyH2Inqx8YjO6UFFEhjvExc41LrtX leWRWayzsllojyIGnll/A95nTahw1VhPoA/55zXCBN5SZPzYkTC3eg5Ycm71LV4Z4jGa4W2dZLEq YB4OSGwMOgCRqJ38HDgFMifyLAopdBEGKlvgzmEiKdcUAjgsrhw6PiabQldrIeA+1CTquY6+uC6B SBdwUYiNUNbdk2EZ30E92p07tkQD3ZonHgMx+Lb5I3LgxTGrx0BGBFieGCYLrfbtogQjweyiY3SB 53bV8s6ogJyNtA5+QoNh4wK3zuhSmAdw68wgbcTd1aA7zS++8HQursRIPCAHn+ASbYhd/WmEW4ii /aMdXogdQCYJHja3VAtv5n5OwD5wN78D2+5IfJ4EX1LPBiSPptZhurD5G0FwxWx7tWKJmyRwehsF FQg9hV1rfCFlxw7dqQgI4UFoudoqrRglosRJQ6HJlzHwcl4llYj8LFqIY2+NkwdjAwl5aS2BOm+t JFB7kGGZ7Ee/+5LgnstqV6+09v+79ObVaOyFq/c2D8XIczg/dEvj+PfD2GObKPSwcrkY0/JrX2wR nPgO/PhPwIuZWiDerwiX7myoe/xYZgMsxJ95YuYDy11RtfuWJ9gCQzHH9qO/yyFj8YpT7jSswTXk M3pLDyXtFJaKDhdgjjuUfzv7dItek6pwqhrmCG5OwrCoQ9gqT4B2g+hzsiSc8JZWV1SXJ3JgfHTE ppt2P4OHJBUUn1yGUpWw2fYjGK0o4Ixa6JfiTcAbENghipUbMx0plI6sMmTQpjL64npjGVacT3Uj 2fTB5xOWm945fGDmxuf0Bh6AACELQ/I2cbtya4uazW2XzWTHpaTNHYN8mqcctzbk9WlwS+MRHgOj ki7/dxwgZNsZuHIV8TLVkyl1HlFXF/XZ3hBW5ATroka1RfaeQjkf40F+6Fa9LiTcRChPPAWBD6ew JmOJZjmvB42pkj4iyRugc147biaHSSBZs58ATdaw4s9m3H3l0buuB9p8a6Hz8m8PGTZY7uDk7gdN nNXXFGhU7Et8mobbwPPoGIXlAoMnL9DFUmBBTHpgAItZcOnO+2PYzygcgJQPpYj+3HKiY2bHLrnI L9WOe2UIjjcBIrUepRH4DzgtPN4us3nqSh81UkCn5piajpvxhsfPySeN64v7Jq8xhvrIN4FdsoMP 6Drzt4pc3av8lsFY86b1toIbZx1VMWClltoJMQKEmZfkkNx/V7LE3hhN8MNh1udrdKsnCP+/OuYm Pq6O4MeSpoBdeneqYX/3qy8Say4G12Vd1P7jo9oViGNSaNuSoCGtZHO3mTdrtqS4bql5bnr4Ek14 QUUeQCRJ9jRSYinOTMEZHZuwgKQGfvnmh8B13Gh+a05D/5nfEiQd3Y/vDMfGQBooB0qPrkXSGiRW Z2Pycg3KTpde+9pKYpCbn2Nl5fJH+4lZk4qVpvPO6lBaAy7F/D+fdfKiPutXJ7NqaUtRKDgI9Iwt XuEYd3LBj1ixXl+VxVs6r2cJPUwSw9CTYbf6xDCx0cndcPSF4fThcAnvly7bzS21S92D2u6XMPIe tLOtxsOM+vv6c5L7FTF9n/RRsZVxt/W7hM0omOVawgosU4KHAxkbJA0S/0+ckm2xdnQAzST3pPZS SBkE/7TyKYlZV9znJYEmqtSUXEeSb5SWpy/vkzPTwHuouupKKlglf8EIzrL4EpHLRjIy4K9psKl2 qE2MZK2XJZRJAU+qCDipBKo0zYnh6ZDq6JSTXgOaAABoc7CmTEWlkGhXlozpAIUDGuChRs0KpW3w EMRd1mQVFIL8balfA5FWN+Z8CnPgqGnZZ8L5pamthuGfd4TN35enyIGTJCFP+APzRhNfKDVD/P42 0I6E9Vqd9mxh6tG3z4E1WJqiukrWYHEKw5KDBeD680eT0niKY9GMdJRux8W1NVJlNLPvrHyOlBid NIhxtvHkzQhtDrGI4cnUxhIK2JwLwEjl2ZpJJTulknMARUBZVF2Ia5Evu2Y50PKWCdbvT+WcVJJo e9dJYGus98gm1Gu/9tUMiX4uGYL6IZh5AJFNYEfJPZ893y1cGcfYi0ruuP6pcT5egl75FQaD4305 7jvkKZfBL/fIkk8AbdPmD4kWUmlkJt1BWVC0zafQD4PX0xovfEVwRgEald5TdnUefcFLFENqnlc4 VxXonj2GzjQyD9P9L9w2bERdzfq1H8j3JNuODKa9/y+U+dJJd+I0T0QX46MezpjFGOdBwJyow3Qz WemoNLu57V0d/A1K8emm/selBiQfeHqI8QR6PAn4jGp0n2xsUOyoNtz9vj3lvpnt6sVTWGpDJXEd 0AfiHMB9+qEK1/7B+kB1Pi03y10CyxKurQV2+L8oWfhPBN7QNva4vIxzTzOd6+M1QkV4/gjjq7F+ 07/7I+QoEjFGeK6YJ3npkYc5iPsUM4PRemdGf1b5EXvRoaPQmPK9CUJW/BCbHt8Tl203Y5g25UlI UxkFx/35itwg/F4zFHpHIYpdEzJBNZVriguj8NTXl4/zmk1S6U9U4tpHLyBgGAKdrFmKVIKHQxB5 gQiS/jmCBDCaCNMiH/eqkqDvsu7bEX+fljkSuJXiEd0P1+NwCffcQoaP6qjOufEgReaUoVVmZasS XTLWR8ZtC1gJXyoaavaXyj8NaK4mriCcMfXxLaqq3KSU0eNDp28mvKgoJhHg6eULhQzHfnUN5MvL UvePbu83tJdjDB5l+gaf8c7pqDepeTHrCo2SSe92GJTYFPzVwaFOIrPMaCbzGLhxvbtqSX4+eLMe dNNAX9H0DSRi8lB5/bh6eKG916Em4gtkQK7DpxYdVYxRenwoyffgpOG5ULCUyO7hu8l+5sk1KabW 5qRhhhwT9XLQkZyfV1iv9XwvwF2mqH/sZHQxtaaDzQzArsQInz7279hnFv0KgAQDX6rx5kIc3pBg cNfwbTx/E4Fd4/r4GmN953bPCO/9n0uGRafXL4hJ5yD83q3sJ3qmTLll8I3k+V/v/hgauXfnj45g PmhuKcd2iyaATz2yAGWbCamifPsKHoX0PESuZSlZhuTxIxrkzG5ze10pJrEeC3zjs0s4W3WhfYty MDewRQuqG2ND3e1UbTCnXuXRjX9mOcgkL1QzDw+dHdNzY+yb+ELm5ZTngey47YU5GDzNPeLcarjX HK+vaz5X9irNHLKzf7J6vNdqRm2yz0h/YN+yBDYrniT2at3o7bsm3M9PQWZjXsYCuXT9Tl3SHSw+ +5KUfFcPVHkHzLD/CT1Mg6uRzVDue5/dXQxb5XCs20FkJp7kD+S+sYJxe400y5N8vY0zErpQXNC/ dBqUgQEhaK50OoGR38oZ05ecgHhMkiUDJGq6ICxlBDGmUKra2PmCcMukOfdfDHZSEcsrA9iSdorW v+RNkX2ackQs5ujoIEtY5T0V0tHKbE/DQDf49lpgdk9Gtz0tqvgNquWs1+0TxP1pKFeQR9XYTWEY /sD9EryQ8qA+QhxIqmgeHreotnvgcP+2n7aRnAOxdT73DzlFvWq+GIVhqkWbQsyYu7Ci3kZh9I3I eNeJo4O30v3xEApFED0572CEgodyxmINwKbK7FdPaqlxnOH7YA/FYeuEka1fQTgzVd16t45hGz/e 8VWaynipOK+isp6btfddBzVVTdpYpLjtE7naeMN2METkANZ3e9T7sE2Hg40+jnY0SeqtrR6Smgm5 sKavPT7j3abdmx152cMmTIkC2EnsLf4vFu03eRbD5KyQ1Z7zR3HqajYxTwJh6EK6sMzfAYGUTMUm 5pksTCEj8TPmnCz3bCKXrog14Evy2tN7AeWZKQ8oUUAoS/AfaioxaKzQz/Myehk4fPT6h4a1Nlol yyHbxciV5edQ33IJjprmOezBXnywPyXQ2dFu4ODmK6fwZDwEtbWkhYDjYXKA7k7S37X3PFDlW1mx jgvVAFdXdzDfrDjIuuGcYzWuOCWvysOxAqLYHphhhXjtatB25HQsCSgzrbplAlOmbQ2dTcEHxUtt 3BUxmnBdQw1MjyjLh2LT0zMA+wwYZFTK19EUJsSIqPrpwROxXE3/sJ+B+GFS2x6HjhHkyYNQmgZP PVNREC5Rc6XC3hjae/bYjKmzyxj3jUV9H1jGhvCkCuka+ZbwE+jKMpkK8+l+unw+YfYk2s06V7aG qoTGhHVEdQghb45uSYcoC6VsShDCx1id2RBoCUUkFC6mmccIJyh0QCimvtSJm/BcwjhCo03ipVuY t8eQ21TZFqg91Ctui7vD4aSf8NTZKXBFaGWmw9Kd3gB+C7kmZlrqht9nxoPF+jR2E6o4+XgJ54kj +zc8Peqs/Dj1Rxy8lLAWX+faSah4kj4ysw9GjpX7gqb3cY2OjyKHiz5tEg4H0eFksjIkA6jcZ/ux Lmsm01WTfm/p91ExOg8A7TJoMeJXeUaZP4RZ166x2pe2JrkY5oFWfqg2n5N4Z9UoKTnerX2SK3by kMe6/bP87uyzH3K6oMRJOpdEmuOna9gA3y2o7igQtNgPLkt+n1NWENSM5CuqZ+IwgWQ7ukn1lI+c WyhJRA5pd9PSVLOQCqljVfRZytMyc3Tb48Z696/6inj7c6aBYd7ffCnlvIpHA5RJDg+UrNhtVAs5 QiAK1a0NxUheS81yEoY4uCUEKZcAmRbZ9SkWBF81Gcl4d9jMjfWi8CPp+8gAHDiQl4PCTV8Jy46V Xe516Q6c+LecKeDT+uY67SyTsemJfycd0T94ShU6bOgzDz76V92fronRfQNy99kA+IHlEJYDs3Gs tUR5TfnsWQRuQ3McUh/VyJ0/bjY/Efo31KOJbzhVXPcErTRY3pT0y+Taxd+zbInvDPTeEnf2+yfr XeyqvJ6ngKX56WR3t+kviolplqgHCEtfDbKvy66MzsAX6d4Unpaf4NZ0H0DkgtTdSzurXscxPY6L INs1OmdQ5lX/CVg+JGT/tWo3SeRsuNRbZtDSV7DXQQMcmVw7wLY34/53MdVe8roV2AgI4guED56F jR7LqURKoVPd3d4Ws+mGYq9MoRSEM9SNuqewDQz7LHX7+0nK94AVNxrq5QWsheIbdM/2E2bTq3KF I+JXmwBvfZ/MrLJ0js2zHCyJKbO8dBezbLrjuds4h+6sRXu0JVdmqrgW3nZzMhRTbwU7RQOTQGJh qKfNC/E0zvwMi1G1JtkdwWA+MPXGQN2NDqgb19nL9CY66YdNGkf6CpBScojqw7scuT3cNa4EcMlO jHw3dpWc/2F61CM3IjJhA7Dlvo4rTQgP9S3pfpZtRLHHCREmaQLSWDXClCzyfbRUocayH/J25q/M M/CIw0n3FhCdsjQl+GPzez09HmOF7ekf55IrRU9JHWWN7ZiEBdHMT9cFe8FuwXzegYtOYr1TwoG4 WSI5TPpgHer5pcYgIQPnpo4vYQ8+MfiDk67Tu84wlpmLMumDTy4jQJTVM1IcegzcZfFvBOlExTDK dHEpPDYaFo33wfPlriW+6n5NhCgB4zEhUW5du19HbUGKW+iaeZgJunCX5lELvoLtCl+jz+BpjBkO zrxQZbgpLojDFMGaOYOzh7wTXXTM5b6b//P/eSmWCUQt2DHyVCWnuGMRdpt/ejVwfZcsXoGsmLqQ uZzDYJQzhSsqVsZ5POywiZV2ecWDfdopAb9mlFNwoDp05zpIhiQDzKYtR9LJ/qvsQguWxx9bnYKH Ozh/DkVZ8JGOdIZOS/q2TK1sxfzfNlYU1ylFc6cz8z2PLLUTFT7qjdndhxFY+jWAYvUOI8CwPJIo 1XA3d3i65UgbudfK9aNZNkAoHoX7/KqL7l+ERDAhU4W6NUI4uG3cflaPyxnRR7DZTC09raNvDjWl w1Qa+hZ6QRNsE21/4DvoQyg2OYR8/w2vHm1Vw3uJrivfzBDoJoqIVo7/HiGTMNEOcNZNUcAHDWTy yyEPgjFTvfZhwby87XkmDRXCjEhRpj3YgErWebt/C1KVDtEvbom2eB563hrE/yidJoG/J5xTxCHQ clbG+D1Xyq40S93BXewY3NXVtz/7A6Yr6vHXUtgqL1CgBRARmxXTC9R5udOY6h+hR1GWvKsctHK/ 6XBUOJdiPSziWHfO7RH+jxY027E5pQVgoySwaylidCBT+q0PJfiWKlo4FQ29aNXvzB/bfFCii3N/ IRQKrp2y0qPqjRiswOQtQUw6NbAmMNL0ksDsrcX7/GtqPU7sgs8z5MI7EGliSdYEC+7aDKAbeWC9 3Aryg2Q2IV4Nyhjupbe8OAQCXPBp6XG20z5g5Y0Y7WhWh4X5lmBXG5PipElTKA5ZAC4wOCvv5Die +KvORZ9DVikeHo0boa9QjpIGQGXC2EHD8l/3fpNUeVlvdblHheU/iaZ5vVxypp4llL6bQbmTh9zJ yraW/sq/CuTDom4sha0jmNH2ts1JofX7xMOE5TdD51PcFhPh5j3b6cPX4Y7sEVmL/95PIMeVXTYE +o949WHdThdX5vHazRShjaxcV4MljwuSpNz7aq3IDTWC1wSh2+RSI7cyF5M5+T9FkSC1aS43nHMo cAGAM0vgJ5v3RDLFoIxsW3epruQIabOYX0Z2DmaEKGUTSVOg8dGVTwOGYX5W3K3RNiJGIlPw+WEx S6XneCVRMG66R76UVJN7yVv4KHipuGAW7hnZjb+9KOy0wrNRlwRZxfnoQX1PuAtiHGkxilTLFSFw Z7mjX55xN7MZ6PSQ9sVoIIW7pX2rzwsDcUPqY8QTnqqSE4v7KWhhB/2UNZjbmQ7fASsU/YBCZjmR jXIYlt9Hd8w8c9SyEM6fvrSLYyjvhPc3fVl6XspsCKcKIhjiIIDP4D8Rg/L0OxkeX3iqraVmg2vE d6a3dkGlkkAa2OsIcNvmmkpqJSwhHMNAUm5283NO6Wszeum7ByW44In/jYuIPN0SjczyOQV7yBbM IlGXpegD7BEKNKyZTAqeMGVRPO89jfIN/T7blvoXP/5R9Y48L2mgiDumZf6eqiHeqeFvsbftFRPT bF6l8HilqrLNNqEkqhnrqzGI/8b5ys+01BVlZpGfV+mFMa+5AbOfFyP3NPwiAmpOLx3kNlbafK+o 7/CnYRBM4R6uIMKYezACn5nyUtyaG48/ettuMjewle3w0s/UuFOcPZNy1D81lnErVYqkb9yLvB8y XZcgiaQ6P0HIMOpWzt2yMz7M/coUhcTq6jeK05EOQqJ7McL2Yw0cMp4qOO+Zp/a2FWTg2FHsaNkG fokhaqDEpE8rppOP5FHgALZ18lPKS3F2Wg6L+1WlXWLM/WN0Nnq8me4zbAxj5fGXHgBFgfuxEIm9 V2hE6ODmPJ5gQwdRtZTDVmoYxg6cjcNnP9jStV7GRc6MStrAcNLBX63I2avKWoCEHrjzCYC2Wmj2 4PnjNTihuK0Q5OmTpzhJ4gJRAEHJouxB74/1MDSzA5j7Pb1UTRdylUsH/Tmp9zLPMWVd8gKkGXb7 hCagVgn2hd0M2uZpgfJpKi5w/cLhiDVCnEdsBnbBR4MOLYoBFJBUuKIJ2niYRXu5fh9PRgg8LwRJ TkrywLcBEyyK4KpN515sU9UG1EbLW0QBPuuJKuKaI+ozoG2X/vI0vguOT65jkjGJcvXYcJKyT97u WjKKRSjJ9KGFt6PyIeBovtEnfvqYW6wWlCvAkGvn6GgqZT0OsBFn9sh0RoLxAzPQrXUeFrR9RRzB Q0NzvkOFJKtPpBJ7PD2VshTqTlbW0cj7awQ7DGD0CfhEHXnJ0+tLkiemhhmtBeEDs/MXz1+sOaJ+ m8RgNlD8bnOEqe5s2L3fc49wQiQ2BkLTxVSQUQPuWQge+8qfSVAtABHJ913OCKu0q46YBdbwWvf0 7A1QTbyw6FlXR2uaZVFLRM6y+mylWbAZtvbUjdn6df7dQek02UhSp0kMI3UzZ6QkVPBSuk0jUrrT 3/KxdKzyguikpY6c4zskiYh9L2ibHoU8A0cw7kWe9zu5IlT5FZWy96iwmkoax4Qga9Lju9fEPmEj xpIjRI0rfgYEvs4fJyTQ9jnvsS+Po8gRHPaeuqlmxzpy0CBmdIT+nWgI4U1Aj3aReRSYNhj6ev5J Qd6m0N++MH/NLYRmZ+C43ws67iPfY6nQNyUyXQ4+0DU2GJD+jFkva5DMCb9gs2Uj+4VVrdk7ePiK izkcbdyiEeEhcAv6ToLKaaGqcl+ZaeJrNTZbQcD1tCwRzZSL3a+y6bXhm9Pe8erI5jzMlHb/QEtq tQPsIm8lPcoBfGc1ZIMvq45nVZCmPgR2SaYzoYdWcMTuvtu62On40JEhuQU+F41slW/yV/OijNny 2b+CTTOh5PU79BCaCgVxrauYqj95A4Ies/1dd7oL4dNMLfSGsft192Y+3QvapvDZDX7qNm/u9JJn flhr72nMNlxK9kCy7G/K3JjrhabQR5TFsEPuQ4TXpxTyuiTzYPPeZPEjonwpiJOOa5NIADyl7BFe Jbs0M3DhA6+zHnptdFu6iE8CH3DYgQZDlz+1NywFhNT4KGOywhFxzrJSHEqKhspCAyA4PnwRGtJT oqImwMYhwLLD81xjzkCwiGxq2yhvKBb65zOVYP0hEUVTBHo+nwGuv7bkSJ9hNrRuTgoELYx/zBvj NeHqj6Vj2UM+ByX51vIaL8R7AGoxM86lX3+v2FgTSZtBdG5jSh6Ls+zqvSvzktw9Jel9vPHAILzh 5yQ0H+Mlvp6sANRbTUh30RrKdwnLZVvWo2rhszP3x7Eg2M9dxzoLNQe5501GuZAUibEky8C6EHIx 05zdQ5VT5Nr1Qm68D9va7fN2IoEmxgknnei3VM9+po3q2XlUou0kyrh8Uql4GboBnETiBoJDxh/u 4GrQDC4W/lfgxUAoTGubnonvVJDATyFMCdXBdcitoqN2hT5hJv0tFigsiF3tkcCtFmKviejIbm/8 j8TUPGL2ClP3dGrZimCSUBdg95LrJCBtaeU6lxIq4oUBudipvYvhaE/SrbKtKA0OSBU/vUs4SaDm oleqz7UY6WuV5kVOtmfJmP6QplbAePgHrV3eY5pakXc9Cdl+9jvC2KWWccNl/ayNhkChV9NR9+JG ZzR27whFfhfEN8ubS2DDnMzJwOWHp7u1MRoagwWlaBSHqUpw5r+buYqLoQD1IPq2sn1PURF2fOhR 9GKRULiUyJS2IjsBrKYnI+ilB5Jz55aKw60fRR4gq8DxRo0uMoKsMhFOF4rtq+Y3G1aRpUktaNMv BbaCPx4mEkQ4BAxpBkn4hUmGPpXBbgRQS0a0lwvfBWvxhotLL0klXbbIOaQL4mXpC/3nvse0O544 PVpMmANYmbF7Z0CtKJBqt6UBQm0xHQ4pF3kWSSKuhVA4ofawDXumtukPJfx4j3a8nEOMKOQLIeiF fk1cL/uxu85W+Qb6tBkL3r4EMMnnwdmZ9Mmxiydg8y19CazJ97Srp2xWL8PUnyvo7j6/C3Xr4L/G Ir3mmZavAtx2kDsm6TB+x6w5gQb7+nJExFUVPOzHj9Gjuc4nkNZJYvxhoqMda/0Z5s2Zsgbr/Cfn UnqxJAV1WIGfqLj+ydODiO/WL8Z9X55aJQDCBRVoPafgyiXXaqylN+mC6L6u+WbqPBsuoW2CQrwr GQDFCxLc7/a165QV6lDuWuIBUnBZFDg25zw0eQ6sIHxxS4anHpU0+gTnO+cTUgUGbMcTWz38uN2a BUQlQwCxmJ/hTaPiatTXErCniTLxEmgBeJT3H9px1td8IXJhl4W6w9HI5D/gk4zg7yCYf7somGqJ lz61zUtY390MTte40JmzHjeEakQZujAcQ+nL8dUmIojhbgfxoj/SMY+30PGk6PwadoJ/cNW+paRh 9ztujLKKTf/VPzoLhpNm/mvtiNf2HmId/vS2hBuRfNBeMrmudTZzV1A68TZYcNSIICCBPU9i8UjP N1is9YOlMAZD+0gjHA5g3c8hQcMGra+mPlNJoHH4uA2dRetzf/BfekzW1gj2r1Bjo+sbGyGRfsK9 vmmd6R8gHO9V+109NJnYzF7OoYc9h6cCZ2C6kE8LkGlyL9K40ENItOH6TaYboLONhwdzDL4NxAdM 2je4LxURjxkwc38tog+jr5+HrMytZqcMI/yPbYIWWh94XZ+66khBPBzDIEsAhBeSfNhZYpoL0dso rJWa24hSOoDBhv4+X6qm8KYxj+6fIH00O2UGLxcmcjU2NR6nOuRD+fqMjBp5Fzzw2s6VlqA+HieK pxvenRlk748pZwRl2/u8bOY9s49GvJPr0aI9B0+owhe4erC7hQvctrTLOokbmBYYOGrBneqiLo3z ct/NY/AD6vtAiNc5K6iXhvIJYv6GVIeC0qH2xBfJPeOBXJzuaOFDmb8FLWva6DPJqYU4PQ2AN1WT eWQ40ZxOjEe2qx+bb4S8TOlAmkUiDKABzcZT5f6SpoL6nVfrCQOvZVnmfH1/37ge2MGvbsCCmWkc qd5gu2fMFdZWWn1nAVjtwKnLulJBfdzh187RU72IOVD3wT2h0SA57AEFPm2YgwzaKifNS4K2axHL tkhDiY1rpz7im/qM/i8l4/78BJvMJBKMjLbV4Cy/R0MheTXycJgkbd2P6Th4C+smjzs6d6ZkMIDV oeLnOjNqV2EqKmjM+qUMXqWgrBZpZF5ET8hTdb6Tn481SDAqNBYMS7JbdkQs6nYazuZEQgRQXx4E 3qydIj/A2xygFyOFj5jf++BchvAAv77YAzwuuvTY5J4wm2wUZ7TwhjWf8p+3z5jw4WA39YWdojdE kiAVRCA/0Yprj2DJ2+3yBVy2W097mazTtrSmN1eEpoF2Jx499zaR8YjAlhnpo1RiW79y80jhqUA0 jqCBWrWzHGrCpTW2uad+WC3sIm1ceZi2ox+E9//6/pcj0O9t5JnCRpeXKPGFP1w0A1DaheU0Q9CT 8fcGNt6pq7IpohfpnNjFYP41cShYL0xf10YIehan8CW+F0W9TqE8pUx93MHsuiEbzESUHoop0KYl iGFAxrbRKP/CefJtjxe6UXR7QIzzWq25Zw7f/kQ2cVvv31WMwSdW8DBYZgE6TN6DiMRlsGWQX+GP w6SyS0X0wIeuv0ZP3yddKiJs4/8ILyMQUF09q/9Zo2y5MCtaiY5yTd8T1zRuBULxfbgPLX0BbY9f U/0ZkF2S51KY12RPihS+TEPN+hhGdA6HKg/5efGn7BJ2PGA/9tZ0cWjWL2o6ZLlqPU563C7DY4Pd 45Y0LhvWpudiiU3GFiGv7yJCmUlyTA9ljbwY+nTXo+MCcHtH8EJuD/f3mWSAi+QAia9E7nKGFN0y 6UPNT/w9APJj0GHtEBIBhTthbeRpP8KEFdawyGnQdxhc7JhvItYsN/AxdkDX4qGJWs6pa95p6fNO hL9XurP0V7xOxAJb/4y1gkaZt3GT/FtqlGVx78S2H5StTJYl+7Ct0RDzznxG6ZOuNvqiUBWDakhX KUVAtol5ACEkkOWmieH7ztAe3bP2hbNuAMR2LOGfcae+9LBY6JCTW70P8EUj2FqlEdkfAS43rfyW wgXJsMTiloPn9zNMA5aim0L+73qjfy1IB0S/X6PgdTHaY3sJTHlB/BPlAfcq1KcoyHDAKPO4oQAe oHgrN+i3nLb9tQhK0JOaBYmDdoiKnK6aoCQIher9lwHuVIlElJSSirZ2AZ3mlbYzuWToujyb4SS8 nn7KofAD9HtUYIg4+f8KECPxmfoZ8PQp4nm+czDanUFYbB/X0HPkhJro79InNmfT1l8QTdKfMn7k YNJpwVJThpcpIiyJF0dlv0GfTjmZQNszP4sakNN+UZ8/m7eeGNnb92HjXzk7V5B5ztGw8CPBHOvV sC3XOQz1MKegma/5GNiNXP3x6EnfG9bKw+5N/5/dwSRWEBth6OFP495nlDf8c1yEGqOLq1Op4sUe JudnR53g9KsnuTLRhQajNMQUfvZI0LTpIoDzZtU5lQg6zzZwBcJJ6ikKZR5spXD+XcT0Y1k8J8d/ OTSt8GR6bwKE2xkdJGfvS5VINZ45o0mH59+5owmpCbfFVFcJ0kWvZseEsOO2oI+fXtmMHAjna5qX nN6spZ1Aa+FuVRFmJuv6KlP6XzdgnP3uJ+7bCRaPoE3Hre38g4lkT0jQ9Iw/caKm2W9wYT4jLsvF yQ5aM1ElUPes+8gBzZ2N760ztzp+/NaG7B2xNK53pvB/QwjQzfh/xKWA9LcEHqiP7zawS4g0FWb2 lcr1C87NQU5kHn3OkZmAW85ERKuQC4XO9ggqgcu0L2HYXKc885Prae4vyJUqv/2WFbcyRz+vyDsH fBKfl7UY32JwcwSAjdmS5Rv5FtVVt0mcYKRT5ggkfMM08wOMnJRVgYjEVnd2Rx2PYFTMw37PSOoM NX3jyvEXQCVWUhAPeBM2xDXMdEwx+M7TY4nahCjq5ikK++nHzWd1qGPIU/npW9/79IcvuTgYQIQk qRvjkBP//e7pcVtNuhZRvG8DccSfSSfTYCs4qLh5Hl507Pw0L5kkYjpEGfqBTjITW4bDEDxnJ3Qc +ZG5xM/wcLwONAc9pB2CqeKSqSDA5Q6xjt0fkeuSbHIIeu++v2w65zMa4KqGGuHb5/gk79dacI3/ 9kfUIB8KX3wmmPVFlKACVQTmhMhUxifcQ9yy/Q8kUcvVwgtnS0njaTP3Nrcl4AAFpASNIG4xllHV Kt098xIp5BOOJKEnjAVrA4I60R4td40sZK38GoPRZVxEKRbEjD5bnqlStOauBe8FmfHe3vrt3pAk SKkbhZVi35Zvkh31h2KDQfXrbzInSTIBXdUAezlaDkkRRDYdbC6C5Qym5eFJqzZf12fWyOHcKCOk /lIyRXoH63PRb3/szeVYsdM85D/4LOIVh0/k1MUOJW/UKRtBCEzlK8oEkyo8qG4BG3/b3GL5Ffeg Wj3QVp9AP39RHDPk9up5jwK6vEPwk4HmfNfUwAB0qZHM0nlor6KH1t1ZLEr+/S2Ir5YmB7poeFFH DmUwfY1/YqVo+jMxXsEWE13ZoAEMzPUipCcYveV75qKXAX12DX6x+Zg8iwffgq9vekqd0vxQWLjC Arobd80araCjsU/MfLbhzG37xxvqH8H8YHXHA19aOW6aq0OIVckNEI6vHYde5VDCVxHpDPgofM/S Pi3/QKUrVYOEPYCPUfz25PC5JKvpSDtdxBOEu/n2w/6/D4+BhZeGd5nCcPyOkghP16XRV/cI/ReL 6O0nS7kGs6M0wTRXJ6R2DeSt/ikH1kzVJm29UiH1EgUmiTmt4QYDv/10MqiwypB9nOr3PcdlHd9v Yz4NNu5jK+8GNptt/I6CsKdZJUifDpNAU8buFSrxPJxq+Ln9CnEFmKHGQOrTQENXauv0TAPSrdkw G9uHya56Lc2wVFskHB2ttQBt/suZTGsZ51aECILywYF5GMEAc9ZEUE4walxJxao6KbVqxGpCKZhA E4nb7d6uMatmK2cdC+OkvW44vDVvYa3dNDmFSqptTAvPRe1lbyAknu2r7kHUcrmLbUHdQbT6Z2cC 7G+zGTx4MHZF9XlGfr538qzXPjkoI/MJW2Ih1R30ZUF8v3JxuxudqWAaNoevDVIxQL9BGRwLYFD9 HWLNPCLjFxNzuC7QrXwLC7MlUVeMhy2Tkbzci17ea0UwKTmUS8NonO1+qix37DnDruGETAjfk4Ru +eFtv26Mm2T8bmxm9DG1cqidPmrGTuiDr/bCfEtKNy9MO4XcL+4ovRZZ9RH6+VpWy8FI4o56tKyb 2Jjl04g5LBMev4rdxbUabanMx79eWwUTnba//KuQStR6I6TxkQ5VORACp5knOfshJtPgVvSdLyBS F2JIdx9OvJAumMg7zgz8PgJjZrAT3M/Bo4nPFccmwiKqZ516XiG/o3SQbFKW8Vvbgu9Cf1j/Zni2 zaPNrPwPLyC+dsXZIkxDAb+lBJ5BM04j9EJSUdd4tb0DmGbyFh4If2Ws5II6IO056Eu7fJeH9ARr PLx4QIMdZ2ZqOD1ojp8O/ajc0/cZHn7K+gxmp5CnfTupYW/hFC5JLdzvYsS0XEuCK19/reRw74JK aJZT6d8unvqnVp2W8Yc+J+wSXUgiu2osKEIXGwsg3d4Au2mu1fqUq7fWp5lTsITGtkrStauxU8/M QOaXe6NHhuINiI7YO2cYb2/ImB40O/5aL14PlqYVre4e4Vo8SGYHmuNe0vIbo7no/4FKdTw1SmGM 9yz4QSaLe2qBFky4wOtRU2lpiW79dgrjr+UAybFIV0S3atlC/FCXCaS391N3WZwdtR3yJMFTklJL U/N6F7Ox9FlHl4JkRZP43XlNnHCuHG7TcR7ExMjiqRdNCX1EaR8xOER2soaRIbsdzzObgXIfW5gX 6ECka0rDIGPKrzkIfnGR5aE21kd+Qa95WkJfW9NFo8KHoIrAMeMiSc+j/Tbfors04KdD3n8U5fXD HEwNWi22yhJxST8Cg4yP6gnvXB33EHgJbb5kZXXRXCsukkNFX8axdPXTus1K4yb0jZOaCaDoMSr7 y6SAZj6nm3dbe5iCMXsnGzBDFs6e2Grnpxwp9qicN2QFbdNT5AWDJUUUe267FbDvFAX3O4Yi6kp9 t0/tY05kzmFIAwpHxshMezR6J4EywaYFL3QHaN0NJu4Qul89oUWPS+vP6Bzvsty1Lm5Tbs97YAuZ 5FTfbi6o5ybj5X9z9rDMct/lHFq3dFsE1ER3mBjwqyabwj9UVCt582P+1IMlLdRI0130l9mO8ah2 ycHyEB8CCd71pzIhWqu+N61P68Gg6MGIsIN93KbXFTGLOZvq9fLHdN81D3quOyNh0tGy2UHT/iqW IJkl65gg8qwt0FK2wfvjD0fyN4Ba/2lUWEePZl1hbsFh77RHCOIAwk6SkDo1LvqjWgs5lBy+uoTd bBWkrhHrNe4C2rrNHEhphpsZNHEbwx4uhJtZRPnekDyKjKvEhjHWQcWiecUcQLpQ8O3hVjd4GnMV pVEzLc4XEr7p4MwnnQBrUWqcJgFm4U+FXKvFENi6FTDa7TOcsehOIYxsW5+82S5BIPyRsH9zpaAz UC1n7rYTvj2s2b8SQiwQzIWPrYu/k7ANcLfrgTZpkz0RnN1Ppa8J23yBMBz8kg+ux6YBMPw+/+9T rLQswvB12VeWwlWozc0LwVUUDsszWw9cAuMryKhAy6iOSElTJwNsiJGHcMoyllmWYwgxeBwvvjGf H00K38DK+ZSaImElhMPJ9rPM2UwUITBr9bEsJgkoLxJPu6Bw2KCNlz9N1Afe2BVptygftUyghWkp 4U3SE/2JsgvKQb/IZFM6oLMaK5sDHavzKie7dmP2hi/uXN3u4zslOCsA9ysuX4AFV2/I4JHQS7Mg 5vEySNAH+TQ4+iEA/sgqydusjcKy5KiZJYsnHGvvcCS8G7VtMtlKeHIFsXt2JsBiEs0ca7oRZSn7 brDIyesFg7FWZoSVbNEYBakoaj57DeNClsevXc6mHMe4djTvEXGHRNe1uMbtcIyItJfu08JA+xeV 1vO/RUa/NH9eyD1UtXpSzZ/jnp0s8SrmPpweqZ8zpAWkKAng1X+2k6HUbd90Wj1xC95xb1MKKAqC yjkVhXwi0h1UYjyJ/PE/QuzHOdicCFGeBMU26CKbfvzrhXpTlz8TnyjHWs/+TQtOXwE1mhyRd+GB uza+gGjl4wFzXK32mfglwISWNGTVBX4GW4YyxjvOB9Z+WzYSWl0DiBrZZpockOVhoMxI/xgbxh/9 qq+DXKdHK5iLZTro0euu288Cg87Gq4oD/dFa8mjKZ5y3opj2I4SGamEn+pASxU9TDdK0Sv/oGQpU MyGw9gAS2Aibo7JMo/SwvUnZoMba/MQkFONHuOu2eZmXBgIzj5Xnx0e9FNbal1cutiOXjkv51egU ubO86Q9UNWPfoIfZNbT+s/0gOuVIlC+PJVeQsXtK6JOH5wEMoruB8YlPgLTfc3q5cLH8l4S5cZKB 1IxmEMnpVpb/726auTlvwVr5nOvcoOU1iTE9HPtEwR/kjcctT6EeskmO8OlI1myy3vZFLmV1IaD0 6yL7Z4pDZXr4d3vgJ+IV4Lg4S3Rg6tELfdnm8FwBQ5PfZZH5PYLYaZ3tYlgbXvjMjNFItjeKI+S4 hLyJj+3OyLRo9hEHalZ5bMwsPEXaNl8MHy07smDzXMzw71X1dK2ncENKmCjpRNSFkg1QGXlDSUE6 Lc0SA3fRGud4iojronz9g1jU5H4tSfJTQ7HT0sVTXgrqZOdC5AGN+ac8YwXjWYr42qMpv3tXDw2O V/8HhZC4R12RZv77N1CGPjLL7I9gonYHl1gz1U4t++x06d6C2eRmMJ4ckBiy9wBjLHEZsbHNHqox /zjwEVUB+r+FiuCbjUw2gOgLVNKvri1gV10qdWx3QYXdGCTx20NWDmWhCHdfP/YwQ6+8ceEyI7xl daVmU2jjyX5iIH/5dJpmLPPlyRC03FYnQRn5T0ziWDhqvCnvG7PHNwiFZTLvgRgyqXiAntBAorP2 F29FFAYFec37A9m0Uma0crSotBwZepJAchdqrVfKkOZkdgTJTNLGH4Hn5NDdQqVjaC6GDlNbOzVR mLg/WrW3tna3oNTxgO8ROyl6wMb7QE95v0u06UgG1fKGSFEOuMMRNgUOXEtSSfHz51mayarc8bvc 0JVT2xWb31zTwxNRl11DgkCLPQL11setffNwFsY5pNSVbLEw4QVLOyY7PGIsj+LEXxDTovhmf5cK oYFF0UCYd5kLYqdggus2ocCN7we2nZ/rL7OokE1QWVcZTwgGf5nAlxAZfNeF09JSUBDcUWEDim7S jXaIj2dN8S5GNb0ujCbh5ex1EzLAL4IQUQlrZ5vlTtjpQuZcntrHJZFMxxLNIC1t4rZa23OIevIf V4aOl7uJo615TankEhO/e6vuKCt0IYXcc6I4Aw/LwfNc0GC1cVIkE0nsj8nX0577HJc1tFPZUCnJ 1T8/zDZ1govPfFBAtEjurCaYvVx53ic8jwYtC5Q9VHaUeId652Nbd86wks1U2eNVjiwVrVOigDnc a0WlrxB8EapdiMzP9e43fj9/G5By0chyo6FDKZDNNrJpzffeU2pQuFjGk6UCX9hRYXaLnuAwqCd+ NRI/8N7DTLlOoupWB6RdVzBto3EfM89VKgVTgQIcDGwx8+2G8BuA6sLzP3i+p5kdV6Zc1sp+OK98 f+Wx+j1Nj+8q4+ViwtvScRDmecRNzVIZuvSpVq7H8ImRBF8oHIstqixReAoa2rEtpC7eCLlvM6yJ 8ftDvu8kJWJkvwoIdo/uiWYvPYJadqBgtgq9pAIWvkcMTyx50ic1wQVKWif8KfPHHt9xOh47LBsg OIVxj+XXQAy8YirFc29LKXn84e5meoFk4YKYgrj5YSzmYs8LoLrNpi3++GU6PoCmioEw1x5doX7m BWEnpBuJkkZBpwIoNkLfCwaV4It4p/KDPCOwW1WharyAn4nr4S2snIF7wTwmhcxzLk5h0X6TO+dG 659Dixnjondx8qR9ozLImPlOpzpJEAI4uhTV8y4KtA1LIb6r0Y2/qX8SDCVkCUVvqsqlLQYQVC+j +qS7s1jezjUPboA/88nDB9vBVqLnqn9U5aNWFiWNyeF5/ls0igxmA06xIry+QnnPobNW9bk3aJck Rao23DVSL+8zSOtiDNvvcNbHIAjsqVfDr455xQQayxUru1paRLOCN0ndRI0Y5VJCvaDsuaWhC901 CJRJ8XDeIwKIWf143mwJDSzz3UURXSxtWa7DwxpdXOn7Q6K9J76qesXOlBqaIIFdVILGdQOvFF2E hknA/zMr9JVm0GMzMEAbnOm1S3bSWX1jlblOyZs9ZdLiPvS1AxVJwJO9sJ8G82zzuOfmOlkIaOD5 Sx4E/GhalLVyhgC9TeYiT3Q1oGuqW2pF8pAhr/aanHAv73kNk5vUufqzXsfD4b8Xrqp2q9zpSbEP VW2whvcgaZk7FMz8KVP9TPU6w4fCscCDLYXrCDlH5dYxOUmqk5zULnqWjZzYYBrSxBOxPlW/AqpG U1vFwAm8PjbD50xBhCqyJb4bowMBgY6efqJPzBGONfLXhBbaURMH0eHCICs+R1WfJCoQ5ptXsVgg X7Ov1j53Wet8MxpRwEn7eu6TvvRSpCmpZDV1rz3YCLNuSgEHmSLTB7I61B1LqocsQrmA1E3P+XFn K2gPP6aoXwvFaZcC2rBbI5p8VPWX2Xilv00ItUflcmuqd2v+gNrqGfi9aGxF11P68dKYkM+9DHFW K4eS5mhiDXcsDi8ejBQeFQ8WkIYk+41lLIf2dt3ngx9joVb87CHi22mgryKluyOms71S74sZDT7I 3+ocl2EI1G/jPV4I7D80F1H6qsOKRnjUf6A4lMfDCOUcjhHW0jcc0ETjsST11d4PULoudK2MAZqo P6fcOiye2QtbDKSBMLVf5ilxn/pMaJRh4UlTM0fe4OMJHa3kzww29UtHC7kcEKAxv43+aLNtzImr J9Qo0ot78chBU4qZmyRA3CglEmG6RDij1MVKYLD9jXYnBYihyb58spyBr5okKapc18GeCrMTNo6h vPCBwenRBcH7mRHfCrdYyya0oJG53ngCarzpNgaIAgAL6zbdHwwgfh62lJOuyHj+pcjwYOfDr1o3 4WnjwTZaVYd4sW+GkUkY/MoLOeGINY3qCddj9G9OJafLAZk2El/EXYanmwAHkGk+Q8J/dtbh0K1m 3A+G16mkh9CGN9MAS6HGoxt7cV6loSGsfbenL1au8fAU9hAw3zq/fh24/eSdrHi/nMobuO9ILcu5 SOYIfM454in/eeGtA+7/Z8ec+CSwiA4xFztLsbIZS/mMdwJ9w1H+fF4rtF+qldO3/1SGHPgfs6Vw iVBAi6bdXIYRI6pDdR5qTarv6VVu2sndH05TSLl+QP9ff4JhvmhpwxMNzP/TGz2qs1WNdQP8l6LW CckY3oJZLseUX7MiTCt2zhkwP+bVk99em92Cy47pnkuKYsLEMjmvO7VN3oVYeLIiVBZuVB1BQPQb sq0ormwyq0dsdiJl9bZ3HnRPNBeDPLMdHxdrLFs7bfRPuSRiG/OnesI85cnk4BmWTKWhh2jI6a/Z utfmWAA7WwHI+6okHbOR7CnWIBY4Fe6biyG20wN6Mc5I6iLQu1PUOqtwCePiHxj1cgKQlav47ot/ eSz3Wx/7pW7XODYUjcO7aVdWQbFkPnYXciLGbeAEAohr56in7vdMtNuoQbJ8jSTVc5ikKgMCPgoi QdQ7F/gVS9K9wXh2Yq6Bz/5Yu7WBXyUH7VE55BsanWwpMiEfppqpTM7Yd6UJd0QqHjMKOqGeSE3i XPw45QN3tiyUIG61PDh+0R+FUjVgX1LBzKd9IHmtXJYHTKqop9e/MTAw09Rt2+xlxgLLYgP3mTFQ eHOXYf1xzFlv1YtUSpJjj7EafrMP0LkB6z6YOxhPSWsSlRbnN25mgQb280XFcJST4f9/k62L+sbw kA++6ONO4skILlko16XPkNtKi0ZP97AcbiouycEEEXyCArsCiEg0SlXH2s/OELwfUTpjhjmvJ+uX tGyLRSEZfEfObp8t+PAYhnWGoEVBP3DCSis1hcPVO1yd3S2+tV4ydND51b3cziaetWfsivOlUNgg b6F9nyYnFCPnB0WMGpDPEML08Ge1AQfSLPTKMCYONZyhTe3oXPqSHxLUQvdiZb81g+ExxU8xOk+s TqNpz2jZ0wuiU4otn73gDESXpjRhEVSV3REyk/eYfoNjLoKGBNBpVWPexBKOCFUyE1IB+1qjgFQU rMBxG3ipKQP2Tn6wBErNk0wXuMkS51N4XJ9AKvQjc3cHXMXenV35UnwZc32+/MLdyTWk+4cGyu5e gPpPUx9n2CJ9gRaW9EpiKnqZjXttxcStLq8EDj04scuR8V++swZUjjznsiKvlN1SI3GSy/XTCaRh Ixitf4I9gNxNqoDvC5wsCBRIUbmJe9cHlUZbQTgUFepMSLdeWLX1QPaJ5w9QUmCY4SanoT56YJl0 v3O4lkreLc8Mp4kcVoLTe8/wJeYfOqd7UijBmdROVWz+EMda1Xi31dgjm1Euov7MFYHwFl73W5u7 619lGxvsWHInQZsxSlDXtoYdKaDj+Fyf8CZQFxfT5mIHp7wLJzKcZqk8yHp0agIN6rlXBnCdGz+x ZIH27Bhg7Yh7Q5pRHp/Ymxk05F+gV9LucbzzZhxwagGaLtolY4hC4XQ3fgzyY/0M/NSl56iSGXV1 v0yGJoy6733D6cqAGq6SFjYq56UkNc/vxTJGx4H1C0vSdBW1X10CUPgZF+BUJFGFBUyiSuvpRx3n /2crN987wo6e8VlFGHYdkJaTK/Gj2U8I6VQaR7PdVN3ThP5KD3I9OBGi7VghhGA/EwuqADic+X46 swLUuW3CykzKKzrnv6iiolzKfAFWGnIj79wP7AffZkoh4raOTIrkyoa+SNaWWVPga8vUacj37ic/ Ri+o43O38oDjhoVyElkbi0pXjdkn+geNO6bNGik+gL+hkozgUUx5c1V3JA2aW4DhrZXgM5tB7/Ru LsFf7T4usieHbdyg3B+fZ2N38I8yLCU/dd5XT/tl16XhImyP36xoZrxK+FTThl5f8pg1RRM/Batd Sni0u88I03Rl7vQGSL3CFyex9vPxwnatIg51Ad0fXyOogUkF80WenQ29jz4X//kZwLKQgww0BrNr A8+4IkyhLyzzxpbKXPY8UXBvnxg15KX0DVU54o2p3j8XyUmUNKzHukGzaEGPjseYK4Aay6eJw4KY uK8jrSJEw9vTC/WOQxtWPiZLScVw0y2DpPKR3LlvmUU7FIyQND/0VFDpQuXqbHRrrkPcPUhfEIfq AyImd50AV16Q7rS/d+vXSZe43SziNXXX7r4bqFFWeNspbBsZgZ5Z5rcFO8Vh2PYEmnUxvJ7xPXDQ ulTTg0OJQzE7yfyxOK9JXv8OkSrDhbG/bf2rGG06PEimYernfb0qd9uGUjHOIz1gYbWHcJobbbg/ o1LwjvJgYvMYYpdpFPHgq1rGE4qhYjGowhXhA8uXchUsae1/pyrflwIdFco7NaIHee/hHLQfULH2 ocSYEQDAq/J7KrOPPbVXyCMelilUmJ/rxqewnBf5/G1LeJzJMmhr1EUU7dJ6o+9lRn0JdfJ+/65D kxNDp7uyZ/+TYFy5z1JhPCIBIAqCGVI8f22U0qyCGnXQXe/OY3UtzQkbLHvKUf0LsdPXeammHrR+ HBum64DaV3eV/SAraotrz3J2fE01UAgVao41l3iM7h3Osx55B0fdU4FZbliuRGQALIUaO4g6MNO+ QQsZahjFodUS5eWUxzA29ebteuLa7epbKBz8vg8F+iZa5Go2mqZzE9RdCwUxHU5lIdtHdZOCxdR2 fHhTSQPrAj/4qJ9jxdD6V7cAe3vUKbmVKfS3lWFY6DLltX7uC+uhzn45AAqOpSa+z1I1Fpib/hxO RXbNGkgX+NPvq3nN0+2jZt8jZbIhZvgCDkFKt/Hh0qMiOeWHu7d6n3lVP7iaiDRmmmuplGWJGIF/ OeYcxHbKofAfuoUQ7Nq/NLMCIhytMJPWV1CNHw2R00FN92Z26VDpTs1/k4izr1xbGfKBEpk/EG2v 5z0ueYXoKlBJma4LYnyVgIpHTYLs5oG/RJF0jKf7qeqcBu6Isc9NgN4fBs2yk9MQljRaiEV7OCiq ZyN08PdJPuJHrsrFkJeGpBpv4dq1gKfy5Ye0bagd/1U5en/FugFmTsteKgRJ8gCU6BwmHVFxlUdZ MDJawPAC3xF03ogk3f6BSGW6R+EukneylDh6IQMQXLACqxMEaqjU3sPdrEBRqll0hLzB1BLywm6n nBld4ybsjJoKsiIUZQgsQawtpaJM8bCeuE7QYzxuA4xUJhaLX+chLRQQ3xpnRXhTtJkzfa3WnRTA 9zhB32ZMVu4DFv5CdhVXabDWYrztIJk1pT/AClQayalNSDG0Yflnh0ZZ7TdFHe9N7nJXwZabhULO hMXmyuZ07AX+uGnP56NpKUwirNWwW3c0NY7uVIhKvLUSVP9RQd12JgjozPpu3D4z52L0GSds5f/4 95X7CUnoQRad6XrBzdBFzm+Hj+7BmvldgeA9mqFpDiTHdLUFKi83tRxfLGfZzWU1KHzQmwwKboP8 MEi8y63u39H1ksFPEDoN3nXBKtJoKV35/SVTqtPpJbpFCMh/vILkZiAVheGGmE0GzxRrdQ+H/Fe+ BjAVCAbrqVi2+tOjIUZN4K7A53VFk6aAynlv+s965l+Lk32ltbz0/1GgnuC3S4vRVdJJFPddmG9u qRhBjuK56rN3UnY0ctPErPfRz8qG5QEq+At6g51cY0DqwqRp0NCQ+j0gv1yTTEeCXoKNNJ7ZQF5L VlLlCyna+QcjxfXMwOpyaiHtG7R7TnMxK1jR7rD3BD7HFFS1hjBujNL2AoRJwbb45E89FI/ufxVx fMWT8YEyTGsOnGMSy4vkVdymc1eLNYhk9dandT1+cnv8moCu+rdaSMEQ9d9whfb3umtGSJfMeo8v 9W5Y4QyalO1px4YHcl4cCyenO5/DybSe4oZ7VlGmUh2sZJ+Nntl8r40ty5j7jbXQ0FOFiFzStWDu JwjthTW/lCYa2xJUx44ak9EhY2ZAiHCexidCcN1Ot4bxQNzL1Ph/098CMIn2jf/VjSSuMehrk2PH lDGZrcDhwSuhHh8I2xzxgjZrk9TYYgr0y7mM13x0d8ethp14r6itXd03ynpajzlC/ZD5XbOvQjxB rXX1A47z2dJ+fSWw/KpIhFrhtyJRUT4G4oZG1Ym/gWzqSKd0K455j7zlfg/fK89SheOFKqcR1FTK r8NF3GkrgtAMrIT9B5XNlGDHWfYxiJW0EbDYK43r4Ge5xFJ9fMMKyycPJpyV5rez8IeAXyuwwKGH PDqvUkYnooxQhifho4tSqmPI4dVuD+MgCyIy/Ewx7g9GjGeg+qVI9TPkzpPTTflhOpHtRuy5/Gln 5d+w6IOEQcj1CGg9UvB+JISaPN5gZrzjt6stbPiBmr3iN4KNDD2VFERQzZ0n8FltnATAXug4UTBK MVHp6Hig7M7lTdsjGhLBOmovpDgYUL1+WIpBblS2igsITr048x3F4zzVrfcWXjtZe+1w8q7PcCDw 2nIzMxlrTVKAba5m/ac9sM6MMFWBg/sl4RuCV6MLuNhu6ci1+gOY50DGdyNlpU3437pMVWhP39do cXZ8hRuMJ9xiZhrCrcRJMrVRwiO5DyZsNP2rHoSQM+26St7O2Rnp5Xe7tR4bkRv72It25TBrSftM eRQiavy6NYZs7mOl8XlochVdcZgUZNVbZm8tqk28qcUJwRKwhtNf2e1AN+Dd6PfptJGctd8Oyu+e JVhXZQ1CpQCkPTqWnsh19OrY/i6UOsHzk498sbC2JZ4uFRuWxbLGHj6qRAWfg7CJ4EgMaPr3fu4L IzkuofLljtT9VMEFYmIB71WS5Oc07Y/CQyifjLSKxR+FXRsDNI1QMV9G31bV6tcGzUPSkoMP+upe pdkXrMNp+bl97Q3sqYwjnnY4V4G3GFTgSAa1d7Evjf4HcdFnRXv/R3Y61Mw6OEFNtY9JZquLZkcZ TJf2dtZWPTppRNUZboRrXBbk3lo2G55dETt8TyHUAopvGSi+avkoVSqx8EJ8YNBA4VDUAyqWUQ3X G8OyH2NPkRMV36GXYFfS7R1xxWxfm8LupQoeFEd+qCkBh1GyAIOXIv6JBEyqduUmRW/+4noAFEq/ 3S31muKunk5AFu3J5p4m52BA0maMmzlG58iMSN6SsgxuEFDNXFW6mv3Gt5rC9nOeOXRn2aEpwZW/ cWPJ6qxsDb3lxZxWz9QpHSsPBRtECQNVPZ/J13z8xBqmbPht+kXm1P19Xe4BmoTPwz03cWdfu/NN QGsewf9YKN8dhBo437XOy6FyPzJwU54rx3BbTTh0K0f311Gw3IxFCEUU/OlnG8fhLGp7c0n8pmfv m1Co7MIelUiODZkpAQMcob290jDIcDAG7wbm7l1imKbyUc5uf+prV6rbSjNDbM7yX8t6OC5e7ZAU SW6s3SndGrjVjMqprEbcLWoJEofyy9DcFvWVEbTgOVpJqBlVBJvdvmuEo0vkbAoljTknwy05jGfG jEsn2ToHOVJ2gXg/UgHHVoBnN5zje7c3kf+uhE8uA4y/HdFc+Thyzg+m+galRr9dDO6tF7ofH7Bd 0uEjxLvl6VERBSmaJSeTvI1cVgZYiDgxPtsrUPfkBPpXHSZ6Wtu8SqHL07/kK6an4KCS0EINJKqL 5iIakd0EMhkyZs1dy1WAz4PPUflfjYBsMwidaaju+jVNwzze0cYX9A8+zVuZUuHsJLg0DKL5KQlK zN+Jsj80R6QclGy3fdTlN/BRXyNTsLf1o5J+8VL+p6vm0E3pws2r0ECD/eiLIfgGXSgF1awX2XGu aaoyuDpZKJrkdoDv2XiUfmkY167ZGRIlhaF0trWfJLrtEI4c5AlxJmxHmIyW3NbgLiutpAe06O39 vK8FfQGXNOLoAql8+2HXdEegVOdj9/JES0LtKKaGCITIc8vamnVzz0tBYhBg15cZyvAqUTPWEgBG /muDBRHBbmw1m0MAFopuUPwLmXYXijjeaSJDyIR7laGpArTjWUYDwE+e7BcjY5Gqrjz1xxG4yN6g 3Tg0cxn8Otykot6mX+cksJsbUdMZu95rTi0IsJCn8MteBWMQnpkexlp3dlDqn5o1wXx/LhF53cg1 L5K1P8T095y8AKwSrB/a2024F2NFE869vss/V0K4cLvqVw4et8TcC2KxhrUgGXU7h/KO1kNiP/WC j+ch5zveD75+6+xdhtfMG96U09c8BICTCYJIfnF6Ftm+f2xDJGCVtUARWRR6zMwEgr4MbhcviIVX b0VjeS+YoZ4EovHYX7BGDgDnDfVXVy+E4auh85vXJbFInxpSnnju5xXuhkTb2M0F0W6pKWS1+u9B nxR3BTxVWNpEvD2cUXJlLOVy3wtVynlQEx04GznJC5U5NsviE7FQvsTMLQ3X47h/WbuTXxxP12sU 1cOebXIsjqb2eyxbsfU+1R3BsxLZx4ny5fbWEtk8I3Jcy7p/XxcOrqUTvJKtU7AAddR9BQUlSW5a 9UMkudrxf7UuDrsItApsoq51LXruyf3dqEJINl/GNL2RjEPJodBtV1QVJf1zZdhjg+HMchyemGwb cOmsC8BHhasqDUPNQpe1SK/v88fthMwSTiuVjVbJlzvDuCltolPsy/A2qKnARlOJ0I5W6LTHtM6o NzQVzj9OUGLU8qnymTO9ROwqpFOCfbKzLInr1QMtO4Tdwsdje0Ge/a/B1IDQ/C8IELn3IUgg2FoV ggTm/8c/dVZxlVEMsBd8Hu4nsTPyCxXc01NLPPthD5xtIAtkxIi0Zmu//kdwXrbx6crApuKVVAtS izUubaEZ/sZz1y/i88E4K51dAnwDF/K9mGKL4pvhI7cIB49RrGfah0F+CasSq4ZAYioP1JX1/XGK R8jFKN5vJW3F4G291yvnf1kAe9XFIuHW5mSr5jxPRbCAj9P6OYaqvprPoR6bN0rGSF0/Ae6YzrjE 33/nuUTsHXSovowSMfmGUn45hi2gcPi1Yx/IImZzd1Acy2458VgtLls8R6fCCJ7VLjwx7UtmoNeU o1RBmKIkLAnWFQABLIBnOo/5pRidfxykj5iVKQ9Bx2DMWTUBV/sundS+7qCTH5pbivwWoQodtCaw +yUbsWXB74qBWFEAS7SKo3fCE+CR9/kcTOe/YeSGKbZ7afhWHLXdnkmaLmlE4m7TRYYhEgNAxdnq ml5u/3BebvbR8ZQrUglaTMwFDl94RdwkCET1QfwKju4uq36lK0dpwIGatn1HBmlrCXaVCOgG/ru6 pPO8SJ5gtIrq05+XD4EG4sbts8Sf6VU6KAh76L2NKcBa66viGeoiZO3H/5v10QG7V/eYXf7oKOYg 6lZIeAImzKv3e+vJUPAld0LousGZGaUte64d4m77yIdnBhAfqmJI9fgkBJkeKQto8WPR0HjKDgNL h0/8L+sRFRkgWKfZWPFmYdkd5WSRZyqV0dRoXejAcDxILkb9j76x1eKyMKxMPDezEQcejfleJZhr p6591U0RBRtOnVpqy6bv0KbxDw7pW/TJp56ArLAcwR52JcWlFTXSWYHsqDZURB9csRsL6TQJJ0v6 EQZqkRKHvOmfOedK4G2EY1yIAsua2ph9r9cHCYT5ZQGMxlkoaDQ+a4h8VB/mZuJ4piwqCE3dmeQ6 NFpZYS4qKsQ8GcsfIXRUws19OPUYg6157zSqcJsd7JK91ACSkWxvrx0AokmPkdK+pOigF+R72tC8 dzMzjfRb6u7lUWrlYY/Cq4x2+VCer2lA1GbZ04f6dosKIaVlruRj6RMsAMedqUScTaO4/keJ99V0 hLucs+K4Hq0WQubWc97rs+GkZElYgxw96CukSRaoVPzzu/hl20GLkf1MVPM6XOzozjFQo+/V1Xa5 TyBPZHTQG7fFR2XY26An9err8yyI0ITyCwAY3Ms7NIV48CDwXJtlaQt6WSCbATFOGkwkh8QwNbmU Dmr6/z4ioPO1hW0DNpOxH9uZD66PFEOxoUT30gScVvVx/0nk4VlXmuZ25QCgT1Z6vmsElHh4aYC8 fclqowbmNaoH7oHx3LcwxlXVaoF+/LMXvY3yyDonu2puz3c6XRUBf3eMICMqeEFokGfDEtpARmBc jGfwqG6ZOdSmCuOy+eL40Gz2cpBxvJb373ZIOZ7YcD/fTHCNO7RikWOp2RGD8rvf2JpgSy9ebCF6 XdCsHUqPFN5WKqusCpaH9V0ah0DRtQNNY2xQgC3NdDiVS54N56iYoj/bBLa08wUFbcRqNJK3XG5o M5ZfD0kemUU4Vsrmy7fFIP58894dNNL5VJGRo7TCs8c6ZY+0vsCQNKmbapWz8aPFGgvxW1Shu24b silHVyDoPeH16r/HgNdmco1XBm2PDE83sa2IVoUh66L0ejv0oGQpCCHO1uS+s7GFTLepNJ8yEAS+ Xo/Foa81CD4KC1DlPIYlFmJRo/PBlZ05XEzfC5Yxi+4CNp2+Wk0DInRb9zLL6+K90BRKorvDUL0v HhlFtzEZ8SMuOL3MliITZ04SxB9B5KKomu1FxuxrMffE5Ui6BerLJ/FKbPgXhpu80UpKfnThZY0S M82f24iO1LmIU1fq9riuWM0kvD467k42pxQuljn6AtJXj0qRNaYWV5eMQsnlJ2c/VJj1AUYy1yJc Q8A7P9NufHmQMU8Hcb0XEnSAhU4oY5Uouws51GmFcGMI7GQKqc0RR/zGuLmsC8Lg4h1ZDuC2XKVm NTVCELekiwCQITe5bYQJksYyrQ594I9wgDyHQuDulCMnzYxJQZl5mTwz/c/zq48BZNN/p934jInF j8tkW1r6ppTAV0MDLq3+cfqKgd1RvHEFVQSgYwRHSLDwbqnQnuU/ZAPNgwqS/u52z1SCtX9vpwsO 9nsWjtFaAPOT2oA392Rk7GNiCUOBUjVNpwqQmB4r61sQntQnuGf6sxG6nhezwvDR+DwdMOFSgrEf XjIikELh4RG/kp/zDwXAkLuxI4l/mYXTGboG7Ptk1LBz77ikSOvY/YzCs30/dfdMcXT5uY+orG1O hecFZffm1XReQAc0pVWKD0LCjhAAvLJy4TlpfVM560Pu8DKglSC1c++cECXJIQAH3QZnNRDVw6z0 /5l/43eXEm5szIHujuArXFWbWYRTUP+CiVN/Po0vSVytNmQ4gDEjTnGFfwVQsmAvcTJh0D2mdIt9 i1shnJEqkPPwjZXJlUQHyrJ5QfbBGNzfAg3CHv0/kPxQhHEuhvqh4fB2lrulMJ/sIetgldg+dj1G jq6/1ojoQnDzsxXOhJq3HpxyA2StMjywA1wcwCeWMIne5+2Cl/M4FmzGI/2V3BdpJFv0pY6f69Xj I2XNKaQG83qsUxOD9HprKYdt7eLYnF3hd9lEe4JLsn4Bl1M/vR29vCl/AEitTZ+sR4HYiZSYkFoe rnBQ/34lf9ynmVy8uRA0RCpyKMqJp2wSDcd8LvP+7T9JBTlZeXKneGZ1BsBjcjGnIYS/lM6Y37vP 6dCaAc74975yJ0T9JiAIERWEcV3LaenqEOv6fKSFrT1uoAX0M5orBApF+0qMNe61Vlvy6Ph0RNbD oFdTRoqBkyB39iXunLHifyQF0c2ZWVslAiuWqOLT/XmeYZ4SKPQmDj6YMHDp0psM8z8n6k2+Y+V6 R4CzlT5ytm34eex8b50mlNVtH5bkDaQiEd1NUYwzHqUmt+PgujiUSRIaSs0uulwJy1oljU+ANovW rx1CRAcVoyniIpXLfRg45JRnFedlbAb4egBRUo2gOLcClHS3jXCvVXeIFc09jSOqz8HbR484yR+w mkjlqcTBLrRTb03CaXF0KUY7f1I8AEvVFGsGyPhLrFR+bgCx9AGjHQrl9Hag16Z61gWumV3TPAve fJ+1euJk+RJ3aCwiJiP0AsmdEC0VJICERs9wrdnmj7hgQLzB6keN9RFYeRB1W8QGEkWlyc7+4Odm NsakS0Bb92cTest3YbHhmTcv650LbYw+K2ju0c5DndV5jjb3ofp2g67YaDrDwHpIgUvgrtVGchqV YVTbt0/eMvSCoIaoOvRgLh9ejHIs7DeOsQJp+StXk9ue7Lvv0mkX3PKNuuWgP/E1qUzlj5hameQC hPncw/9j4w95wV2wE69bGpCnHQDi0MyH61/5i+0MkFfn7Mh5XqxxMN7BHKc7ROC3LN2TTnGT6xhl kCaCRL63OamJqWLpM7TJgp+g76fS9oHJodzqVEaq+6mgD1FEYoH22d63u4iLtcwUZdR1tif0+6NE rvIWdoxcz6II0CKDbkBmZqA9W0Bcc8Zs7tFA2UQPPXsFsssyUx5rPuTVPbJppMNrQllVPhbSrvq3 U8j9tHvJuj790NOqLfB1WxfReiXOKBOJ1HUEOSbEK1szeRueF9Z0IEMErCsVq28EgRi06an6u+7d EJWJsIlxVXKQJ4179r/FzYmwtCUbhOiPUlFt8f2oUQGZ6EychcmmCIK84M1oVtc4EjY97vUv8vt7 HwaDi77ZxI8fCtnUm1FJBVodUKnBCN7s0XXexAw8sGfAp+2xWPV8psd8VQFczykrHRfP7661+S0P 8KHx77glGp+seYUaaN5y3vN2VPTfxZKbo02pTZAjSoFE3LA5KpNZKsquBtlZAD1/YVpjlZVMK+mJ ajAl/apLt+pVU1aExmgbrrnMIqcF5VC4o2Bz4WpmVsarkwciZvhEM8zoYNb0Y5vKIFvwy/y82tGU SYUkXSgzLan6sjut+hkcywMmugLuHaoSshv7ejt4eNoyQoTb1vgg/SbKa5vo6bcOn9olVegbaiHY WNa2ZyaDjd24+4Sm2EWDP+GaEK6hcD7VF2lrisFWcw0Njp/ElILD6fsExCC+JcktQzq6sqZFqEAv 4ybmk1/HduD2dJnzUbkfCe4yuwWFv0N1an0yZnyOV1D0VuSI5NMMK6nyeMrNe56dIjiJQGtu+te0 penYp1pMtLZE3R80clHUcEcbOVurJOrHDZd9WZkLkliutCZQXyrmk98vmZznlUcEnaNgz0uoRF+1 +69Jm+71XDDVF8a/zG4w8EKoyCyHjcMff0uPJBKqrTT3mZoimkz6WT/DuDRuWKH9ZH2ZX/9mFvrr 9qlqRxpBhPPbYc5gms7erQ7aYG2DqCD4Oe9rQQ0FraGGYU1zNLxN58iivp9S2TVCwElsNmSdvbIv CLYfkUXlXqqR3ZSEyjMp1lK+PCdjQXarXUhFr57C8Hr3FuGt2esJ5IpsGzrml6FwQIxx+QYuqQDR TQpbbkdiOQxS+VCiAOP8UV3Q5yz/Ajka+Cd8Lc1RjTnFXMnDPL6ZOeM/g6dR6+zLkjqJYfpdG6r9 xoV1WgHYp6xPOCcxTqyuJnbiKCNp3Gn+Kd0fWOdmwZ9eTzUkMZX2eHFXDs4OE0nbPjGAqV41yJDM W9RGKLuwE6M4bkyE1FULEULeKj8QSf5CyN31gzPSvT1TrW1hSEvEyS7IFXLWqZ3Y4Ae4uYdQIY7w Lfitq2F1cZM0bblEBwagzcKCX6NsA8fHUcBaZRnzLyWPVQZU68fMR/SmYoBZvEcdzE3IqaVadNKT U0VrKyeRhD7p47YldicDVYtH3I0CBJnr/gYN9qZ/ZGYVJVX29hvGZKRhAeM6Rg2LlgmHWVv8p8eF Bg8suKgNDuwueZ2CkJr99e1VF/1yPn6A44fSPhSDZIOf66og402jXUSmT0BcUFrB4G0To+wZoMO0 bVx+/bO00C+WETJNW4PTshyhdyNTkP/EttwM+bH6jb+P/PC3s+LUr4q9tM6/Y4m+B7JB3P6tsXVA u2+jnRcfM2IrPsedsaG40T1OiPsFjIU3ZjZydiciomr5f5NL4q/I3Mc4gLSaYs19Gg8NOIvpGfEq MRnutFN97fQOASh8gmViIkh8LUkRqr4LXX5XRqSJEr4OLRyLRWIHagYNunswJYkQdKuAOP8VGz4Z tLRBlyppuVfXnzOTpReho3h+3gv8Av/qO94ILrvj0fbLyCbG/Cd9boxk581EQcyrLPIQSbHi26XJ bVQ0t3QZxRJlaYaphN7eo6Jsw0I5n4DAG5vOQPx4tSbGeTUSVevBifYZn4QWw9b/O5xjXSaNuBEb za5lKYpZoE42vxhEXk21ptfzGY+noXlB9L8I3lObBCsAt7k/i/QmQrKJOXQh0Z4AB3WIKLifjpvj zsbilJlGDBuKDcDg7uhgyeRTArdcu5ShuywioUKG8UfcrJ5Bjwfa2rEOJoqnIKxDvEOnF6grSOR4 nTrIS2Vs4A5fEP4TYOw/Q/6qRf2JRl/sIbNt6wMrI3Ib32Jd/zOotvSGtNmtGfDVck4nTJrC4I0E /yoO22x0FAk1KFBdrga6K7ZnCqYdDcJad+j/wqb2vMVFDhWy5aIFMTYsBqGUaDcQYWelt6KPMhl9 XTks+uWM3Iz7vx+2F4vbFrjoNtCfW4G01rFFaYg73m4h61VdzsDLFVTtRGUQ3GRUT2zhlh9Bh/tW QkX4zG68kY/fUZk87TnVUGotWj5H4lTL296tyDbku3yeyMCIm6JxKt6zGfjlKlMoGphWM/jQqgvr JXjI3DWjbC4D+p6oIGt0Vvk2ijfOJ/IPajRb5RZk4NCqkbOd3fT+7T27wmh0XYh26sHEFK+jBT3d sBEdWzGaje7wbt1V96icSNuxoMCfGb8NpuOS3ymSmKvzFwpaTghFd3Agb0iqnC4PGSrupCIN/P/9 Z23M4H3AomzdDxhEBeIBa85VjQ+ElkNXRbmSwaBhsxVhc7gkgeb3Are45hCLUbjbvXaDIQDVRCyf +905/9Hyt18cdN7HQd3hGMPn9A3NAgbq06gqtVnfPpWG9x0KuAnIbO9H6KYJNuFNjZ7GVuWaUygb Ko1NC6+++JSc7ADFujLLAkNpQqxQs2gSJ+caFM6Y0RQmyuyaBFI3nivNGHNi8NqHu+OgiIUSFjdX BX+clSFSXp6YQTh9zlfk8ZVkC29dRm7ybZA/NkfJ0a2LS15yXGyIBTTYYSXHhUyaQPNBYCGi7P0H bsGdLLalBQecWWWG7NjBMaLo6eKNyjO3g1ikseWcY3m86rmxt9KsqoFNnMTAVvcbRpb0R7XOXBpm 7zU9Sc8vV4VbcUhjIhQVoryDFWNpI6Az9PMa+qaDvF60PrsypYX9tEFvtc6KeDJuSrpvc/55Y2Te 61n8SfkkoLdA7VzX3OLmZX0pxczSYHdGavjbjj4h3Wd6BQeucxwh2z9NH3Zz2CW0ilccbmi72D1+ +kfodHzgBxJdW1gNQ7u/pCakQAtUzriN1mnfh0MWamOtjv7B+HPUzb8CDTSp5243/UD1EzDSYbzC lGMH6Y8cvX7Lge30StAOuFoM3OApaTJyvN7xpiliA+vqJyxWbVnlEErZ2bvhWrw84wrGhJg9Gdr7 UAw+HEkTunCVWtA1c2BKR/GfSr7WzHelKmHNaM1g9yqXfcu5YwmMZ9Gp0IR3CZOgg2N6kDCOb09D blO4JjSsAHhaHNHK359fOIupnQKMTSN6TwZzhDCP4LgXCIDVFP1kOm9pgQDwXxQibhvv2uNR5H0W G+rRWXNzG33hBavuPTUmKlZoJElQ9fqMcL/jEqoi5NSn+A2JXWiOEtL15RLaAHBQEw9a5F+ujwOG svx72RuN2sAPrm3OrxqILWYk1uZIOGAS1Gtrz6peeNy9e5Z02l1YKcuB8j5cJGAiO7tzdeZoQxBF QMcj+2EkW9775nD8NkzVrvMwcPX2X6NfT3NCP0x3pgmTVoiy39nYSnSlt8c5A6vD6oCGfMmr8yK2 f4UMVpPc80Tt2FbermDp5NQLCmwLkSRLKrY1DLnaOFujtROo+bhRb7kFuaeO4li3n/21WqPfqSYI OVi+PAHkAuU3kBkEmj+wwt4qINcg4hY/YILwNJWM/bfDmWLlKQ5Eb3eJliEnnQfRxTq9B3dyKUQx B3g5FY0c/vGJdyXcvHzx3/6ZKIE1dCSHiMNkMNYmDrG+h4gE1Kz4qEGZmG0tv7g9RJCjDAWYgvT5 VMUV8/PCvDGGG78HEC064TITYJZoHUuNAVi6/O7oi2WlxHWe/bLfVc0dpBB+uVKe2Xh+94ATiGrl HNTiE0XQD5RtkLwJmX5IW84rmIA1Z7jwHQ4smiad4I/Wsh9ZXHldIeGh3pMXuwS1Le0/AkfZ5i1E kotgHL+flJCDl3rUg0qBIGp11QtCUWq/isDh1VW16LUCpPi5yNBhR5F9dT+4L0H5OTG1O2yupNHC wddsOSZnHqVGNEfw6GOVL/HmcmR+tXz1VNVDl8AxTQ6i4nKxDkuHl5/xvt626l3/c0TkeGsS+DJT BN29b5NTmKLXL2wUPfUr0KHKxvk+Koh849hOpaX51j1/YcbawtTcfz+0+rQDQq1C3MhbA0wq7OkQ 3+u7fn2/6Zm7+5UunrhywfGa8ZwUqjBfimkl9ghmArIq+m+ecmVIIdmiH67cK8x6InSr1FmcVdBF ZhcKg0Jpr5MDVUYrHhimtK8e/kWW14cBTzNGf0tYoaXevsVN6B9l54SomwfZWejO3sQgzmCATSkr dYt9d/hgRnIoVnGjnQLvDOrd94Pn53smk56l8M3VL88WG1G4vNJ5ad0LGLAD+9/XIxbtjVFjK1qG hSSDBCILAxvD5v4dE721ZBBeyKzaHqXrs712hl/ijYx5MO45NA1ZvYoQFlOhVB5BmgouZ0dRdKJr v9hHTR/Cgj2JfkcVSgfYayxaFCzgztsDhTlcVTE/nuBxGbgBd5kPodLzsvbwuHh3AIw+kFdAmxjn 5uFOXE3Rm7+zEl9A63ccVN6a88m3+Nxh0zHa76lwu0alrUfMys1E8uhljmrtgnWzI1RRaxVI+t4D srqCQ2Zf9VYVybCVy/Mscaqk2yzpj1eMnFFib+uLA8W39NV7iXvKYRR0LImOuVc/Bm27hAJj9/iH DPBM4iDMU43WLCTwp80o6wFNB6pOliW6qorNrt7h8cYTHR2ffxDWnhKmxDLNNiLhWLQRtbyx+eap MFz4LdimzTQ729S8GgI78ZKVS34/hLa/AVXJLPX8nODsb33Qmzsyax6Y/wp5TZhbyn1+uBdstRCX q5QLT9asougFeZIzOZrTu5ORfhclYJVMO6Lw9EWlm8QJgjLnXMXZbRh3z1aCa7+s/0nKR0FzwzBC gdArazeOd8XApTW8/ISE7WW5gxsWmwg64ULBM97M2g1N8RrUxuUsaJJBaIPHOZRN/BkpqNwJvicK 1DDM4C4PIWLNh3pmSHIWiZaAG6ig5dXyKTI9K23DMb91KqzNUgl2yITmiCDr31Od9bCO1Hhmf9/u kE8FKTP/G0+ZjLhr7wnnIMf6rsdnfwYBwTDe5qJXpQ3RB5Xij2zdNrMUqqC7ppZ5lsZFiQB1gqCs 4mOUvQNcPd4J5xeDp5Nd5vDnRkfCjQqLs4Go/TRawblgTvh8H/fn/PJ8CmQOEUsqr+0YgQ7OE+hU 98gQEbHrx9asMSoBzDkAIquFZovm+/esTCCQKAt3veRqfiLoQvTcyeg8l0yC7lhX3VNjbkIhgc+p Z553Bhb4iujkcWNwEZEmgLljs3BE/dhizsJNeR9O4ShtQ5hvQsbV2VPuAwRioEHSZIROGJdSop7R Cx6DyeXyoJHuOjzjLUGmzX/xj3GeeUqfe64LWdTa6C0nAF7RbLIJ3OT+EGq6JkCofxArCm553+tz C2NfGa90HMKcTGD3qOFSIs+X3+nLrJiRjW/rXYFfbLElf152Xu1QjRAXMNi0m0XSOCTzTzvkj/Z9 mZGEcsxyjoSs+SjEkJNkIIimnrIbmGUdT+xNcFF46xaigSEyaoubAS5+IaQH8hCz5JGaXwaO/5Lt jlkDSQOqwePvmHpy701ZBasbkVIc1+h4HIDcNrNZqtxsWUkUZN6Jiv6P/U7p07apByxIoc+vP6tU mCJpW2PRCtwr/+xz7m0RYjESNOfpXprRH3cTTwOtCWJuZv8OUwFrXh2U7R5hUNzv1ArW2FgstlBo eERwhcbWwkQ/prNlOtXGVDGCCOJFT8w7q+cuI+2ULeKJz98u8yT6AguVx7bz5VwdUMeNXtmoooTD PUOE0ss8J1cZiqZ0MUMWHHScc98hge3XhRrcdX87fQro14JD9ggyrOEmtMT8KbV2MvENiMILWeMK Mtgxw0G7IArVlSapy/vcFK+5gie8mZqFJqIxW0XB98PaAgk+xGCFUhnLJeNZTZ0eACInSWmbvJhF VqMKGGw3YOImBKPn68pzMGIJsNfj23H7oXlEWDL1wSoE1+lJksIjs++lrtVxlfjC1GfDAfGPOJad ZiHNbtDwzc0oaQhzG9mlszXPcDHd179dkLO/02itJOdMSvqJ1mI/ycAGkZ3Vbu00C/iHfwMYVNxD xZ1BPp5bHYGgXhzG2ZResxhE3oJZL5tgQrQOt4wmNsvg0LX70YvPUw5xcFXs8uHVnQBa29VZv6do rJ/Ncs62SNAE1zTckHvwxU5mlN37+GOGdHRTllIOPA5TF2hnoU+JNmLutDCZFephOf4OEkL/o6il k45L3GqMXhFI+pb5iMvCNrIVonCrCL+Ew7fJNbVzHQbcWupFHTrTV86eRRvbKHN8EOGv8rFF1eEl aM2TvM9iqGe53S0mSfcJZ1pvbZAwv99aqX/OG+AsKcYS8rueGxTcs/f5XRYPecck6kCdwAZBTkR8 X1B+lXG8k60NNf69Ju3wpCU2UHuJ9FcoLa8kj90olMP6zV5f7c3rlI+CckOlaOk40ayJbzlsNeUh Y12XYTiAmwdGUszoPvmZGA9IA++B1noCkrkWvZd8jTqGebba9qkvjfqMdPx7JgYhFW80j7eS1WcT CRJBKf8wDTbMEXm9MBKmJInvsWh/ItjR0/Az4bQ5xY/zKdUzlQykuD0WDxZfD/veCpOK1rr/pFIr joyYWCTU6S1Dk7TA450yfWVBj57x0/jklPgJNZIiImotxHTW3ZsWeAI9mZ3wbabofEk0jxYSW17n 3d13A8pwH6rOGLNkAS0QjV21vO2E4FIRwyFgzXLOtZ7Rf4PoqloXMSxrKOpRcNwfzGoXXlBmOx7e 435oqcN3UZdZaWmxV9b81A61OoaIt9SohEu/tmTxAVzDbmaLQyGWaLwObnl1KSrC8gsf9bQsotEr ojwRED3dVE8mqUaY7wJx8DUKkohXatU46AF3NwPL+kSIYpMz8Qf5U7/V0cgaF1T0UNmuHSeuHxnt FXxJfygVu7VHthFTsZqoi/vwKnf+xiDXJD5/sq/JYsrOu/7ng85Ge0Ju/8SL8nJaAvINxkRj5TRi 7OJkSvHiWzS7i6btKXfVo9fWp69RIiVq4eLQCAveNU+Z8lUsQDjw/hOTRZQoT1wJmeuuOK+BWG8Y uSTb0S4RQaaGGL010rkFKzeiu84AvMt76eUvQU6iNB+wVxq0UOunLUx0jeusRvz4nfEtoEtV9d4G zvi/YA3P0r2rk0AmKODnz0jsA90gYTVA7WbaQkohP1Js6CJndvMN6j8MrCSwvVMJbAE+Bw+2DMn9 Lfvgc4kiyngVeoZa0pKIU50DqGQw/MgbMKUScs3IHN6F9dz/FIXBMhPZq/dJz2Qh41usDYt14Q0+ dK7PuKDKC3rYMtzQqSMONsJWKTjyoaFcGPQIfUZommsKFP1KyqSxKH3CLx2etM17/egr9SV2jx74 jo4qc3R8nl5Mmi37H7FeiyTJIGNs7/IBlN06TCFl+YzYyJYo4n87lfAuYXc3PIe3VJfYaPBxsLuV BB8tY/XS43pCrrzeQugXqQ70xpvkWUScbGG2wMqdcYpUl5/pKNXyQHOoper0PVKvwV0DWI4tF+g9 u9YSC5cQ5/+i/ZzR22oDUoBTbQNjRnFPefHyBgc+Wb9zfF+eO97SuGXGEH2BGfAmYftgc6rW4KSK m8G//fHjTMoGKu89w0tU+XP1BFaeaMbassSMXZciP3IK95JmBUNMJJCgzNdClc94PCDoeowYQfIt 7BdJV0Pg+NUyPTfz4YVlYwW8hB4UWcvB4xu8QIOkDE3+qsDp+O3nSTBjiXg2B6KnSTzwUtlBRndx 5U7p8MEBiUA67ERa2Uvr8ZeXGbr85KpvpHEzlguwizywoPKcFKwK87nhB6hKXj8dCPNLnqzsxLJE xG/Se7FJF5ONtIKoP5v/waeKJeYLpxQhBKpvCvP6n39giB4UWepEXdD0sh0dAtNkljPiL2IETbzW t06CuuCKxe/iF/5iVFpRpotdGUwwpqW0vxWV8g2LqII0H8YVt4xDGnNq7lpos7iipe047pMF/PSo BDaVXUBje87jW61/hQk3EQ8JSqYZq3O9et8Xiz2MEoc8/R3qyOlzCdp58RUCSacZSBO+e2+EDV9w YSSNFJdKNyXrCbhP9h4vvUHBq+7JJCnhzpXJHDMd62E6mdsD3uyMZyYQ04zo9mQZ+HInzyLnmi06 iz3OipcdnRht4HcWHctpYsa4zO15XGVTAjnh9b/7B5kpF6UuuJXIzyj57R/Oo636qUj++TOA5HiO BgkxxtasZXYB5u2vKc7lz/Jh8vud6+dj457YLUOARsYOnF5iGuVKD34DJxb7oXLQnJbeqtUFHXOe c6WFMrSoqup3obZ//xYbflpDYRDem96S+KanvrFdXJN8Fwobqkmw2SEZO5ajvOncm6nyftOgXi3Y GxzyvNoH6yfo3azZSXQlmmPA5EsZOZt4VbGmkQgQmp13FdF78Y9GoLDiriVZEslQ5lTCjMA86hHD zwr6dBmOzYf0GErdj15HYa56qmvC5N2joQZoEeNxOPOYFvFNj9+n8xIA4B+SoXdC7kouO8t3VWf4 Y+36fkOd00Vi4uvcN4qfS6KgUOf8yYcAuqFLKys/o4MsYWKBMJc8MIKkJ30ZcagEbhG2DIltx5AO iW6aSUMb39L5mMFLMcDYTi9pEdCl2mHb/Eca5s5t5u6OWTU0NMhVXEXta/U/FDTLvUTyXYKKSSkb hwKox4s8nefF9nd+ajD71KFGg1uOHNhkHPRGGY3LjnYdc0ucTosWkx1wYSWL8O7iwUqWEoixRsuJ Sk4AfRnZo3pdsiBAyAfIC8ttL+R5Du69GbNbDY5usbgbSZ/Kak5uHitmTpcFg2Plzf3rEFNH5jg9 N1ouUDByabEJ/y9HJHUYpLTFJDMy8zR+FOrhrwt4ivuv63CoLZoRYrSl/zdm94vryGmBFbrPhm5h 08RmgUdMM8IMHjcmON4wihLaNNnVQGBp/trL3cn7D8SQWa1/n9DKhuwwiRhGRvhd8FlBPOI2ZbAf MmG151dDPPb1BF49vYY3khCnkk92MlLSE7HggSG8dooLGdIUnh6lG1UeWQhS1QlEGWUmIQ5Oof/S dbIZcn0smvrkRPPc7QC7npZtviFdRW2cA34+cmPMgmtznq9eUb0cGcKyhnd+Lq1lFGi3xHopBDGD RcEi76qXV8WtJnVC6y4gVeJPPQkMu+oDndTFeAFO/F+77R0UjLX0aog+2lWa+yhG1Hkf0z6fgHhH o21qli6hEhTVg2t4q65H0HHvPqHgw9agq0tGJ+qDQYnGX/C3ciLmuHhalxKbgI7DaIJyjUTc5Ane fNz5vYjCQZCgzy6yrCCxprtGYaHzTYPAXUCvtJ6JglvUqc/NIGe7PVeXZX2J/wfWrpPcQ5N0w/e/ s2NOUgGTxZcNSOX+ZCOMdf4b7NRFosT9eATBl/yDCpXDs1nU/zz9XMEjPqfclm6BS+V2j+Ttq7Zn M9lLWdI3kiJ/evW9nHO9Li7tT75hQBNIc5yhm8iHKb4TYLnKcUC0mR/4d0peSgVgQYD+K/bIeFnd qtUcvPYYKdiaMHGU+AfcMEk+6yiwdEKlDHrhLMUHvekpFuN6WWl7px0Ha7UJ29g62P8pZApOGNN4 IAD7fuambuYzUGq0zwYtqPyDLW9G0Izl4GFnpy4qzdLMaNlcWn8Q0NGM/rhVKDoFOE089h3UaSRE jYh1k+lsECqoEXvoeVcJEWdPuhbFjYE2/YFv6IkQ7LqGbEXAxltDd8ZWAOyi6O/VAWb/JO34riiw m6AJLSing1UGmbT+InTagu9v41z+BGjZg0U6etrl1p/l+dnSswxmLhoNQibxkNoEzfZX/Loe/YSd i9+1m0T/BGNAA7piu46Es+v+aQV2Xk96JKVMqwZBa2Yx+n5UV2Wlr4hDYUc5nnJP533bu1YBEO6G pCRNoHVpcHy2BqZO/onpXwmow63ro5U2krD5aEFYxEQuFd+kkhynzL0F6T3+z4vxADfLnwMQbCb8 yig+CaMyZ7QPD9lgJfaJsogLfIzcsmgBCRmooQDeE/K4+sSUyd3PEp+o8F3NZc06ga8Jj1v7e6P3 VZquaK5aL723/Z8cTdq2Ztiyn4FpSHyChs1ldNb3unth8blncYL0jZxjvztvArPK6dbyBNeePOgR dF+1xe/a3FUdqwvlKmd06VapKTd9PxCemHqdW15OKp4MQ4Zo7vn/pUuakxftYC+DSbBCNbD46EFy ELpAm2fscV3M/s6ttt2K8GXTYBhkPPAKw4wmMpw9MSzGRhsN/DV/rzCe5rA1XbD5P2SxOul0+AkI /u+YGl5yzS5a4W1P+2yqCyYIupps3dBzw8e+2ykQAPVvgntpgLXQ2KQLnxT6hk74sQV62NF7blyk xjIM6vQjEi9ROGwK9yh18EsUjbFPUrDUGrJZM8qQGKFnFvlRAVABRdAC8h6D1RerD1YQU5/LXn2w 9gXpaBk/iBoPBEynRxC7vOdyHdSBj3oTjIhxcmxuWvf1U7O2AlWOOvvTcK4m5qpzHATp/KPA6zMi gWESm7meVogZubIBpAFiZDG0YwB2DQZV+DWq/esIrhfYklExRSxyDQ8trIKU6XMopEpKgXsEQ62a baIAUE/uuxG7pa0aSjnJ7z+T2CZplsBcylunPjOohl6PSNvO4c1whimMZG0iqFFCwx807WMAJHdO BnA9zH1lsi/qcdxzY//Fzred0J5mrLsGQ2qxLjffsKDm60NOfvNHDO/68L+7brzb9H6wuxOFwok9 h78pNoN2VdKYxRx7gLfaynX/5gkfJqS6LL5TGWXH/u4zuWKKjEVxCDMYJMmFc5HM3KVO8YE++EYZ PlmIvOgZgGrcsHG4jSHmwRbbdDh5mFo+vJA1E81UOyKflmJVk4sHGleYGcdNXZa0mTvRq42Xq8YV +L6XzhNVcsn3xzlOoKfQPZtCxrMEhYKtfs92unDljD39WiRuOiVvA5QtO6JVUSWsVxAs9FRCcErM ImnIbLkmzOd7zfvM5egmuxezbZj0NBfxlB2hCZzEDcl4/trGDTQpHDHVbgkE74NexWL85RtsRjFs qDMuJnWkB7yNTDIVdCUrxeAO9bJqtAKGR1gT5krJ26JxPM9+VuCSvY52/zZ4bWLrWS0rgmbh2AgZ yXt+VDALhBBwi283K5pQTZg+McTx0V8u70jvA0ftu2IV1NF5ND3opcPNUGjHSr0r/GBVyV7+jFuj 9M7p5m1k7PpRezHDc4Ta9QtPEUmo3HboxwZH9uCSS3JeNw1FkAyzDLJOkN/JYftaJmZqVEjQYuFt y1vpzWVK6cPtgTVtfWNmqEoTQhh3HdcgeJ9UPsMQxW/gTL4ojjRYm/Rrk/chsJ4KqsAogEptSgTO OopsSq+mmTMj/5zG1J7LU2LMyu2IQ8etWwXTmptkNWB2CuY6oQf9RylYn0BqMJ3DSgsTFmLKUoFb xAkuEQpTP+pMK53MINL5Oatb/9YsrxT4dSE5BwP+s4nRjlmd/jK1fcc7vgWWL0hYT1COWAlS4TtD cBbZt0YeiZyqkWAkdqrhxAA0fmDQnOJ7Ev+WYW+F+Czi3k3pJyHAXXbIggvZzByMneYdjAn4NgTr luO4kH3mgT17M3Q32MH/Ewe53c//hBCSxIiFN8Q+QEKrjfqAuEu6GWvxj9ZGObiAHAbGSE6lvSHE Ht5b4kZJKFM74j/gtjF5uqAw/zxYug3RVNoFPb/0zZ5e3jabAkarzP39QnjmJPNvNM1H89x0GVAJ y0WGNAeT3CC00Mvj6t5YnsEHPQm/7qg5cry31LXZg7IFIlszuKQdLpzW/+2KN3J+9uQO0NdxFu7Y yBnGdp7wpOd7/d3NtgGSbW9jZeg+2chqVD4iSGyUJbwTXTdc6ZqlpnA1qS+B5FEGyimMqU7B//9I AKqClvSa1UK83sEToGlcipNQOoocOUIJUE8ikZcCNqvSiqUcPQolw540as+bvP2lX+z3101w/7ur cgbFZLBXwm5Y1xnwrynFswuofOZVOb4RgOcLEe/yFIKt/Vv+gg/BQaoOGjNv2u3UXCflqYCio/Rk 2sTy5ZdgHhg2QiWaKS/LFa4H7Ei58VQPJbDxcMq6CoVudqx8ZQQXcAzESwz7HlUyt5aztEW0so1Z Pk/H6hgw0FDj5JFnp95slY32n9He0Um1SRFkjsxg2wfN5JIwcjN4ZwbodYE+Ijp6UcBLICvIC1wK tvtt39gf04//1VhNC2pPw9tervECo3HNkz2Ipb9tTzmDPho1flmThn7oSbl1aNZHvrjP1RMK44Zo He0Mn3Tphqcv9fMxV0njL/mqzBGzYctuhJBkY+prLO+QCtGRFGh8BqW6SAzw25++AmoOONJZhZVk tGJtXrADZToCBz1oAo9OgAPy5hWVPl9jTT4lr+wbW5vJBprKxwDYv41bhjiqZQUKcPz25nqOIarz xWFRwLCFtyYDWXkhxHKgkMwAKmbq5FOfuqB8pT3uUHDMLPNPpPGNYSxIhZEJtSMZwNcORNyAgUxK bnWllymnlOzUsGI0Id8Qr1oy22xXfCXAn+M2uV0tr6zSuTZzWSK0uMdYM4R5GKXYgNPwvYwIExrl VEA/jVm1Lqu9nYwouFRCWDEpxgoY5Q2zd60qDjcv7VxhMbM+Hl52S6y4fUJFmdFfgnTN9V7lHfwP wYh9HiK+tRujnkpd0UV2mG88q0vq5ai10HS/1znaFfh+4bd/3NUs4GUfQ/Rmc7elSJUBbQ600Xtu mK+TI8pKyN3B+eciBGlY46OLPjJrLG4yYuNFIMtIVlCWK1pfCQZ1vOJrr4JrnDyGYwG4JAziVoQV /l41juCb8v/N0pUTxQwYNBKW++UGYPmtoGKqP+exx/DqILAHYvKYTUweW7RCFA0xfNaJrvhSX7j5 ++WIChnJDf3kP3PASSRZFjOWUlS+E77NklAkLQ/NBBNRtgmC7XpySk83sw6ofK+xKAljkkM2F7nb 2ci/upJlw0t/lL5FT/oLMhLy+sIui+Lb1DhqFopYjbp9QUN5o6mLpw4nKjl5fTG3UgINz7ocQnfn 6XjeCgkvDsY4ND0etPC6JIYqD0ujsJN4h47aNn3bRB2R2Gpx5Y9ULOeQ1kiWj0WDBTZz9TGCJv+o ukF+RXiwRoEJjLCcWIFsJru1IEHkI8F8/GsHBl0r7JzHttFY3bhfeLpKpOaZI31F+OR9b/QI+k7T 7Hx3wLoaB4GSbRCingKf6Ny2Hqb8CDYZoICwrRZqU9UNu2JCi1y4GPBqPiANQ5ExGmT8lYM4ER3l l0+JWQWJVyVTHlc2Hp6IQkRvLUJII8x2ljjorXrFljClGKZ/WUegyQsI6OHmZNeq3r5dWmmB23cU n7+sl3EnfjWZjcS1rcxBHmiW9Igsvyn71RU8Gpn5CYCidiDAh6gEE+4pkogB1YEO23FScXlaGI05 Dw6ZO8XGW79sGOWZ2ZlMK0XuKDz/jP/kMGWLVIcdFE+ThtF7olfsjqwyN6y8acxs7rtV0XlfUANM kdz+kMFdovrui/HFsIE/ciH8T+D45I9axzfNRvTK8ejUYevn3Ah3Sl0/upNWeGaWd9jX1bUyVlYb v/TtobnZxHZVuq8IrNi5px/GHrrmZVjG9vRCpNkOR5MQR5jshrbm6R226Mwgutl1oMqHZlBXKNEg WScafzafuXxCAM6xYzrxby0j25EJzoKLb1MCV9mmoYmSXCYuixHjnYV9cvIN9/V+36QPbI+t96Y8 2AWSDm5E59tSKo/EgximFJaEKXr8SCz1jvBNvZZ3ZK3hZX66vNuBCLcFeoj0+lq/2EYGIdaLzpXT g9xxAOY+JsmpGxU5qrAF9LgwD4/e785yaMbipbgKxmg8UOHgJaQRFQmtXg3OTko+jyE1RDnUXBDT Id5k/8nM2L1xZcJvc0q+O6Czm2uEJUICOrGeMwUX2DQmdRyaLTs77hln6ffV4lARV/GmVWyJ+lob L2gdVLT8NtwFnij1p9grKArC3xk9WwukLA7HzPxryr2mRB245NeYeu/6VgeBzZ1u6ZXprHPrmRGJ 51qYrkKw91vuebT4jDaqoiDqqahjGDQ69FfWpuvGDyj3yYaPoxlO5YwFEXpEYT2zOdj23KSKbrDh VpMd8V+o6byONofN5k3vYPwlKZk4GezV60lDGEdDcMWxRdfgWU7Hjb++BlCDs+38mjN/7L7ibRla bh2dALyToaWLeeymU/QMaxCk7KYBTSndTTAMdw9h79YjJs0No7TGHSQp9Ctg+1wYEkAizYLkGCvf OZeOANEuv717O6iyizWZgk/wTAJf7d+uCIgUX4XL069ey1ZRW0bkX7rVhh8cqe2FkTmL4Dwyq7Y3 FKxvL24rtQormkEJqUeQedk/s19xLwa9K6WPSauYiDx/AaORWDGuIcOv5vr8zDSHUPNiT7mMydxE 62a6HikZD5CCoELRI0Pp7UjTyZuWBMd/cWIC58SErUU40qQbE5jGQyLmuRSY7E1hNvbX+IaQpF6y /DHFavyTg13ri049AMkcYQIVHZg0Jtb6VE1b6L5z9bu7G3NFQ9FIi7LnUTfxenGqq93Dn+hL9LSO p9oyhHDdkOwrkHDq16HnjYJkWyS2lL1aHtOS2+XPKhoutoEkjduEP+J33ll8HXd+Q6tcNNMb9hHN TuzNzxyFOCbp+z/HSxa8s8N3riRs11qN9AtIObarKdVeu6eZj/BV6C4SpUTh54mSB965nH9h+k9+ DXfwpL213MWjbU92wFu2Tuyej2ILA6PdgXOd3gqUJVDsww2qYKcpSuXoRDolmOw2yM2oO+iPpN1R Ldx8mA/mlnQdicG4h0lW3FtfZAz3LkLpDN7A95Ng/DsL9k3yGAwSJMy4h+BYlrAMVhFc7eD7aM64 urkH0VwKdCcaFOY82+P6B6fW7Ev42bdRTKENk/TZ5+0PiLiJdS0kP3shLVZIoOVqGQTOGbuChaeN kesyFq+eJPO+HaxUDUB87U6ZY2PzuH8Hd7CQhF/VJSb3wTECnIoHzu+ma5uReym+fxGeEJymJ2y5 yjOi9hvYokk49rEGU9aiPsptdqm7+0zpvoucYwURXkabA/YVWRFz0E+/YrojZ6tgXF1+NvoTOEwZ JZMco1LoFZscWQCDLx63f2C7NWb2gOUqZvZM+NzYYPNiI2jp567HS3NmGYsTf4h1GtzGpGSI7Ji2 q+hDfyUWe37ItnWkROjRGQ83Beb1r3CHGbQxB5XaIB9wCETdjjAfHAFCwQ1pNjWIAFW4ZVwkJTjd dppia6vp4ijX0G7bRArOQPH76Afj+M71jqjMcCdTOoe77ACM9EM8Mkfr538460J5kIHnCYkeaqai pFrF6+mpyxuQX+pqx8yhGu5uvrA9ToxOcVXSS+C6u0ZIXtTazhVHG7v1uvoWJFVvH71k59kw5+Nf VPthfHNLzXgGRIEPLT4oIxdzGPIkjW4zoGMkks3oOG2MHEE5W3XlAPPv9rFA5Brze2gpb/c+KWvy mryJs2A02lvohlrVsjL0YYjNNFtsPC8KG3SNRl3SU8EyluwLBmTskTtqAJkHibYGJJipSf/eh3Cc KKMlk9RS/WPiqhNcuX8f+ZzwMnYKsdw/MxT16dq8uBAm4ken6GKeA7HilmfJpMMQbEZNOCu0Kvx3 UOAU7WxShAPfBq9tzsKXL5N8mNR18+tlvmOrolYtp2DEIo9F+Rog6BSDiqZiF1LnX/SsYEH1uhzG tUrUEDv4HUHoW9zqWV+oA7r4NmFRi7oJk2u5n0Y1b9Xj4My56vLpKA4zIu/bko0asJi05U/UpyO7 jNOTl+YzWTeODBPikJzEfifwYLgUoC9XxEVFgz8xZ3PkmgiWyDVuMk4g9XIpbEDjKbfbP0cppS2Q v5A5BLSZQryMt+BS6EDc4kNyT7lMmgSm0WLJQjK9XJKARYi2wT9GuiuApxTlJBaPve6XjKLtXRUc cVkq71oR/LwVjJoVGALoV7+qz920e4ElKqWEsZpqBOBZzTkGqTHRgd9sm+95DPmpCSe7jzbgXwnp 4JSBsDd+1+DWqBdT6Li25CQKdBcFWjFu1dGK6vDV3wTJcQtCl++9A/tYPaYA9Bjn9+yc7DWIycLm IpSqha6NtH/MZlCzlFuDjpCnGdvNovbeIbiHlPDoA2aPU9qYs7UQwCqI7WBeiWtUxd4IW48WFZfK Usg+bM27r8Jja6kBjfBgELjRcR4XyEO12OnZkzKo4WZmpGnEMCQxdqTpE6eMyicKflOlFz0mJejh j1IbWvU74xr7ppdEMYwFNbkXNVyAgPrOEvGq0Otj+fUy8hT9Nu5Uu1dcmuiXjGlohvxWt9Rlr29E AdwWP7RorIIwZpfS/jkUGd41bdd+N5U52iaH1k/JKHiBg8FKvSFF+cBIRy9+jANHEPQHKRN1j3ks nfqVD8yFC5vrurrAMps4qCqY41J5C/L0tNUMU20YDyDNHnd65VjRkYnSop/l3FCJIH3+2J8FTGbo YlJrSDPttUQfWTbeQtgweUn0tBR2ho7NM8QU8VGEc2c8Aj2PP1ES1Wd4b1ihXSrTOom5tg/Urb4q dVgP2zP/sktzCwFKKz8+SbJNkmFAo8nQhBNN655i4ChTEFbZyA94STHCwLWKTVZ0Ig9aK40aWphF mBoTXRdGnYVCB+C/ycF13h6tiSwd9Rn8pBQ3eE4+L/qLvjpgrELTmlRiQpK5guMPp9RKgBH53ZzE zI41i9xoE6j9yx1vPMMLJvcdjTO5xWqDEQjMtNTIhLvfa1L0G5iSsHryjcxKcOKWV612XqqvQ2Sk OxwdjhjRCha1bzz7vKJniS3pGUmxahCDQMML+vvW97auGHSlmGoh08/zC2dpWlSgh7hoHexj4C6S vSsZOSOhA5EgDrUWEesuMK5E0nacK+NXyfVAOkLDbrbmRk1bSsM064aCT7lUoNWT62ey+NeCkWgH lq27z50FJfSKndZbzLuxFqZqeeNWkD8bxmNOSNqz1USHe80lYWPwG4gTb4k0a4XbwIL04E2Jtupa Isnj9Z/qsarcyjoRqe3ONiiCc4rCt096kBObtKDz5rnVy5DXbXMZIVobpFD8297numQffl0N1Ziu u7gYvuwJqWy5VxoftsX5sLsGJchmnVtevh4e4eUBsXcjaoTUgdGVDCp1OT/5iRWeuFVeQWOcQnKn 7w2N5N6LyQRCofAqB8Lb6/742clkLbIlAxt2JoNhL0AwUSMmxy5Metr7QRS+5YtFl4oKQN9vl4cY bGFBg/+5pMdZwRl03DqaMBVNohitXHFRotFRj0PqWy5KToOcXm3bRxC08Y/wmnRkWzXP4DN4Omoy NM5dmVjMjj7ZOFgJkVn0SgOhyjzMZRSm025la/Zcg/WzLgQZodUlhUomp6JCIpgjPCl/5muWNDyT DEt/i9ngnFMWdiDZvZVMmFaJTWNfUesGmcEq1Ba/nZg08ewy0GKaNVpW5Jhaq7ickJuDGnyQmOtz n501qShlOh4TfmlbiQ7x2CpSgz8xmaA2XC3mVcYzE57CXKDT1j0oGzbzkfagNJ20WnO0osFppgFC Ium9JC9h1IUwfnx97Z4NfHnmllNhu5l4i+3Mwb5gtfBJy6tW5zl+0YXFJKcz3BMTugyr8Jx6EbHV DJOmEpXFXdX19bHw1vzTPpYJMeZ6fma8hxXZ9mMfExcTNvrB3c7rJCggSdRgr9A31UZeVY6l4tfd YYmm0YqaTxdoThQ/r7NvKDYIjcNUJn4RawsC/w3GNUmacIEXTLkNbsA2OFQtIIu2gRqTCO2u3FlG lddUUxPfx0KJd7AtACgP1wfU6roH/RJq7CVRjFLG5gApb/xmgWu0NULNaqyMWxhBSO1EIy1rZWRO C8VkoLIl/ZXWOhxXqeBpJPc6PehWcbK57gyQ9zdVm+WEhkOXSkgUVZ6J3TBAqyiq6fR5sn0ntOog QX+RG0JjFuvNOB1HYJeDeMNkDU02k5D0ehcdRukxjSs36hO7BLaQUJiz0Wz07cWugju8gGLDXNzb NmW4j+EGhcSprExk6jBJFUa7f7jSFE8tfb8DHiBQBk+3XT4vlqTZ6fh4856HYBR6sJMlABuj09EQ p0AMj7kaymel3R7/AtvnP4MMV8QJr1Q6A/YFW9VAHDQT8AMz4In2xCalQCCIFFiA4cwFBMOg1bnI yVRN+4HXwvwLBeu9f01/fcbHtYI61NQ1Az8nrRb1V1cFxCJpqYdOgMoBmZaloCSEi4zMeeO7Rt3R pol4lRY1OGVCu9DZfejLIqVWhPYZUaoqYYaBNPfg40cTz1+IjfuGK6rPbPXdE1VXDui2bBsWveuE dPFT35h2ifFinjAF7TDdRNVkgHOcd7KyXoMAUKnnGCPd/mKit4z/1DxwOWoTJkJIpAbKPuSfVqmB m5ruRu45BkO5AF9pfe5KWmQbS0mwIbgjuEJIlfvGyrHBZYpUccB/Vc9PQnGt3n/u3njsNWNB69xV yUxhG/U1KqxfF+EKlKRteEfyh6zaHa+9lRI1yhsrHHUoV9GH/CdgugcDppmKEldwzQodKcP9ljzP jYFWgMxw6P2ZYGwf8E2ZGZ7GftuLb7Ar5xBJL1iAQd+fXqCwji1FHHvNtFVXHtFvQXEKk55oVLPl RggHSxEUtw6lPdHfdpScFTNDF5mToyBkqesZztwOijSmfG4CjeHq51mJleMParuLnLD9+V1mEgjs G7/pJckuyjUVEpb1MI/Mp6LI9ZbwJBNNO6rrfYYxRs2EXWL1B2NstFkbgDFwguHiCn4MoMWNmhdF jmWLKS4IabiCpAdBem59yivSYy27eO1erjV895n9Xo5dL6KPNeWrA/Y2FCcjmimtslUXC3CD8La4 KGVzx4D1xh2yv6NVeZ6lgHNpBipBspjOmGC0Io7DunRa1riGKMk9poKVJH17Lv5lZz++C/W4ewlN ZNW2YPXmHU54/0IKMqoc8EfbWMbJhWviQcgqPC/B8Dj5aBIqqulExpL1I70lN8JoS1sgIM+2EUzK SOIVT0Ouix/okbzMx0g8VUxsFs0cTDBkdRDVn0sMcMq6H+VSvqxn+qnoBT2SP3a45VHMCCVb6spw 467mVJO2lJHATTxngttu1sm1aHRLnlhoqq2P9WKjSW/GTYB6euhVAf5u9tfeOaNW23UmBUBTDMZ4 KRpRdnhP4PyifB3Iwj+iYQjqXhQw0IXzKIn9zDfyM2D9cG5wSZvF+F3iZ6y55Lq2hxi918FFLcRT HXKTyFKD8bYlVbeaNuhGQbH+SBVHzFnnKgTZwUb2MAceNeUj+XLl4ukY9h83QCt+M4aZTRvnE+Ob NWDIuwqfSlRN5LS2Tbqtl8ZjBd/hFvOIDU7+epx1pLygCKtbOFydVhghRnh0i3FlLMdX5FmntFV6 pznS1o7aJCJ5QaKxMg4tya6m73fgIsOasGsnTjerFx4YVBo9csli5fVwTNumXl0R2dX/3LE9BoOC Wq3n+vGB2hZAC/5LNJfb2kVEUNLEzluXeLiMQuyxILIps1lhW1VHjmG/C534xbgmqAmufDL7n2zy KR+ItXfyIQWtXkSCgzZDBtHI2ry8GEcpdn6nMHnoCfxH4bP95jzaXgEnMX0AVVfs3hpt6zgZP6HP E03Km7q3BDIUioSAzzxClPblC7CuIwQ1e67f2fhAuoGrrlyOeoRRN7ZtBz86tnMgCW/7MOCJ31O8 DEvJ501eoK7boFFd5Bo+lKU8Z1gWVa28u+lGvBlgE3ZVzlnOaPIQL0ekrZPXuQEWHW9yPUhTL4P2 lftXEJN/WHORQ1ZPitKabU/ju8WsbCe5m03ivoXC7efnke7LLd85hplXbWfuyimSrNloC7haY0+/ W3L7NX5Eg0u6fVoh4JWYXZ4+w4PQGsbXDkpnNXBjC6fWhk2I/jBYXcRoA5KC93MpyTN6KiL/qL14 c615MyC8DC1PRwpnkDt7r5K5MIK6lysJeH6brKJji/ew45TRdoZS+JSFdwHjsTotX0TW6IBE3C+N S9aiHsrKpgt/dbJ6pzLMjnIfTsoegNWGjSqylj594rDHIpzQgE97b/ScoqRFGutHoxER8ER3mlP/ 7naOqmoYEuIf7D02ZgHL67Vv91tgiP4GU3nu+Ac6F8zv/XNtlKDV6HHtjf9CZTr7lqeQQpWuxeZc NFTaVTAzijAuFXauXs8nVLMLLvabeAPq6ao0jcuDIWwGoabQQLnWih0mmn7MBX1hMj67fTVgbVLR VDzBDeATHFEykawnyt8tt2Di/wBw0wDLADl46rtmf3xipXAMUw/yDAEG+zHeqO3EoQ3mKCjZ0c6l mH0nPhBKSv/ZXzY8zVzeMDMxl14iFIc4IB+byDQOAjsd2KUQvC+M4/I0Y/on9XC3Ld24+DzHtRMA Ka6cZxLb5TJY3r74606ObnO4KA/TM+vaQnFKKc2CiUUL4fs4NzW+/JtLu3OQgGHXV22Wjl6Czr1X U/jojr3ChhBQ57IEm2xYVQESEOl5B4enlcEgwUoUE8kuGQujK8KcRctRqlB6ep3ipn39h4saTcBh 7ztVQGpmGvqPzVSqv1SLqmgxp3uIeUlP6sBxXBeybSCGM7uhrZRu1EtU2L/0ubAaFPzvxi2tchFg Q/9+WfqNYrmho/xCWfMoz60crcV30Aq437zF8h2sy9Qmd//7wVJszv72cSmZIfWPc3UQzlqYdHsC MCtLZAjWcm5KgWCeWHGOUQdXn8cCRqTlBnnuPHl+ViXuddl3ugs0ZHtIpb6EyESvqLMRwnMiQAwB hyitidZRazyf8VO0IYRSXfO59i9IZ+b+nRN65Bb42u+5WbtIVfL0HY05pDMcLuZqxiOHVMFENTAJ sxrqczb2hmmk9tG3jgNeu42btQr6X6y2oczjoAy1Oj8ryo5zqJWFLWm2xXmOmz0k51GIDLLuo/Cj o1RRW7RN/6YFnhnwFdwFt5qlmaeUlXZ9PLV1M5pFIsbI2bIEuGk3EI8VvAJf1oiFJnc65gJ+RzIm 5OFnEVaoaq/soW6dHARelJ9+px5FXA6PzmySPphY+MjoWkaVNoczXnGTmGh31AMg9kyT5+kKP8lP IAD1SlBsDvZRsvS6xA6MHLF81UuSPuBE2OTgfHv5q9xUAy1EVmoK3DyQgUAH3LIOiPzGuIedbmJl 7s0Pbz4mhobcojIl2DdIJM2vgeBeG2bsjwOCwxAgfNzKYH/9Ry1v+0rpw6oBgygPqx1xOi3dfE7t HneiSi/qUX11XiWGJZwEWm4AMwG56gbbg2NqvFWW8XR+DmqL8Rbe8ka276Cz/X9TBN/FF9vs24Gz QdvEYsRlL15RScnInay13t/deH3+y/qJUqK2MbYQiymFtz0y5crQMYm7dT7lLSY01cM/7RmMncb7 f1ZCUcoA5p+TkuvDIq0pClJlm10OVCQS59fYVkt633wqkTvKZ0haFmLtGd8zDl3bM6DKWuhF2G2+ SFhSTamVQMgZ7sxNvaovbn+k8R+ui9X0I7nbb8eFqONBECXpOZL7mo1oVtRWJhTBz5xj/jaI5YR5 CvEEEggm/O7fe6ZJgKWSGWRBjXfGs48ejBkEy0EUFCeXFyVHMyU+1x+j68LqBCp+17HUpPKCZdCC F2vqewxogq+nuXwK0ca0b4wQgpyQltRxmhmoB2SrsNRfLUUZcLu4OpHNapiPuSJHR1a3x41NUm8D CG18ZAuALhfLNoMJiraDOTvaJjmGDdkdeodc6JKcGMYToE/nfixuT5S7bmWIK9CDp5lC6grjl3Ti uzkH7BVqPBiqOiKjabejyqasVDFOiwDXekDCtqUD4XiqTGc9YSemJqMxBaU3RwdT3wa5PTnyMCi9 XSLdCvVElIlW0Y++rjEno7UZXTOhBuEUo2HZq8N7jRXHnQDKVMB/820f01WETH7cL48u1vJUNKRE rcTJ1cvQdLxIz+RgnHJMfdpR1OjAiAGe/pFzq3tT3D0CpfbfEnskpCIsZ7biruKS7l809OkYi2ob RIXXlLTP9yVfBVm68CHAlH4E90A25uVdsdCfwfOH48iE3j7OlsmzUcYyrmZjH89aV1dUNk66X6Zl Hfq9r/pWiqQVzdvZXVZ64KO0EYrxU+QD3iHEhizZflrbklS4r8E1nlZEJjkdIfdcCzn0V6MbWzOW SUpn0/ohwDrff0nOI0s7fXZX8EEwKOTmJkol2LJI9rVooeU5/i2+v2ikMOZE/GzmFjZ2cDsa+WD6 IdlMRY2PLAt8svcHoYTXFxUcVi/D7oLRtY0mwFifR0C/itUBioChtjFCtFE4T35Ycgv/jAYORStz HqexIqSarGZSEXFRlmiTX8l86yqMj+BtR2bxdC9lCOKtG5R00xP5PncIDSOmGqqY79IO0SgDtTJO Kzb7csu6GmWN6Jpwiwg7hvd6zDqXd0ASEexljiFt3XQD7c2YvNupEHSEJ5OgI2RnegUVwC7Ykzy7 aiPY5Whg55D7E2NcktjqcnChaBQcQg38biBVfAYqKqRgeUCon59M5idhGWz/cWsXLn0Th0/DTdTW oMSqzatjP9jWWZc9Kp0XPoJBCuhdh7JI0LqRy8cP1qZQ4bIhVXstof2eFwFEN8sXeWDW1Fe5Gs7+ 9y26Bz95AtH3e9tVoyuSWIDGJR6XEITty4JTWXe1HL1OL3WZIrcQF55mqWpngHwfSmzZIsiUmYN/ tfC+5tuHEqeo+Mtpi1sgY+HqwwSpZTFyVKxKs+HTcT8Ws5Lo4n30624wDeYNO8fV7IyhPhiXjuL8 n0lWdFuC+pARhfWmTTqm/tjNHACpFCvFgnK5t+YNzA9j96yfvG/QBZUBBl43h8EONjaDfpNRlKko IgvacQdQyudvB4ggq5Y5JXVz5kmW35dG11TmBeicQ4F5pdIbm0JLoMF+ndG9jp6oPkCMMCHbJV9j XnTLcsiB1CeVhl6xQhTZxN+puZ5nE9p76t2rzSCGma6F+15KShpDm57W0CUQWQ8jW+l4+ebHogYV nUw9BFm2EfvKYD4X7j/KwrE5gWZxko/wOCTGtwQiPQl0rcJ+JmoxBbdCeG8rvqVxBDuGq4DepOCV O1qlLOcPJe/snQy4MRyCGhLfZJG0iuOjNGFujflmAddV/Bb3qA+3DNZQZybVD2291YhqUgprnUoH md6Qtwa5/fAD8BppGP475E0ieFQaY0GoP6PSyfi7i1vy2Lcewj9nb8zoRKeXffiztxq8E3nIrTME Lp71SxtPWmNRsf26zHKd81FvMhOS+MzhV107OeY6PMS6hiSDLwTZVaVfo8iSkZDFKF8BZ1NBM7jj sQuXS0qhHiDRFq/byNlEuK3Fn+mpH7i5pI2dv2I5iBxu6ooVQXXYm0lYOjt1+1ip/DJjGKwJeL4L OVo8dbuH61ANd+bP8cKA2J71rxJ/eVMcUtzern/0CU/uaI8SdFMxJiWa55S1Z0mZdr+NMq/zgHWb fETbUYxx9heYfl5bj26KnJ4Ih2eO0QpD6IURTp/DpAoWUz3qIinFaFvMxoeKK/ggQRuOSNME2wsm eGjHkaKL4A2ZcMuv+H7EMn2zAkZ/EZhca7IX6fhi4wb2b740QeRxdth0rktvp7q1VjpUVsY27h4M Y8U3VPkyTr8aoHcbbKhQ9jJudAsEOVJlrYPkq4O2KnXJWWiRjfJHCkR4LzvV9P2si1OxYIF/aE6I /ic6ClX1Wx6BZypO924frpsvMR/+48E48Hr/uiio49sXWaAW8H8Z83/U88GzuUaB01uHZb77pXjP HXbF37My/HFZtnToiN+f/POQjv2/CGypcrBYMPNzmZVU4KkbXOJxCnfGsy4tmrdqPeOmRbINxLCT XOxKVZDdwOTFO2Kaank0fFICb39SXX5zZIiqOBEKYZgWgmhqW/B+tlYhhBGD4fuC6yJYvf1GXUEM o5dK3DR1izlAmIBk8wVxCZazzyc5NgHiOhNzo+bEm4M0kxMzpENg19UZNpRqHjiCXb+MCNERSV1H 5CfRlrwzhNZVBawDSxXDKmvU32uTby+7mbmIsdz+dCgGvwRrguEXB3igIZ6JZb+PZ/i6zpQrRZQ7 +KZlzJgCVFrdG7EZrCnSr9pUXBpgK3te8Bua+FJMdgEZyPAW7mHGZZZUUxuR/IZS3WZhobDJCuaR vMdYlWOcZNMyxaYJxgCSyaQLar8ekPeJeEMrxqJXKgkOlga0CqxTVMBiakxgnNn9UOlzPTrsWMhw nPEUsxAJ0H0S6uO/4ybtdvpJWEeDNMzxpatPceR+oS66ja6QviLbf+7J4FY+Zpv6UPyftjUQboN7 jaGZjsy4gb7813wDwoDjUVyVAnn6Wlypw7YfDWXuE1jJz83/xfNAiGJY9Mcqmefe6+LJ1zDnuJaC 0DA6w0ay/sDklFhCOJhXan7aF8FdfQ5ur+u1Pvv6Rh1GA5MWdhy0l0aj+oHv1TXUPp7B2MF+6Ogz Dn8lbRD46VMeEEh7c2CUYbPspOgn+6iF4G0FceyDZXgxBGjTTStkRIniJ3Hc0A0m+qjesSPcQNqe 6nb3yTL54EYcwRDGPUpHkaEnhuQFfGgfaCnMuzE62CO2RXM1Mz44/Hiog+qtJQ/hTniqkwVpkMjP V4z6xXL3rb4yqFfgAWlfxO4obS9XbocUJydfbmDlIZpeKNlzJNMt+syTTcXh6O6Iqf8Q9qgDWGGl Stsd1Q3MXsamUbl93Qu+e4xBhG5XInBgtVJRITbDLwZJwGENmswfaOe3j15rcfiFAZzneMGCE7Mk xqzGYJWY7Iy9PSplbpzDC3nqu8jqn8mtNv1TNfBlWi0AyfsWh/oPFEmbLBwPUv53FglAC1xOGIMh sEzSlgmr7jsaq2uCGPfoYNTyqKyTcPpA+AabB8fSU/zfikMe70BBykm0DGNbxt8pQLepBIr6L4fT hlhwTr7nmY9owopoLzbus38KybleudO9fNndHIzMcnq1Rqlg+78FECAoleLL3sOaqjJ2Pf2+zm0K UCT4BDo0u2uZibJJSMBsYJylE7c2FDM2/hFq57yUQgYBEtlzfAt9OHeD2/0ZeaIC2HvyQfp5wpVS LVxSiM0KGnXRA3AInOWe2T2JKn+dl2JSvyYOaO+C18xdUiKffRbXpBbpTG5t6Dv03HGI+rEV214f vpsQEl0388Z7TAaWd0IHxGOF16eJtDHf/9hH2B389VipGyuVr8/COHVGAJNNAqg7Efc4u0e02BGu r2FXqpQ0jo71GnPucGoqScY53FN4Ki6S+RN8+lRAGrVSifXh3CPZxj6VspGio+AB2iIatajpjIBD 2Y/1feI7fotxKeiMsoTPiz0cMskLBsU2r6o7bC2z5GFpo9tgGI50//+/rK9Ud0loErh1YqvNJEm0 /4Q4BX8j+avdIJPctU6jXs5aeIbnRvtX1NyHIwbPGRmE1queZV6EdBe0acaw2rz/yafisQiuz3Ph 0QySWLCAE1F0rxQ7xtHEg97RQbjo8ndwwKIezspon3cpiukDGjKfeHI1PET7CkaLN6i6wQcgTTLL sElCF9++551JsBIfXGBVAn4YMgC7LX3yJLlMQKQOYVg61Pj55Droi+3lIEOfoNabHweeObIQwXOX W0FbuaSnK7/3rwkRlCDZ3RQH/oj4PhJKy2IsfA7EpJ9lMSi7LRKtpXH7vClrG88HoAuwoMo3PEIb LX3KFDSbp/6KsDx5RIykdLafvaPFBI46RmyHRfjSJEzbLVGcjsPz+Zyuk05dsTi1Ye8mAv8RYw/V nlYpYFaE0N912Nt94IZCYsBBkDQTtJGJwVbXYXnDa2vrBPsdWma4J8V+UUl+JHDZFx5U34KXQfQg huiWAVt4TXP42MOkASjgkjWQBjXIKr1Wl6shZ06j1VqcNzOwqkc+KQT9mgDCMkO4iG3fKQsteZ37 wCDWbnWOosr9feEdbltoMKVz/MO9eieqGOU+/IScyb0YQogRb9peDG0NAEWMP7T00apArFZtWoWp NB05mdAmiNWhAp5pwF2Fqp18K4edOy0F65z1Wy8o8+Osz5M/+mysyGR/ifzH4KXxNzVCVElS9GdP 1BNtlU4aL0Rjp/1jNdPEv/wFJ+Vuw3QhOpKtwokjph9HwxiRu8NDw5nsvULdT8XECS/kjk0cL9pf OLeW1H85x9xqWk9pEkTfpqjHSJYHtLmKuSWt1b2Xsbx7T7Ux15y1vF64GhPqUqXoCC7kE4JH8Dm4 hPmdNPoqeGy8p8OQN/58yP4m7PtixbhRMG0Wk7QLdv8OpmSKyfCugp0cqVoyBsuUntcuNp9B0WN4 Duwr6KIhSQu6ntx+PmBdZJbPlf8yG02RD5lTuDZpL/GFstQh1Xt3U0QBJb2nGTtU8KlPpu0NR37C xPVflBasmxYOpmpYTHiGy0d/SlSPb0EFnIeHEkx5YHFSsYYety+M3FLvTktuSiNN1nExK/Xo81X+ Ww55UoqrE3QGdks1pEciBpzmzeH64msaMUN7mnbf8t5/ZdaWrhJw1BbnJyXLf86C39uDT5pGcUuq ubZC24tO8HFrfW+DYliRvRcortE3MdxiLvXvade1Q+bA/TBC6Zx4nQ7dsIUhrbkwQLZb8MbzsrEm rXYl3Q1psVvbrND8oi+jVr2cCpYzQlfrq2FpcoA/T4eYfGi1PSH4FncAZIpdAalAlWWt/8xS9mt+ BjJ4fs1gMHriYkINZ0BDU08zH3sFFB1Mjs9H92oqmz/hblHjADLqdcEO5iHOt7RGCKJoyNytfXC8 FYQWIvO9SHXINwboRppl/d2sxZhxGzxjGyL/c+ZGJu6e6RlRytHbbkYO97+XLHVZuDndjjUV4D1t pUnf8seKyOrBTJdmcg4/+UOEFgGN9jgM1ypL9K4eVbUUHNiQHSDW0smjlPAnPqWn0OZHNkz6YOFY hirkQ6IzknVk7mWAZ+lpaMY+ujpJlTTnQQ5imbPdsc5TL90QRJgMeGzm0qA7wl5PvMmu0DVmIrSB FtHoaVPAbK1GHmMFCvu2WUHczrQftq4hIAHwJ2Y41a07qtAX9Ey4k4kDp3dnnU6JlA+KTEEhuuCj +TEmLpOvd+7a5Nfbn7/GPPDAfPEqF1TaeBaZfSmUC0NxeXxo1hTyXGym6eYDZ/4yUhYFImfZm/P0 HmveQokqhfxnTpRNiEGuUZwOBoygdz9KOFSTlmqYG26SbCDUEsWSvTWceSP7xfrMZE9LYzA7nhT+ 9u0hIuudn/5r4N/psAKVAw2q1Umji1isA9TGcU/HJ7kVHjRyfAS7XeLAs3lMsZNbXPk2oNJ3JRQP +cbZ+xDgsnHEZE1kjRd4K4WWOQojj5CxB3QKgffLwoyBA5C/i7PnKAsAuFquyUaUNqaRi36E30QJ LKJJ30jyZ8GaY1EE2vkUrIPLOQULKYbwINNud5fo9taXevNLzBH5LZKwATSUOLFkJBApmOLnoSTr i2nykzRC6sDzAOgFogKfS1g66i/KYqXjfI9PLxU6EZB5vARjU3WHeYIlOOK+BPi5Fc8x1I+id0rW w8VF7oX8pGnRTSNORXil7b2rgZUSNpx26SNwsxUNPVNK/Zj+ypXDDPA4F5ndcMcFr2VcX3jqbSqS qR2P3SeIxCxhYVaEnrdCufeJaZnbnsy0/JG0IblmOiONa+nsg/Svy08PlGKP0Qd4jAyklaxsStQM qrEVptkJ+8MRaWg5AnvHUNotf5t2sdpRT/e+40MiCkRc/ejpbtljlsxxDNfEYAuhp9tD6/HuxUwG LrEANlMJBDNECDoAfVw/JlNJc++OU09LpbwIC0hrov3klOQqzokDQ+4RnsKevTG0kWqP6JB4T6xv bfSykcasxi2ei2adMl3S1dp4rYZFKUWjBHNLVBUPQihuYYYslKFEK61ekZtnTJDX6A0AOK7e0ada 7lOdnpQoqQooIPpBueFEeUx7UWq+leurgRw6f2IIgU5yVKtfW9u8iOlokiGLgcerUzQX4gDW/avT vNmYXe5l+lvZegQkcmS0zEZF5K6Rf7QxZygrQhyb04JmIBxfNNARF+NXbdLRWYOukhYfEY81wWpd MdtDQKVawexg3lz/RG0AGNZP9NdMyhtktNrebjN7qgmZGWBoUPmcAsyxh6myl5arsZVetC0rkYRX BpBIWr6C6HtpRkb1HkdeqMvVP1J/7WT0cAF6Sh/z4ZtstY6PKmSryWuvzI/WKY9xeVbQfU3r6pTQ FjVSz+JIFU3BJvQTO9WtQr+P1g/KWBtulhdwfey2+oAmMRwFq6si6Lkmq9UUr/65wvXWMOfeRXtp sAtBjbbyfEfC6PTXK/iPoMztpQyBBWsoSubbe73hjtZ95YhoKebzjBvm+td/wSK4hq1mDlYS7Ob2 upIiBqUwsWExP8tommldLCMTq1/SLawK47mel0hk8+TjN5km/ZBhDXDAW4rwWm4hMuSkeDoqxBji HJtOyizWxchRPkxFzqvo5Knq2HJidJyvTSD+qNYhQoxp+2pyBfZLorZx+3f+uecKwAkqGEI7/gQL 2RB9yQjFzB2CgqOKVwY8+Tx30ltZ8B4PCG+W4e4lG0qHfQUNVclL10bpsSkDUyyORt5EMXO4Vvbu IYrAt+vpunOsSA0Ww/PM64VakNraEDF2oRirAcIeGO4gX3osfikJKikGzMsi6WPwLsCPsIt04Vy8 UZ+BJ1u4uxaMbE0ot79FnLlPxdOrurSU0jde2qbrKt6gHHUjpAFKXYtLFUJqRQDvRtLIIX4vSP0p H3j8+ozvE8FJ/lELik7oFbfOSpgK2RfW4RrW3iIzyTeCizOCZlDag9SXUbF1/6z5itOGeKDRzX/y swIoCzJVsYfxkVcabMQ+FCpo3KcNSUtIff2NWOOUIJgeBvwfMBC/6G5ZjvH/Ps/bYQpU8EaGQXK7 QHs2//dWeb6hsWQjDaWtfWwstEqlho82WaTZy1T2jaA5HyXX0qaRhRYNVkmFY2pjw3xmyy6yjrDX GC7XL/IFKPt6PxTMYDmchD8hyH1SSpQpeBIt7Fy5wRLDRzmpvnV5UcL5Quq9XuhgfR+2EpBLobEq 36ULi1PUWrGVnbifdhiyZRalagLn2j0eKudZB8LecaAFPFhbynewioLj6C+89huSXb3EMSpyR4Ga cv6KxmI9mkam7InrdE3V1GZhQW6y9x9sqZtHh+TdoYdDn2vI5Pw+FMsMofSfc5KTl2Mk6/Gprxwp 3pkTrS5iK0e7XiKyrkZTugj6UsQaUEnKnzs+lD/M1/1yvgdofcbFxBT5lrRs+pq8C6NYkoQUWBM8 bFc+3Fzg/EaF8Uiy6KejfdYrOBbMYQbIWjD9fwlN5IP1flTCoaEgS9QGzkDTqtXCGJUADNi8ePrV +6fWYCwWncshJFPU5y3DSBAfi+OYWP7Rl4C762465K65P7Blk3UX2c7cfB3w/YSisgTZFf/3cHTG eBpT9IDr6M+0DhTp8o3qBFy3WfywzsCDr2SjF9ohTLWDeggohYbTj6NsE0eo/HzQeIBTHR3CvdBT clJKA9+CmhWmMiPwP/U5Klrvdn4FB6MW4+qT00YjNbDxx10fgPKnw6StMGjcOWT+PeIkehQfe3ej 9sGmRHsIPrzIZl02d6GWUqaGULabiaeOR+yDDHXmWl1kc9qev/LNA7BVxrDX+7p7nZtmi8pOlXhq SBIRj/oOlqrEXIVZO+WZTW/EvWowvIy5vh86c6APR0LaF8u+5TE+JM9CT4C9jTtNPX44pN6PIbqP qPQcbYL4+Pc2354LOGjYphTm3+ndJKUpNtsEy/e9gcUXEpjejsZC7N65ZUC6eHY75excSUv65Y9w 8g+fyHkfYJl5l7ZJbt+ZsH0c85rtmoLlHfQ0CFNDVn/QfTzrhRoJLzTwbzwWZ4h7WV1EftfNh35N 8JG3fm9dhqB1fVcfEDopP8A+NbQBptWIXxyYoIJ4BFyhueShJRxpgJDtnu2uKGsma+dV1H5/5zUp nHUUSULQCdhSsFy+BMc66qN0ztIWHk4kJGEUs8dPElmRXnZvP4q6HmDFtEpOW77QFeDp8EoI3yP2 6oVocxZ+Tmteur6hxEU2WVB/8q8ZwOXddkXS6+/ThEQn+fI+p+5Du0d8Ea7j68CPpVmGeh7hc8S5 /9/a+0bMhg0U2yBL+So6it25GTZjFpOykn3zWOlZ3tK4+v8SDLu8Wfr8fAHDYRVra6JgyRc9YYNx 68iYfizPXcd/7BPlNHPCEo6CTXs3vKIXzcSIMMeTg5xdUBy1rXPCTxKJfGEymPRYPA7PE4WPJYKD Nli1HSux/13xDL2CF7Pqs5bpOI+EquhWn++Ta1qHzmkAOKJqhgPTEKA0mGCV978Fh6acjn0AdDnB xqIm9G9hUGa41FVnAZyb8TEjJAnDNostuuTRjC4Lh5D75dbrqwsNRLtKheG+GlYX5A0AC123jALE 9RF/F7Wn3wP6VIGgA55U3rh0qu3owdzCjllfVYx/MZ2d1OB4mtXuTx1WWgyBJFehnYh0VimVrfaW kCBMwUIaZJFhGXIxGGniM3eS4UAyOYIOjZ/136ESD4oWuYycbhKpRls38DJE0HpTZLN1CQogj0TO Q3nEDlx40/JhYhTMySwH8RPKfqhLJHY8WYj0cGPrh4FtvawD1hJUnh8lUMTRMJNKy11GUKzdmK1j GemTWmJdu5B0WO4er5fMZYxfNW5xE9TIXDqg476wP5dm4hZ6hqqjfPjtmDq70BGCsQp/jkoANNKF hiVNVmKTxgcge7ERfTeXUwOv/UvEGlKr8/Wt/XFhFyd8SMcDXiZneNLBxoQ13hjU+OmeVDJKn1UP E8P8deA28dHc5U0Ir2iymAaAlOZd9kVG/mkt8Q6/Qpi+yOzgff+q1MO4ruJdHVc6NppvRRpX2fB9 cFl7xwyPClFZXpgkSceSa0hKwp557CjqHh5EkidVoAZdy2ZFk7Rf4Lh0OoV8u0IRspqix3XdadMg 8gMuyWbcZ+YWiFPlB9rQnu/JZ3YBgp/ImaOVblG9Pbi2OBPYMlq3ugm/RCJ+HY9fJYipMzdo0Osc VpYdbR8tU4YwrYcldQ2XpkeCWa2IPDnSGCx2BG3xmFppbb7flh/8ofZcUNmpfTMuoOqeJ4bCxk5B huwF3zUCO+HC3KpQYOYRoH0D80v2o+X+xxYWUdposobAxLX4hQOPZAQVCojJyGzh8wH7Id7DHTsk YId5wD1w2mLTBC9UPSL/Nq/keLMY1RwMj+nch8hUkqIceZcL/2cLze/h0F3S+dIAkP9veh1BJvlI pupRg0QWZbZkx8abkjrxTYDW5pQ0AZDmvlWOTW0lZJ0Yz7JxGmvvjkIWg97f5HFeY/ooX5jOJAto tU8LmJfdzOgEM6lmU++84Ci0PB6kzvMGmleju5x9YSxbdlgXz/it14LN1no6fAzNjEeLP8wxW6S/ wNKkvhQ1lIf1DClDiDPnt+f5XJqX7v4r69962Yp6qMpV48JVscoc39NhvKP5RH97r9244OnffFzn hwPFRz1Il4NXbllBTwSP6pliIEWTZNpVGeiaXyz3jTwHnU+J1892bLtsMXl4aTs1WTB13yfKIEQH qyHKXAbKOfHg/Xja0nzh/cD7eJ0NXXw6xfAO6f3LgPqVaaldZww70yE2DV1z/j9PDUEVPMmxnlXS RLqtjrMWkbC7E7Tyv0xvsX+KpLpDrXnI7MKdkMNIEyDgQEgt3NTpT74LSQ+vz6Y7eHqObbJCQHCm NMP7V5iiU/N6gPkOdcFPiMeYfIt9nD1hmNAGzaoaz6D+F0zyUtP8TZ/Sg+EXAPE9e+AjPvDu32Ow H79wxmU0ZmzKwAi0wWUwUClFhpWdIzzw5KPH9CWGty7uLRyJP+KHn/nukuCe+shvCxWtlpoYzWpq /qb0peldby/embPqvz5pv9gUwZXrTKBSIkQXHkUevFOfsHaI9B63atFW0LZTEduAWp1wq7aQoJi8 Qtzhafc+Ijj6ZTIVrmZ/ivSJfsUYZuvnkNjF/rPM8ZzAHP+i8lggbPnsGKKzN2840i63qG0XF1dE 8na6HeGrSO4LAIzXlFnB1/tcAesUbQpQbRJ3+HNsGaji8BfUFioa32xuDxfpaEMf2GdRjavtNOHr pdFXkcDTftW/r+wSw0+9NHdKbrmjmGv8eFbZVIJvLOFd46mnL6saaAsBE6WkKM9F2/50nKdYxz2l VqEugIPcDSwan3fVqlyW0b0bB7H9WYz+sqe582tuLcmoWmJ1alV1nRL+qaLqlNf4RCZniIQIlA6g S8RhYEEyMOTeE5z6tKczzAX8tY0+5IMhsSgLe+po0efoiLqMGnEzHFhIHVzZCnF9RySFuSHU2nbZ uH1cb8NkiFrl6zUOHoKTNAM5Xxzf+kxvYRTexo724B1xd37ytFhXtSm2iE2W7eZeXgJdmam3sW6C PY7gAAnlSTFOUCguU0yjzfDF/pz55/vRnGg4vwN50w78Oc4WJlz8muPaPDUfTdCqzaYmB0cxkv8s iUyfo1MEX5K052acjvScW3S8Xvy8JL1XAYN5tw51XtZtc/Sqk610OIG/TZS6Pml6uv6lZLJ5vj85 hxvpvbF39C7vCSJ7JbdJAfCk0aQzW1s19zdJCXdgS/cdJ20Vd+nGO2nCxv+RKXQkqjzq6+Pc9YtU R/+vnpMTSG5ogUC2tjobyDRFSDvDjhNPGrYzWOMP/JixlIqtaVsMIB8C9nk49iU97CaZMahXdHlv HWTZugqT47Jp/+iuolzle3pUlV0zqnPiF3ItufkrgG8tkSL1fm+BJAvGW2LzNY7be1Hk6HcwJXnX piMNsQP3cs31oJJ4+WkOH3BB8TcoSIzj1pb7A15SCiGKB5NPS5Og7ASUxzG/bZGJpIDkg8Fpx//Z Sbtvg801KLCLKXbUzuJvekvL++IcFV2PoO7TOpmIRLFSBNTGGZk7BmaYIDlj/MgDQISLoEZ9psTe nr378fXtc7DKb++XmQceLAhCkU4OklLph+3nGQTjVJ6iZnFHq9JVaDwIFAT8vJXE1c+qPk/QNlwf hJPA4jRbtPMlLzMeSgfrBSsE67yny9m57k8CCnK7Awg14vCycT79nlXe6spGFrcQWqgi06CocKmA T1WO7QgTNUNUDODjrxAUxDCRHUnW+GPvCsgLFyab0dwazNPYPSjZj3fDjkwLkRZ4qdKUKjY+WA7b 1mrLvVbRtiLM6HmLtF8Hr9M1xgRR4a0Ok+jy9D2v4hkcZmpG/0brp+8LN70V+WCBAYieRNbDwD42 Y9oTBqAT2o5JA+p/rH6svo/ptwsi72yhTwPd0tPPgtGamDNCY7jrqEGbF8Fc0vrkfR+qSG+ppNu0 jzYS6RKbtrOiekoY4UxjWs1q4CPhZdcBc9e4YGvVDdp8e6ty7l9xKg5eUWRB5TQyLgUTfSL9QQ0m 6t/uKUNjLUH4j4Orsa4m11sdseS9pW3FIxiTl/fHmhM1EcleJbH8+gpABtDQ5ltIpR/m8FlZ6C/s 7UhZpNSNwK+p9U3WBI/G+nOg+SqNimgdYVBYTtIj88UB/rE5vccnCyneO62ank0IrFAMrf321g+u QLTFyYPHrQkRgMU2EHscftA5KaLKscPkVt1YZ4OQlOmZptdPvKJ1Y+Q+CNmz85+NOEhxKQDJlKcD YGfypphVcybJ0TEfuhedZnokW+F+yCG/8wyt5FXq6iX2In8pKDBOTHSh8xAfMvkRI8PsaLHdaovE Ekzl3bqCXZKXHjtIwI4y5CYMyXDWBWglrTQh4AAOrYq2E3mS/azoYM0GRzx0zJpAosKZ0c0SNn1F fw4NTa2LYGxmjLMvfqzz4UaT1QoNC8AaEH+g6hhQsuKHRRwoKsTxE1yYD9GP+NJy0Mr6VGxnS4ah 5tihKjU2uCRX/Vm36CpnxBuqB65GsGu3iWdM42d/mMQekgAXYkt/i3EcEzczC4fjlcjPS7l2/kwd K6yRbkcg+eY8Kvdd70wuFTXxPmR/GTLdSzAZdWD/+t8EZ5O9Emldf30wyPSWZr55kZC6m9I96V64 8P9U9QDpGUSbP+UcB7nHOuJYz4NWhNsOq18owFeo9mE3FKNf7r9ZBWFog8l2vmsv6Mo7IBfE4iLN OwjXHriTj1udgfHeRYs7bIFIrDoeSALDA6B05+UDGUCJWtQRJgQqpUfRJjlxOMby+bbWbVf/qo2j MK6+OF5c9XGNGWkIobg/DmMhDFXu5fHYc/x3KSSmURdBKIeJKrHYhd0nIlOi7UeuAqMiqWNr+8hl UGl4RxbSg7bki6msJEfX8oCEsYAgFdrLgyuwZ3LzKBcH5iHDbEcJcNDjkSdbjVcY8ys8h8gAKwMn JjZGQdfY6iyKzO2Txg82ihqCyUBL4fdIarau1i35Xqj+39MDixE53gVG6w92XImfcUfu+Zm5eRu9 5y4satkJ6Oklwi89cLo4w9kjj61qN5PUpE9NNZzAGlVxgeTonRoSg7YoEThnRYfXHg804j3rI84I WpzaPZUdANhvxyQfi2F4e3XdECbwlwWUBDVeSjYzOIAfzuG/n5GatfktfKUqkcjqPLoDhL3kN53u uLluSBNpV1Br8LB9G9Nt52YsRSS833ajp3P8Z4zYLMz8WMq6fhaiJiRtlOzeoGUsXaeIrKRlhNlL +ZlcHLKg20Y/mgFbvCfMAR4lfn51xNtEl2LRxXKWB36Nmu09FPD/nVjmqk2lqBtq1k3jJezvpM6w u4Q+BkCzou9OuhonhTvcVU9tpjKSFg647XgXnnI21fgsQOQnRvgeF8jqLDV9G5G/LPmEhdM9hjqA rIXgHc73eQEl57NpTawiKmGGASPD24vA+S1Ph9DDSz/ExDGV1IJzhaq8z95CCnhgxiZp5Hxo9nQD DMTtufeJAB7+6ob0zgtWraiiznsXYx1jRpEufivsg+RHGADengZSD+XDIWheiBiQuoWma3jeG7kT EQEtmzhsvYs8sIyHttHkIpfd/9a9JNEnovQY/MTsQtjDrNEFg3RKm/WeHqgEwQgRR47vbpoNdC8k ZZj5V0iwwiLCywDTw/5N3VNK1/JX94C0+addWq2on6r4WizqbuBY3wsicQSMJio7xuiELwUOo/TO jK+BfVIZzeoGBfofUVxcNXd61K6C6ZvlcJQ890S2IU0aTXU2JBhanLD/pyoznlWdJszacTLWva3/ NBzvFmI8q6BvvLK59PXRAP2ohp0+VrrAzY4TvZ21Z5zC+wcMXL9v10d1CDtpcAhWHcfE9DDE4Ecn 8Aumy9J32hCYxjc7aDml3ZY4GN9kmwRw2BltsTJEnEQ1SYjjBna5ZZs7LLdUMyyTShbIAGoVQpGC OqiuM2tS5XHHEBn8BpTDJiPQPp2PpmgOFWmphXNVSiIAmMBQaIthMQ1dsYvQVLzuftmsq/ahbVoP jMdl+NZzxGJcpYvcf90gZGE/GKh8oe2gk1H4ILOY29RWTVZhn/iECuNhXFj1SEIirTpcxcG+Zx+e mf1OBLnvFQLpxSROhOCwMEaSEqX/+sQplJGS6+vPnPN2Ckd9z2RrT6YJNwNr9xnQyMsDp4fEUf4E b4uv4TuCSUGIzoOx7F/koazRzaBkJVXoSLq9K06LW5mMgDXqnfGFSzdKnqSwM2v0CVYdcgPaZ+u2 sHBm++Uu4rt/DHqyefF/x9GUYvvOHlEcEq9dMMNR4fsOD0SWAFVitaq70x6cDItDmT0POkN7mC1S ayhKlvhuvZqYnvSxoiwm18PYgjw34FDwoVZW8031iF349jHPLKiBUJKH1sGFpXekczlc59Wc9jfl i0d9utWmZfn6hMPFimrL4EQak65RfMIclD+6Yw1gis78MAJGIopOJTdQkHph46Y6/cTHTofKHQ+R 4AxxySAKTsV3G//7mJu3GqXZ07hwEO/XI1rJfhn0dCQDB/i1Y16i8gy8VBT60zDTKXmaCZ08mTBL X+1B2TMmcDrqXXxXcJAfVEZQi7NsW9qfj/cAMAuJf6ikdYCHzLbjfin3hLM+/xyQjJxKwiFUu+B6 XghrMp5u5WVjiK9sRc0D8UtG+P1JmKMz9CcDHmOfjSHq2quudRMO3W0c14Ti6CFk91pkvRqWDh4m NeIZHmB/H26OW0ljMkOSmckQ2vwf+IHNqAmbMsZOoqX9I3UUX6k5uMzTvNbq5YYi3lcEX3oF0nwI L5dhIOG2lg15VGhSgVQV8b3rq7C7cD7vT2eH+tct/x6J/CtdXHcd/cTC0JkTezWdQkY8ZoNR0qZP 3bfExb9YLMwfDakBVHDF4p5qk+cDQyio9x5VNjdSC03gfmUqWaCA9P8YYXQeEOrY9Z1UQud18ToA NDnvT45K6KoDM7MsNJh3zM/Z0jyTs0n9jIfdqhJZWncB2cYp1iKpEriu5zKOqJZpFtHnXE4MA+sj lQ6Tcq7rwmQavFCvS8wNyQ8rYawlY5OI9tYJrMbcRyhrxgvmLsycqv8DK1KpKgIt++VTUcpzDEfR 9Zujutn8BBeKqkf1vIfY5wl0bKhP1bi562IUxSPLTDtOhevKb1w5QcvM1StP2N+wjJAqMleGvW+L tIxyCIi84YVpJDP8xIXmuKT2VUh0IKHWP5TuWUW3B0gIqNcAablqS0RBoTfL+dw6u6UINJgfrOyA FKKIy/fHLcMqaCPUBgI5LxSUxqfrbQ6SrHac6xKz8liunYSVcWEfPhP6oTvVlSXGcwsIQOpjIY7D 0tiKluDYTszEjrpoxZ3Er6L0tpcfv06D7NvjPHpu4yu6bny+aOWS1MMh9v6FXIcXs0K2HEMAyAAZ CHl9WCDyvlUiEW8vVOTaaOt8ACZSpui3BMyqbc0A2kZ6A1xP8DK3i/fK0irG7FzNd6pCvVMoRRow i3gJCQ/Yfe7j6K9u5afo2JnCqDXkSUjcI4J4QdQ8JDLKK/wQ7sD1xRocLxi0Z2jxvoNtfqIM+XQx toA5jJoQ/o9XVNSer0YFvVfAmUqhqJ7bO3NDZRqaDj7FSfwkDs56cJdB0fKt4ZjJxvkwe6BF7H5H M5brGF8J/377MLjms3VcXST8NTfawKxOkWCH2dSxAeeipjsIZw4imefxImdPHdJ/+V9ovn1X4PDK D3wT45fbr+bjygHwVLrOeqedS/FwXwABCG7w8Ajdl6zehws6CZWO8dUlsR7CG8o6Y1+fey1JXU7m Zm/AAPEfddaFC4lhW8JUUHlQ4lDuCD3B7IIs+9Mcy5h0yWk67KQwrbtrzmOstnZ5enUROadwbOPu XVIVANPkUagZHopgidL/nW9ju9E+x+lZL0zGyeRdnUqRNw39CIooDJul45XT1ypKs9rSjq1bkJoZ ltMwtHqs51GvvUxdDxK8GpF53XHixxqblkqZB6LrhgIeu1rKRTWn0qBrGM/CrlDvH9SCuuF1iFL4 k55ixPGMKiOZWTxJQwlkUqwLwVYIIK/ngnDWh5ttVwZvdNz4Z6jP/l2xTVKrW1iBDcagmW3ammTi HVUBG4/JRDOAEUMIolVWuLfCs7zt/YZ2t2cEErx7UoiZBaEy73+AfPcEPmmO5zZMhfhCMEFQQrYE iRWNyvBfOB2QwhXO34TwZGwktu2MojJF8DWQTRDr46RGm2ur7oC4GycIuW7JqHN9VJejSom5/a2O jM+0Uuz+FLxdeP53XEG9yHycC5/3qtGvFCQBHhMlmQPJx6QmnxWXwoJ2GBW513xOedv9D2X6G0K0 IzCmotKe2zz06paCA5FucW8jxrBX3xOD8yQ1EKIW3bTIX5KCPBftXuQhUc2YZPLKCDP67qg+5Gn7 vSc/+oH+8XUSfdw4y9+dKxb/UuBjNetd0/GvH+zwsxcpk5TfUfxkgcjJ4Zuxh2gZ9Urr71hUV8F6 S8JsB+szz27B4acLl1a+Dd5mSIra/OOl08+WCchxSz+PNPPbwV18cUF5sxNWUp98Tm83UE7WuMOE 5m3DR/d1JZEarbrQJxGPFhynG2LOaHI9srQBg3ysY213ePZUWI/hhePIdzGiJnv45Dh5/zjmYdED sBDVrpHpq/ElXh+2ex4RUiyO2uogReEvz0NPFfxykPivys1OjGlj2WnFsulEy9xmybhZUgxSy/WE jv0VU1nP8B6nZ04/SU01UkVNJQbZVJ5qwCOLUvuGXBKrtqyYkRJO8tP6PtLZ8hC6PSMT6AvJnDZg Ctoc/gVST32GwZkC5UBEEE0raOHJvi5kO6WPyksqWN1F7UrUxG2pghxvxh1oQB/6slR+VLBw/P5h 7GKLoKo/GhydYirE9zE5OFk2vrAp25jHjXBOXL5486ajbXmU6legCL0KnyVzJM0RfZGGrJnbKvIl 3x600FFCrAemeepEXR3ian0lCvozaMEUUzTEHP0YT5Oq9BACOEh42v513e7nBQjsUM75bstRrwxh IXYx6HMMFrh0w+biddsmChfKyD/R2/gcTZSy6/5Vm6X48nqNiWOXhcOMoPDNmVLc7ZkJXTdmoe6L g1Em7InR06hUb6FB2dE97HYYJBR2KqiX9vt5M3Df3fgWs0U+m3jxPIGP+yZn9TgSO0PmpIry3QSt FbiMhX0ywW0Mf2DigWkMdB6rWhG4BqnaNiCUWOMgxYDjbM4yQeYKnxM6Ww7NXz7eaaPq3mwDhlaC B9cCWa0/Y9QbNZqviI7V5NUIHynA4UxbWRuFK6lHVJhRrkxpvK9VscWjlDIegbghK0afbZkbf/l7 pIpBBvbBAqT667RJRtBuQTwEF682tS/YCNleNH2611fVyyWF+HMYFcqwEGKpb1wBvYn2ZmDnU8Cb ZjTheRsO8ZapjhqNizRRrcFJr2Xe9kJj3hRVBNJ0GzYaDxsfgalNbv5DxFc2BWE1jnyNJUy7qtOP Kjxs2vzkq9NzjXtnnEy1DC+gW8cw9BM/lC/moPZ1pqta3c/CW++YeMXWnuoUguLs8XmKDRZgzGCk i59NSA8Fewd8l/MBNz63kAmGHk6Kr/5Fpz07VUgrUsvCQF3v1drXoZHAd6tv4uOG23BP56/qGrI9 /xA7ddivaACoy7u9rsHhcc3YA+s3219zqvTsoownNWVQB7rj3N+18la1s7LLvaMHIIEeSUnBC2Nh VjnGn9l/dH3awlfTCOi/JxlLvGCNEYNMyWYgo7z5o3OApg+39+YB2AaCM0emqH3poKf10ohIm8Tp A1f3mZ/rX7X3+2n3B9B2h0SgWb7lLVw3eqleVGghFnT5vDYONRYB17v7fQqEeRsBrNME2ln9aDlC JdHGUPTp/2h6I6W35STZG1wzbh23K1JbPI9/xPbzQX2XA+IJzQycZdHtlQDVmfj37B6cumgHp59R 53IoryMNZVlHpIqHizZQ9ff3gkabEufitc0vQxCrsWqYM8VZ+HA4/eRdVZ1coMSXPZH/OrPr+EqE 35rRmaJfD07AjbNdnAsSJSVzvLHYpIj0bXMHbdVxvQx1QoEXCukM8E92UGMXO2fKvLd4pX1hVh2p 1Sb3GsTg9BbUgU1UTzzQ3ufrjWNvJSNr0QhUy6g1yElF1aY/8Cr64P6jBoXb8rN8Blkn/y88YSKf UtTY6gkWb2ZbSwCdjRcEF6qATcQ2HndMp7/I//leQTFV+KRtKUS1Yvk1qi46WuLItBc6jvlJIe1+ rac4yfd1K9KbpFTOBqMaHGLzcWwoIDdwUTfje3RmX4LVxak32MaVzjxNlv4sPznW5km5yrWHT6BY HyYkQKsN9XnVkhHMXqTbSt7TAR7KWL2Y9qvsqLff9aGWVK10fKCxNupBBjPEmC/nkP0aFANuu6hu TUi9qLfBOEYP9j/5nMrR3bE1n5pAQQv0JcY1S5HgXgkjnytwCiR/JXVYj31SaC0jtDaMhrmaqCH+ 1u7+ITB1YUrPzh0s+Hel5yAq5V8sk+XnRcQE4KHNcUp53gOB3An9N0dFJc6UkE4lRReFLIRDwsjZ cOQrKLt58QA5dNzQxWt8af/913vLvaAd9Ldss2TdAnZ92WHnArUXEAjPKqwGJxTXQqdpp5GZi+tk RjcpxmNtPlDhskcTJSZO0gLqDvd3BY0lLjsp7Bx03alwPMyckQXzSse8nIIj8mJvuhcFVkj4KX+q Ca9zghPL158rHSQtIa3AxiWM6i2fFcTW44a0t3bVWy6Is2mSCGO3HVwH2XNN2CAsbzsPYZboS6T2 AuONblcMMbj3Z/dOcULCswKXaroQzvsasWImOe9//hOW56WMP/iNYIsMLNyVTmRvMWpqgzoNXhOx jaC/ggwEWD4KJEqTNwIX9OtlD0UvWKy1lWo8257vGgoGgAJPCoVJlCz4691lZwhlWwyEmIj2SZI/ 0Fe2zd+fsm3qZdq5lQSzlJ92ptxWZ/omSQ/kbXSnkSVKbBEnvnyz8Bs/Wn21TXm1KCXbUNUhF3cO gBkTTKCbvP9Zw1t2gN1e7Hh1Xa9ts6H0JUQOt1yK/cH5LCIjOLvoisjoSOMJaq7mwlseIMFdjTee gOZJTrU7C9plR/ktoxU4YUSTCT7LJeJGfu5Lw49v36sfaTcPEKMkKCfoHjFjfKgx//W0pIjbh4o+ RpniRQ/41UMXkd5wwqo1HWWwFrlP//3CpjgmroCFvHr/Liz3KBZoKwU6PCVp9hbgA1V6HDa8aZR9 tufM+yj1sfWXnRKlGjsh65DQte+tsCVBkKQ5tyddMpKN/v4C4d4TBUP3aQI5foGkGaKd+9VrciMd yIDxA4i+LMxrxnWV3E04b3jVZ1gV8PKt8FStAhAK+niw7FSrkPmQtQgGIwG8MBS4aZqvu4YsH46Y jrUd7cjh55o/sYSNT6qN2pHbx2SVl3hLTGnX0ysklTEL8j3bcxUjgG7m1rinNWKm1LSSdeefyPkp E4gEjAxq/sLeE161xTPL4t+3kTlPGsZ2rt5a1YFRBUddSchBWN/8f+hRc1Bqos3iTJBPmoH1qyA6 KUyzNVgPePfy8iH3ez2luFxPt7fzUFD7rmw7BDmTCZj5TZajYHN5LGPB21S7LFjCcROOqm75RXdZ 9kJjLjjqgrUbhTTo7fCAq51JgDkZsq0T2h5tKQv7OaMcVxngeXzumWKuwfTRt4kKC18RS8Q90kC3 p/T4vclczHEERj58hla3QMsEMwu6lXAFvHy2AtasSoZUEjXmSs5eHzv0EqWSln3UYuEUxjQyI1Jq s2kuqsbEJ4zHn7ntd90CVzHnmyNTsNeNPeHGoXUzzTptb43O7Xgf/JhtYIhXz27EYkTXu8ZLecz3 Wa6N8Abaf7StX5ZxlnrDJE2gNepzCwSg9h+MaXzv5iy39OsCNhCMaKjcD5siCTP3N3934pu543fu FLESd9gfxYgwa0LBLiBRtzK9603Flp6kQ8H50SyJuUtw/xHfaZGKxBR1TMiTLVGtojEEVuSfEYB4 L712n6SzbG6IoxDU/WRvqlrEDOixz9RKuiu664U4XZToP3itqBGXMxiLt3BUG1oLfPO1dEARabp2 Ih/RL2F9uruhHqRROnUp7NkVx4gK5r4SoYmrS9LwWzbTVypGDK3xW3jWhIJUNhRR13SA6QObW5fH LqxrS7JoXWZzU44qeoFksR6Mo6x1ypUzMXHna5zRvyr85nujxf/VWKR46MflpejqVNhMq6QqoZbe Pb+98IAHto7ltmVUcV+CQtRxygE4QfKEEomJWZyuqgOkGFIrVyBaU1kapHxuz/4IVC0C2S4ZL0dR CwafGWGxSNlWXGqo5+zw0MMvxuI5pxJprZatbJ1Blfm8Ax9c//krwhKruZbsqbLFkXdCx3OvC7vg K5v++s9nFG4KXHgyGrBfJERU7tpgmW1lIJJ5BTkHYsC3f9lg+vqdQsU3noEmBe+lUivCPUuv645t vbkTa9gXVHxeOck+Rl5TxGF+9rv+Rl3QXNufo7y5/ZCF35l+JJmYvzeOIpzxO9pNA7ys1rxoQHET U2v8OZ9/MdTGYLG96Vp5xDFrIf7JpnTYrReUtq5F1gWswQ2wEU9VCjvetbCWhxWN1SfXQLhPb5Jo OhMqEIiOSYbqulRt/KQTniqevaHa7ec63f6D2JEBPJ0Pd/4+0u7ascL5kUkT1edS9nTDsb8687St TpPQE1M15Lcn4E9DMkWqFK3OQsfXEwvxVMUlaEFqXyjchlu27XEKz5NSZR33uYO//rfxYXLOGtIQ xandG83wrgQ6ohM1c244dYBgmCgRjn3g5pN+ey7ZD8Z622+XPiqK5y1810ywjTkkgMzA3sxh14Kk hIiPt1oohXG+Tcd+OdcrikByOx2WlUjXVQt1LD1IH3kBIwMeTmarIU1/8CSy8zFHtLKUkjkY+WJW X8Ij3EgXGlLKX65Zbc5LB7kEbgAeXdWox+niomuKT8eli0JvwpJV8MprvLQ8D2xZI7xopZAjnzu6 XxzR6II6MdBoPJLziM8RNrScSNPybgotCFBVuencU5ESeb+jE4oG83VniDbpDpC3wLo5RCIieDNt eExNKijUsqHVsNZbmhI4dSD8hWjIIjLvc3TjQi/qB72H2PqJBoWdM/G0X4LCRKbe68u2uoJXdRHy 24DgqR2Ds/hKaHxx8ogyFiit9XoyvbpZOWNoqYjOQGq5qVd5ykzaltLPnFM5U68Xvo44BV3loLMj ErEyQgEAqo43pr3cTiZk9b1m+56PRYETcej4SnChcJ2Vm8qRLSfFP1+sdN0HzVXNgT+39v+mbkDN d1H26vBHO3ACoP6jpdkiHwS9VKGB41Yy8NCu53rnJhxgY9m+gdje/B0/FEMJsxKQ/YzR7OoIVVYS 7q6Kq56ExfKWI0wV+f2pP7uwNvSpWdf3lhVu9R+A5ORtG+0skTt3Gnxv0ZPKBFk3FzVvHpLIDO8k p1LlpCIrI9j58UKGEKVwXCMLbB+pepPndyeUyIUA+gATVe5ZRMcQdSGq2THJ61h4UV+VbWKhMlRV hUHD7wKWF0eB9NAIMiUGD5IXNP6T68kmHGIuWKp85U+aFef31OfUHWn20Z5UjFOWyYW9e8RlZ3K1 exKBfiTCigkvL36Y2+rfcaL4rfEcQStZgkNNtCZ6j1yZ5siu8k0QZHJFNTqxKnyePZmTgnxtoc6J 4KTYGWQKBAVyWKMJ2btxsxtdoFHBy1H4esmyOMh9sSmBAwP8BiDndvUIzkz1Shjzdow4kzieErz2 +sZL6a2uq7Xb10ZcHI9AZKf10aZEEhLXprDAzbbGt4n5OLj21JC2vMu8llVNbOkXpLz+WmJPP2/v 7bAMSU1jCitAI8/tn1WtnCdixrz3EtKVW4L6kXeTk5hp9Z3uaxYUpJLvtLJUyhPkg6+9wQmPC3nT 2z6crHBUBMy6SLEhJPrSnMIt1hfTx0+d8xPdVz8pVr4nvHXdT37jD8L3nzhQuaYSKR8oadnfwfv5 IS4tpsl5n//ZJbDP2D8QPQ1RUduQ5VCe3L4gv+q74XMhuE/JKqSg4zH0fQiQmT8afpIZzzT26lcE HYcRN6tvsIs7XdcTKaPYaDN2EmGPpasKdkUg7g37GYEI06wURsdaxpwZUadUrW2ixNsuqu1MNWgW 4Q+rzwtgkuHPrcqlIrIAC/TbZzt5SaVwrOdciK3B/58IytJ1h36fMzLbqnl78DT4Hs1azS/WaS6P 3xwr1OIUr2580aHJYYxPiVitNu/38W+t/KXfVCbQs8ft5Ooga9RSZLaRWJDunWpIKzGbpF4O5rbn vsqn+zMoL7H9KuuNuvkNUBLbqUpudPOki6L2J5hrzXUrv0/O4dBTQt5GCMyB7OTG3f/Yun164ULy OFaKCAuiAMoUgBR2C/C0LYKBfjK5WuZ1PaeqksJACON7Gmlsix2fs7cnY1QFl1WpFKIT7Vf7OFuV Ywil4oh/ZyB8yyvwCRcBuLOwuzNtP7q6v+IOoU1AK+McbB6cqdsv4INr7lfBoL91h3u01qTZZ1rX 17wfAvwscjs/paf79EDR7bv35vx00MwsrNpgHTL/CKndOXLnE8bPbLN5Pc5cm2bm4GeOjkmQuDoV IFKQm3YQx+I5mRPN61Q2U9u5yxkZqsTkYEc/10srX7jzRCc5Yhgai+Msf5pfcubHndpwY5xpZrMV tlWlbfGZdESYxxiG808wCzWamY3GYUPgkhXZJFy5ODM06kJ+8RsT2ilbqQ4gBnbp9XmVeLErnfJN 2YRDerXxR65FKVDfTV9ddF8B1xeY0uv0D0BkjzsfoBMK3bY0VOsrbDjNJFYI9+cRV0c8Tss1IEpR ppC6PF5HEOcQkVlDwa2lvoxpZ7/d+ucfLrFkjPmuAObLQHtX442moXnqMIJQEvRlGxZ01Eu84K+9 qK1xHnpOCxzy45TJo2USHJ9hoGZOwnuv0RJtewsw/OrxfXjTHXctx08Ezn1HPjTHdvYmibULC77z 7UK2e5xwkFg2ZUvQ/05se2pHuvahrwTG0gDU/xJ0Yw8HqdKgBrTXRTi4cpoUWOkls/6qrht5eipH UOwY/qrIHeMEffiYG7fm403Ra1XzteYYUpOCknPi9RXUmD00UXdcwpF5n25i1vUoyKT1bMwXEcpM gGwvyVpwFAAe4S15Sj/hKebB9znU81kV/2n99PhTPAu+7tIUKQdEQ0AA1wWosSH7R2EVDmisuqdo VXCxLB5hYfDe3ox06XzWIPypSTHT3BSqMv14GgKcYChcx4Qig8dWb/3pqpWbySRP659VunpVv0ev WF53ysvJ7b2mFPxOle9dtdt7v3EjqNFChT7nqUfzd0PCSgF8O6+StvWkKYejHOG84wcqRF1y6xR8 zXrBcauy4obSkekTpJYh+EH3R1aTj4eeAsQFXbjRu0koeWMsJ40Lkrqf4kpmENT2SKytvRjoHT7i ltXkJ6YsuVCpK0QJLeZbZO70hEXD+b3rWMOpPlANyEumLg4QuUDRKIDWUYMU80DXraseKtob+rW/ I3neBhczsmFqL2wgaT/Fcdl6CfqkXQI6PaAuGphyooDknAWRBiDKNKFe/R6rZl3EMRDyvnMostik QVf5f0BjSPhTrxdlL2VwRqXIaIouDqRk2jN787+pqX5VpyMC1zUXCCybrFBj2UTjBJos1+T8CI5S HSVMrhoEkjKrsII00UBv3njXJE90pxEkvBoqcNzvBuQnZ06k/nNHsp17II/LGzf0Be8L8n5kQr2p r2NLesWRTUBw4aA7U3a8vYauIKliRt5zObEzsXCrMT1ip6U+e4QZwIW9N3q1DqPJt0mxfWYM6aTM jeme2vePrIXj3gOQCXONNE6fznoJJs3TI20abNhoCeZJeL3EPXivi5Du7RVm+CrUI1VBLu9KEUC3 L5BdkRk43c5rykBvDIal3IrYzQW++H/EBsHECJdp+LKn8EY5c2qNSuogzLHJmkGI3/8m/8bdEtCR 2Gh3EQ/1TUOc1IIWPMG3TdgR05n22UwFQAyLwTJwrO9yZTFjaznu3/82iZFMOTMpokdKd1EjsV4b 7hpMW715DMTqw0y9Gmi5Jv+3wk9IXi6jTWFh2YoWko+JT4Z4Q/yS3iLuScaLalq89X1PrPh4FO4S U4c9xUhyk0sGGmHB/QtA08iqLk6VUC7pF7djpeotCklTZ45hKU1tUSDP1w/JkVykIuNOxMRoTSKP 0pNXNZIaXr2CLtky4VZzB7tBNj0nJfo8edE1wSRb9l1HJIwB9HLlLQ8Uc++3XiDCOX/uwMowaEad COv4mdR0y0PGyHD5kYjMyrgBhBHJguFqEBAqUiH2wBj9U02aet2tLM5SR6eA9DsVemuMtTr9aUrh lJUpuArjoZgbAdQ+5HeNIulEATL6Ortn2YmX15uE9WXDXUbIezfWWNs7Qv/P16h/esVFiy9GrCfS ukrWLUJtLYGnOAap21+AVIRRs0d7/GfSVfSVX9LxdSMsOJ+nW7aS1Oqu3Kw0icXZwzSvkzg9S0tl RcrmTwg4DcAGUpgRSXW/L4g76GUY/0ir9vfGsQ1yQVBivcjuVPd0vTfY37L6ZIRNxMtT1ix1igro +byjPBJl1n0AU9TC1Bd6QUtwUTp7/JjX5llwEEJvhjoKQjobTPsbQ/qhD2SSYOm1sSL47O0L98kH u+BjVbcQ5xTMKXEjI1c+Up3JXr3wJ2t5Z4ALmZa2wp8LeqnUDMV7T9CbN4uZUK4mhCSqxB/tKFoU 6NU/WI0UbjLv4vboULMGaJa9H6nwp9pAjiu/nrclRkizuZYMF1+fj9wsDePLSkhjmImd8Zc3U7Uh auv80c8wk2Syj/sw3PXcAOL3PYqqBX7vbxilDcA6UCWHi/basYRkWHmX+PLk0N93BfGuebMc/MSe 1dhmna9HYHXb6/6vfhikG18fSMoNzhRpD159y8T6iIGXJ/h/irPs0Mn56RHHIvzHZkyLFNuC8Hek ypBkn6mjlKoE91XPJqsrzozYEfSq69/u20IuXGc/qlYJLtSPDzJ+Nsggte98VB6FP5Skaa56y7Xj KrfC1LJj+ZHHovGYw1yarQqKabGiWTGXyrp/uYG/34ZQQcKaqDbLi673/WrJDGAmiVNU1dqRXKYs PwiuCuHZDAK1BwTOcpKife+ybLgRjPXkylEnmQa2HKY0iqtYFO9THPvtn18BiL00/EIwB/2WxRbB vCUaBIst0IM6MACUuK+gueAaco+yhjMimT/y7PaEtIo28ouvAiaYH58CONWJXj4E/zuno873jqCm rYKdhlveHEeFNKn6vVp1onpr8ZPZZ2IE4zKsTFMdTtFBBLBWwozR0Ea/9J0047FwwwmXKqXC0l/V ctrSedCfl7c5PYoX5iADtTfVGHz8JyZxW1QDM+PQsfv3lnhK5RK7xX/jqxZzqF9ZesF3JoOr3WMs NQB9Cpdf5phf2VBtPc8zksUm1XpMFUsiTusFSCVHz19tuuc4nBmjZ+RJiOdinaRka95YE+yPhIuX 7nunyv9LwFJN4EprHnm6nCclKa0ggNk8FpgdyAWIf7PdhMrr8Qfpkppr4req/yFhvG3ZjDZ5gdQt pog7ZjM/XqhLfBYScjgMfVmUoUmFmu6vAled8b5wVtDs8bQXdQ8Gz6tKEYlIe+B52YvC2LyggKO5 T1LA53pt2b3VNoWWi5NUDk5La6TnQo2xBdoKqkA+sZW6LOFduOPSsN2HeWNhIiHLIVudM+wJ99yp PgBKuFagpoocJjWEtjBY/lZcznpkMmT8YvF4oEhmOJhd4/t+lQXiEoky6qwkdTiUJRuqpuU90ajD JUWbEqWlHZXq3aYiFRZ/uxaC3C38vzYlm3kJWxbJRYKfBdm0cQsqzjpPdz8Mnydx93fMPG6G4fl/ yh8GUvoldg66LUB/J8aiaZEC2TAQjI32BFytffmBI3qL99j6uNoFkFTzSD6EP/+nJX/sp+9pvbUR bQudpZ/PZbixHLx/8bpsUyyOUFR5S8jlvVsCx/Py7q0vEP3ExsGXa4HPaUa7oRr8roe1fJM5OIcV mV37WUIktSJBqefHj4Ze6HsbvqLEhj8qsNgQ5SvOkJf+vTpq5Ypn32fOlT60n4McNkA/Ie25EzKc l1JzJ3eH8Sh4R/4AEy1lZH8jGyljfvNjDdfo5vrGEzAZiNEh8mI4fKC2yog7TsS66x2HJSf75aNh G/3C0QFggQRaKcqoHLfRVFOGj27KBzX/4s/doaGk9SheKLWXRaLyTSOX2LePjOCxxNZ8rNWVJ/hf G2uvq+fuS8rMw0W9fmo5aUDGABIwu3R0VX6AEePpgPaWQcN7EDeiDl8mOxgmkboDNvWlWz7+9l4o PxY2AFhE2pkUgZylssgjZP8BnrXf3/IEncw04epr0QTWHveY1iMwyVpNnBQNh1q4xZPuC4T4yXpq QuhQTtNGPNB6z3VI4AMZncKVopb89mrmLyWyNkrfHeGJSXGIL6+fYa4+MY3/0y5zefOzoZHZ3Du/ 0PqBSem456zelvfDt/FVutGcDylaQXeaTgwQpOkWofSHBT5tHMeeTy+9zBE99eb3cHFZ44glHr70 W+oITHmZkKj3Fu9h6yl2VNkdXsn3bHTY8K+puUiiQs/Og2bAKLv4FNBLfkhWQR/P7IdF1Dh/bCBU YeG/5vCLalXHmLJSYRJCEfqfkfgkA/I4Mht86S78v/f3YO61EKRG0qWu7mbqJfA7QiVKDaTa700H cXwP9VnlnpIvYgodDmgif3K0jGczddWBhUBIdXNVS4XSUzKuZeNAAJxjJicFjPReFNrcP11I259d bvPkS2hGbIF4TqSOg9EDEnxJXHehCKsU7zFTsWGlM5BeLJDDOc9rLRMmXFlFrVThKEQjJDqdjR+p T2SmxjLvUUsYhYxbN8O5P7zEcc3jmAEtyUaIwAA+RMLMJ+08DW3M4VPBNSSB20STJJSYUC5soOR9 WQWCHB/OlsEiw1HlxS4gRBuHeDxtOqw31YMLCZ/g40sLo0g0shFzQNFpSilnbDyuTHEkODfqYJyb QM4o0LAVH5ZDm8kYIyZ3RwhuR1rbjMpeVRoox9GtPv8FF3f/rIQ67gw0hCMBfdID2UQsqsX3Q9jq jfsPPDXNg/bjLYHgHQnL+C+jVPY29ubSUlVm9BtJX4gL8m1fANKdFVNilJTIlXfdLJL7l76tRuly duYRJfeOPbnsuXM8QiRe/u+8KO7gLBz6Nu3bMdQ7MH1h5gNoqH1PVISRtYAy+Prh6qgROxTqhaop bGam0ctr+A6khHvOkXCNjZ96LXz0pvTrRo328jz0Pq6JOdEGOeThI9wrtuNUk+CP6RyOAFfblJvx zQm0+Qr/Yz9NwLMVD6iPSc5NBjOG32+QaR8YlNrJx+807uP8U/EwNx/Qmwase5ay/e1osvYz7yeO OjUrqDXYKiy+D4+xiofy7FQv/rFmz9qtuNxjl4kLmcDr47xEJytOQgV7wAfohVNz2giDZGZ4s6Vn avLSNAiqvelMiy69qOf1mtsMlYzjQj4AfdJl1QhSUwjwbBu7x++TrDflbGu2Xshu1dk4R37asccy rjA7jWIfKjylAr4TBsVC0NbdGnn9irahiQt1X/MFp1F2cZgl1V09bqKx1QdNyF7HxyDXM4NXgWaM CcZkV239oJRMDj3tE+Q0Yk121egZ3m3Z+aga4qo8RwhWssRooDtmI4/8fOZdIrBaS6kqXJ+YlRlh O8nPZtWo261aaYzPdpKB/0TlHjhSbLUD5VraI+VxNJNUlCyhP8LbMz6ncd3eCSwGT+bvDqMwjr5C G47h5QSOXZE3gaS1XmwZZirsLGUt6u9dF2+esnzcC5W8C5dtBCcG5v35wdeScBMxXQ2Bh+Iyx0P2 6iXJSXMsajWvBUTCMGQ40U22x6JFLd1zi38H+BDXR//VAjj/BuVTDN3VnqOs2WiHuqMdDfNb2Yri z1hTNTbsoiG43ziQTn6zcVLJJ3l30AeDuw8J8Z+4xntAu4liR+/L3shoaExvtg9yX3tXP+XG/KaU BjdXBGwp28fprNexvYQ15V33SBMc6iHscueSlUhl1VjHvWjiBNtejeXqxivDKf0NkV/tAQHpihSp WIHEs3bw/McW3fgBSlgCcms/dMIh3kQ9Bl4t6Bk2FxKlMO/KXwFm827Bu+xQaFpr5vief/Ia2wui ltBcvp1pR7TUmvawllZ0sCAbKGVVdgP3bppTVKIIRBOTonoOfG3zFPySHtqSanAgikd02OrbuRKw 99njf5NXXS0ZI1834W9HnIsvBYwqc1gqEhpfnG7zztrrQG5eL/U2VdgsC/WqJ3ozGTzc4pebApPV LT6IrhBJikiQQjc30mDGlgR286IEj7eO0oAsO6zQp2qQKXu606RHMN5BYQjNOTEe8lh+IBxqAOai ozouwqbiWFEt1ekbVmo/XVqapqEOUHnF4B8hqpO69kVuZU8i3iYpkPdOvoKpasZH+9riY3Iviu3M hYBMgDyKleyu3OT1jPK/i0BMoEI3FmLZfKChUpJsU697cw5BWmNhhLwvAB7P3ERz4a/TCan4xIla jelcYV4MpWk8tQbgpWz0DvS+W5C8Og97yYTLTHrMrJbU6vecH4DMu6HQ/cGKEdiIdIvjZSa/uo/k vV4QUkVQ/CI7UWPMKl5xut+PhmR60cp3iEiqIJ8DXBP3vjDkH63GB+ne8GBxd6AtKRrZfVavxghD 88uZj8lJcjW3KUu7akYDbc2UUcdbcpP7kppcHebGD9w7l3UIpCBEeZOnL1pxcxUMghemagulqq6y nSqbrlOSqYAtf1KbQw1/+U8oPSxR/XzegkzuP1DWcL3e3YTMRjeM3l5fkg/0VSJ+YYhMFEB+mEsR 67/WXi+ppnRc9cp1HbroV19vjZSwZY5PGr57P3utdk3RcyqjpMFvrWJRPZssc8Sm4CPKYt5lus8N flgNrx5P3wonNfI1j0JGKyhWHMs2suIAAhJz5hUnA0tECmA6pFHTXy+/7yrXnYpKe4aZkmfDU+w7 03FCRU+5zPlgPomN0UUyCzletL2Z91Bt/x8qspxbEKugcbO/EeCtuDGqob/lZubaZ7/iScSiMlIs HoIDT2Lm2BsYuDbB9GTWa48wb1IDvPsF4O4DYgRWcA1GVgOMLyY220futmLlumrYVWz+mi2MHXHT DIUWwvOgjb152fkzexCFdA7S7VOkkNWq9Fe8R42Ll9KRRPHBoIzYl/z+xvUU3d3go8oCDBbBBCf1 bB/nmpQDzZHi7oc/cukKtNZRuvqQOUXsxkLgijYHJpsYC5/eyQm0+bpVVIKhBaMgv7d98mVeP+sG +S7X5ulgUMrUzGdNJ6KIQlU4XU9z7o6h7UpuxEWpJw93U5CZLOR32wZ/BlVAkUUug3W2TYKGcKg+ A12IBUeGK8GDmp/uv579a9gBCBK+WeWH+jbbCI8QwY945SZAHt2PwsMC/7CdfdBQGzQygbfJQVMJ 725ScyvDXXdRuHxyAkl4Br9ugjk9032N+69ud1Nc5TlFAmd8eSbNVH4HJ3ARLNMdJbiYHGClInpl oTmj45c2Vw23beaqunPBQ8Fbkihjungcc5OaTUZBwXLyECpOfM8BlDSEVHOsRqexM88me3qwa1re N/Gs+aBbfw5fENPD+XZ+XhwcXiEpxr6uEIxiRDFg8YmpP8m9OXcZhCcDVaP3x8W9NaHDSqDwSRPC WXzArpZAQk3nYvd6+K3EFBD1GX3Dq6Az4wuUgYDnhQNaweREVmMxdmXuyd1kujQHurdYSGy7PsZR afpAGs6Gcgi8eQm7FLbs9w7ONQFQD82Qfy/1rTNUkywIyMMVTroVeuIVv07M9h2JL/NbxkTiB2ml O8f4GOq/rJZe7WkDpQLelm5tqr+EcG8Xb+t2p5eZQw0C7P53WIDIqgcThyyAR3kIZvkCYIlJmZA8 l1n6057W/1r4pQ16f3FBuXIDMV/TzFkpCuJAXstSPFWnUsgGCTVn//LAVjYx++8x90CTyidaJwtW UkmEnxuHmjv+7lAopwW59I+h5WnM1fRQtqIpQ2Wud0tRCg6YA3IfEVPk4P1Ycd+Q7lVNahVg6tFs wUFaHyjR5Ifn7axQom6/xMQkY6Zu/hBic9Qcvug0g+VfjzLo8kv4XCUGmK4LUcrLpcXSHJIeSUR3 Sa8OgvtmFA7c/9E6ufEq97BEr0KS9Ds6XMTzznLQ2NCmhpFBaIQknVsDc0iu0YKJlV7RNF5LariD jw4GuAXww6o4qfCCxltcS+68KtGlPGjTNTcWUH0GziB/5Gi3+DZ3eXbRZzhpokgNFvngUrx/a7oT lLQVWRisLPdWLMyPpDTJgzTb80Msg8qxt289oyTnfiMaqcz6bOLl4sApuCsPTOkPrEFhDEfT9iSc 5F2ndtqVg0cTK2MhnmVyf3o4RB01YiSFV4qWuzyoZ+/T7JX5FoRR9h1t0KKoyRRVlQD+SP0Nh2zb YILExFYU/JT0mhoiOhyFLF3a6kKfJfyx2UdrRTsjo32fCys7FoM/ulpcmgbxvDGGfsKlIRTro/qX T8n0DvLbnxbUvdfCh++/BuYeoqecRHD1LJQXvtUf+BP5hGDUJ37czyRHZwgC3BGiWjy7+QDUXpda AnwKA7AZTS9imjm5cDQMoQcCJEtMQrWxQ1eT2xw9jQi31Xz9MGVyz5NLlgNQhWEgTGO8TlLxlpkd A0RkI6GrgFwAwBmaRq5wa4jPQW9GF34YcZMdCQhG32fdJ/Wxq/q6xNmNgiwmYUaMmlHG1RNt9MPf vGtPy3kWRUUdyWBUmmeuTyuA88UKwnj9Oj6Z+rMvHgyevftXLg3tiM4cSXkV4MzP9rvFdhJllzo/ J98oMyUq/6cHq3jc3HgE7Di3/ZYNiw4eK6qC2fp9WBn1mcC6xQEP3mLqHfZkBLSOnMGzaFc0nDS2 ERyDbnOhvMdbv2K/8uW8nXV9O+TxXJdkSTrMz21GUKGwSf4td90Oc2qJoIZmfnQHN7Hjft8xzvVg B5rFibN+b8f7oAxbeoPccxmLnutweXWsK5athChvvjsHsNYugrPyxk+Fy8pE4seR8uA7+0ehPgjw S26CbvbbbjTDAqxMIvMhew+D5o8YeF6JUayeSFa45BJiR3oNL4HkX/Thy+FAippeN++6yF2ow8fd 8KV5dwm229TgfTukeubC399CXs7nNN2ytkhOoA08L/sZIkk2hmUpRlDJ0IG4GEgkUpyyRD64vpT7 M2WGkkcdE7JsYh3rTdZlY8q0LYEwzAwmJWOVE0ZUjOkRXtA8YqX80opVtC0aSaZuzjsqPcopws/O hRWRJxw3TAb0IBXh6s2bUXwzwntcy1ejm30NCRZYGADwOdTjN6WyHX/GGyHGZpTj5qHb4fFHfoSb DjBDfBdHE6920t9mv1NsqpPWbAok3b6Kb8PWKDwTFoeqks9RTDBJ6063JsoiD0Qf+5jsT/pCc6XZ 6CLd/+sU2SsONOg/tWUJrOFrmPiScxPDM2DleidL/IJv7uAfQEJfhqGYtSp8VowaxkoleeIsV1fF RlXjLmaLahZvKeUZkTc10lldwTJnB2+4ErU+drojZ0OaILx+6CWHZyOvVjawytPcmPdOlCgRFWt/ IyWi6Lc252MqCCviLKlGajzEArk5amZ4HELUI1WG/42ysYesrMBMTeh0xCkps/Esv9f70x1YoFXH aR2fhXL9XR8LlVk9HQydSdpdXzJ37ptvOo/P7CEd3M198YXByZAjB8FZIhBIOkP66kI6Hk1qWNIG S1trs1nx76DALsGFVdyCfbln9W+63dENbxESSv0QB5/CnwjUoc3WygVinfimlqDZVnoeqVc9IFxP QXtliRbeqRHFXsL/XiZIZL4RldUXq60w2OaqCk788fxGSexGwpDns0O+IFBNnsWUhOJj5M8o4xGn 74gQu+npeRseVbGSLipiAoq1HvHALxR/iivodwcSZEsugImUVusiX8rmx2VLiWkSiN9wnC6QkVxK jzPBrHuSSOMFx4tGiqtmM5zSBR4GKgUVjhZEVvzl5MbF5Oc1Sp2iYOKYKH3kzk+r/S4PL59PtSGO jktvfgRrpGxjR72W2F4Ro/UrFi8hDzJ8o6xYe7szLjd4PHmAsFN2c1S0UauaaMf3d6y8dz8UnI+4 CcX0N1onE6WXClN1CKIVKT8HBNmKUPA45IFAu8sTuUI/BUWnUbEYXrS4QPgCEgA6+lQI1nqhpMet WsGldksodVia5mDeL6rRo5bzKIXPwiKTruQPHRuZHx4TnGDAtEdzSzgYGGKts1SmgtJju1foRmVJ WBr72iczhHQMkZbpU2HxIqsxvwtIJ+FNl4pdk4i8BEufuhYnaIKOWRpjt3YfriejRtQX6u+P6+Bt sZIxVuzk4rzL2ZVzJPrPIb2Q0+QH8uTVlQ09YOGRmuNBicHR6am8uwaKCfluJBhQ/8C8Ox3ImzBD IC8YsM4VpLQXoZvMgHnO4NKVQvggyi2UjfFyQis73l1Ydz8zbphYcNI+GX6hFZDtuBGZemLg3eAD UaG++ImqurHinKjO2xU0W2/T8kjM1pSk8fKBGSedoLrMW6WcqhO8SQp4aXF07KK7aFAHhL+Nak17 Qqfl7ZQN6Q/0yj2BAH6xOFjsVLbXFVpINmj/G7ED3d0c8Ov4gG86dOcSOe98JQ6sbPlO860tGMKt Z4hGLntGRZedskK2FVvwbkLfrQoUFq+1j3uOqgHKyqaX0p9YmELF7DYa8xvCzBiq/HA0FC+MxFW5 MLSxc8hQdGxXg5MzRpoOHG5sLsdjsXFwhzvB7ewIc/dew6Xe6dKYlibHaq9toGXYbIksGd97lrhP 99JM+Q60YYnMano1FeDDUNu/QvH3g7tAkK9HBXtva0qISic8RKz5fbvwhELSWhksn9H3vi6H5mcQ BGyoccrIGm8SiVbPi/SF4KPQIieLwsJD3aqTOBi33ZkfYWOy5PmNLXnFGt8XgIGncLqyIafOHHHT hijjH6DJ9DtGoWa61SRi0Qbu6JPHJLk6gaE1mw7lb2oMZ1aLl5tmmFJV9Ix6mqDhS3AHSP3uqIi5 P+BXiiqN9AF+SF9GPLqljGD+XctOTvtAVQD405HvWpgGI3jPwSzXUWMROE6JL+Jyz1EFLyUistZW wTrqRXHmX69lCFYytX1GXmDYub2sjpN3g5rfjwM1qEig3xVibFmIQADh1m7ZpzwCXP7bpo/qDOkj jurzs41RnJ3of7SvBhS4Ua9P8W/NrRDxgT/7TxZFAl3AL0nGYaazvl0JhLWW3mRBKkt4d5zbOS6O 75L4YQj9petJs0HKsqYGftU+fkAbaMwYAVEtdeJXABGRKUIx6gkVyTcMvE1I96JcNakTCFAbMdBV Wt5KgouhpWuD5ZKP+KmFXC0Wlb29Qpl0ImxU3KVHkAW2GYjn4s7+Zf+YbjmSanj38GaI+c6F1HgD 9oiZXMaoOVQUwyIful7j9zD6vOdY/fNdZfzXcTws1PeCVD3/cb2xJ42F2DAgZ6QyERUVcHkuLqK1 DTKZ41RQfW9YqY9r03cKLGqEnmVjYdFPjUnlKqsxMAwQLWXMNnkLy05WwaP7eaQsPMpDijE4hKW0 m2wf6D0XkYjN9nnC4oRmULJnrg47OciBrQMYcKi/NvSqGTkNpz+A0SNbVvY5InOh/A5Le7WZpbBp ZTigjauTYSYVu5VoCWh7a3x6yqDedABXGy5B/tkvvKvK0MtO9RfzA0anYeNX900XbDUir5ijj8U5 +DntmOCfR+E6IRK4wPcgP+NlmQcTkRzS/tw33iPWa/DmfJIPBFfVckXukEwmWBCEL3rxv13rrYBr OSHjIcfL2adjLEiVKeR7N2dZgySetzqpIGeQZ2Vg5PookX8ZCxR46uSawL584DWuA7Q1Mjv+P2IG FaT1xEvLRqO911Wo0kqjGWnpQwaLe3hBeHQ6Pgfz1kLAidbWK0MIPd8RdA3kwVUBuUzGBuNAXBt8 girU2l2oYgFnhupvFf5hjmrLEZ1T5yCTRe71zvBXNI+NTPaLrlYqfZ1hZOGeH3dHSuHLQXBw8y0b U41C8Sft4Yaf6U1JLGNZ9lpR2a4O3FrZX1m6vxMhtrsv4z5fMnOIQEv7FbY3mfZeSr+cisVwe9PL zs0zS+Zxb3JSCaAVVnhE6assQAO+1L6g1ceD5VQ9S3MYnFDD+PyQJC3ZJnk+CtMtbmYn+VwpiUf6 y9r8/PyICJ7Xdd5l1e8coGAmOkqcQJCkKsyzdOxOOuCcraDmlE+qlSYlDQTg6GPsk5zqc/EfTEVJ S1kM6+bQOJOMQOx/+rJ59bkUfvl91I9Bn7Fa0ruTbyu91UzlptEoMTJctaowkW60TydyA0jUGHzW N3eqnX0y5hOVWwhlMaQlTME3MIsOdt5/8YKKfyciE+70I2caJBXFhplWoBP2l99yLz/QlBVzM6A6 2LKgYi4irCQsMuDB5noDuM/JBK8teTGbs+oPnduQ3Ao9Qv7v3e1+/8OSalGHYdlgRpf0JjuwP+gD HyMN0DMkNP7OggVrDuzCiUONJVJ3r3pJvFdzUsrETq6r0jb5QSN5tk91mHa8bhj2Yljw6fsZxlfP d3WgdOwICmCZ5ej50yhfAfvWqFYOQxO0Yrtfd/bIzhqqoDUtVunFhm5gGnXjMzM3bHm/Hn/FRiJO MKTve4whpg8mFtmRuZ4r8wDL6POj/z7J8BjbzGwaxq0m06/N73rG2Ywb1OEOyPO5f3enzionp5f3 F3OaP+HKgFGcqcM9z6OAuZtqnbi5ftQAyiDvink50mnBiRD2xvZSnZmianIIqQ0DKOTVQNcrjlct 7sRnyBp913Gk6R51/rjdiFewZY2UqDqzISSYjVu9He9rzY+40OKstPiPZVgSp+mjDyhF2ZXXwJ1w Y+IQmyiwmLDPDcWKsBV52ORowAVBSCd02RSlM343KcStYlC3cnBz3NP3kHHLdZ5AtlFf2AEOeD8d bOK1n1pYYxb+oRsC8+xhnK4fAL58EeQCbVLDPbcXyyXpFpR90Br5k3DVZ0DocBn6PToPDEwM3XCR gvzWmpqpe3aT10DNGUETna7/GZ1raNpEtYz9mqBt4EaNvZGmv9rByDqbtA1uNr50wMssF9IH6CWv fSqj+/j5t502w18OsVONF4FRSA47d+w2myVmoQqRkDQeeWD7NnKiYHfLiLyzO4Is2fJAumnnf/VU oYcnAlBYN4GS/cETa7zK0eMPpvXLDG5aFUb3A3hdmPiOGHQCGopMcgyK2Kp40o65TIgbPmeEGvEp /mabwRGwMlh4mpEfiPSh1hATQPTI+w7ACEh6yA4RvKeRiZC+1ohVllqy2h7W+SWm4yG34ul22CuY w5I6lmpmG+t3SxCAu0B7GqByk90oxevmmdLJl0APXjxImgxIXaYpKonYi3BuER4F4sVSxtqg73kE LygBi4TIiyYv3ckl5xkHo4Ouq13SPtqlvnq3k/ssANY4aJEyOG2tNo7QjGsvViCB2QV+hjjuSTGf b8wass2Z7g+63EcfIewr+Tb91j9LoYoZgokRvYwLSFlEZuKOut9+fAsBAPygkdy57f2SPagEi/XM jw6S1Nek5PkPwFoKGmA5Wr35ifxkBmIbAoQSYYXc0BscI2XYfCJhJs6pJbX1Pod/y9uxF3/8h1Fy hL0SCFzEmafOr/D62MhMHXaibGGajWWYiPx0D6RlQIg/L/OjdD8eE63dVPmTvwvBNgcXGVuWxldQ BRBeGguDgXQdGa9UDZky3N0QAWJmfkl2DjD3oZRSKJPmNDYMM0gv6naBHFw9Pruujayz5IXWNh5Q xUM8McCj7Uq0D8vgpjmAWKxSvqKuqB04PBkN4sOt0UZiLg5/gFCRNIT7Pey18Xawf1ahTapae3tq 1zNtM7zSqC0U0NAF1L1CUVImwbp8CWoag4ovqiDNtVWe/UfQu3P2xwqwi/2Jy8hQN9nk0bza5s1P ZNRYjWybODzuXSPNxGf3lzOuaiLcfGxgiojCf6/y9hWAZC30g0GIijCWpW1AVSHf5huzai6MH9lM 593yj+arx46m45kmN+3BOkt6iBlEJHAP+ORJuMngvuL2gpWu1DUOP20JTt4idflf6iaz2DHuexGg B8yA7p3pF+yWTuezn/IMQ1UHktVnSLWbPx8kVFfvNgmqNCdvB31omnE1VTcM/m3rdMOEll17CRfO Ee1hm0Znnkazl0rLPQW0dqyn/566HIhrtDmZvzGphV/NPgmoUEcv8UKu7TJyJrYcDPiN3/Ss9lF8 /5EJcbuGmQYTuG5oXpxCVsHZV0knmRBSOT9/SCRQ7vQED+pKdEO9Kw8sDt1YVoPQxTQy1/hhqDmF 9XXnoSEGXUkLEZS9k+o58krCY8XhhlmAMiN8c+IKmPd308a/pD1gwGUKr6BzXYCq7IA/+W6fY3Yz P67xmnTEaYKhXDgFIKHqbfmWLc3OMypPV45q9bD0uZFkaPbhl2DLx7Xces2YAVfY5NALJ0vbYKcS 8lVma4FFld5kqXzBg8izVKHGXnvQSDdzAPxSVMUQM/XgfDj2bYmiyPGx5BLNDgPwx6JcCygDGnUW OPYmme4m2dcbOPMjdkThUgqNi1nZnl8JrSAs4jG+MJMrdwd4j8eBYUrbQYduYVn5uM0xR0hbcBt1 KpQNDckBCXMY9w3ZO/nnEU5zTZ9NsDSXlMRsStcfW/EmlGiO9Dq5a+wbxE0VrSbS6uVukf37RLc2 Kowwjj5g+kLUxFwoLDzUc24kysMrBEb2dm9MyRPQaVMUjPIoRlw7a1ZozOxbwifns3C7kBvvyIa2 qAvqrRuQHtsBcNMoWeJNQzniCtD6eDDJRPo5RTqfkI5bp6Q2gcHBmjyJWzKxauueNUoXbP8j2Oun sS/KN88d2Q774E7RATOUAN5l+J7YCrYDbaROURCYc4PkM1VWWX/fVDcIXncT3gjYJkG/CNGv2l6M tZTqGj0KGwPTqOPg8oXbRvHsBaPF4UKzyiAHpMRZvlHIzz/XOcQFub/6VaHx3o++RAJ4MXstrLRz mBFS0B9NOy0717/Vii7ntT1T6itsq+NUtzEL25+lgGTe/nf0x06vAYqkjboF7G6RfjNIkE57XSr6 xmWv7nVgdLKAqnfUu9WZSxlLheGjTK8IqHSfg0CRtz8RE6l3sk/Rha/Qz9i85fx63o44MijOTWg4 0noIpS3BW/fqjJfXybDsMwFQxJdVJFLXZM/zxm8UM71KMKMnTffyHjVr+L3t7DYh8XFsrdM7iRDF aj6oO3jreJLu99/9eExt/1fz+xo7qccGcPC234jWA2roojdsK6RMDeMREQ/PRRqDrS7WN8uQr5nO aM8Jozs64bFms2w722qbLrqpv+mNbT6KUMxGyFikEQUTHXtwSpfBxL4XlRnw6deOUZheqHEfHyzy YwIg7whmnirSaTDhaMc2D6WoOSvvUEGuXOh8sdqekbRX/VcD4+tPkGBqIMh3Vv9ZxZ5ThaLk5hwH 2tgEO38tXvrb6eMtqYdY2uRzLmEMg1HvG8LGc4qHw47ow9UpRsY6DEat03nIObal7Kg7P+PY9vrM 0oAiiHM/+HR4WxbCTzOS2cK/GxULKzk1pAq4eeluQ1w7LROuwm7eb/hs5lkg9eKvxztC13bZ5AmF Qc75KqH8ez6j0vFmzblmJWbEGsvjqK4Jzj+CYpwfxQPADp7I2A5hhzNZ61eo6v60Z5bJwfSZXKXf HYX05Ue5E93SmSN0dOM+NZ4f127Vl3+N1fr2/Cqj2ZOvR3bimBetwDIRtN9BUwyWZOPYWqI+tqty 84kSnf8WQdOiNCDCREBDDThvWblM8fTnPCgZljt6HW++UwZCq2ErjaPxO3Tb0u+YQZsNyjfVihgX Y+vL48QSE1USfwnbgZ7/fCOUlRpij4A2mGjhGkgHUaZApTKEl4wuU1X0lHuAtCJ38gx+duG7PtGU ZwmpwxnV/NJKaTqe0x+1MK5dzeqxGkxND4b2qpGH3F87lOVqO0XBh788MehoiJepIUfUb1ic3xcE IdVHZxxmG+Se11lc7RKMSmS3/YsffXa02ZYsBzDEOC5KCphUDHjxcqx2nPJDag4Ypksr7n0oj0+N hFTcI8nUpT1tvQlpiXjbQLRCktt0RrfDqArDMAOEm+qSKAky2XQqktwXiD5HPT/0nGWLRkb0Klmf kNHO+cFJtRgEQWG2TipxrSDDMz9Mt+YD3KGcN3y86hz2GpTEV3ikrmRtuhhADqZ0R7578/A4rqyl 98MnBLfhve19owsk1eEadsaSvKiCf8L/7Vp1/0h5mqdwyoA7ha8G9zEC2IFcPTyHqrEUFE+XSudE gnApEbRFFU2duQ6+m5zC2ixbTB0TRTeeklr+e/lGj77X7lOIG8lCkq7ZHsLKrEL+HRIeXCP2bb7V TfuDMYyGsUMX+P6TKbNRYcIwE2uHo9EbSE1phyyZ/LYb1yeM/Oxg5f74OHUr54S1SRD0z0yKafih SK3+b/Boxw7QFEgOHRxJzLE451yI/FHGxYLjg0GVSxk0IwspifQoZay1Gf5023OIu5OVnDyoY3DR DMDuZo3pB4oRpgUwogYXcjCYtXPB6A03wLjxTKu6DjxYN7i4Tt3HhHwn4unYI6UgeasAXFwRqHUq Dc8/U+5Wo16uRAOCR+dCJGPx5s403xFzXaS99XMS6x9UTJRtZ7BJZeF9tT5jv1UYCcGRXP7P55Dx a/bzv4KxqDbD64GRg/k3JNJ4qeqXuRKpV6jz6rKvwlsMc0yWSN56RQFknbITQ4M9rHDjHUSBCepS EyVaRwpnpqHI3i5LYSRmZYOVz7lAWfgJEnmHrYWkncVw2FipGwtuBzfouW78lBIN65Nrg4ovTry2 g8g+XhJnKYjOPR4cHyb9Z+vKdOQaQkO9PyfWIO6149OvPVBXsp7Y+rHNOPaPbJnaqBOrL5l4eAXr 4b+HOQRfVtIQxEI7Yu5Ag22CMAP0K4VTbiXnAG9z4TBOvvp/JLviMqm4PdTYF/JGQajja+2HFtf5 8Z6E1kIz3taurCbCHqj7AVUf57FVuym4htxxKVBBNab0xJM47LsXEXToY1Pv2zM72wuF6ehRAILo A2BcIRkUrZNmjL9h3eb0oNPym4nxQ566fQVi6eRWjWNfX5++3BYc1Qwuq3WEpNR9RRKG8GeeA0F2 tjMp2SIchd35BahHzzALgrrZatohp0mPCzHiTPOyEQhj7Q9FZGyi5ogW3l1hbTo9OiuJ9Acot2qj 5h70K4VBf7rv0mhcSHmSOQzElS1EPD4mf1PPF8ny5sa8z/OaOFKTAkbRqwnwsFhKHO/rKBW8tbJa YtM07EYfK+51DOvy/CNtkAsV2b3iSrKbhKRAEnYkysQ+l9Qmcn07teTUKsN8LhXL/zGHlbcojS6e j54gzKTJ+f5GDglzUPechRGJ/cgrpb+LKk623TBaY6tSDbDCVzLN1Iv7XJTqRtjZRVD3lYypGDk/ 0to/7W00K1VPIWfcf8lOIeTJlFqfZI6SS2bWNGXHm47kong4qFEGERqjAZvVPtB073vpPj0UTGQb Ismx4X7iL50gQnHxR8lbRp64yQXLYXVIeYL6heKOT3JduCDlPZIFfey8EFZw/rcAUsmq9nTx9GkS Uw5OeQFaOSHVdQApExlia84MqGOilKiQAYGelgopKcuwMgWbvC07XfeByGwBaeLYbJShFOC8CkJo R88jKF3J5gc9+rAYs7h5XSNHCj3hKvi66StCFMbuCuXOllItUhuyUTTgsNiu2pAN6FloAlIkW6Gj rWeQJpWd1fvi4lYUpPRdzGuVMIykx7AMeauRQDRSMgsw2+RS/1HakCC8rkpw0c1BLXeG+9sQc+8K I5NPPIhMg2XNy3kZyybrbH740ENeoJouPixig649HxVgaErO4v3UoRe01HX0UVWbpjZRUWzivpmF nadBDLpetfCGe3fZPG1gVSxY79dwlaS/u0HTQhVluSk+m79eLMtF9nHtxjwY4yyR7f1dqKgxGCPl BfCxlxMxShDpLmDRJPIDKi0lJm8HhBz59cyngkJyHzI4jq0fVUks8+SCYiqHbMcbZGRcRewfOsEE ZEW+Rsal2z7WwJkRWhzAJIGsC8w40HYsNkfXTORRUR/iW8mP+NfP51BHfYlyapnJZV4jMDV9cQVw I9CHP3H+6R6IDQ3baBTLcr+3PftBHyVnHTSr0ncURKkNG4venx61NO0I6YPAJ2Qwux1pVR4AoykR NVAXHYhel6t9Bnu6kZ46JV0rNgJY5SUxVSVowT2ffR867X8FQJY52Oi7OEOXjKPnZFBvAbgY9dSZ KtpdfzxJPQB/D7mI9mfPlqe9QmYSO2fPzmD0Q04RPYmDSMYdESHM8Fs9/OKUqO5xLWXZeYpvPvgb 8bs9QZUAg61czAnWcyQdKBUDQEcns5eN8l0LXup0nbT+u4nLa3m12VCcpHPl4EB2UuUHHkY1eL1c v4tEkV4mmZn3s6LxLoRtPnBd4GfCWLSRKIc8Hs1KqM9Cu3KGsFE5r+2QnI57yu6npDNkbhtlGAm3 egEKJ3KaSF3RULG29x5F7ZaCtjPlj2mlopwapYUk2xeolTq9E9hEXt2WS/MMlDsvOYp68sG743Yl YjDYNDHDgqbOXob7UuY5fyE0ZRsxmRvA6N2zfWM2LvtNRIfZxuaTCsLlzqWOccdko333AQw32BDG m1fiU4RacLU6MfaY9fYrqb7D2VQNj9gRgYWfRCi1Nv8cSq6VkVztcA4X8HiPCdFR4ZhiIRvD6tmg buxXXt+D08YL02dfnjPQdPCFXya9vk7v7m+l+Gi3qrY7zKQRUOUvLf83mwB4BYVpAe411dPB81zu MXYTnPFLeehoRifQbwZ94RleQ5dVjLalXOmBP/2RM/MBmQ73lLm8sf0u9sgsYj3hAWRF/cmO5r3+ LcZLCXkf41OhBhI9bdTERrcoktEETGDMZ/C2GJ0EqLVbyPo5HkJTzlesyfx218gX6Dqj3uku2Efa wpwvA1BrbIeUNqVQ6nTQN0o0fYDAJ+KEiSV3wYa+Y/HYxXr9+4EkYJHLEQRgt3gMCSQQvyS16NEF E9GJQRpSHq8/WxPYk0JsTcuThswBXI0+bE1ZOu4YteR0c3SY/BAKMwaH2J5Pe2NsId+mCq23R9bR ZynQ2kU4nHaCX3fKaHVMYwoT0XBNGvDz3C+TVj6197RQkS6P+YWQWmPQ8yVlsiGrkXg47qMI35uL Uz7yf30bBRT4H0zflXebTz5kknsGf9VgRIoactKm4wGUGJsj3FBRB5WKjKMaaTy9QFvaEAJ5Heq7 aRN4Lzi9C+pdgSCwo+6+OtYwJUie77cRvwoKUx2KHa/Q25IyDqJw8SZvx2uEn7q0rpYLQuB0luCD Hv+A6I+kQyj9sL0MUm+2UPcsyq7LtMDLkllxaxVJZ0OExozml7Oo1Q+oFcFFkJxYefjsTOs+E3yu R/H0D2P32aGieSv2x9yX+/I2XMI9kczuYynjqGqCDiSJF8XAMl5jbmCqVxTJvu6CQjE+iEhpUVy2 gWfGvfBT/K8CfbAUyVSKVIts3m5Ax29kkXXUhCx7DkYAn0Ez5in5PuMe+OEpdTf6u+bZAm14ihzB uJiyhJjMB1Rxrjd9rE1TrHqXFyelLGW7dwS1cqgOX8UFdbRkwyh1CNAbh/E1nOdXUEIVCUfMWPXB mf+mVZOtjm1CwTkLqdc8srzRIAzALlYFHdJMOuytVtQUPYr5KxWqNFGh9IIe6OuJskX/Xqh7yb4w 6iJCGFNJm5Co975fpKpGJiRNQ5uvyAlXCBnuh/xk1kVaiH6wSxqS14Lc/S2HjgqoE6RZ0hucyD1W t/nIosUWOKolMy8Z6PfEc0kdTbYYYow4FAO5jEIjSqPiNpnFlZyhF3zl4N4g3pgvSX7oTPy/QQZL M7K7Iumb8y5jbrsjW6Uwm5dpa+Z8bY2FAVPCZT9TKPXg0plqbCORRrjlk/+ATTjN+L6Gx4MY+yoK RXrtdDCz//qX9V8kf4nDC/M34vEfTx9bxMknjJ1OQzdpcpgco3FmmcAW7ZuE4W8mNC8MT2GAl/pA NAC1zEgEoIufcZCmd0mc7j734SqkPT3CB0TTybnVLoyK6M2cAU/uf8ojm7jLKkj8SwcbELCYXU/8 7fVUkt9K58b2U8j89YrXZfn0KhXVRK9lhGT8xdxui0J3EjC6pQRRGWIHXxfqh1lOC55OyzOeDdGC Tcvo7aoVNPyKHBFcwUpqMbKL/oB6Kkn5TAs4Ks70q0zsSX7J0yAdqXQ2+6/m+G4iGZ3NTHVm5gGU 1Bvm7OVr0Ks3DnNXeilGQ+1Ex8Z3LgbjN8dnMkq0FFFk4/K0rSF66IdyfZIBGt/LWr6DJIn3r0+F fUepl65PPksusNyVm0uLdwc6XymZthwlgWvr3CvP66JQTlzvkqyL2npS35/lZM/TeoqZLYGndi71 W10QbOVru0a88A0pknD/NoLRUKPYl5fYRsmm9Q7oRAV5DPZFq2aHHlldGYfPBdrravjB/sQRQsq7 5k2xssi7JCgcJqJgSatWQFhf3iHv81Gg67X1tQrn1u/ebY5eGR4kT6w4Adj126JHhk4FnoH2rbcR pcOHx4L/N77pRCCbX1IRwnF0ehgSpSXcTBzFImZq8PVEWIIJUWYPkFOqd0DZMogY9KVsNNUYEhoj w8UMTo5ewt/fDx+hpjMb/QiY8VyzuKSk/fks46fP4+e2eZ4G4r06c5m9oZgm6yg1dzkhGc4/IVgC EIsn0ziLPm/Q5pknhaRt1mMlU2Hs1PQI/s+uY4tRfwHIqkOauWTOlGWuBqxjIOu11CFxYLBdC6Vn Ex1C4cGiyg3ZuHXlmCbX2/KSWmnqJPSLOdFExuNsjD3QzBzBBgGrzS5EToqkSm2TL9g+rxrOP0pO CXpsDadZOS7j5W+I96QsM5xJa30ap0BOhtQHsuEdH5US9NRmTZ/RU9wZCWBXGaKrOZ7vdLHk0Ajn Ly8sOdJ38Sq24FLQl0bYlUYKcaTOUsH6sVuUbe8Rs2OpXIA3ZpOdUYYRiuV4VI3vwOEOM1DO+8EW A6tSdZQ9SmcvLLfuNuWqIuCs+l5eMMBzRcMdSXdUjClhyibobK/XI0LF9KQOmCh2jWyqvDnAgLEi EBHs+kx0NU0zqZmB07R82zq26c6QZoKZaGl0zi7XX0CmxO/Gw5Mp5aAzbtuEaVPwI+07unEFSMaG 4H6zeTCPeoFpYx259Tu3wYf3AuNaGvZLIyUw/nmo+b66/oLEEldJjfjzY1aDekUmHioROZ2Mlc/l 5QsdhrWv7z3fFuCCacbn02ZUi2GRluwQLqtHcnYR3PDLpXHwAaVe17hMBJJAdd7/RnBpxpCI3/Cv KBCjNwPEX/IyYFbBdnL/omkCjeoBOSr4WOcxA4Hw3AVZCgPQVXWyXElp0eJ3HotqWokVfMOzxq+l sqYHOLfcfoa7DSPAWp5k+2XDApjd1FG9rOi37Bhtr6vaMqWxHUNHzgJvz4FaC9NSXX6NcqialDVX R7o/n/nvptIVG/5SiWu2raimmUZgLl1TYOW4HPu86KpEaHs7irX2C/02iA7XRasa++t6eM3M9YgO kk2aTfPkaFJrOehoMhWzYra+3T7gNVb85V+qfpX3LSc9pKsPMF1bctOjGr7Gg0GP5K+upnaeAXx9 lYfIyqUwsFTqvBwScWlKkD/KVqslV8Tg/DkOJZzdw+RB72+MqJXEMYHl6h5QVHYggOfi+b0ZdIdt nq6jiF0pJTQumpWh8jTOchUJo9UWF4ym0acdWLKD7y1eKItW3/pEzlkMW00AWFrhX/zeviW1E8YI q42UTtOtNwRqKtAAIPUmKrecn/L0IYjO+bwEmxmBUfbfRTrz5Z8Q2rlICYjs9Iq2xkfWSouA+9Sk rzw37iJfX2WFvMZMRnWh+N//SZRiOdq8YSO4+svzC/ViYd2tIKMzjKpW40txNg7OJzO6pBhtxr+N ufdDd4GiiWb4uyHQYDNQQcIgHc4W+PdSqS7D9/ohzXhUx1DbZj5wB/EDqLV3xwqD9Bq4BzH9P2LC vV01O2/OWCK9aS9ypEoNAH7Za7N11lwWaL8mbCQRMQ0vf/oNjfm03K4XcjWuyHTgY0TlwI6EOszc fqQ5NFJfKHfHYPRdAHwvujgcDq/GVPAFnNE6VEDBRTKx9i3u1XRrqWmCRzD6KM9Hv/8PlxYYqFtg Wa7u+ZBeYS2PmNWb7SG+voZKn+kWQL5qab81F4iXVMr4104cxf2R9TBUmv3f4cj3LuLT7XUkRVWq OOwS4FtFv/NNpa4OdwMveu1RQoW/FrJDR5w5PWPjSUwpnNhXQkZY1jeGuQousq5AXxasU0kAHxFC yPUgn62oUAAlil5l2/IiZ6KAs6QcdmsMA/cp6Cb9XBz3Wj+CV1m0BRdnwYJ8j/RMfihsW1G0UOIg FYJdeCueMrRs+8U2cUxixXx6vVJAIzt4pfa/gll3prCUwkeWopoZAtZCStBSeh4c0MnqjpO74DC6 3DbIg8b8X2YkcmV97IBbE4ghlzcycfnfLTLlc1zAQofGWznOx2MQpP0IU1SvPzmKWbDJhWn/RA0r gDQ9mPoooVQ8A2LJ46mzUKu5/IL8Dr2FgHXgikbXLrZXB0fSmKZaINWhGfZYuP26aRyFBjY2zhpY R/PZ/C5OjNatzYdGGK18jNtUi8up5z3KnRSUjYo0iV76YYEgvT6qiQx2D79DtD5gXlR44vQ5Tart mytZf27WFqubfQTXWugXFoSZJ3h16gtsBmZaEe7xxoW33t/xj05gWC3HyoZn+3EBB+6ZMzbflikJ Zi9aCNRve2eanVxIZe3SAqzQX8HXhU7PPxZDVKZ/N4XaKSJJoB0WcopPgNh05+J81HG966iLbWKF M7eEnkfrYnXkAKwta6wuoKjcJxXk2Qp25nM8WPLtC2XpHbHv5jv8q2J6znQc9Cb67x3rgYrX2tVP 6ILkuN60g1Eur4Hjevyz8YFUZRDz+tj3DtL8XOxrbmXH+zVgsd16TTsp9BJJZ/P0oPvSDDe5sOQr ZaaNVA89ZKXTIxJLvuVOjhfwt0w2SJYRY6BZr5d3Vmp6KGNMl4ND0VtCdj6PNEreV+lqRsP+QQNO nr5DT1qgDYScZVMc2de4uiKZsh01wZMQkobKhnSVywQXKgp8Wbq0yBxMTkP6c+vkwf6C27+rtvIg v/sPwIX7J5l6M1SGBMf5FRwbV9mnbXVW1uox0l44gEF0FK6kcLW5yxm2JcFAyWiLCqi+nVl4/Iia Lz0aN8WH3pP9TJkc8KW1V4HU2ATWDl1uWlUHL0FJOYiZnmq151W7Wx61iiVGRl2iI1GngP3wMHo6 8UegKiM+QLxSYk05cnxE4fclXNmJ4+9o47SfZLGl/sqQnTd1rSNJrrZvBk2A2Ri8TsZXr8cLJlFy F0IkbOxriefe8sW2K50Sb7SXHkc6zB4bKs1MLPvUykhmlyY3YJymoql3fjZWvxk5q3KCdN01ta9J g9OqhJrct3dNlvOX1hodQKqcC7OQOmxzSwfgWyRUDHXSq7JjMCuyPyroEc6q0J5b3m1+WvdhOeBO CMkMvgv/cSTv595L/gfdv5BlFPjrfboXOANSVB+ez90rxh4xQKMyy2889iipkuaFyJOfOLL1l4Z7 YH7CfHG5AFtunEHDarkeIJbp6IMpRevMhqTA2w+HHaH7x27zu0pEem8N7UYqY8itS9dAOYtSAEQU /m0iWzG8gTOT2ppJiIEIJgPs20seXLp0qGn1CT5F7gG5TS6NPQk3CMjMM97lx+A0QXbj4TcjsUKf 9LNYN64pyIpeCCP6YKSjgAj+TPpCe7MoGkkqQtMN+t1A0pcPqhVSRhFmXkopmBPjqYc1zXlwb5UC 1/MC4LLlUb6vk1fgYnXkiePnjK3emRLSeAq3JDMRnxTkkG139lacnsYk2M4TSvUjXaQ/n/yVz52Q M79SuaBqdhuAUYdQlXpshiuV1XjJ7+5VyhfhqeiFREMapY5mRbq5oam/foGr5Pyams0Viywjciif dl/ChfpzABK9pbUzY3WXH6Kv41MNo2V0hOopz5nKfedddbQubXzJHfewibjwdwIxNWVTta8DEx62 rcwBab9mYyyHCZWrM+IaUujpuq7/YqK+g81LhXWT/x+bKAWrnZoVvwjfsMu5sKX8JuSSWxkrnV2S gsEiSLKRfS3qXmzrSjTdE217GSWYFz3MmPNS9QtCsCwFBoxUsNlAPoTARyGSZgjFj7/xO00FRVpB XKAQguGUrXI8XJ5sK+idOzWZpQuMqIGi7kcIoCCw01urc2lRTiOy5FKKC5SVDtMPZBxLgqSO/dxy sIv4tYrlncHIQUTo1OF4bxIHmUDLqw8aWwgPEffz0P9uQrWV1wzXn9NdrIUrqfPkSUXEZP8XA7PY mufI+heR/uCy/5bh+Sb5K+NF8IV5t61eYoPIYSmL4YYidhWJRYTeK3tkGWErOcN57aVzqwHfpdg3 hOqBT3zfZG6rr3zkh2n8sgxhbmIj5GjhyvBcKHoopILAAoMxQzZ5zsYGT2WO/VGf/WqtNKmmyE4P bnrWmlUVZl/okCcj3BpWKsTUSeDVXTTI5EnMvf7G+S8lobjvqDa1AtcDE7fBdBjUuXa3cX/9xy4r lxTo8s29o6Q+IjeKwaDm9nZDrk//ff0movJmaAWr1/lmps33PjHU4j2OzOuB5QG/s2B22J+PsL05 B+jN7zkHGrl/S+7c0ch9dKJEixDwk+DtaFHNHGKE6604g8t/7CRubXgmYAWa0shhc3uUCWnqJlo0 1rcDLxAnTQMs0dlRt1qr1IgiYUP8To+rsWiC8zmKDxAl/GrAqnqv2gq7BGtRFeHVs9sYpHjvLT1E gyS/bATaQKZPZOGZMwhHF/4vhegmas8aMVV8+eEOE6MHirpmMyPmtv82VxzYl4/hXItwvnraIYEf lhF28DTMx7PRNCNLFd49YRERstnz2RKGps84SbFeZ90pqQBxvHxdVkHZkk/kLEtGRZPd1cYjwMO3 WSZ+HTmpqylVBsUDFT7IjfFJLbLJpoP6SiHg2T9jnpNtKjZMcArbGErnsqRNvokSlKgWmobSkTe5 YUuO4nbICKPKdwKS/d9wbW4O1Z73STt2r0wHz3osmpQcMUIlBoKbRAOydMugPNzDL+C4xp19QVHJ tzBSyGzARXKV/qMXHEV3DQuiiMtpGz/8sAoJwD/FE26kYiPsUe+ffHaqOI7xpYwvNctaGsXczUx+ +nbuVe9XNT5tjoy3jQUN0uqJhN5UHTLw2nS4fTtBRYp+dxDx8iGBQ0P0TfhEzuazZUorob1bSlYs JFjn64Mrte0mbcApB91ezQqWyH/Su2bF2UbUnUiLQ7vC6H+dGKhCEO0Q1PL2KjLJJe7NcCBBuMXW ZPoFQYMivFHFJRPyfgQu6hKtY2TNaJa8FRzHaUyAjoSZ0wPofWJBAeV857r/o91Lb50UPIxZEt6m C63pPus1i35iapDE0NHeWqOn4SnSPvkLBrTav1CYnzMaGiUoEpz+Js2zxvHo/ouqgQhCCTRJeFYU m0+hHMcYMz8vb5R0AVQJ+/5PhU2ShK2WTkJQ5dHxktQNo65R/yYiC/BbZN8rxzB/KXnvdD9HwtEn xrQuS+7DYFk2He1wXhZY9wTRbPzQfCfOcX+DpzSiecephMxXwfhqyKafPLaPnFPG9FmbM90EpXPa kUQM/rySYMswFHcszlHK4lx9Hfo229j5BQRT0D0VkhrzXe+Hc1Oui0uQ4QP1TyX2x0CL3l1tzVAs FX42drIKbtR2UjDWhpJKU86iXwfofxnPODenNrpNv7HP+1QxxV56q7JCQSWHpn7ru7UJOZ1r5N+P B1thiieUklMBkQUc1fC4HuS42GmV+SZeaoRJekD38PEvkTbPz04QwgHhgcabGTX0jcWLVrMkVDvb cYe/OEZj+ddTYFYbuX8pXE0qD4mHe5pM+ZZxu8hAbY0wQSvNSBzK5LAfb+jB32PeHoXD8KAYKOPm y7v0HVFzl5VUokJWnQKvkTJoLKqcmqW3/7GEOfn/fJJhpS84FwaT6mwDY1Dp8iSmlHs531dxc/bG Vb8QmOupuLzXZViWVdV6aHLmrvkjTvB/IMhJggKbiTrWJPh1HLxcAgWwmMRw4nNpQTIRQXlTGor1 fNnRnpGF4MBVwo5JXK5MRXTCG5EEWmP3qEK1cYCSbh/Glaz/qQyEgnYEvO5cxBMQ3eNtIqnqYPdn 3WiaFY5AA3uqJiE1Kvi0cYHUi5qcOvwLX0vA9sIPl78lCrht9OQWklFKPKotlK/L0xg3tzud3TxM y2IE6f7oWN6BwKGsUSVx8R3FXjOa+RuyULBj/CcoGdr3abJbBcfXvbeA6qc0E8Z+VORHWjpvvuyL 0LzSu1IYI7HesV33MNN+qAuZg9pRBM0XzS67Lhchxwi7ZO6eN4WH76Io00kP4r8dN33bBb4oHkkb 4H5DxoYFVjFKXaSfpaLqVHocvHTDndU7TrkQvD1cCJgbEQNMQm4A30Oj5LgFt/DuAdSuCc1OZW0e DkfLmO29GSZlvG32jXPUu+105IE2Uf82fwHjZI8VkVnJHLY8QlO+40bfTpP8abkqt/q/5aQQHos/ yLzHooNl4DUvOIXf8rvUChtuwnVondQxi8QdrTNpxYm24Utp0OjIAkrTxaEsJznE0oBHYywqNnat bHQDeBcGK6J18BJjbjGM8Qv/uYGPC75iwg2LZKBH353p0qUZ4tALwtrRK7+ha1yL2Q07e/IuzFwc 0O8pUtoYaAP7GZPm84UCFtuSuTyysW0EKNN0HZfye+p8V4MkgeXaamxxmMzb0ND8X4N3Bx92K1oc oazZBIRwVdqNpgCAoVra8Fk+e4UIGXsXVc5Sg4VhZmv/gHsNzxC66wyuywzZFlejIqQlj7Du3wTH b8C33kswxNkzyCpocQzIXqIJqh5paknGkBh7a6rIJVwFYcKG7+/Tz3NskSWAxNIAaN8VZIzL265s ZOW7S4Mrw158jHrQnMTmxGV8UsepXXutxon0XFAQ6DlDxnnrazPT3dx8SS7Ptb1W5Gxx4hjtt5hl jhHruNtmsG5IGhQHfx8BOfwA/e6Vjvziktd3LbiImQWB6nJzSUOqFbd9qDwgXM414g6QP+efEwd3 aRTIbZIvwlHDw4WSGN405WykFSBDry4xpyrovNVE9Kq5gczKqaLX6UwPv8Y5Y1t5KoqQjYs6+SdV lRSFh6u1WJfEUiihA4bPcrI5hIF+hUH+rxLhd5R133YoixyW6m+bvXlCf/dE9e3RcNuEk9XXBlN/ 4FHxzoVhlD/rl9SICX8FxOcSo1KdxV88Cyg60RCeVyH7cbHMEg7RrO+3i8I44t6UtA14Y6+VZpi0 Xh4n1NBC/wld5TvkTImjpRhrdA8YOW8XpAQ+9cIqsMW33Y06Y796avva1EZFlRyVPKVGRLXux6Uz tuw9QJqA6qkPC1aEmB2ATd19woUwgUPzJ1xyISAiB6kNIFWBIrf8jhCSqIVUaDdtlYIQYbyU2DHm IkMLqEcBVJWmxHUC5JVKJhWPecpGPafHr2n0H9lLW86gEdsmF37PHlyrNatmr2eHQKEz4yhkijqt 8gaqSJlY4RB5loOqu3wtQca4WHXsCL7eULM6J5s++W1YsySL2GzmpbYZnmiynwNb65LRtF8mjJex fn2BPMlJ09cdT2nhK0CR2lAHyuhCkeqI9gNjq8PY/Wa6B3st4rt84aV1uhtYGP5VfOL7PC93GGco eC9Mn2hzQbWITDTawhGFCQWU8elbHjkhlKB0qjsEyh/fjRUQpF5LFMUZrGDeu0WhhrFwUTzygbcR hFROZeIFBCUmEMQNCFY3OKoSnbVlyYOkCBuXi71ebpNl7jsPgaJ8JRB/fn53OOe7CkOWyaHI1FLU KeHAp4hsjykflANux8jxdqjSoEpOxYQqajXsZGcAV84LcHLuQsGFjZ+boqLL+s1vjw8A48H8vLvH foqewtf97zE6auRGdbVO17vf5huwh9hKiL1i8IE9yYW4va84mYP0TsvWHCSQpeLQZY8SnXJf4GrV /ILvVMSReavVn4fkcADK4LgHIk3RI93rwGlLQM075brdV4TsAJG/eoTB7liiY6Q1Le8eHe+OKv0S o3ns7WIIdpGSO4ktzLVsBnX9vxDbPo/lZmOIkBHKWHxADfmtJjaEUnBo9V2tyr6TxSU3dVRYNDif gmYIgzRIl1vQ0cKzV5UiuaTSmcl82ldBv0KBDngMedyB1nbMHbQGk6p5iaMj1YcbdzRdk1bZtbz1 fsszn3GRtL4LJFloGZXzk5z4QSttF3VgXXRoCwDGy22OxJYzUYWNThDnJTwQkmTiuodiOHzJdmp1 DkJrhvJ/ElWbdVncj4QK8+m3FArOQCuihF0egNkC07Hc5bA88QWRhacrFErbgGN2t4fKudwJzbS9 SexKKjAfYIgDhg//OhXsBnBeJOISCWHVFlIX0xa5DrQyqxLVBM7+hSq+4eOp/0gTAr9wQHslVWNt LdOEkGeK1z5v26Wz9vfTPrUpjFemhXRgb2TpW5Qysb6ZpkuihrdLfisajK3DYDJpa12uBSEdqBij 8c9bco3nmZIX2IdUGHO0vcg4FlgVEokL7BK8kg4DW8id/lckJIez4pI698XAqzHhSfhkpPYtNcOn 5CBOSSnPCg1v1YFSIyXAtl6dEIASAvOAlEtAvan5Dkq2TYjXd+F65myphcKADN3mOwcVdrcCvu7a FyoEb/G4pPCgdpCI6AsLItVW5Vg6Z2mhZripWXGiyjFlT4I2yVRUM21VhEy8pJnDbGflwiYIhmej 2DOas7HsEnts3gWdr109HoaG5PaYhGuU4k3w5Zo07hMcFi5ncjHcECK94MkQUMDhFzn6os/W0qUc c8ypLbLjfnnBASwYiKimhpgPEA1O6pJsRhcUk6aEHCiGAfGURYJFnqkNUmOkDKPE6XKPOxE4osmR nJbqWHVVd+1IlL3hoLG68vdFezPTJrj0kM3ay2YExgtc6GTig+azwkVCCErJlMc6qbQnrvJ8sgIs BnwQYZ2RPkp+YbleXPbydNxcMlfhOmXJ/pFEpyYYo2EnbWup00Q3l54eQtc9HZYbudz7SnArExqz MM8kT5L5SWi7M7g8WRsg+4xoOiKWqjkh55/gpHvrstunZK/treMA6yRtf/hfv0VZTrNSqfZ/1oDd cE4v5XRpQVOEGMgx/2U4mvCp9JBDhD+JFM8WPUam2dkcy5HHrINGpVjmjrjYTt2qEFq8YUd662iu ku6mN7UTyvHA6japBcykz1MvCilALPaP0tf1mnK8CUQApXDuYf4Hr8fzvzgb/5XhXfeOs4dbuqLu 4Vx+ZysfdQ9Ly5Xu1eNWJ5aYlhoNOWij+iRf5t1sjPdMFbFVzg6NSEw+eSLRpopAmTfCyPKVi5RM IiLf1sWxUzJtcebOMH9v/1OpbvOR+9Di7tFEVDwXeqKeArEvqKyl8wxN3c8n7zX6Zw8kP+/j+Wut fdfvkbXycgRF09DAbq/F1H5IVlvy2ixjVKvqDPAyZWPEoxtg0L4vTTQFtTsvHGFjCN62Fh9vqPfp /JuClbnwfhl6YMw/NJ+0uTPxesutTAvsLnLeTNl2uH0aQyrNvGGqMeg74Juemfhd8jnEG1Vt7Ld8 hb1nyyk5/S0HbU8seGm1wWTe0aedOuGET2gDd3Nd8WwA+4QoIDftDikYYawWOwrchM56YNS/Upmx 1HFbnjwGLBupxEbcA5kLZeQpu7wk2YlRGAddgjbWOo803ZgnTfpnOGSLbrLcRw5hH4lHFfpiv3EL jlj9O/SHVoGD2eIEg6y5uulp30Iyisulfqivgf2lNVKfniJIJ1Zd/xmcv7yfBrl9k3fV6+hI4F3Q 7uw7fgbnDC4SqizhIc8S9frrJphnKdJMIaIdU5djmmjZmvX5Tg9tnC4z6RmFH2+0+Ylnf/O2xovB 0E37j0GLloEZzHi60cYtoyWFT84xI5ABZc9e+g7atonvS0VunjumMXrywnz70mf2QKbibDCai8EY J+UYg8ms5Nj2I0jKSE1RaEsniHQwdS65AWwcZl+7P9Ssvoz1FGsDluK8MDgSIP8B1HyzYmTtKqaC OeJ5Ygb7DePmX5s/20aTX6Y2vTkntCoRhM3AZeviPwf5DhPc12qhx5rEbu6QAmC+jGtSZ1j/acsf UmNBmD3/6woYWF40dLzAgDtDO1wzqUtetZ0XR+GaFew8iGYTyGljD2AKo+w1LVEZukddsXwqBZjh kbULmqj9ZRjuxZhrNrIAhAjU049f75k7ui5/m66nhp1VHL8fEpcppJiLTJBie9C2wIjMoDl04EbT jnHWXg1G0eraZ6enNdPw8loL6Y5jcJg8GjmyqyiEbxc6W1qp+HHv6gnHoXdiWPi7o8kZp0mNWKqb hv7Oae2vDnSJ7r47Q6P7zGYmJVVT0v8IdgsHjbDnGTE91FOiXvezeDDy4qmMjOGd5+bsc48ALZxc NhvFunpKCuwvgRF6tyVetsy46H6xN3PAdJMUbWd0//02NX6b/troGYtjpyxvGCpJSa1a1QS5UEmX UGISPrNJM1eEjzfoKlhFNNItPTJBKq8ZuI/L8nKXPxFklaXnjEtMkp6WCvd0ep4PaiqcdoBjdd9H eqwrRhhPrzo2k3Cj18lQ9mNJbJ4cCetEZ5Ew1kxcoWrO+HRj9rCz/Xbgp98oxUnWDtPMqlvPyzaQ pe6s3Mswv5z/0irr+4wrGT+LvYhi0ne2EHa7yPMyCUMx1yao6cDi9F8hPaZyad1j2lrw6DfwpQ9J DtZXejH9PR11fFJVOdWHgK7UqX1yjyiAcTrJRcwlUNDtLdAx5JK+g39QrBMHJsOOTAjYujic28mN 62RCuThd8R5cVWbGZ8UvYZct690rWSHEmzxBrTRBrLcQuLQYY0abw2iXIKT1siFDglpcZ5Z+AUEZ Dz+1wkWCcfMtxznad3uvwbXMohNG6djyATHta+WmIR5zbTL6TDCquhd43ZSog0P+dMPtRLmhk2Zz YTFOJfRRIrZh2B4/+alqVZZ/dYnaREkYckDm6s8GGAdQXibBxZA395aIakHQSYb2GJlMDP0p/swY UnXZyucJsT3WCYnHC3tSHrur1SzO46UsQ8hUJE5puYQbQ7wKNWxHbn0gSJ0zG9Jn2cWIqQEm7u3r UaaM0kgad0SNzH7m01+GTMv71Mp/Zr3inWref+MCiKcIjlvWFrqXyOaNL3cdS2oA33vfTy1sBxoY nG6sBjzN3uIdiBTVBf64uOwIf53Ydwd3dufBexaRJFmH8DoGWJK3kqDLFse5kYUioGLfU9s9eSvE XUr+mbWABZ6LryTIOhcoz+Fcj41bkSNJ7NRFoQ8A0etXC/QV9I2vvgGTnr+gYkynT8JuKNvt0oOD do2Q+gKEtBb2n1yJvwm/o6uTJ4AHyYthx6OoV54d22JKPASi1kTQc60Nx6Ez4jlsMoEPbGScExQD D9JNORRpPGJ9nNG4GPXkLV/y/Wq23pF50VKDcDgSseR8oufi4S2773tDKWJJvlCVORXm7yfSZF1Q tQ7qllQc/LXPMFci8VIt+BLkeUud7k2L7PnlXchPsiRJFI7Kvt6A1c/1lMebgOV0aq8ZSWFKAH28 AzbkwnWMLGv7nMA9YTd6TTSGcQQS3ssavxtTyF2z9K4XKcgvt9yZKs90bETimPmEbo5Ua8wbTIDG 5djEbzjOxonxWwbI3ecvma+7o1zBFOzbVU+IRQCHo3oSKAtPgkhIwmzcXnAZU/krTz9GUdrhoR0i RdbIfULUxsSlPeuY4bXkGytfylrKO3MueAxSBR5PaYWMXgMqBB7uHPjs9x/lciu/XhcC4nrk1sLS 6Pavj/wIbo2MW4peLXHt1SMACwoqhPcw4o76UzQqxmomWI9So4wiMJcfhxtr/PBQ0u0F+/AQOV22 7I97tp0Hr8a7keIftYP9D2RHWo1u8X8ieJh6JtvI3otwtoXeMkBpxPleVkpIUiPPosQxuk68onKV zJXvf5SnxmdjAGsJb/lfPy34yf3Md9Q2hRvqpOrHG5eYLuo1EO+4x4vMv0Vla/OdF6+YmlFibG8A enrHBPR0Z9gOzp51nME+3DuD5QXhJUG6P+QLSA46yVsxa1aSsG3CZbDfwL/ey5m9o6f8vSJOyRuR UlZcFwGiqqtbMAWUwUH5vsL/yR44kLjq0407venTawN31Fb9qko6dz70z5y3QtnyNy+LxRAlAUZq 1oqRxkaQwRi3+6Oy8uT/NBYSD3QWx1c5h2dJ8cL1dZkhE8vmMcnNBLqZf2rko888VffbDRYtyoKc BzXSYkuluKqWqABRo3z+YjbITqGVhGuMsODIxEta8FK4fT63a+LMuD8Dv3vkVajAyk9BHwlgIDYb QyUVfpZbUnlwUYafvCNQ25neUB3zXoDFOC3ja0IQNddPHuRdfwBD6IRQr5awxvVTZly6sZWvqqH0 RmjwZyd6COHNllNNffvN6AN9oBOvTv1HCfCQN7pvaWMaSJEVVI2/9ghO17/hY0LmP8ZaQKIfy3oO /jvbmxKpwUWndsv1SYT6JSrSwvOQplnh/Hi3A0w7d/W4MwJ2tvnYSVre5JVE3dCgiT0WdJysOjjS LRA3Y4jLvM1e9pRbzD2xIOHv7r7tBn7OCRsOIEHKoaZLpP0vPqjxp+q3ZwKfZF43vvF86L8mJxu9 LOKQ50C6suE81oE368yeZD6bg0gGqi0ZWMZ75sP4n6bk/7O72bpgPdQl5G0Tv0sSA+dL3yXX5OCk vXUfF9Ur5VUexPkCyx3wRYj4jVn64Vtvnr/h+z4DZ8f4btLS8Yz+s7Lu7dmmKXj8VYaTbHaZtO29 iqAhfy9IZBJxko2LLikFwj2Fo/fM0Nbet4tWVm6LYUnK7dXHOyUByxHL9WhRxLO+JlFvTvJLk4Ri m8cLinJS/4MGOU0HFRLj+7vH/A9xbh04AjuxLEOYcjYXo1+fHWjs2v4raz/77UuwOvlSxiLf5+jP Xez5Yb/q0bXrlSxseK7xAXyc5TviPdET0430yqmzzFnlGTOS+QQ3wheV4ZdM9SN5YhoaDCvgcQqf tb3wQyWBczx24xeRSninVavTn9Bme9C/M5ldAzOhrqjio6M1W8ACp1nL+jUB163bTm3X+R/thE/8 MDOuQE/BhRrPt3TXuIFPb6OxFVE4qiNx3EdbBw8ZMfxT2NRtcay/6P4skg05TnHlyLJBueqeksHX f71o2ryfSHrh7iPGN2ySBqedAhXlHVqUc8o+otc++uSyufu6RX10xOPgQtaPILw94clAt4fSkYR1 1/ZY70hyxwjAh/qj0cnCzBr0lUA3EBrwOtYBqJHAMsL+bswsu/RkLxF3qCYNop859fwwpfQPfD2/ i/q0WSyUJklLvSyJ8kxHytPXxFa5vy1tH08yC7mgePX2FiRRvbkHH9yaaI+6bqY7CZv5AdIPGubb EOmidnioRVY54Cjwn2T2vl8r/AkxNsJI7kFYKpOUAdtlykm6FgaDCx2Pv4IsOVwYgLtF0NB/VLnm CL5ygqli1baJFXbfJFNbvk4gTIE2lT/mxhKhsgWr5fvXge9N6wU8QPbkzDOtBn7DFUgys/xQLN5p YgAPzgDtPD3YYnLwUvHzsAc/oqAExEtQrstFd+UeRRUG/y57R8AIApG0bf3/+FfjzxkEoWSA/lzK S6r9Zs1Xx3f0fWf0q8W7ekU6YCeKPIDTNrLg1ZKEvDlIXMfiTUMfiMIyM09RJfamek4AJRjaZhFa POjvE+nT4+zJYa91TI6QasR5D8t3r2tzRSR02RxxIX8+5yGSZz/z0hShB1d4iqEMmX6LiWoXNL0+ mxIJs56TOoxFhA1f0h2mzKQ2URh0mEBcTSf/01pyG4nCPdFaKHnZJhb3QH+BkHIrn8+/gFmjU8Fv esx0s/8ES1k4dD5PvNmh1jF8iSsD+VL+LCfy4N7JpSjysGfua+uTeY21POsR7f3vOhy0HYt5eaDX AZs3fkrv2p862IZxrEt0IPnwUInVDQHoP+jEEFfrftW5Xbq5y9oWQPJEjHnFwmPptFK5fBF4cS26 kxd0ZwFKVVFsb+jvZVWaFEApWrznDTR5qUmG9MuseuTJyIjuomsAnCLbHhU+4dD3dRX1JvUtIuKa 6FPTWV2LYLlEouzbJqMBLzalDWCHiEu4vfyaZSj4nsjZo46Un2otkaOXCoWPtP2kTU+SF1AYNBqf /7HtEBHwQ7lGi34xOEqiSkZU+fTnKnFvX/aj6gRPgDBglZXluTxgrFVjV1nFu0npVKphvds/kLTq CFToYnDoVbbHu3DKKxVLTbafAYumS5edllhwLH28dzEZ/8K7NFCqIIVlEnnk/ruTHN/sIcUE7ChN d3eeZ+/EXnD8ndVgD0JwpcqBeDJgp74+/coxbMto5a+pQw+n/vYmuXcxXJEmQbGf65ETYn/nuTF6 7eDnU8S5EyfswK8Nm50t0QjdS6lDAebx2hHKvS24KJZ1ZHIGpCdg7LKCNiygxer4aJguz8ZhFKlf iHL8x0ltbL6PL/8kqq8jQorckt7U84tIdKuK/vt0ecwGrP3ANJ/kLHzGtbY9feOcxsF4GvyFAxQX Dc4ODD/WcvUHX5I+VbySVd06Q2C7r2seA0aF9+75TWu8fgJ0jLBTr/1WGnbFAeQgM6KlieYlQRxy TF81aOKDrsitCVyvpNiEhlUYtKim9VgDw0R2QUEikyMZAWdhrBP2acoqY4Ha/n5LrWOLXPHIReaP 1SXTPqz5Bt5yfuDa85rUCZuDYcv8JDR2NH+8+MMzOMROqbNV4gDv9NGzIwiql2nJgBpsqWBmARnr Hi5l7HYqJxWub3HLsQml5QhHZhPt1/Y6JkTAsMYFbjM4Tse6guwMLOBwExifZtSEHcznJaeA+H2y JZJIjAhZrn2kmooARk9cFrmGQfFWSioRVouLQCPnugQXEEyvjT7AuAuggoCXsqWURnJyBJ/iKaGs QVanoTKCTzhsJCpGezxRTM9yG56WXS9YCxnZIBQN2yHt+Q0LoKh7/6Z+NGadyL6HhXcj5JDNf1Ai C0iI8kHtnFyfnl0twWesrlznflfHskuONFWV+pcZcmm7iwjuOclG/5ShwFHg+mnE6bmoJVlITToW 7shFjXto7B49ZzCiLnSLfchmH4yGE0fU7WBoadx+t64vCBg5oQwGhtlgLBb9sqVjxczNOt22orvj B3EGideGUlCVYFKWQ1hcHciHPYNeWgp/0YkKJnJq397HPTg50KcNxteigu+ClcBqA6c5TxXKaJvN mxFuGCF2MBT4dBmh/fngJlp7+0RBv/QnrxmyMdAPadSUqoLHCwfEP4DAkMj+4OKeeW4xEuEVIMTG tdwc9nrwu4ayCBod7qgnBC/xnF/ELYwNVHbfhrQODRUex1ZLotAOnUDoeUrLDfrpzj0LQhytJnlQ 8f4htaO730Y5Oyn8KyHbceR49GuOUDb8QTg1ydnIRi98K2hOTpgvQCR/0ym70q8njHwhnTPfWuK6 ZYoqxQnFz0K/TVExfzTUZu7u9xzwxol7WWkAVBNov4HWXbUK5rSkiedmSU5qgLrHi31DARI3x9da nAwBTVOyIHlN6oB1w8Vbej30xlH6yP04Ehq10TrrKXRNi5GPSREGYgZxnGXTGpKkcPA0WdeVEdjC Y1m06M9fGzWUBYXgst/TMyWd+4XFDFtMRyFdsCnMIug9C6dpr9tH+v87zb34SHPVLuGWEPFGBj0b p7vWX+fGhzcKKCzn11kTYsNyP0d0yIo4gRdvrH98y80Vz3JEck2+iEEOyfSYOMHQfyN3fZ6zRf6/ HZ3Z0thecvDXQnVKMTXRvHhB7FRUEPVu4bD2iaC6kUZdAEbTZV1UwO24Lm2VnTgHNgt8Gpsi4Rmr 3+B1q3J28ed5tHZs8R1lqYAOcdUFjNPJgYGwhtEot3eZO8b2y2Q84IYCb4TPdoW6K9w/KbiRG5Og mJqjE+CyGlTi+QCcxlXlsLQz3wKakZFeBOxv5y1owbqtkEds23WG4EBF6qE8oDPt9kT5VuzXgrJ9 3sGiIuJ6o7GTokHGUE+qqBOl8GNs2Z12O9CfxsdD+RFskGwatFh1TkRMSkwTSTPaWlakPwWlHcH0 +2skBGWbbkrI0XupNEobdI65ifF8Xsf9Fy/zEo/w8YhK3b71qCF8+15L+5jC57cv0i2QMgMj8eT2 ovmsQwxInLNIaQA24GaZaKIBtfCBIb0IqmA2G+IxTMtfDNWF2sJrM9/pnp6dOqzUEyDoJKwgHkvb 8b4cj2li7/qChpCpo/phyFh9IzYlcDgIspzAFDZeV9ITtXgDxU9KxSOh5eVmiS2NXtMjvEPN0Lae DJYqwI1hQZvwxhqq9Rz0FUSxF5op8nLh5bLYXTPx7AWe3gkOwsiwxQUeetS+IruJCKguUjlzdmL8 yaPLD+28PellHB2SqV7hY9aOCXJ8kQJmb2GkmEIbVVaLeOhCvhMLRYlSCi1iif8SKVDZNxQJZMUw +Gslm60+VfMcQC5xV1NBwqVV+Qozu4sURWzxSi8AIv+e67SGBaDYp+dpFtOYTs144DMP1xRyTOM6 MHvXuPLvZzeDp/0IEq3YLZ1xHJHnKpCx209wRGUXxrhpt8fXfR2W5AF7kcBSP6rV24pmz9hRSwfS dEb+Lt+1TskUD4yzS5L+86E0+L6GrHedlY3Jd1BxwIhsNFZavRrVgBUOV7D8v5Bk7A86dm6Iyd7b roivCripXGdd1lyyNoFSIJickIi+KWROikB6qDG9ZoUF00ak7CW0edDHq/2upUaqLCvuE0FVjjkA dLayWvJVOWbj08BnEBntnNT6WZzWHmZXe4d6qOVnRTQBt6wW53A4obDW19tOrtjPP+5I7ZG+DHP9 QtOlhsQsFZKDTXPp8EGjy42XE46ggFkKaBgc2NPrUZESrV6cwcxVNXJuVMH28h86ijh5MkkGlAn5 dBPMNyqK2xyS90eI5SyH6zy7wGnXRzTTNsp+lZKRyzID4FZqPYqgJfV9JSLazORhHsdi7fQpl7eX os4oXkI3Y5im6rmUNtecHTvRp9c2SGTfAg/bTPIHMIbWOKumdDn7aKdmMwIfMmNVpZT5fMapsNAB oqBnpBDTEYGAPwotRW4O4XsLEynX3b5lRuQYeUwXLYkLQGd6kc47OGiAvYK93NKkq5x4pkMXHYHs WtNEQ2253zwgiLFFETwS1rWs4OnbmX65eOCPaugclak28Prq1OGdMKERrH6w8TBWkAV1WxF6h32E kopqd7ahUQymPFdPXC0RvuJruR9MwRmdSQUKFgG4xaYgrSimgewuUuKFk7EinHcY8Hn2Ww3KXx5h DqK/kU+dc9UXGrBkwRDvWv8UuJihoBpEkQGSG9UDg2b9ny08eEa4vqFJQWPYVgOmOM8Aeg7uBPep sOfjkRd4vl0/kIbIAHhuF5dTdMe807bRFbI6VSpMqm1LDugsBfwLRGtFf4SfbcbeEmMKGYtZYroo WGLiXsFoj7ZsaMnZT/tOsZs2eM+wF1If7QlcnDiXJeHD2LQuXFwTymwXNcy4yyOLhUI8TpALVuYH X+VMDK2e24XdYD2OoZl4KD4A1roTFKOdn2d6aPpJQ0z0/RbOacy0c4M2T20xZBsWgflEu1N3yiCD IwpYV1pmlGSl4biILadF1u4DLjpFcaXdYX+tyvcxm/oZ6h+YlwHyLdWc6th8IbBpch4TpW/IjU3b SOJ2ijC9lFY+lp+oebTxozNyGhafrBSDZSu5+2/Vw2bnbSe3rgNVYQt8qDordo1Upbb6sdNksadL M+R8r85hagXL43JVyK28SvGRW37XxO5dhWeSk9usJtQUw/xUAKpyVIS/lu93sLYqVkMLbdetH4MW 7z0IKidLpAwEDlZ/6o75yLdPTNpVpXJ4bt3E6UlnlJf2UBDn6ySj6Y4wMXjEemYb/MA7w+sDeKBK 4m5ETnpXTCbefJY9GDJbmRBlor7R12kfysKinfXmGZ4OJaMIzQIBPRBCr4Izb8H+9TGj4jVj3dMG vPA8w9sHRZimp/ojc44+/pCekNV9LHNuQ9XoubzCgSjqGq9hCWYDLKp4MvXPsEu6Gt9OgpRBaSBL ms/ZXuvT6VSzKqYg4qzf3kk1BIPDoC3dP8LA7aM1d/7s1D6BSAym0mpTbIkToG0mKyTExjflvSF/ RnMAuoObIhls4NIwNwDzJagp5liISA3OlW3nsLr98k8rGbZf7/5TznsGyGJ6Qo7NWcD74deuokzf uMRIieH0T8Zs7aF+yzLaUA4Z534CIDt0nPfujxXNhJHarRvFE6U/7lgtpFYQEeiRW3wj44kqOfCG KnFlq7IKiehBTfwhmOGeh1xFzOH52GFtGV+rfsQP9oyLKx1YpM1UV29MxZl3Gw/NsERLYY12fPAO hFjPJK0X99G/gUDUdqdJtA6urERkO7ALsd0NxneMgNzDTFb1AjxIxI3an25eXs0070gvjM7c62ME OUBquS66fbJCkxV2xGWsEXERB+Ahj2ktkJkE1g9nqKbIMCwB6W/BIr+n1nzOsP5ApeSLIEKzPOeH SV6BUdTq8vaPcPbH9Yq12ENcnJ8x+SoUsHFB0VX5ZbutyieaTN9nRn3GgT7eLrZsIIfE0DSnZ4Ml ePYXBnwjzMw9nEJfBrL5wpDYmeEBoYBA3JOFYOXClTjkSvdxhKQaZ9zGWz6XUS34cLnF9JB1Ohhn u6jqqTsQwiTq+welfH09/77bjC0dGtuuY8rAp3VNdo/wGdRmhVUOP79me+GTRBj1Y0+hnRzQ3oMp JpQhAt8jwwCoDogm4fBSlMUzL5ngiI0l7O2ePFfI4gDgTP6nqyYeWfs2UGQ/Sl2RPHQbO8E7/xuE u7jgQYD0AwaCMZ1orukJ/pkhthSGg+LQnb28AZACg8rv4SVl0Nod5sgIAuJ2gNnxkJtgxbKrPaoI n2+oQNeyJtvvZMEGvFDAS0hg1NmqiSp1J6UKJrOAym6AmSutyMkR5jSqTMPjJUZ15DYs3eW7Nngn RoO61aMvhq1xSJtz0HNiF19xLcQPaTzmvaucMgx2+LWkhNOwAbInw5LyW2MxEu2Rm5femIQJ50uP x1BDM77wslMc3WDquLIEnVfOLNkptg2hySMTpeT1I/9Bu4eFMvD712X0wPPkgfdFSQcgBrSiNaGy htEXlPCN5jexs+fuAJJ13dP9I+iWFKinNo7y++LqeVhTp1qpePRiPS+UPlN47wF464heoYA4EGZP 88KXzfNu0H65YMOSdfRy1NrmZoToxVqEZCxrWjngccvxA075Tw5FBHkz3GxZCa2xX4xvIckFgf5P C4qM7I8/IPCavVYrQZhsrPRqkimGB9WvPDYI/96RE84Fb4Ji/6xP9uh7xsW/jgbSW8d9sVKIH2/B y1yh0C5Lyoz/sGf1kwRWQYxD8+ePMbnFUpZ9BdSTfcDb4SysLa/onCt33RNfIT0eFvNDOVhAJwBj Boktl04A6LxtJIgQfGCHB4gL1IuOsNDhyW6bbQvnFx3DGWz4PnoKFiirKAnphrHIWqUcXZ0XOZ4q MxaHRPTGMnPoM5aLcANil1eNkMwoGjwbGEbe3zdDF5Wt7d7Tay/sv1EukeQNIqNGxp535y0c0Yyy SFiDGl7EI4P8bn2t+VqNTWEMKwBn5+za/01bhl4jdBXmkt5IMCH4reqcE/9IC3YeBlsI8TgRlXeq 2R/gVDrKufGbyvLr4jhg48LNPp/fa8OjYrT1RWg2Otf08yHL9SmP7XsV0M7r43VMSUsU7n1v8Dml lAVQAhJrS02xI+ULsHpJYcjhJCj6vrlr7EatBPoIjfR12a868oBe2omgwfNbbgvA23Kp1NxhrEzD ZfpKKUEcmRwNirO9mGFx/IWZZ7DDMQj3DfUMvpvtkJaHGBs+pOLbVRXsO2/RdP663JuiQjHDTyzo PHBNchB7f574vhjtXd0yzrBSnx3ZOkMSJbKVXDQQId3Dsx92VZzvn7+k7eVNG7afcY+zu42XBmlM TqhN511o/GD9uZ8tKwiEqTRFXe9cNxaruGwg9LOo9wsjHOt0JTqDqvM6Kxcn5sXyBCm+uTP0YRev dYUc0uS5+ojYKXCUXfLDQdG9oaFOQ+oD3RVWYranv15TXNx7odTgxf1mRXMZOqebPQRojgdxPHO7 6rVSiJJfwKtAKr7f6TqWrELINKAnFYDZhwoKQMjlriMrAQ1gOXuW0Bin0jkJnSyhy7h691tWVQT7 kGotsqqmyqHSFdxnkfg0ZRbvjPG2d4HIsnqHS4Zrb+a565hbA6HX9KyueehCqQ4yr+GL3Gcp54af OVb6B1MKEBp/t8orcZ9uTQxFsDkQdmYQkBGDjmzeDvNdW0DHc2S4TKz1qr+TZ/XhPxDLu/1pcWdP Vc1c6UaT/IOO4EwV3im1kwmaLvQl6EUMO3aBmNa48fjwdH42HkYvO2CPz2aiRvlApuXCqz2SD/mO CQ4KZHeZBWr160QNGd3A5tZ4Gv5svz9IczTMJORTCZAfHmcCSnEVw1bJgNXRTqvVBJxbm2ijM6ju 5PAoSrx34fw8EbXkia+eoucpcY1nPVkkmFbTKuywFmlARxJgpyJss/xhGtAoF0S3sS+FmIokRAtr AhrrNodYzdtJu9rnob56UXfxDuSErKByj42B52xWEBJ0WecTHaVXdVJGlNJLd5go70wqOfB+ZTeY mmrS4cZ8i9ET43kIhrmcw87GRMkUIO5OanyizRJSQyiWtXv9SZ+xHbcwWkHnfyWLWOBhdAq6TBhb /koSPIAVRNeekRwxEWuXFFg7GbNapONBeKwyfbZio0IhXJgGnx7VFSQBmuVM+znbw2yjmLldP1Y+ CgzJtytH2lm5/hBLEt+VlG3RiJ7gtxoZosv2WNvPct1nA+h731k857C+n9j6g7zzGeaK32As7ydV finV8/ywGHXB3+/V6KqmthgxD+O5/tHnadht4aBVtFMtSRJbRyFjs4FUUJNuTbyCLZDp+dgyX7bO Wb3qPsJmul8lz7I8t612fGgv1uxwjKxKn1oys41V6UiYI2C6Fd1OYgyK09MsxcRroSvPRK6mpinR xC7tHWGW1vT0sIp6fEttHqozIQF0iLkK9iwoQmaE0nr0nPyDFyVDJZ1leCGnaZZXxSZiZcM/hTv9 DOXWbJZZXFpr1k8ILh5hDoGUGvP+MgN5SFFCoDiHUK85bon9lIJXVw4oi0XWf4ql/r+0uGZLVKnR kN+0mkPSCWubm0TZ5H72YDDJ5dsF3PJp8QjwMvGpXKfvRcpqXd4IUhNjTJzJ0/Gfo10z8llowKlI QdETqUDAdSlvATl/+o5jrPf/vmK9d+826hjm8rzribXKSHIinRK/G6wxQDGGRLvRZgsaK69GzECc w9y0zEF3vnFMb9zEn5X3mE+NVqduViscUSPwiYx7978PguJcGrJyu8WIcpy0P+5ZoseqSpsOhd5S uKcAkJgGtspBFdf3oqtdQA7NAF7girYlaMO0uxTKX8musaq2/1y7hqfOwUnCcOWerbhl9Tc2E2Py k0UCzbQMlAJ13Tf8KjZyo1jwYR5L7K5dmvZwHqFJEM+TSFRrG0xVoH2cJfs479VOC3s+rE8miTi0 wRgjK91mR5sDtTntzqGBaTg7Nn6jAOEOOeXXiReaI8bWLN55vRIqTDD7nfsa1lF3tndcwk1U//C6 3fjKHPtNzBibFwDITrKOgDCTuxiFQAZyBRHi3cjCxMcGZ+dyBHLFwWGUwlKC+gL3vPrPQh/PPWEb 77CvtIXhf1nKV9/uCYewwUEcQxZhkA1lZSPm1BcpYnfySinKZNifJxcQ0VnHHAaKzOSAHXnatCt9 5DtEcaLqeUUMTsMF96pFDZ7YZpPTiyr9eiqzgVgmM2HbVtWuJqkZ/PuN4CR8i6U70tWv9d5gm6i0 73vXo6oojwXEpeeKEyEoDZ3XofmsbDDV2L03sse0nwlY0NzvCq3J+m4RiMFQ7DlCM8jTu3Gpy/Zk BivybK0PfQ8FHX3ngMgBmO74b9pXB42aDYk0UPdiqr8lsR8XDMiZiIIEP4u0X7yZg+IXXSkCS1iH ZQBZynQiEr1i/v8E5sQxxd3z5DcbEYbZHNYc+PaGEOiLsf/9VGHIgOVqCAyHuyTHFX2cdxWq7Q43 VPEckfC1Lp8vfwm5BZgZesW4HClJs0eVMJ7gCA2Zm5gkjB/1QpM9NJvlbKE9QC9JPT1POPgfJaEJ MwnCkMKbr1ZucLbHxWt2scnCoQewdM/rDO1Qpu2MDIxF8ACjeXCPYwKVQlUz/lNZ0cquh7MWyfEJ xeP5mPVHIKIvTLFyfeUrmTOTZXiDAhYAN0rYzeFaFnDxPppxlZaHVZJFSYd2ETUYCbRjgkf1UlyS mjJOcxwL66TpAFmFB/ySRHn/ataBMvkR5g1zQnCldspYjbHrWpVqiAy0ZpcPFGZ4YclNXO/l64DG uvbm9PrD9mR6B1VFKnkSaUIJQSOw4FrJ9sjW7rGMTqwEMkA9/wUcs9oFjODH9Nz359nidE5Y8qGk USUX2lBcgz0b3WUph8GKeiatlptm/vR3YO/xOyvGCA1+93XIGscyZ2JLN3a+ZKRG6BSfCnHgcOxs 2QGCoWtfYx+NQv7g+ZN8rQ9sbA89B1me7IKO/JJ2Xh/NC/TWTk/g5Xg8mGLEkOYn9jKspCpSilFq PrzMESh1K3RMkAvcGOOd6XHCu1kdBqsCvNgQRQ2x/tV2uuDcmbpLh73AKD6fyT9aIcvuiRXNeH0L sD6zTymlLlP01pwKAl66eDhPW1vKK9X331ld0O5OCPIOHWtdfMgGp3LRLRhPlU9Huy632WdMkxG/ UWc7fWG1SUorZZxwB+2ZUMiua/095gw59DVyblm5AdAKuOsSlAZPgiOIcKVeV2wYNJZHO7XF96eZ lnsuCgPt+UXCDxXR4twqbnD7Csh49YHzNMMT3ZXTIbGH0XMkDPnXe3BLyL7TV6wBNtly8EhcL+bu cP+omkuCP2HoQ77SN/I2hgnT2p9IYIKY3Vt8KWMy9SYi/qcI9o0zVF9+IdzEivRg+1BWsSTSjYLu /v8EaOrFRKfbpQa4hV5ldRK6cVP8gn5bajJezWIB9xc+dQe2nfLgHixO0VlXt5AZQZmrs0tpmnjs KihDLi4al9R1w6oM+h4vUqo5/6Nes/j77QEm5h5Eyi5Fk1BqVqsJBz8v791gQRoVXBfJu/gHBIJh kWxTMVkoTC+SEmYyupNVPHH+43nZ+U062ig53UCck2wJJF4JYO6DyyXhqrrWWvsrzR4xJQtUdcAF UvaHMv8szb7Yyu/4W7rihhSUIP8rqNlnZY31YiaIJjuuThzEMqzHdChaSUn/a+FmSJY6M8zo45Q0 to/DgLl2GtlX4qLIe1di/fJ1yI8JQd3dRjACOTNOLAJYutwh6gu4/+7xBoZTrmCAREE7S/C0Mpoq 6bYN5D0rik+87CdYmHx99QdWREh0V9J1K/qELkPSWGYnmU41t6zM3PlWaUPRHs3g/rCNdC0sOTTn SbmN6s0+mTFvdy2eTq+17sogDht5aIiDf2e3uo5Aytvf1e6VruypeFpBtx5tq1PYOBD618PSexJ/ HCPILERvN8lXQGzdWF8gKArdCkTboCtvl6nR6OnFu6Lh0nmtv6AQ4BT2DSbdM+LQi0MwcccppHCY 0IpkRQ1cBVfQ6pJb5G+KrJ71Y4tNtm7HU+9D0JBeEeDjWGVJWGtR3pvMfJRxsgfA6ied9zTg2lju sXWT9Nr9iHANgxtdBFvoWq6xOY8lxdj7XFqsDt8SLMtIqrGGSD1etiB/1ihLBvJ1zEswxAuPhy4t wKMV/np6VqCoLcZgPVVQPw14vUmtNdHgj9ZhtsmojPGFMPA7ldThKb5I+uwM8VORfmXU1dkZ3adN 49BS2AYV4IOYz0CPog7pBjzZNCxUQgo/sscK6gyH3Gano9teCm1xnSHVV3TGfjeS53zp60vKAcHG QSLA+ILyLz12tFp+g7Eq+eBUcvEL9g/UHQJPiCPsy8Ff+XsOtT8cXLGKBf9mDpnhu6IL2GuD+r+9 DozYHulCc504zXu6kAps+zUbFvcEiJe0lxXbgM1tLY0wBi0zs1NCrKaCNWSod8xg2zuWrtQVH3bt u5HDRkuppEOX6HY6jk5NBtvEEqWCRtppxJbZl7TQ7gpOAgEaQ9EmOPT6EYXxaQgkHidrpeBq9aSk qL5GOSbAADHr/XOJmevMdwa0abxyZCiel9279iPss/VPQFNd+m7lU1YUmhGYnyAuDFXWdMPmZH6Y P4rAmBxSrxmCvltvhIAC7zSTBC+0WBy2559LN+85FG8ghOFP+R+Zib7CRLoObIgljQ7CyeZRsMKS 5pbZCyXNigO8rsfzuZQeyqqpQ5ofcVZFeJwzkFyXJzLBUEjUI3ASTyEchjb6/6JLfz20VGD659Ps Z9COmN/2Mb0K3XuUOMgJTOeeGn1Vz9FoTx6NJIA5TzUpZtMiSNguxXRQavAXJRVKde3p4P57xemq /xpSyJUc4TRRUwptATIytAgnECjPdsQknlSNWmlFcwG5z5MvamShWEBV/hRn4TYwBmCuYan3fpng zbYkh/ZU06YRvN8HQ00Wq/YKEEp6m3QQCBYF6bTho0/z/6oKYmUXbBoSomQz1CdrkmrswJpJIZes mmW7auwrEk5TGxvLoKI0itqKVHM94glFCZ/mHaKPgBNzmfOVXx5hB/5u8NyGAIQ0/0Xhx1AyQz9G jloDYzipfYH8CKgWe70cQES0f+ycL35LTKP9DA5BJJETWoVE8opBC3DJ4ezASSqUa7ThMzCq3Po+ 7jqjSGEN+jOxZnyjw96dASqECWNC/dExqmlQed6g+Mf/PG1Ii/tzKaea4FIwycTXr6pTDMWH6g8U fgpjjMmaG8DxDFxMS+OmTl3JBMSHQxh5WoHp9NfRN0lL1vmCIQ3TqGzYjkhEHU3urkQoGRu8wj2R vF2G+O+yCDLSjEELtauTGKQIQIy0xKrRf94Xp7ZOMms19m9bDJiQkxu+1yUgT/qQAQoMPIRNt2Yu xHKIWqPY4oT8tl2sK6FjRVCjdiYQJpEvX5qhjxjB+fRd9V9BXSqGSsQd40+br3nVBAl5Tqtvuu/E DyABgurnKB0zIwBdtBgMJFSk+QPw3hdTTXVKJBgCXW3JfMMMiVP4hxFHbXn8NNUbqiMWAXPmEF5C tZOv1T/lHaDNRZB1r9oeph7f6TGY3GivXEkdXmzIc9klZn5fUZMrE2IzhF9sZSZmMqXDvQCd4Da8 R65J4pEepSJrdQ1cSjDMXIx8o/N2TvhTCP5tdF25F7Z4FX0tPBYP82gtisohcDcyrjzAZIux/8xd wL/YgnKW1IwUur3zLGb9QIh0zp4f3VAXY87fdpXza2v4Lp6VoHXossUNeyUoAO6+DY5HZvnRPWR+ viMImy1szESWWQavTGN2una5kpqYDKGiOn0jDgtYw825S82yCWY8bRCqfuYPppcAafsfVERLgFkr YHyy3wcaOelTxfvpfnUWubZHhZx1Y3X3JeXIq7tBQjRfmQvLyHejQxYKdSxzRcveCl4DHwC2Auz7 p/nPQP0Y8boFKqwgQMqOAXvURGFQf/Yr6nBkSpwQsEnPZjZghucKsr2CdNB19/N8ttVV6IAPa6or J0+o0qm0fUjG2YLyQkx5xIaWoEVu9BfhTUj6UgW584TTPptQpHCHVv5xAxxFTBs2zKVsRNaYSyOe p7t/eQUoQSaZCOZZigbsEvlm5LYC85mbhT3+wwAam4yQWIONf9T0vtfRtIvh7NSVUKaHWHhrJVln okd+nbIareblkr5QT2u8vHUU/dHtYPPfkij47Z0znLvm/Z0OwxUy/6TWbLpbclyoUOBhsUItr128 WWcdsoLv0miZ2cm3PaFRi4s2BufbUvETJxYl7JdhouDy2HsTGM/JZP+T0hwjqtsD/wDNHD20UZo9 gKTaIOvkv14J5gexoVqm1ZD7Es4UzO4kcWy51dLJIbNI+IDvfOcasXYcoG3/406X0/qynxs/p+H6 L2+EW+srV2JY+rv4OwQpY9ynetGQqyFxZ1eFxNNktl2+iG8kUaFivx094BUflQAso+7949XZcsFt ldYF0Zoc2nqAFaJz2bQrrZIyGR6noIApKk3ynR+k6rqWgRjaPZHQ5aQWOfApimjsIPM5KtTS9HYU 1mdx6VtErXUAxkn/NoLJ59bLtBqm0HAzHb2fApqtqb9lRXwyt7H6qv/du588Q4ZdrbQFF13auYog ILrMMQGPV3ugP8RPW4+b4vR1XJUieHtvYs/mcSGn6gLe3exNwzt8Zso9kn26gb0bXA2xy8xVlU5x Aa3qXhZmlqoTppSnYWtGheZ9RmAgwydaVA6/XwGJKgeIgZZ9mkifQe2wGCQFmY2NxTrKDvSF6FZP plVtUARQKv6gH0FZvjF3ZavpR93+udWhQoaN29IxOk5a00P+v1WqWq7Bwy/Te6RQ41qRAL18Y56f woYtGIKiIjCTm5dzWcWFtTxG75c8LwqqPHi/LWoYgdFKYtJf/kU1RmHqNr56TsVF+vcfpeHHsmUD 8OiPmUEu/mfgDp3tPaPNxuwzehZ9tFH2HkYhclqBUI1N6xuqGjpJ6R4NDDLcbDqKWzTKLbpvO3rK jTymaOX0e0MJKZUoISJ2gbhBnsCJZwEqDLWXvSvsE5b1qjh8Af0/LtWuBzUtVKSPELkFtepL4nhg KNB6rYVVGHhyO47iYFIPYwxmF+kXR7KXms/UWBG0VoHu/kzZ1tY1JJp7J1I//CTIlgvw7wLjV1Qu SrnCjN8uMGZdmEj6P+hl++SSplRMDcTzaCztgWTt/L3qPMCEJhKQdnDMy01tvx0S1wiCACvb4KK6 fUSrhAgRoRAk6sCup7RqVfzEUakiAthJVWKXoiTigC1SWPwnhBNgbv57T8QwwrWvmpy3FFBPskW6 vWIuazhI1AdWqJA+ytAVwSM1X3FDsu9ejJn545E+M9Xwv5VLpYjE/WQm5p36JhzF4Gjm5Cl12nvx KYWBhFGvxpfjKI9VyMbpmZ+8Uc3850C0VHMAq9A8zQ9p1LPRiGcSpwbABpLroDQsEneLIF5T9n26 kpzkGEqFbAfphWOhipLprHSa+Ne7yHU9Cftkg138C9MlTSR9cMs7W3oo2Yl9wxKlCe5PUHciWmJd 2wAQrU1lisoY1hWSAPQj5ZTCSdyZimVHR8Rk9VPqe566cNhlIz760T+12F7Bjm3rf5ENRAYm2ac7 R8jlqa+SvBeobF6Q1Y+JpRhvvYO9r/GlfC5Ddrr/W+q0b5l3HRqChXmWkwkgepyRHDXr664Um/Gz SoGFOQ5csAHKQycphmurbu6YVaGLMt/Eghkwjaf31LgDHLBmS0pYBibjf2wRLVC3Ml3hZPVIyp5s /QrfDk+Suq0Mwq2ttpoeox+0SBytihIyIx4Iz/kbOrbFRXm2kRsqK5883Sy/9tfFcF7nBPVQjJKC oI8pzXZVlsXHLEzZFw39DQ6DUFYKW1dT0LN2G92TIg8PrxZWb03nKXyzRxv17GtbaBofcUMS7W05 Yi+WOC4vo8u6K9jz8GKMEQellmZFbnhxomhBoOSa16BEWIgbjQpf7BjyV4rPsexG7bfMeUUU5n6d qdPOU3ck5F1yspwwqPNYBEKCRBzqAPNyAILd8URji2vJBK9Q3em26ETmrVN96eEnzmnhWcUHPKQO 6xCIQa+L3oy2MOtfKIgkSUW9qTcKVm9TvlvjrwTcL33yFZ2UsIxpNRWN58OzOb16SDUkqW96Na3d B7TSDZgRGOAO8dQS2gFRqF/VUolLEnFOKizPus758HLzs/rVaDNKdgCzLZMwa7qCq7DYoTQeacpj /Iq+37aB/g64yzGMUUEe/bhXjj0YNsHfO6b4i9w7n+XgLD69AFCgd5BHnKDXgvUt8NBcK6cyy4Yr dtdgA4aAGnuisHeRBbFH+ghxBoW4A/bzmrQS5LIsRR68Xqv4Q+4pmlTU+g1LmYdmZofHOYNExzmq Ggsc+R6ppNNtV+XnWV/x5FNfGkqRcHTlNZpTpy1mPwQPaIMOZBBAFxDatgdBdvI/3wexx6MC7deu zuvCGH+nWKNgNX5pJGl7oywXzP1ptK/1Y1lIwYNkCRT0iOn7/ZHnPyKIq2Ny2KH9PQiIzgXeGIcL UvncSdqrNAXVrLY168mKHeYcHWxXccsv3zzhN2S/qGYX790Knwva+LRV2k2cQ7jS5a6+codQyZZv i7S525km8y5Tzs6KeFQ0wfZemuwSuFNAA+HP48PyP9174/vLD2OhFbOYtL/UxMyAKcPZs7Uo8Gcq EMuJemYWN3s8LNHmSGTm9lxFFRmcBCegYNh//0yx+Tkrfs/0yYk94z6dr20EyTjNuzxMXoHimfPj 7HVrunauP9ytD2HwuOh6flsiHqAFQNVM7Bfn5ZtvHnslct9R0F28SNXFeWmE+rFIl0zoQcBe3R6d t9dp+bvbGAePSpx77a3FbqKXkUr4NeDVjiOyv74pZjiJJB+oCZ2r8YivD7RnrkEz6Vjq2u8NjFo3 4iyhuvbC5oNiea6lKqlgsZ/JMjjzqwAPxDNDg/mnfeUcsX38hv2Dv3MGgbB0abzUKrkLV7wTflqL T3jx+LI87ohbMYcL2SaUxrAcD5zTZPFGVc4Tf2QWa8a7fGofbocQ07Ww4aBlIhNEvOBKKBgOZJnH n/vB8pbinhNXxrJ2UmUQqg9Yk73zDBNZ5rcS8B+fCY2qLIhKIgao4a2/UsbdkNv4UQXuuJGcP9L4 B8nHtyb0NbkZX0qulWHIpfrgIy9z1DzGwtH52VIIt1HZ2mfxyxBh8/622D8uk9Kfrk+V8r9mrl8j UMgkut35c5s3BK8/99MQpo1YvGhxGFGY/eIrg+0yWsgMiBwtMIPZNFZT8HC9DJzqVW8oj3eqSFP6 OFAlxlVDrOBImaJ2U31HBWoHHiW/5+xvkT8sjFK7fbIEODtlYSQPQbZg/W+aiSXr/jMyvrnRXdJJ njh4eCn5JmEcgmDNalTcZNTV5MxHLaqAftW6Rn50iQclb3CJRCKbpPTzEwGPN8ZZGaJi10JVJh92 iUfIjtpesHM4bhumN0lRV64nv5FwZyrDNZYj2S11GhjnYPUpA4I1joiKQkyY/lBcNU9JptBVd4yb FfkJJ531J0OL4+sAOpBJGanB9QJW4I1YycTByhXMA+d3TAObyTeIx1wTD3XFcRiEfdguwTyhLHOj bY5MvlCO7pE7p85xpPH3vFTHJzO8qEzN22iuJsvAtuIBXivhKrsPQ7zhrVqblLxaYUaMfF0nG8SI rKN7Umk102DVAZXJV1elNmiYAB1eWfctxejAdYXm6DQTz7SY1N2B5Dh1oP1UViA9irEV8JYSVyqS bS4kglPH4wlYczwYdMk3S6pUYpyKl413NznToBYEuMU0GJPgkdIgF68Msu49a+Ok1dTGfvwZBwFM dnO8ZNPj8jG92fAXh+sMoYKjBYwYZgC8wnVmOWBQbsMe9VpXjZ/8wbnVWG6wiW3S65M6WUCyuL7p Z/LHDckXKde2BlMaKkVMF2fjvyiugOtewu8PKtNT0tg+he/gfx7XQV5gd5C6Bt7Ek/EGsIv9wwjE Gt7SOB9cfkZ2n2GEnPwnBTf6j+CClqRRmNjTC0suXjQr4INW7FwAXMBBGQQcVYZBcisw5E41UZdZ 0yr1mN+zpD4jLlrvernN8qoMfId0JGqIty3KdiTuy9pSQmAcjmWMNyLT110XzRAqpwflfZ3i1Dug R+bApBPk3N0Bdw+KR0PaxJj8Aua9rPkC/7y0lUPQwTr1Nq2O8QWwsl9oy5Ea7mQcWYsTm7kAwG6N xD2MftWP6VCyjjRQgg5ZdVgpRfoOx3dwuu+ghC1ZcsIL81W4drGE1ooOvFKtJ0Qm2AOoOwCzE+8G qVKxtP7mh+KHYE1XHJZDvNxt4u4UuAUtnQZICGcLQGhm7JDpjWT7m3mYkrN5BU8bmnx+IoN60/Ms gpyAlMpGjA1+exxqXoM/CXt+w6LPAAGWmsgAJSQwtNZRuOHsB6WwXO8FIZlSOHZvTqtmZzqdm6/L +vP/7FftxNWHNRnT8V/k12d1mdbsd8DfiViFyzIKIAcTEGN0kzQrcnk+CbpaBhK/y7i92Gwcwg/J TM5RClf7bxCEihSua7wgaerRJpsIckcxScsbzYwKTz+m8WL82cJ7ZD7aqqqM8rGetF/eycTM/gEU Ofdkpz6sFJZOI6gQVUbnjSE9PsU3IJ+R0RPXAqfcVsms1KnQZWfxAWHRGVxPB9h6bdblHwKQUTsc KLBlfSObdulrKXQdvrdcqE6+4GOjrqmEscj11p7meaqH+CSrS/7dt9GR29i9ru9rA4PrhX/xEFwI s5keCwcY6o68b4zAOcfhkkNFYSQpPU2AWKePaxN8N2xKigiGE0MaShTyYcBeDMeOmNKGIfNvBy2w qqcoE6XbXJ0Naomlr/ZWB0gYBHoN9XSMG9nmiChtIxMjF8QThr/X8qxqIUFo9QA8T5Of6HJBdF7w WNbCOKMTjMUihaye3fD+lU9V0xxnTXTObRsRkF+Ao1pCldb+jX20AfKPA7YGjpKxK0X+nNHYMmA0 keW4hAMAmDKwIBFf5Te09aWNqnTjoFk46OrEOiJOCjj1nfj9RHCmaPviNty9K31Zr8yNB/PJOkRF 9Wm0Xn4lIIiM+QIn4gbRL1YERz4r8cPmVA3oAIwGdBhGYX/gsp3zoQjxYxYw8FC2DJ17N7jabnTW o2LaEEyyTINB3rLOIf3jb7m6E4j88u9aaH/TwZgUy5iAOjAf10Cas5cy/DImcf+dV+9tRPi1MSZE famkGCwNWQZg1Vf+WJBaSAWr3dv6qOEjZIEAesUe+Ajzz1AHf7sFTsjVCGoR+6EaPEPAOEr58uSp UDpKrB0Jl3zyr0Ur6S6WreZ5ww+jgGoiiSTSiKfq0mlL1iVC7W+gZbwIOTxKlWo7A8Y8A4yv865j o8zuCerD/n+/rbLF2gJiVq3/J7Td7He+45IhiyXjIGhvBwrJJjMQkPrpNlTFmG5ul11qOgfDBaEx 9pCdb9HzXyi689oBZ8IcuvOBwg+I8xIlK+00T+T1sEAIiv0IlYD7lF31AS2Xp1hTYsTbEbwomQI5 o4Y2OEYqIMN4sDXyPTJmHG5DdWWSmKIKMUO/HxdwvCYmf5kuofbDV4/jd4wWaW+TGzJgR5ks0f+Z Z4zS7RRyH/V9DZoZxqNIET71+8QN5W7WU1/3HB/qYpakfqca2U4p9AT5vataL4zUwJyJ9XSS6VMz PyuacEr0cqbr2PPhocQsC+8KZDiiTEScvuz1AYuEJ/jdcPAql0LHS34xLcH52Ox7PAMRkgfGgKna 6fMWM4ZDyZyAfVpCINPalMovdQMvn6szGIVU010QNac66aaWTtOsJ6P/WhSyKntIvLWtm1nTggCL pGci7EGvmuIlzbazxHiyyG3yn77Ewfwm1Wih9s8GsrWvvYh0YSYwspRhYwQ97LxGvsmWVxcL8txM Kfi6UveMYHSzM2MNf7Zv7CcLuLt+NzgcQHXW2yR8zGUQni0o/ErFXuV5LrtP82DMD7wSF60WXF+I K64OYWv7EQcVCe6nviAOYKlz8gZZ3UqiqOp2D3Yulp6uVEqypmCQWsmDPXtoTAQSfnEPsH5GQSHx eLMHD9RuFfiwr7wCabELs0/PV0GO1KvIWmVNfIv4JW9UFFOXJmU4Yf/fLib6zzQpPaKFbwnBijp/ AtjzZxW+70o4PZSzzOI8uLafuWGMWNwm4G+gsgUNdrHBUq2yPZ8SkR58qqIfsig+YF/PCn6j6ZMw 9Ex3AYwExXBCCYuWZCQrPHfq+49VOFTdOXTkbdq7D8CP8fQRYoe6B02cmKrKnAfJuxoN8mZf+v1d /mQQAWeU9yEvNCYqnJ51B/bjPVWGASZq7kCeutIB5N8bHVA8JDR/zZ7glFpLqKUEWuLKOo7fpnEM Sd7LvJ46vV/eawDeEt7fJKSn45Ahwj1GMMVoizt9ZBRN25BpGcUipYDOaa1kU5+Ka+WjRkqeae89 /hcUU7fVC6PHgy2hNmgrwXTWS7H1z6B2vI1sYGF7+CKBtnbMddyxia/+NsGYrh6FHb8y2Dj8WfQE 8Lo2pwOhU/CF2peJyRj04IcNG4Fp0z6ZbyYXlbz1ZpJUx0Z4yFyD9L9ab5V+a3mdDf36Tr1u1CE6 qHAKBfU/KD6dXOgOD9WlyLfRzZVeIkcSOeufayjdWYAMQ1MJ+7pLDld4tti184NxPMnSN8aLHp76 qHtrISow68/r52bSKtkgLWHLz3/Ry7KUVfnymlu1N1M6pHHAZz/NNP8Ge2W5PPainQfFi35cr0mo v+v47GoWH3b6zk0gpnLadnyn1LbTVStrhQR7vUJBlv01Nb/PfLZ4zNrCHsrj+OOxmygf3q2BNbc9 EJi1R2ihlxSEglsqWIaNyYPfmPIsPxSp+O4hwZN0POU4cXzODp/a3/zgqRMr3YGnHIQ/pI5hJPux 3CHFlHwNBuMJQETfZx+2qe2QYAw8exdldznYFBPqKqYGXybpErohKL3+aDzWtRfKkfrGHvh86t5u tqoaa3gLgxsUfq4iQNMp+yHjU1knF6WC6+p0tiPpChgiK3cMNAlh4HQShdSPZVkxa5ot62gX4d4d y+bwrligv2AKR6QuU/8BmYSErkOSm5MI8+GhbingFgo8RTfahxX78EbC7ZouCZkd/GvkbQ+2Sc6L tpmp1zGkn3nMefHQAw4iMXUsDT9OHtLrwmYmXt73pGze3ezjZLd5HeuOMhkloyyxd5ZeaAtwcPmD W5HKSX1utXyZQ4InXynPsk18WVEJjdDfoYr0rkSyJp6wFzIkMwqfcYE19VORqdnLPEauh4antEI7 fZ0AN8UtH0PK/EfltzpVzIX6v5kXQhKv3gFebrtyOdIesBcpejC0sgXq66ghXOghbqCZqeeMPHKL KeSaa1J1d2WEdMTE14K55lvuIVjY4UDeTdySrOv8n+h7IXwwUwxbt+DP6ghIyAbuOPeJjtf/4W8C 2VbnPsMIJr0lPwcGJKPX4CYb7MS953y6IyDRKSqJDplu/AOJlzrMQAnUQM2EH2cs/TLptGN5bVbz M51cEEjzFVk9CuI9srRrQ7gz7zHwEgdidH6zvtwkM/HwubWgQhk0glhiJ6VJq5+eB3ftAh6Dybn3 HmUbBz8oTisUse9b/Xctm1Nak3VnDL8o0jpVfYf2Ef5TJ47JjS0C+KPrMxrPRQF82vo+agSTXz4v RvvXr9ZEPNcy3kmwe206MP/dcwCsZJBqmBsIaXXW7usdKzwKQOLbDsIZjAfikskrZviOXMW9Euya 5ISy79wShyQDHURUCJlysfDBMP6R7l7BFBdqkCf1DmJpNcqCj1oGJSEh09rocmlEIFhsDgN0bM7I f+lXbGwAiCg+Y1iMw4mdSeyPkn8ydQpPBQumPpAe0mQBoHWHtnWaeW9b80W2gucrhZJk80EQj2fP fcT+gHCh0QXpYWzLc8of3thyr1Wv4lXpL9KSoRgH6QZFbmVHwJZ6WIZcaYz19zcLMW5W6qaRfnbM O3UGEStzm0OKlZBSLC1inuzJeeLv4wC7vba4wpdG/8xVX3bSp/pVX8WTJ9jellJjThUpOqgu03uI U/3Aerr4hbGxR8xhXEazAPM3JLfAyzb67c+i96ggke9TJ6r7YNreHDtHERILRjUWYVBWR5ebDPnN MJtQZbfMBG8v6wNfj3sX0WZDMERH0poaxXzPV9LEQ+Rmkt6HjQpr/KdLBD3Ribh0vBXlBbGZy5nf WVtT602ZgxAzBEMoq0q4R1IwxW49+6e8oKz7RigI5KPnmGy7Q4WgMZNrPSAsvcGiFTFF2yQWI4Ve P41aHhWCLI6VhCdvtQQEwbGqSPbM3kan9wxCyRcNyv+C8nXE9Ffa0csNgANvc8AlX6KMKLJHGwYg M+0vEu6WhI564chcso0VW1pg74EiHLf7wKrCZa2GHd0kqg/gXea5Xr7/EL17d1I1N/2lsGH7njr3 StJSsZOndsTDnsF5MH1pXsknZ3rEkFLhaYuoVFrF3HKNIT3Wwud9J3IZB88KKgL1r/cFnA60Z0r6 e60tn+PJCU/Dr1Q+WpMyD0bvtoseU65DYd3iFPVoYkOQ6bt9XYNzpOa4Sw4iXuTFq9Otxt/uEaLQ 6c0ngvQh5HyxLcBZYsVvNT5LGnWjf2oA1uc4PA+MkEiQIfPfzesW81O6HKW8YyBwc961GKUwjFIo pwG0huYiZYsF80NY7ncIAmm6yMAXk7K0Yd6dBQyTMPH1EjYHI8hJrVjiHSnq2cA2w9HkB6NglIAU 3Rk94d1lOAsPTa4fdCqV/P+oB+Ydf5OfcDoR1kpg7ng8cZanaCp8SiB/z2ZjETDfs6jzm4EEB6kg jPGMqt/dk0kgclsn53kLa7DuIJtJbeTiUJKRpL+Msy9uDycXM+lcHfcDT8HJShwGoXefxd5s+iA4 Q6/Nish141lCWolqYA/y3y2HeXw22fPMywbJdN4A7/627OHNjppiiywD2ENXjW/soY6j/w6hQIoj lb91ahBRZPNEbOrMBV3rOtFIahXnjvuCAtO+ZjLglHbcfvPE0ZMb6mhBuiK+bRcNovwo1rC/CTEu pWn6DS0CdWF9x36GmXg2aGLQ4F8yeGyql1hnx/BvD/YJ59BZ5DIIgftPjzmAatQWEutunaNlxkxc IymBe8KO4gKKd07jssLwYYFD7gRkOkppi+VqE1OYyGDsehaPLdKmHgXq1rCGE0ZNH4rK8n8PxsRH N8HmEqZtjHIyVu9Cxp/ajx95mwou7x8U3b2tClo76Shd0QJhRhv1Q1QNTWmCRjNad+BZguKGSW/J kvRt5xKsZZeIg2v4uN1h7QEHjJzSEmDTz0DXHohlP8Cc0qa5OtuvoPpnKLAgpj09zThKNsCkEdsk 9uvF3MGY7v0KPsSwpLqkizO0riMpV6xJUn14P+EFTehbAu+Hg1btfl9cvBRwowd5UfV5q3krsnkf 9X4m+PEhWrww/C5TxDBS9xTMzd+PAwZ3/dhlv5dfbEtpwqtI1zfNEKe03SVKtS9YJXblmRU34qp/ KW1Ewaq7JtrLzFjFIig2+iv7GSZ6Ec5ZKOFAJQjIp7/ruUlglGJFgLY1nls07aUEt6C5SIJZZYcc FGI4k9WBfWiMlYAI5sMX07lhHThkRK7G5gz1JlxXousr+RGETbSoDcXoBpuRAW1W8+c/quz3ghBd 2lGJAfMmKt85t7Ck/mvnaQQ7V4UccZHSRsOugOvC+qkNPQqvmL/hz9WsRMlXeQtq+TDB/miOlONB vCrj0jIQ7PIDYNoKil2LlukaEF/SuD3dF7H5xP6zMi+msRrQd88hwLavYJlfyNuSmw/FugRwSKWh jX13kgbLOlQtp/du1PFgCjBPN98bxXdDIlzztFrcyEN6Jct5KBN2XO+pB2f4TYId8PBwj6XhXMfq 3NtPWsd9CG5agMlNFBpKpTxWA9kUE07JEavw5aJ2YlgxbSojhYAAov2pdMAfmdoB+uY4/R8d4YjH tm5c6zJeZpXlTKitGn3f+77HBixbDSlDpcz7tnEb4o3LTmfWj4D1KO3xDooT8oDqqkRj90SBYrfX opJn5Gx6UtbMcnP/hHViQAM7N+TLhA36zjM1JZoEnXVzwr8AO2qAQU/3KwXMSNyB0UqsIIilNtn3 EAdFqs7H9q3AIQPhHvK1/r2rvf+n0jxDTZG0IKs+1JrWLXlf1JkhgaGjC5fbXMM1rlV9CrRcVAHN 8DpDnXjeakyFS7MuGqyO1oyMP6lEwbG6j+Iv0FK/UZrZKWZfQtfu0/pa+b4EFh9+420XFTDRUZnL cWA3pubJiHkox3DDuE3OlSJ+Dre0OCG5vhwdj//2m7czGf3OPymKHD871vYczCfc4Q1Tg0AEiFkx CwTKB5HjuCv+08Zx01U3A3NHGpWWd/B/5o2qGMylls2j7+M/62PmEtK+XKIhLCqxxrQOeNUPnNv/ 1gJSTQQRwzCrrry2pdiPEi9m7AqRp/rFRoZySxAd/3dX/GBvBbhyxzlpYxrFoMOK3NU9SaPTvFeY FvSEJnzK5vGLm0ynapIKz3/vTBE/t2UUwDF0A7rLlFInj13GzeBIqr9OujQ8VP2DSZcBO2Fi5j8o aBY0lX1sKW132pPxr7spjwRBA3+2Fi2tDh9E5YlZUOkFd+UflTjaWu1Q0/xlWmZCX8sP24MU/MjF OpbQ+o92c1uau+zSQ23J6b0X8fPxbW/19JsrQbHRsWn0azshKKPLd6oyFPSDrbuT+9HEJYIUmzxl gL803rus8cHiKRHPkf38r0n9snLgdlSbRUSMCgJz+irGMxCNQ3nHqKlDHizNPdq74nOiY7V7K1jy mKW0jGyU8f/k7HiMSDgLbnpfQqL+2UuzMkTlo17MA5rDO+EFu/KOo9psOxmJ/YWt+B4r+O/RZesw IZRsQsfh7REn9U/PoyyDv14qCkfldl+U9DF6zH30b3T7DAwAxrjVlr7DyBk+oTGUxeCRxbz9QmpL sHX68wd+emYOrZ9rCwo9QuxCx8byNEbc96UWpL0h66jul/Vj2Z/IvkkOh8i6o/rd1krHzyPevQm8 8v3mQUVyGeJGyaVgJTDktUrdE/OlLCOWlnnr4p6fiVpbFtdECJTws7KnJDcNkbbS5J3IYDVbwPAB 6uNJvF88XIfkDJ5SHmHPfc8t7zDWrz8rMhxDgaHh2BzRFm9aVDMeZqieSAy7ubYpB4nfVx2onTIp TkR7FIyKp8jXW0R4VXiNRBmhG7qaYnqPHBIXU6uxmqznIWZF5Jb3FS23ypJfrSpX/HHTL76ixaZj sWjhclZNx7z4RuARQvXvu2GIUzFF9xl+bo++uI/kYThBfJOIG2MH9s96M0MBq4a/b72a+zCbBUh7 i+v70KacbCdf1BSUNYAfOoSm6G+FVWFdbcAJjT6mWO9U5kEPXeny98T3onaGEwf0FdoAKWcYMrjC 65mcTHCxCsyEfuFOXQ72DwrmNUFdbhdKL0Yghvs8FyaVZ2QOqdKiMyIjU9uUO2GfXiHlee6xc7xC fojeGTmVhod+lRP2rUmrpy1HkZO/F4sd2JMo3zWckCjvniLt/Fl9HZ20dOYDYuToFVpx/IM7rOpm GBhhUzsUFwOGm4uQi+QFX926MvWRBUXXSVz/790jxvs4D/One90HEaTAHPIF/YXuq+Z0Uz5d8Xfi HLBbUNoGA6B7ePiH+Xmbungc7n2gz3GJtW3jtCEhHNO+xj7+j/N80LJ8YeeediRJAz967Q2LmVb0 oVbkslcVuXdJg9sv9O05t5sXM44WYSCdDlESGdRJ+0GnzOZEJcQplxHa3EW1m5IOmDwJjy2+EKqo Gako6f5v+4YbEBwzqG9KFScq5mTKuIz9kzPmAV5v/IIGTm5mETt4KK8c0J5luN+7ZxigffDTkQlY 9nuHa/n4cw60+8Dw1nkBgWcycRAysf+se7no72mMZ5LftYWvdiSDcmEy1OtmGt26kGS3RaH1CNp3 bX0fN1D2FAmJTefAASsY0D/HkI/qkRGnKJJEUv8JwxsXVe8a1eQnvpzQg3jxDX0XUXvNrb98HH+l Ruhq2Sr5T4qRZSwlyAHdJZ+HVVQMzx3+sTkZavTqK/bSacW+UzpIRE9G/EfpOdMpTGjAr0Y0aYAL +9LAnGW0lT+CkfXJ/d/OWtAbJLMVBRLb2MqU8+YKrbOZlfFQMh3xG7grUDL8kzIcFOEO4jivDADC q4HAhPPi0A6i3nkg8Qf9jZ81CCIP4mhEhrWtCK7lgoYUKoincIys22l7nmPHRY0KLnBXD8bd76iP 3MuWTJ77VDUqDPlAJQxQd1C4fbOTAjhsjhEUp7Uv5su2+EQWfDfqUZsNIvfEBECA0cd7ZvoTlxbU FmGP2C8G2jW1OR281sL5TF4PdCsh3K9sufUWVM9RNRfjp5lA/GtEXkQwPU5eCATTNk1v8J15sNMz b1TyIVScUTcwYJbGl5QsjtVK1BzQ+PSyfjyE00RyHJp/tQ/AKhbrWi5PvJHLveP8CTItkHB1ZHmO FX1109NPhbAsJz89+LVOl49R8W4bRb57HvhNmJkwS6lWSyyc3J+yeC/Swsm8FrtKJZgUe3MR34Wq x+rEvWjJelrGFwzZjQfJ+mOt3kkp2C45T9GeiCXjy0igknlyZIQzsDwNYxtJ9YM4V+R31Hj0sIvC qcC2kbygoFGcHOBEp+oEX5SQwe5NGoR8qMmKuEPDpIs16C283cUH0GcnErWKh7yXwcQ9mBzLwDbl fe/6LUvEvTGXHEHkmEq8SfRkVAPhSP18i9pnH1W+vqgpRHISWPnmQGCMq+9aCdweBr9QYr8bfWum /D7v302HM8Q0b6u8tixC6SEd0HepoNW3sfkyU51Q9V1W9Vl4/rsKvOVbnWI5YpJh+CzGZHmWAJVs vxOIXXkwb+hPDa4EKCr3IO+p8sPtvM66LkbJiXNZzG771XpbbdIqFHbAjfjnCwit8XdVEtueWk1j 1MxmgvZ8rAYWTuwv3A5wunbvnKMBJoov3y0jjo3OpLN+zgLb/c6OxCGqXVBbVAjQwvEivdMjol2F mviaG1pDwbq+CTqrT4Qn5LLlXaLnU2PNk5YOBhOWoBnIlIAsq+R9sd4MaEMUe7z4T2W+3YTg/d+8 02xl5O/gGmjTv/OIZU0JjNB1jobtO89B+5ZC9nVNZjMAP+PTVPAshsJdcKKotFZKO8fAnraTZgjv RQzL3SG1DkJx3SmQntDegOUdxS+RCRUEHyQ4fP9ri+Bk6HbpDe8FXhIPgwVzxISZP5R1XaHIs9D3 tbtgwVdaXBY+Nt/tihTnc0syLuF6rqH5/oLh2CmJHu/oDo4yxZemXY/7Tf9huFIS0Cy31Mmcb5Iy Je6IhCGKEiYGlHJTlaFqgCG4NjxUlZsoqpSMRUx4ertuqp51beDzbVlybnTE79XmYGQXD5GDnk0p rTCTw/AqulWNX1i0q0HWEukeW09YaIkp0lxj3llnBlcm/yUIBdRsjUFZ1wH55AKLXqJsQNKco6DG mwUaVZVHcCVgXhtSQfjke+uCuhiM9XArFcbljsHkFjnYLElNUueRLQUWK2bZmuLYOwOsTkN51qIB 7/FZaPRnb80JuXFuyTd2QvEUTLcBJ/eUlpSsetVHOP1OxsmTYMXodG5T6hdOLsaKZs9rHp7WLAT+ J+RRIKrqLqer2CP49+02kRuwpRW38AuTR0Hq+tvU2WkmFBBHcBwNI7av+Klp2BYe/ao2jfYPwhQv t1calD6GpsHhkVbTx6XPMJ86GD+oVRVBhv5LzQlV1uTxeYvhCZXQzQKFze9JfENQzv8I1OqXaTwR QOsq0bzIK9oOEKk1xB3qqpMZmJzmVJ9+qeUvVkRcdpxTbSqgQPtwwztKDNtESQQgLeFE5kseJtxp uelFCeLKEzAhK2efpnou0Vky+mDH1n70qIGFpYUsyjH/1bDg9vk5t3wsvlNRltR8MqBGBcqNEEsI uLJmWHvckhhCK17gggPUtmZotqBB1CmJlglcTNedZgxmjadS3yZq9WhwoSUMWCMtiFAS0RmwrV9y SZ8F2IP4UUq96D6RSxyDAKMJCN6Ypqjdckq/sDOrMR5t46qt/wfIJA1rUc8h3q1KcsyMM+TY/pcd HZ1ccbk79VJ+Mro5V8SW9DQvDKGoCJSRh90ZpjxN9xYIH18P7sVAnaaglcr0UGl8n+zpPt/E+yr9 o/vHJkoQ5FozB7Dlm5lmpTUEEAt1AcqxloYXII2wX0rRlI/qtzQP68uNSHqV8YAReF0DKoAYXu4i d0BjRRHdR+5Gh75ZRTHv60GIQE/BQkehEqwo24+wdL5xA2UZSgHkUByU42L8odmc5BN6NRokURcq 6N46rj16bSVpXOKqa0CGapsWPKG/zHUYU3Wdu9SXc+RYHZNK8D7TnOnTDqLbvtIpZLSCdBfYxh9d V4eyf0f5ufP3KfoA+Uaq8LRNAJT73jvwmsVNkRiBC2tN2T3uHjaSYYpjXDRRKgN9G3/NLJHQ+Vju CqQdMgWl8Rso1WKlQ9UckntxAulk4bQiGWDF/cH1T0DPybeUG6cLWsgDsmjTAyYm/h1qwcO8T2uN og3ohbdqGtZ/HMGcv9MUv0d5sdxeqzK0OC4kjA39HRMJbBFcv0U4n7G3dP7FNsOASfg1YgCWEfHr 1Jql3tqYq/MKSYvZEi3IYHZWe9u47HLnfIgYR5pd9qLsx/Q94sFnjr2KegSfkcntRMrzSBtJcBdS YjjPqCs7lQmqIDFMkfkW3rKg8gEhW0iWkr51lb2Wbv2lwEN6dda2wadVEFmDqHncXQWLIm/JEz11 J2gqr0rHmqXZeXY5tzTb0YTSuSW/Obq6UcmEg84wy7JtjBnux51u03f8zJ/FxiYi0qIGoSfXrj9y MpCG5VSgzN8DEdJ+45YYlXWlPeQaQZRN189wYn70Pbor5hif6VXz91df+wo2wNfsLwzv/8no8LtO FvjdhEqGyu+F2sbBFVH8yk9YdDy4vaXAW3o/v+zEGGD/r4T87TxxRfLYIwjb6Uk9AuxR5KQPbWah EbxTau+Hsk9Wx72Zh+faj0UZ2Lbbj8A63IniW0snHwUwH/wxcg91SN+Rchhir436PyY9P/6xeqvl LmGKd/as71TvFhbBmBiokiiLNJVXykHlwGCvZVg2qT+9nu8WHiYVhN7u7QGI3EKIHOGan6ZcGJds 4f8gunGAjo5Ks7UNeKs2xZS7v0lh9+Kgt7a+0w0GIIpkCT7D9leWAkfeR7gXYi8+Pn6enuPNZ9UA Dl3KkCwpujxv0fVz10yeyDcPUN8sIW+bYdmAq+ppKEuo15X+rhM1GkFIIPjm/2qOH7xMBRAfQgUp CY/hxj+Dx60mraeXE9cX0McTgkEew95fZ2xhPH6q7Rqd6K1ZLXH2jtYu4E40k66JN2iW+Ocn5z+m RsSlfaEcXP0HEaVF/ndMMRN2FuTNmuZldMfqo6WDObgavOsyjvqRKPIZxewLTrYNLh1kjGAnGHDY 7aiDSZ2HLNA//tyPgmFJX2ECzPhcl239RMYBnpWQoDhjf07w+bzve+w/KrDTXfFei/N3M3pZjSSv qpKNN8JKiSPM1/luByEqkjMtLe2NVyC/Q9wTq5AgNvBHkSuzsT8FoheTFUa4wjcIfK6I+VtIklwt ZZKT3uKZOUEK9feQ+jI81a3T9/PaVT4PcNj37gnB7OENMB7gofGPNEwzGFkKImr+DB7ccOfIX1zX f3orLhWDZMB4n4NLZtfFz09T6sgdZCIWYwsff8x0yfU8tsQ4SeOMfd9liRd+JAsx7fqv1dfdaibF fNcVFemQR+x1DMLEHifpDAq8AxeUsuZnaD2Yk8aIjAignymPnnYpY9Zkl1rHwZbToH27YUqgjW9k cReyLiwv7gyWl0/16ZuRfFckyWi/YuA5J20JMc7wauKkneosHV58x7jMqLZ128E/e2951RUaiD7p SmhMmh4kS7qQ9oSrvoT0/vu9fM2JEWh9RBq+ugIzTFU6Tq8PuCihQ02nOOScAolDbgFGSjeuWQsV 2Yc05a3bNnILBgSprEv41SOk796OhzX0GTsdRzPlcPSTf5sTcfRhkevv9VrrplCeM1iTH0YTQ6Gu RP058Lf12doNRVhKBBvWpILPpthJs4G425Aatw21xgcqlPT+tvXZQCxZCF+GHKN3NuHVx0usIe/+ HzFtehBcWMZrYloY8iu5cT+KBRW1T157PsQqcVeRn1dRCK95sWlBKqscrs6KtmHD+GdYRL2XQkjE pl9qZISmzKObkh+lFLw7qt+BEAnqfW3okLGdQjrPMh0iGQXV26awI3tQ3duO7FGmM8o54Rqgl18y oU35Y5YoCJihGpIuVAEaO69KdYEIPe2JdthewnHuxGGOsJG9eFvxFlyLUfwa6fr12OQRAT8piuku gLyGl9nEZiNRFOjAOXJTKXMWieKFlFRUmO2rGKWeSLYWSXP6f6JGima036h9sHOs/Sv3+kfMFbA1 34KgSHJN+ptNw+u4Y0CcOH9rT5mRyZxXzAdB5KO53aFB/qDa9h4rf+QQ4pAfi2cH7xP+MWnIrDAp ZvY7DKCLkUUIwF6a3uQWBclh5ieJMHoZsmaJaN1H7Yih3TL73JdmojjEb0XO0czlprJOOP3aj85+ c9V6wZ5UpwI+uY4V9Rt2XlUrqVOJVxHXD6fK1Z/004WavlQVvxkNMtxEklsC8i7r7Zw6Rw0WBff/ d0mrDiPMp8kR1HW64r9eHeKm/GFtAGr0nMNOtlmYjenISyiME8tF+7aF6oNnJYVNL3mQNlkJWkrk 074055ePCH9UrU4q5UWR3BJxq/O5DsGJTExWYWzucSKPMuoIC2/eWymStqG0BvXEwvHmJHV4nanz OBFyvzbiLSEwXlCKCJ/DwD8UnJ89lk42oOTqdR5vVPLoyB0D+B4jP+OUbiP0DehaIwimZ39Mh3qi X/lS5C8U4qmlniF0jdmkX/HhNvKDbHGqUqU8QO6am95OClvJ6TmD/7di2HHtWqfnLVY/4MH13CcZ u0heFMkCT2srUQVWGHIDdvdTD0tBckhV2MxjKc3+Vvx/oe/YBkma7zhnVdm05lFB4JhhuDYtTL1N 3Y+kE1QBIrmcde3GbtXu6IG6WEUmIyNdZHj/bF9HRN/izJM1Q5ZL4V5xfaV8YjtpgAbRNnmRQbMy mMOSvu0UruOr9fZ3yS1f8GajD4mgNO+QD4xVCCxXAjHo3BiMAHkT1Z17HulgUL44sTHIFyHkZKxS HNyqvScyHmjC1W8EGgQziqr42p7wIbf3kt/eX0FXpZk3mEeP9Fd0JV1+2daNmiOCl1aRlfeRAOl+ 0UAQtJhqPw7Q9vAnZoxPA6VbJPKDRe4EgMQ7QUDGoocxzuEcC01F1tuYu+rh2MnsdtXleKjYBMJI BO+h4FnLKpOu2JqfU33ZXm5++0A4D0LMKuv1gNqVmEZINHBp6yWlZEH07lIL5LkQekJFXhsobTtf XXctSPEsrOeFpe1dFN/zhsijS2oSmlXbjyQA+zJfEAzOZ8GBrY52NpsohcT3YMhXHwuInjt/XyAv LoMkI0i/A0Ui3EfdODVRSss8KEjTUtC6W/XugxZC68iaQJ8lw6Pve1u6cGMZdKzRofI/0lpnn+jD hI9LBW27iuBsZP4t8qNu/HTXm2uxKZmwe4YPAfS4pCJLahD8DI8alJ3y0ZJBQMjVGlePSqoJ057u F1aL95SxOhSupHMigkwp/TEag4AOZBv72DuTH5UsVq77G24zoldTehppqDxPVmG2tli3K4ekrV10 Yi8AgIT1AS8JNXCa5mfNqTOFxyu6utmTAJqSeWpj2LhqKCl2cOV7xuz+6ShcvhZcuqpRZu1SNR+w 5b/xvTY5BzxksTxT2PRs0uwGF+RP+UMPYkmiBxpmW5eFDQZ5a95/6C1SJ4qMmtd+ktEK/Wqj/i2j DM3Cnw2zJVxpeBagKNFnQBna/eWxsSK6i77W/jUXIKRduq3ETnY8QDT/wZT1d15uAnPtjdJGJj6e lYNQ/GP0PkUwmdu716mIk8rpu+b6xXsxmcluTIYjM238dIH89KeZ1wICDwf5i2bF34QD1I0rr8zh Msg+e6p4kK/6aVYXYemSJQONUvDhLOU6bVCU6MYIhjnjCpOHFZO8aE51ytwaHX6mcNL3gXgtJ3a3 A71hRFqv63gRhDuUY2t5aVYw5Rl0bVtC5jboRGVXiRyKV92h34yGGg4X29/TsLHk6SqCDYiT6ghY r3xYNq6fZhGHVpt+n3qEn74HX3vu0ocYtihe+/hueEfYwMMatV9REk/nXY0P6ntbQmSwUmNSOW2o VduhpIeFnStZctg/rOH9CCP5wrQ3D4ugln94hcIYrb92UCts9i8eVmakvgsl8D87lWIzNPL1+ffa m9a5swCqQIcguEPIdS+/g0KvOjperGxari3v9ALJ2SvqxAVW7Vr3xtM8k4HYcb4SOEXTlgOto5+I VrqXSTnkWp9tmfVFfLLiG7DLoPwSWAP/vQE8ypoBHkEFYqfS3jYnFyEbCP0+BlOLYuRCpdlMfJn/ tiy7R7iAwON3SV/btFCLKsTGDCU3O/GmzCqjXIauCT4KII4ukqxWfL+2q9GTpsWxe3NXl+RVlI++ L7bCVV4PXroCLNimgSWV9NAmdIfWlXYP8mzSSFFnSTwBEBvR5B5xpkoaBUEVbWeelnX7LYGXOb0z 2xLMrEC3AjglloJqnnQZPteG76WewFgDhDBdhpaOZ+h3s6bFd1LdQz/oVvNME0or5uvfFVNClodj 0y3VKK5jdAiKtvr2tZELP7HRrP8mnZBAfTaPM4HP8Ny7gjw1fNCCrccyQ7Pkf38OhfB0ufVStB7Z lgVsR2ebC+4pEmeIUBYWk63vi1Irn4J00mI15XplQFW6923OhVL3UZ+di93vAwoQtVLjxDN211nb Tl6kYeTuRmHC+ANc6QNdzdEiZoIDTGOojanRuiAw1tbKJyggfb6v4kh3dVTLgJbjj78XdqH/eT92 pIKhPJQFcXd2o4tkcdj9iZE+auisgl/TGW/yxeFAWNtdJN0nwWDt2utU+wQE0PVqCEH/E8tYPRk6 2MD4rKDdR+rxFGwi3LzsdzR2NdQO+RIDlq88dWMK0n5y3NKe2pqIID5bKtS/SU+5lnk5piOZBuAy bbdeYpVTNKQ5GocPM75Kef5PFR0iZhubHEpMGgp5l9zFgGxmH6aN07pnYVYQXZ7AAgi+AZ7SPrZs TmXNddLO0qL8k6CtLukCn6evNB4kWtxaArFRHBGs6JDbhMuNqMkI/JFDcN9sK4LGY5M2dqUfFzl2 u4yZMamgdPx3jisKIx1VSXfY0zTbQ/S9KkZG3GDy/V4Q1Ifd3UlSxdlOokoIQ81LHu1js3gWxkXK XD8fGlsbV91GE6p/cMxV1Yqddme8+yT6qUSRWvA1eRzpZgSB77rbI41Zz5oyQbAuZh/BkL9BT6pA s07rVzGiufq23eUp6YoKMJQoA6Y/dzEH8qbn8t17al61z8Z3ek9hAW90InEo5SNNntmzxxJ1aZzK 76my5BGJhG5AOhqe12uz+IUpgIfO7ebL6u9mmv0uCLUdMr2yJVjIeiUX8KutLoWNogPiNS8lFaqN PkgNcJBarZV+vaE8mmLxMmnBPOI2Oh3LaTUmZ6vRkGJnMXNWGaeGiySVUKb1OHPcGjwwjTv95mPM KH9gqrmvumVR6YkHJEul176dZ4DZCh6CmM8vKGUZSQ7oxabeU8Sb/TmbSrCOyMe8XarPI+LgTAwF n2IX2uecXsZE7Ci1+Fdoa+1G8Xy2AAZjoiMPvK8e13NtId8K6SI8kQlf4O/TnFoESEGATiQ6ABOb Y/ucRiCqyV1L/M80shW691LQRcRCR2M7ejMdnf3AQObAqYwZtt+lNJB2fQSv8udCjIaSaOIgPQN2 EuQddPfTuMxjelWDtXxybFpC40Ekmpne2vs69mBvSGBmYiaOjI9Bq0LP5BRdTWbfq/zeLYnTcgFW C/Me446C21+QXf5Zx+N8U6b6pfdCcLsFA1uYZC6o/j99w/U1S+tCr543n+edm1nyH/ifPKdYEz6J JW/HlJ0k+93D5ZpJFEhGncqWEuT4xJ4mBMFqcdihcEquEYGHmb1BX9cla1IG6A/F1QKmBIMk7TDb 8asAC9uHsaiP7qbSlnmC1rX3X+iQxXq10UhYby/zNGEinpM5KRARCIMJc9SBJEqh38Av1EosOdPc bFlf3vVT+b9yd62v1+27L0AkOkNZzfPCze457jARjSL6OM57F1OWlEmBLc614TVeuDA6wYC/5DEs FpRU4+wJlQ47B3q4T2ySWcKBuLDtYtzRFhV1TsxNYNV8lbvNaToe+bVaTu6N1NVoiBWsdXeLXnwr CGp5zjw/oCfeAidKOt0x4XuOd2YjYxk8ZfVbaWZHsPLyTWQwfackOSWzCBC3iapPLSiYEhmIhVuF V8HYg0CacxNgpa1sA14nUj7u4V7PGRfH8dOWm8/qYn8xmoY940YItVF5ru33SDOhzQ7o5sedNtK2 ymwSYZj7rltWNNtAskk1Oaq/RFNEnZaml6SjHhxCzt3+I2ril8TX0AXBHs/fnJM3rov1PmS7atev kAG/omelYLoEAzDGvPfqIFRYQNV+A6MvbKYo634LMT5lZIEYdePNpLbHzNbnrE999eoV8GQVnew2 LWpWzyVpRoheGH43hxur/F4IPOWQxJoCu4aF/nIRSY7fmw4zOxpbYUyovIuo9Dhu2gADJgXidZ3R TlmGipv1mFCTzk5/+ODhuNyvm0E1ym3P8V59bTRJ8IQD0r1S2FZ2Dlz4O9BMraVJmL9EobRfpx1h 70pDujXv4yEkA9Yk4aGhdDWLJYdToxHjao69BZnGot/qIIM7k44kvsabQZQuo6fTmCaXvE0qyLaG J/yPkXxnid/eOBm7DpRRENTnvSOzNOPCzRxf9vXYtmfT019ZTi6zPFFC66m9P+25M2fG89AfuTqq IJpGiutm1zXwVo22DPfRjjoyTDjgf6oKxrstFx9B2S97Cg99btS3rZI4p26QfUp/CESAj+sphNkG iprJhUDEfet0T1laWb9FZvlwo4bpTdartdKORbRrv9ENwNCVneQTlT253XozKelyv9MwFXLN/j0K XUtu15jPe7NyZSkT6gVyLHuAOFo6iNmc6smYZB3uvj2+WvUe/QzBkO6+LftWaBLvbtOEo3sE5ogl oQxU/I1nnBbxZRa5+cJWWddXI8gyUTyf6PoyHK3rJJGiwFiqmd1MisgX/81mvdeS6OLTOERMNYho r1xu+VmL1c/qlvupMzv8s+zQyIm8elmlt+NZvzhAGOEm4Ev9oblv3rqRMBq54/P9Td11EHFuoGCD aXrtkjZDCLiOLaEmAbSG1nEwCbuqK/tGzyPUOxKK/zplP9a01HNM1h2GMxfhUMiWCo28RZY7/10+ NQHkFz9ZzPwcN9VxY7bBg+5MgUz763F6kBDLR3qegWf8/e/A0AxNR28p6YkHQ04nWOdcj0jvXMgN vNl8qgVdsUNN4y5FLQoW1B1DPKCUya8IyFJoEjaWcTE6Q994JuCRXaZHEzyrScQAdGhe8VclRVzr pspTwrqT9XD4ED/hsvJEEXh3T7UnRl6pGqhXZlTog8MRMf5XfFMosBL1+MCrVgbfzk+T6iLbcniB jHXLLphnsUmJdfI3oF7oKvrrXvQYE/242VQ2owrcinglhzbkCg09hb8hr4ykWNaar8x9jbkse2PF 7rYpvwC00OzB76/K4gLHH8B0g/FsFuLN/k+bRsfAby9dWA6w+t7qXtWdCbA2ml0t7E//XKN+u+Bu /SWfXtFhkXsL0631CINQyORPnrLuIPZHIljQRzGiPHl3RdcDbFfo6lxGiuIyfbxH6Ukcj2pNNfbB swexPNQidVw0i99HcGkGsPpNcClqoPpvd0z+zA8UlK4YusGzrhgrJ9Q7/LIUWkBDU5jLxVYVPpT6 RnPQbb0X6ix4C4lWzm/stkOMJlw3ho82NJLW+a1PBhuJy0EUsqC2N3ViXQn4LLZv9pGG+Iqk17N0 tL7qVIwVZt6aaEFLY2FL84q2lHsXZsQBQfdb7xgcAXI3+sN5rJWj9GgmURTjKbmLqeQBrhU2wkKX m5n3SeYQOQQXz1Pjz0DOuHDL/ryQxQYXdhtSnoxTQ8YyxFgNlejMPQSjkbbUNmG0ZmFpO5O7d0df PNzcG/nSE5ibUZso7BYLrfcAlSMKIEUa0dM4+Jr0bY4Jqu0E2aNRvdiLVgEi9lRKMjP731GYZ/aF +jLQpjd3ZyQHDiDG10YL9I1GNWMqI+rub1pA59JBWEw5L30rnDHllQFbNbOggZc2nsp+fZ1f9gU0 RlbTvQxDMehaVgpcZOQ2784drnARMpMnZpLQW1KEHzOremzFlm8CWAdMNkgYdtrIArUaVzBHBRz3 mhzYOEBsIUixRAtchd4j8vnlYylbqP50b7TTDsdV/ZpGqYT/bjykTsHJXemMgV51mbjm3OpSjlAO vpjUPj00OX6Bqd1jxQwHh7zI16JVmZSPqKG+JQIzrYd0EwCWeCBDQ2Om2iXApAQde/lSGvAYWoXV BMWoNC2Rqmgq/wQVkuHkYRBFDFwmiV8ZH6C31dM592IDIn+O75Wyi/j6qtzePZajsdzUU+fNnVsQ JNQGrOCjNtX/Ex8HR/+8glYdtQY2muqxs+hZV4ok2i0NzUV7ZkPXx6e50VEe1YjVhSdjiJD0gWf2 8cbhfAA6EeL4QnkyFIkEbBeCgbRhlS3sJ7iITyBA8dK3s165Gyz5TT0LSdIgveBxCP+Bs98CNDIO Jo8eBdC2Z3TMPLnolSECr3oVXDlcB1PQ+B+e450bptKdfRDpvhLlRwhotxvCmdveP0ygPPp9Q2AF cdiU3C/L843VonlnFQ5f66Ie3sMAmmTHFgqnCdreSR6risID3BFKTOYPtmitLWqMDlw7WDPWcxOk VbR5PNPo//6IQOE+aehdwSETEDDQN1PDHXg29nXMDmDhQ+719U5AEOO/+RWSlE+nGE+lYw0gfW7h VunR21QDLO9J9A931L6TK8fZFLah+d58FZwT0FHbeXhN69pR8zg9py+AhLz53Xo/YfliJUU21ZQp SXB4ck/UvKzI4e5JA8ShdrpQ3GbtdW2mEZ0acacrHHhdP5wUjz3AhzLdsKpvBvKlIQTg1xgfBggW Z+J/Ne9ILDrnvuwYXIDIHrF3w1otfpFLrkHQ1nxBleZkpS80cK+XPxBfEYRP7UE++i0OiBL289Qa RBdduSwr2PbNSU5muiBj/g4vdBP6ItP92qHX2OlnBEaio8UnFyr+sCfNooCHS0WMr1sfoBCpQ51p XKNfJtZTnZdcLEqr0STYNAqOA1nVPIDhc/Yfkc0HyN6G5ahjDqg8D+89QmTv7jF0KUYztqJ+FSZU dilCPAm4ezq1r5Ar9LwMeyD55keS6A0ZToRFjgeEjGOzb4iHO9d8KfUphWFvRSjLYf4S8ksQ/YCH IDh/ZpzTGJGl/Nws2vbpQsT0Fs1YbjZ7cphed4pf4A/gcI3voUdYaG6+qCB4ODHuDc/Wby6WKiqi DjG2N59Ct5caH9h//d7ygowibBxbMFCqB4KCsiRR4+sC6eYtSprKhd0RclunDeo8o8H27Qjkk8yI nKLDJfyUSVQyeGlgy+LcMdZ3yNil8srIe6z5/LOJaN4PD1L3aqsbluVoNCCViJC+u3Zd4YAhrOvI mLJiWcaySA93YTDQct2/lVgrxskIx4k2Z1ByBaxRINEhqMBfxJml0Jv07xh9YvW8MxsCaS5nqAI+ hYUDG5Nj88w0emH5PQEcGoL9OwS38rtLmvp7dLX8+hYz7KGKznMjjxLrklDYN0vXWZsmDlRIQY2g yyNWJ6q5o/6xOVZ8bqOLQWhHSmzh7npqyjIzV0xgLCAp5X9guOdAnuzO3OW6qUGyYL+EEEGyBG2l kMAH6TRfZ6HUQlkr/RUo2JJXDcwgpWE8lmdMVVPs5W7egbw8zs5qMT3ADGiSmKLToDa3bOb+KE/+ f8Y8r8Cfp/22BSbs4SgsYPdfsXfo48BeEl4hKeufF1tc7Xjbc9kO8E3N2IvytkutiIpNcAS58mCB q8+RibS6QeWPdcHRT8LSV/b3JvPtaE5WsrKjbbtV5DWLNxB3LtowgckVf50lvsGApuJ2M9mVKZ5N KQ4HIaYHudAvFq1NbkWWRXLP0Vv0BHE6/to5zWPMDUPVncQWuMabbOoJ41HW1Sxdh1NHqNZP2kg7 w2/SQOLyvwfXF1OCRVLzVKTojb2poPXhEc32CzBHfMlV8qsDLAFH85nuKrJWs53UHPUt3oLyhnPz Vymhqb3pnKRqn4xFtcgx9gJlqw8g3deRGBKG5OVSA2E2kgB1ObN2yxALOMJz5tOQP0W4IyzAI0Fk IdGp59VSux+2d1xzf1vJ78J8reUv1pzwtQdn1GdNMS8M9JbWa+BpaYRe2U6rBpG64uLW0/0QjHza NzRz9ypVzNC0bsUwKgWM+1mch+XKvRsmtyJUaBTqcyydpGe5s9mg0fsgGkGYBcwDhPVqVBabcabU moLfOmzpXNf6w+TlD05datyKsSmlOtpak8iafIsIhOQxKFGIGENnylOLTAyv4jZtZbD0IbZeFfHB bpniy0QGHwmibkV+DqwR8tlIci0oRIIxXx9ph46g6yQp7eIZt1JbfW8uP2La6D/xqIXpfSexCB9L 9IYAv4x2oHLx9PdpcVXm0KW9j+x36CxR6Pnc09HZouKyyA/YFehp99A7ZocoeXg8/mFS5d8HJb0S 9kncyH8vD1Em6rUQ5Em+/JUc3uuIqGnpTNP4V8nkgNBO5glFSQNB2c0ImxnxVd9OjqhJWteuvXrO mcABhyGgcB/DI+eYQ42Ayu9CgDTS8rEfelDRRySDPmJYDSM1aUULk+IzVbCX76X9NCkmp+rGV0bB oAwpKcQg/kUwx/SZg22MuWwCJKalBe2Nwnll97/j5LjF6kjhHvC9oD++dUGoGqdafpjHd4/Xq+sq /lJ7ubnHa04Ao1iHgijYWsaNdi9cPTg2kGoeCkKk+idggrQd+PdCpIhQrvf8FjeLQ0yT3+F2vzoe kUocv0JskjCEFJuPtodRDj8hxtCja13BH1VzW3SBZLL3qjxgg1nJHks7ELFu50DPWcfnWE0SPiIF HLgeorbSu3OGzStasO4pvpnBVFfCoKdbQ2LSMhYkjxuLf4NoG+BWDNDAVIt2Sjm+3j8Ar+XEWhrM Znik5Ep/YpfkvFiNIpaelHwCwGT2PsnhH2USAOB2ltICRd1yscsSACVHZ0oCkQ9uFl87PD/pRNvi 9ILAv6Bxu5JlYoxkJmnZVj3/RvS98GjR4943EWDB/Ifb3/prnJruTEtJ/JnmjVQQnnG5/X1sksKP BlDjeTJsz90//BakvXviD7sUlhIIXcFQPFQ5SbCshd/iaj79c20pa32IegoyTT26e/36lez2JfNY pbc7ptoAz+PHwXMbcezU/T7F/+czUL+dcINDdcjRIVy4/OPiCtLS8396X3rzBb6S1cCl4U7E4AIT 3Ok02jjfNQzccjv7yn+hqnSIaxLT4NPqcuSYyAtEK3E7qo0GNzbAeb+2o4KJzXlDjOfhIieZ51y2 kn7nE8GzHGbyz/3bGE+M1toKPRAqS3iasWJ6USZ8cLQ1TFoCkNuL5Y5eZyyy2T7SgOcj0fH3PDmv MEYluagBQnNHZ9KKQhRpsyaTgFFM+kfBd3q+jLlQVgGvPztIAKFpClB6CeZnYUOSIWGsfTSOG5g7 8EQyzfxVOURcYY3MNGUFVt0opIu05+dmKgN947qMWorT4aNajkiQsuIqCNBLAOCn4oaD1ze7dYvo vYNAOXu2zgBB8bDdtq75iSzigoUgQu+BULWiCCNU7DbO0aVmPG1F9+G0fuodV+Tfxj9WJFTGrG81 AlvZ+75CFqquNiyge/ROF9ZYjWqdmbAh4bR9eJ0FRoYrmJHGb2XgyPiCfRIPjuoCKlGtssujmHO1 dEQ29YcBb9stxzJUnofaNmUiC9n66eo4f3IzsLtzXVXXtODBvHoPZO6dWh1gqHuXsF6RTF+o+Lzv yX3kGZGZl4qhTxuvzaOoKKY7zebzn1MQ4xjRw45r4+8YY8JVO8FdCZcNeqtjofUqAa+LbakpkE4n D+3MRyO93SGf4vaZXSMZD9Dwzy6AqlninnONT8Hx5TAsQAQJMGugYyfdN3xdbhdEc9K64F53lIGG 1nVGgrEtwRCStzSJke+45ggM16RtvGAaLykZSDiEJ62RqCr/PrpKo447va/8GUPcmPIYwxUBJ6G9 lD4hY47CDGfTmd/YGEgGFaW3JgVYFGu2msVStpuI+ZEc518VDhNdipJ0/Pt4zsRWlun0SU62aC4L isrm0Ca5CohRED4j9Hukaw2CDVdb48dT3kk97Nq80oynytxkF4z3Mrz1yPmamngPSIwlmWCgERL3 0JDUKBZFyi/XJgiLpXin2elJrjfTE0pwhg44+DFmv9Jo5k8zjt8Sgl0yennwNfxpBDYskJ0bVrnP ijUzwJs4XfilSZ9sV7iSkCJTYeZsE/n0JFmbMf0RPT9l1IDpReIww1IZ3d2ZwpPs0bcDChxivwzG 2lLziJLADWwSZxdZF4NPJG/KYFlQ7xL5QqhbHuOwCuDLUA3UaDWY3n0QRI3+88ibSyNgybLxCIhF u+skw0fXF2xNurrYne7H8DM1OGVm9DlikSHEwL90cwId8o7UPVUf3vyf0zWuAxCl5nUM8d9W8OKd cIQAJD0JHbfwueLX3WXmRpW/tjR2WCQeBkhUOHO1ECyK/hsVbDgpfR/DOo2E3upAPm/iCVqflYqL Y3YS9DG13EjtYEF9kX1Im7X3eyKfWQJXWlcexkGGEAK/KWGU2fKSZVT7QRIcROMhVSqNxCwZ3SCA JyvUQmGJrAphq92MdJMZFerkhrcNYuXAIjdhVXEAUvCrqgk+p8O4fErURTUuFoxyU+Qi2Qb+ihRC QFWKs/5FXkKi2+VjxnSJOIAXqxBe9BjeuDM1DmXvvVIQuJ33sr4qI9PP9xW9Zz2agEu/2A1yjw1Z wvuBct2Z+DzNrl3V4+9YpMTPBAivRaVKg/1UmEcb/2BLbGTIVAgXawQjx0QVUL8F9t0LB9RlLeo/ dA24vsYcAFn0sw9RJLvRYLJ1X0ezG5WxCu6GkDWBptWO9ntkqVzgBz12Gyirvlm+qAPH8woEyZQY 8L80Gzmk9Ln+oyMJe26TDxf2H2J8daialrYqGv+jE1oEnGZ9S4SW8uPrwSuGWuoM5mHZcYa+C1Xr H5TTfdmcb2JbGLWjRyRIa3lU5/qh9T3OgkouHdqt11bYyF+Si3mmKS4xeeGU1ZuKFtxHpyj+1l70 sJDLvWvMEKpByu/rnd8mgHgrVKr0a5n2d92qrIY/EfHxVLSkBMk/R76X+T/2fQGV+TeMa2T76jA1 VhjZVp49+jyoa5IPW26Oo1bS65u3YnsK4dx99gLWXzM5l/9JQ5ADjgW8xLZy2xCdidc/Qp3KQ+F9 sk18vCnSZWJsGohLLn057od8RxFDWY5KLeSvwZKuKX69fSahLywKs8cb886szTkk8KzIyfL52vw6 ICZTyJrthVNCRaddddSGRIvKgE0KUkYH4IRJ3FW6v7dewqg97Dqndsj2sayuHHavdRpVkVpENMMi NnZ1qB9Vnkyv4Ym8rl7WW2L4bRsdwJK53LajD8oxAShh0aqhs8zowGHxbphPpfpCZR99QIySRw3Z GgoY0DbCit9JFKVnAf1dMC/W/FqtDiIcFwF+SiA9yoELU+f3UzZLu/znOqAaF9C4WA36+3wB+BDY TNCXZLTCKDkdIsyYz5Bljxmd2Li+GskaLBxRdVvcfJ0lSzmK/6c8Z9PG47Yxt5jq0ZP4oI76JUog oN+vQwx34ohMsVXLCytp8DLKEJxBo3QgLuScrH3JaThyEO8TrClvkC8Sy4g3NwScirRqi3cz3snm UnQIV7l8WzlGNZVgdj+Tz+jh6Pbr35YIMwPfz5pMQkvQeUYfhgiZgyrEQL96Jh8N0uaTxE0uHJ1W 7nATDWB6tSOYHBBHa2/rOt/H4qb+9z8oPvH+UYwqyaJY9P+4TcICq65dTFyHYGDzZBr+8g9roVZA u3MQpgFCeJgCh38upvs6d3P+IajGu7CjQKRLOc08MpiinQNaO+sTUjEHC5Q/1P0IZQk71Zk51e/9 Y1sq9UzGeRP/qPc1pKvjKOVLpgh/z2WyRObWQvd5PjDENwrwMCGHNmYAS7tqMFTNFNiH3ugTX3X7 FsHC00kk3OHuLIPDjeVEt46qeqCeXidZGBsu3t/lUpyYGEQwLddoEc1qENvhsmud/w3DqFkZGRcG hgD3EKrle/LcXekWKAC1q8c1eTNoNE+i0ctA1nkdiQiMbbRGysosXWGm/ivUMJl3Z/9UoVwxPx3l 8dBRIdFmWtmoRW8f9UkzgBe9nNpv2i9BxeTOEcr09Fcar+gzKoi/k3fRqAng7jfM6tRqPvDK5Sjl o3fNoEc5x+WVbZ759wQsOknu6wdUWXSuDO83/r/LZJqTFwSVWioMO8AbwAPY/Vmw1Vr8DzksXM+e gvxJj7ZuFDtD2olXd5ngdTAc4wI3EqUXL4AdM1C94dAoUa4dQETJcsYH6jJP1dw44R9zfeVXilVW GKfQdr6VSiWkr4P2bUbSUtLzAsRUS8j1HVmlVAPxdqusrn6wMWi20b2RFX0PxG+IbkwWnmpBur8K 7Hp5R5v10PksZ4+lu1+U3xLG3rar7EXdKBz7F/SVhzT0cjGPIID127p6nPALDxyAABF0XvKJ20ZS WVdQMVp/G1IU66saQgQSvAoV4SoDa3hLbw9+ehR6ORnu0VmHvG4Nw01NcRVZQijZQBIyiwE3CUS/ 9ozkhIdydEGswlcZcMBLMpHpCHaoJalloS+3Mm3p+f2dxv8TJQRtkmPQll8S5BQzGV6wKaGyr6oe uskzmnK95drEMZxAozTj92JFjFAMNoD1I0WAC0AkPXRZs27X617+B4IOhVbwEO59vcbEDcAptSLi bl+Es2QzNSHy81/bTxaUPXBq0d4noDsDHBa40+Wl5k4QD/zcMGYaPcwghyi8wfaOr0cpIz4ILXts pdS6P6eApyOvE8xTI/xLMC63agBD8W3tGNmv07VfpvRppVKn226SsvA1zVv8mvmWx3mr+THoe2d2 OkQ8IWkSpTy7Sph61iZeqCRmb5D0U18lxY7CJZltymcrGvDWdzmnAb8/9w4j9ftPa+TUElgbn8o9 23pEqM0fA/Y4yYuDM9W30rfTK0qr8keG8sa729W0GAj0glfY1g27iAibKvtCPITSbQlbbLOjLX06 NjlYwnkQ3sKfYo9l67STciCQp0YmNMo7fYfdx15VlBYGd90KjJt24JtZj1jIt5ukJyXIfd5yXBUo ZPwQoJZmwkvHWUnT6IvKHs3bO18q9W8ZST5lh0zfhAqikhcgpIj3UDeY8r5GcGaSp4UNbyHEZPAn AHU3Lk6KcE0Iu0f0XvDgER3wsG92L8SWOPAebmdq1ODhCVbkGWnXXRerTuTenRpp6YnvlbRrf8Kf 8cFxOINE1Zsd+2vz89a3JQsMmLNSxc1OZ6N2bHxuz8afSOOQeiaYc5+xM1LNHKoigHjIsKzssR0B qlMLUe/LDqL4CzyH2A9KaEEcTqIoxJwKNsn8Ncv7WpII2uKNN+5khW9sJcJ9ARfVUfdcfhpSpAul 6fohTK+OHquv3LUUXnUFw52mqA7fPescdeOdNK5S6iNxbHHMDQ5R6WolXcbnNs9c5j1gvutnY6Fm bqyZW0hYTRQJ/ghimtL1CuP016PBuMaOI33b1uS08J+Y5glESavczQ0qla6jRoqIaOMR67BbskaQ M5dmbaGOmXeJPGNOlPICYjhIq8gfeNzFdMy6y5py0wK6ILg0v9tGs8iMwhtOdc1288YK2Z13QwpI BG0+rQj+1HXZ3OeYYcMAZnC5pFQH9mkcH1BkCF9EhP/1gUrGZP5XH1feN9aQXsiPYljBAM7bHfW8 hgPokoMYTYbZm9CfGboNWjVEYxVG8qeDbSja6DaMhgTM83fX7AnvDZAAaT/EeBNasy+CdhGngoM2 e7wXS9AaMRh7RPMPENFjXRqZ1g562ud6PQloLkQlAVbipTs6NSQsMluPF1YNj3U3LUzck7AhydPL lOMXZpxOT6T40QK9z2cUCraecQkWnN5HB37Hb1MgxgRcq0AFMudtS+Z0XvaLppNgqGVfryglzjwu Y9FkI2fCyN+CrHKfS7g3TQvv7JyU+x3JUXWBERdMSytxzMzDN4Qvxd5tMZy9eZ8n+EBuKK/f7iV6 0dapToGJI82Z+GwjaTg+Pfh6FNl0/skM9AJAyzWj41jbNP6Z6xR7UMbLNQPRjYfIdpp8jXXqpkFz 6pDbmLlEImHwoQvzxUMRtsz67wISYYKa6AqOLh9GRvRXiy0oQm42UkC8ni/CuD3NyvBdi2opaCNO 0hKJM7Lukbl0+AO6wo+TCITBNj5Jy7Il3AbuCckyv4zkfZGxi12h+egYQCJSpXJuAAcqtWYKUqRE Tv5Z4oERxQgtSIN0Dw6XSDtLdh9zuvax/gw5LtU12y/tx5xLJd4WTxnZaXJAiIWEryqHNwychgt6 e1ZPuyeyOxa5WybyjW/1eCQTSkvblfmtEPXFvS4symryhm9sIfm3k1MayeXLDaPoX13fT2fE3oLv 8NC2TFKeBwyhypOIHMDeRCn7+9Mu0vqeBdMGN7qOY1DxC1BwTzgDDmgoz8k7tkSsFc7JSgd+WRYN 31Hn0JynhnHbLTzuN51ouzdXsrP5ALpm4hUQ73kCDNHV82ZJMPFdmpxfblQhGgbl83LSF3ZyCExP j1pHo5gxCH7UMM0g+PQDsXfmOQ9AV4eJX4+XltyMmJql2+EOnKIyQQSRwlGlw8zC3EQ4gBAgCRDX 2rIS5VxLcduxMdixTWHuy+v5hvT6gZ6m6fVga/YEnW0WBQqRseRyaW7poU3MW8KtnSYEMvlhy1Ta UXoqfRKJ0jP9fDqe7eZlLvkPJbUI1X1v4m7TKS6JdEkDqDpL6eJLCoI2Al9cQQKIGyW2Ve1OeRW9 xatyoFdH6VkDGTpPbclVRDPnuI5rJmMxdiP+vCu4EpWRDTobZt8yYg7B8yFXP2CsTYGnfwc7KLo+ 0mbKLqcHc83L8SRmyj+cqSzR5/7WXxvlBsM53bln7QET25IvcEgVw8p44cxXNIoW836xSXmJoT4S Pt0HL4tAV7nn3BBwa+TbpxmZcOF18GR6BjGcFvt39c8DcnETSOoVAJKwJKHJhyiR0YaxE2FM49M0 9nndRjQ/7weIBEDoIWU/L6yf5ZfFYpgrSmNVwjg2mJ7czsZum+gD9+4np3dPQSReQCvozVxIZWGx Nzt7vV7Dhmr9wLu+mSacFUKDU5DOcXhs9GwADej1OwPYxa/bkERx/paorPQbOIL3tMvSZhGKB3Sx Gom3Btm9i+DM9cj1Sp2iqU7iShNFw37rQo3OxB8cooZhCXKhBqpytS2AfLqfvedB3WnjyWXjvWK2 +63gwFJZrkeoB6CHMaQST9IvpnXLZLV2XgADo5jS7fA5U9mdbvSVFNkgUNDvV8xkb3asTe8+0DI9 ZsgUFFzdtCGCQHrwI0fN4T3A3vkGeAujCKFAot1gEtlte7wGnSuF5KdwglmqIDgvzmXNBRIiDIMA 7hGZoE70OWeEuRewcEXBkZq+V55xm3mSNw+PUUROk5/J+Nl7bBQ7djRVFOw/cpVsmCP1UKFoPFUc t/fNGrNI2kT3mK7XQ1Vd7HIJLrSWNcE+6kBWWosUIjU6X6jcPCEUyP/BC9/RLht992J7AmdUrknv 3dpDR6gGhraUFqKalji0/SJ83jh0aIge1nBLpZNU6GqCIR5UUhSeJNQrYpVdl2TSNutWo5ILPjyx B7d9ywuJoUJJh1QsYLSVzDIl9kzLsDKqvmPNUbHrPWp7gFiph47ZsNUGMerbcLycEPIXsBZsM9gL NDRcjDitSOTu35Y1/qhrX5EFLsyfSNkUj69YTXxrJRFfMNSx/UPmtHNtNQ3O44aGX0Tp7Ev9ju1q meL0wbkTIlNmePxjHwVkxCUjYCmE1IuoXnaxZYkU3nAB4qDHSeCvEbynixGlpnu3JAx0shVVrR1Q dcAFh+RdRmtDk4998oVbsFwIxFmaBWi5ZEoejCV/Z4LPgd58QIlRHszOw8p96hCpxeWvielt7Qig NNavT1EakiSlV+qhy+wQncc3FIDU198nH7crfnPLVczTqdpUkCW72TTJkGQzPG9TlbPn+FgyJQF4 wc+SZHfclGe1GMU3BH3t2VvZrnBzTTBXT4Aqlnha+tjFkxRZoAJy13LALqT3wB+auNVvlBS/rSgv /hklhRHBzpD7eaC9QfaDOpEbAIKFQKWPKW/S3kFoaMxCMh+s4M/pylYt9Z1rtynq2jCWlHSQm/Ir 8C0sRlVXmK+tfAwDBPXf8oNfo30rABl3Olk6Oxc/LOHa8ZOM023kGpRhF4s2J77jgjQ1socmPQKZ Dm/G3Y4iP2FFWKNgTSYVFnjuV83uEMI/nPE0DGNXsiRT7vCuRS9qVJTIZ0/TAg7OgtKObYPdTwSf qaKDot2X0Ghh3vayd1XaS2T2LdWMXM4c0WYaKk1Op+VhfbBLvtFQA9ad3Rt/RjVvZKdbehzKmiqb fWtf0TmWPBGCxarruDhIWPcPJt7cbbNTr/lxQpnq2e2rcDpX0EGeY5ONAyv9kK+6aIytOFIAakjK 3DKRCSuXxPVPBni5mVSe33rG6ms9qA2XklStH5ps339/eDi0Z7jmB1jJgfnHvWsDcM/OAWW/ftYV g/uC14cInGfM/oJjDvJ67EERQyMeOF4Xpu0MAzoyPDi6lLomIhatkpvZgbq8UyKfX3nKttNLTg4g UBwqazP7jAu3PWmZBvOJos7kB/Y9WdqNEmmHN344pNZhiqI++HRrputSncN7EiexBu0RldzGzfoN tXjG0IAIsNV3oukyZY0yTIcQ+v1j5myr0jiiPM/358OG+ddYb0zHgwJSgC8FpkchUm3gilUBzTMR RiBaST9zKnRr2DYYD/1Jro/I5s/P+H8eZgfgbXMiuKPQlN9migx+megGcwJJgp9P4voTqVsW7pmB JA4uP63bzZbjuBjyHF5bM0h59oftAA/lqfqJG7O1Et6C2vpFR1iP7TOIug+in1SRVHlKfSqU0ewv 8JbJYKTd5mrPpv/yfytrPgbNuI32SJJCrnmq5krD0jVIwE16lTQKmOSQ9UxVQfmvCsSTBknRIlWc REksO8LKQ9MCbzFEU5WkYuT0lCMf0EHB+DR5nPBezRdujO+e+k3WGpRHib5SmwQDcdXZ/8mERb/8 RgFx6mGxwGPFZcfRvhEgOqumz1QR4U6c8I0AOQHnP6CqUMw69y5hNWZrHvcAs1qC38okitT+xicw 8fYOgkA7oK82ZVXRkkfgj3Iwh0BS1UR919mpfa7/G1nTsVMf+LKg37v90VBHBqwCuYBwnVGqgDiU GkSPdX4jt/xtC0MSUkdG5icP7Pe1q4wI77qEgLOUqFL2uUg+jZmbLYE+rzcRFxSqOaTS2tzmOFz+ +qNI1zwanohbQx3LzbdmYENhPINMECheOs3bD5bKqKkzpGlTYGifxDWFdJAlfuBIU9kRVQTbUf2c kiKV4DuKQMvBMNGoYJgZYtDw0x15vYmANr9zUZg/HiZFW0nji7ACO9zp9Z9m7rDgo5PeCeukNytF xmUCq7ejLkU7tpfx5yQIwtn0XsOs7JBKFY80a7x2b1qR0C9KgjCqsxPNwrdQjN2zuyCR4YU9ZYnM 7/s6alKNo7NCXNaGxX7gwzN+ghDHssL1AibhzvLGo6N1plzJa/dDsmHOFr82gGhtd1p8VF0ZUeo4 Pc330ipdnU902c0Ks3hb1ZnsEelWPtxfIm96hgzXRVgy+VDXQU5tH/PDGy+M5/oyEKuqB5r2Vu5l c0wcbDLqBzgwKuMSUfnh/oEioGRppMW2lpi0rUKLhTlnHQbY4nYbrbL2D1ulCQZ5jWpquJi1s6uA nv4rSwZzk0uSYDKYKE1P/jbnmCB22GpA3oHm2DqZoNZkQzJetiFtaovI0pd7n3zzTAdQGXL+8Ca+ 3Goihkxw3oevp9x6/XYDzua7bXpQIoSKB2okWpPeK7ol2NE8TOvZsnuHpHFUFMkyu2uet0/Q8oUf dH2b2bhcZ08sF37ocObpbwvNNzEt2N0FvZ1RnPNzDqKcudvUXDBaYQJInpcfy0naWW1THpBu2ln7 04X48hYq0N0q9PrKETTwQxiDmII3NvkEOBwJuRSNceQdWrAVpSDn6iaW7ABFF1MiKyPKJMjmOpyF 3uDxnQijJyBYgANiylCjnuC1nxaBCQtFjgSXoxFLzpiJBxXE4V2crgvGifJHGfbSS8Tl0NS2xIt6 +1cTrEC6AxO7WPuqde6OQd6CZ6B1mxZTUV2QAUcdjWYGSO+P2PoxeMhWgtvdaAAPraKJkZrX//vc J+ZCuS99D8f6qGqVGYmwydbVAhJT5REoFtc2V2ijMVT1tsndrsOW5oOWD5LP4irRItEsCnez+EvN lSdzQF4b05G7+9eGfHmPkipia2QGJfx8lkU0XQwcW/4COyNczRSrjY0HjGkwzSP7UILSWT4sGLnG ZEkndxLsteoIMsAwVll+mikuBg1rT8UggYpfFLd465/kdduaisrZcw9fiLeE3hF3e1bAeFAfaNLz oJ0vVyAR70IfhCBrEt14ywuLNGBSQ/5bhbxwl4mJOORtVGIrMl1N7qZInGSGC2R/x/wZlqRtld2E O9an1rDdZ/8xUsZg69BIZ5/3a41qqHozkszPhms0jkPNnBWb9rj/5orPsCPuo23vbXx5CqQQP2V/ 6fehv8rEI0DwiuphohqqUqhtGsB8O36wKlELUWVjo/D7aZwyf3lgqiJwiUTfMJdTvQjK5CvbwVkW v//x/B/Res0cmb5DC89p9W4JKbOp6y4EJ16nQSu9RwGkFr8ZeiZ8j/Xk7+aAol1iQdRc2tNEVSPM XBGonggINd605jw+eaSOxHMBPQY1nLoXB4bmFOcpVIuwzkw6F3iTwyyyHtNDcK4Jgt2bqKOk04Jm kY1HcF6DO7Sl+K1LMypONoS92pZDoi0dsgjuO2/RaLr5kSNP2RRuR29asNDXkr/Y8RJL6CjJ0IXY jCcL5Cygp18ahXmmExyqJ66aVq7SZmzKCrOCz26DXMGDl838XC9/snj6HANSXO/uGcJgaLGGnhXM cn7zv5OWZ4KClmuvSEY4x4+z5BvbxvWhA6Ubnpo7lYoHh11ABttGpUXEQX5NeDGhZ9BdfrXBU/w9 9X9VnSIf/FlM5+9ilbZdfggkQ1ybm33K8FG3IhShUDvDTDQsEblnleY1UrvuMu2awo5tbjeHmBJw JfbiD/BKLXafykD+wwjuNEHHlt9gIOlTYsvJTxRjS3RWX6/LkZia6cgJPbcwcYk4yfHLKDOpv9IF h8JLyX1cfdxm4YMTEnwKVh0+Ot6pVagsQg0K4iTnDobB3mzyRN+IN88DFKQoRqn+ccqgCsZObATU /QeUhPB+ZjQhXZgffVp3GIuxuBa8H5i0l9sJoTgsXxWQWgPu9FrTL4g3cHxN3S3ScRaXAYV3mxcT eKqm7CtPcZdggJldYTl9R98JWCWdnHxXkz9Pz1Y8ug/0QYM3Wcz4+naX2wDPz5I3Eaut0WoOzSHe pSjNaFzNOVNnY07l/65ZFcySuuMtNSr/2MeA6R6dFVfHBXAmBnkTzNBK5yKPdcTlr3uFbIx5g/Qf +CU9jhN1yC7NOECRfAMqeZTWqpNArKZJnicC+Oxc7nO18e5IIiQFBU+nL1Po/5oMJVmSaKA8/0qF ivS7pp3uX1+cO9/I4cf7dEa7qPSPyMhnh1oM15rt1rMkUeeXFd6INwk1axboCWO6osCKRQsFNSZE qYfWxQwyvU/LH5DZHI92WCLAPdiio7BGwp81JyTKA5i9kxLEAwdCH4jhKiFpSsMXHFY+WAby3EBx FrpkneZy2AU6oFU1zVeGjxm8AJPWsPlwfrLGkJ//fzBIWlMsD8/SG3qS4ApNAx5w1DXz5iJEphVo Kgr+EFqSzjPVx9sMSDlk6a2k+rEqR8Th96gDADDxmnsssHhPo2ggv0rDA/DYnQnsClzObvzcAGgy xoDJfxlHya1Y2oD7WzgXeDaAj7Cqy35golq6lIZuI4QPTU7IA31yV9ZS+ztnmBXhyo+aQTPE0IBl cahHVFj8w1Tfr/j+qYOrOdF53EMsS1yF4yoWvGmAphiyTUdwvFtCiXa7kSG/vqDeDiu24ScdGrds jtXPmhRHRKVSooUeHpo31BARpowjKpiRWKvE2jV68W0Szcv59PUMSisCxovScATjn90rvFnR0JcY VBLyY4bunyubwkCrKyaVBc4a9zwqo7vQ8KzzTVhAJhmIp0zV/VlkYQnkS/goTWOS8HBSMik2fsZl OcN/b5PbUz8mxradl6gjilLXIcr7Tm9EpfaWugriPpjct6L3fGV/ZjzU5V/kw4gZ1pEdAr2U/mwZ mTvruf/eNYketKLmMoQNiFQwtQ5OaU3AeZ85dWJ7CN5wVYuVz8zbmSrtacKHpiaKbVM1eINQ0Z8b rddJU9C/SedjNhPR6rs8Di1FcT1wQCVquETJ9sFf4HFYCYaFr9S/I1J7lWxa0nGNJlvexUT9LMKR fsUEajxJKYeSKfeMwlRjYew3mSZaakOnI1x6RxfNdyk8r0gMtB2sHY7haboH0xMEhhwibbyDe5Kx Tl7nwQqLYWdpw/HgNWvonqxr+An2M8jfFcag2M0M+QYH1iOrDnOJCTedSqUZDv9PHxw1zZA7QuZx jfdI562Xq+A5sA0nxLV+jDurAdie5IgP+/MEpbvYHZZIWi67X+02tH2qMhnmQ/kKGFixG/F6gbzW 8gulzcHdwjZV9Vwh6itskiXF4XCRX98Phi3wQkKSdUMbe7FrQ1jhTnsm43iU3ZVKynLHAf1DN0By TM+aMRSAS60nRYmDLqPga7A+tiNx2KttzyRErcGTMnjjp8a9pQwvCWRm/Gk5X4PQndm/TPSfGY+N aj7Yo6Na3gmDvjweioGisV5jTTWhZs4htJY8wjm4M+ls5vkcrHJxZu/9HxQnLuUysO3vy/ZUximx cxafPxDF9aT4vOIyHPfpoH3fHv6LiB0cXXG+8y2IR6N+ApKwA+/msEApzMnVlWyOihwUc0NCQzoE bZJSWXYyUB+lIDLCcN84mGKM82HmviIrjDFqtsTSoma5ZTAz6O9ZZ30DWeRSf6p38L/Xzv64PtWf nDEqXS8uq2CgxT7yukqxwiFAi95PcHlW4/UClIisjsoS37tQKd6eWgUMCJpD59ZlHt6jf2nWm6sP oKpKifdAbEiB6ejI+Cdsl858cxQvuz+yc37QwpH+ZvFFk5orMM5Fr/7hlkoRZX8nKqwBR4R74/AV 1+xA2knR3NXLcVGmC09IwpFzfAfByhGDunBg0QX5ck1s3sgEUn4EbrC+f9TdstxRpn5W0iGvnugT GKsE5w/IycJNl0stgftii8BayU7oyPbPEmquH1hKeOVJKN4t4CPWumaD3g7hs9nWiDI8kZx8gg8x eYozgPGdMiZOeUoKXKyfLvBs2Yzg1jCIW599MP8VXNbO1Ty1PoU9zX432NRChMpgs6T+iMUJLEKU OkyWXgfCE+7irPpXJwFo97z4UJltkxN0swJKXA8RtzwdEqbMigz3U3J/dF8boGb1DSglgnMXljDo YgmiBh5dpeBqOnnwRWrGBrxhwHpsrqHupaGC1GXa5fPkvFCzU4gM60pLqaYgfuD/TYalRv4Jgqkw gLG6PLJfnPVqFZ6Wq6JV4QNQjQr68CQnmzB9jGkH6A9bdHd52459N/fomsZd/W4uGpT3nOmedfPO IaGTdAgmYT166yCOLVkL8K3SDF8NL5OjUUnQa2ZjwNbcmIDcVzryfRMrFy9pXuHcuJAzO7up4LlX 8B3XKv4C4+ZfiUkzfBrah4/RFU3dWS+DskoBKuYV9cqHBJ64ZBnxLcFt/s3CD3qdx3K+TjioWLD/ OjB2ENTJK83gm3A4+MWtg7N1FpMK1UNeAHcc8+18lRuBeiala4JwR+rOIo3XmnsRlnje7dQ/eDcl dodGXn5hBp1SukJCCUj1Wj7BVjhJrIqBfHdS0XN1zLXW8AFrl3hwNDURk1ZLN2n3PY75jwIvH/bE HGCCQirb5egbjUI1eKNjIV20wS1Ve7LFLa3l/rG5nWIthlWyoIGbMUYyIWtu4F6Y7SMQRvn3kEdD GT1Y07ucbTuMk9Y1ZJDO0tdD9gemoJOcLI+tNwpzEILobaUnuhPs6QhQIrieIw9XS1YgFS4NUm2x omMi7KGgS1NunHbgRXJNIPhBrBaw7ek4LgfuWm0Q/q7GoVSTPbjfbbDgARXY4csX7GsWybNH+GWK 85nnT8uW7R5Tex1yqeOU6F46NuEk1EMj1DIJ1o//t/Lit0rPgSxFGVpO3Xkgfi8YA6/S30t+3TR0 AGJf+cw1laoBH9ZEfQT962LN+jf2frGQDNah7P1x3VC9vMwqWOgsygOY4OpLGRa9UxHik7NwuMQk ixBskfSmZAIGBa62lYPO0fMY6J3ZdiE2UxmxrtCaKQ5UnnsnpEZLkAqMXj8J1wFUOhu2PAgih2R3 GbpPCW/MB/DjTNleAvilO+iReM/9Wo/YJzqQyJ4jYdUy/EILBmSThgsSm18+ppDw53zSeWur7tGw zjLbY/CnFPnDFiIptCiDtlWZM0TSLCHW7d56ToJMcFxl8GnD7oyyx4YGTEXtbdqxm5ZwBKFzbwe3 NaRFHLyduQEHwPn6JZxb245IvFZV1JOhwbbAnGX/Jk+fSPzK0y3PpPP2poXekxUfhfcYGFDV1cpx 2F1rmn4zF57rcObvvupAmGfoMSNd/COcBWey1w3tulfsKeBxA54YOrE8HuKCsd7mmsdZADu/wlrR twJl7pGe7+XolE28X1Aj9RijcW2bImGrX8jo/DiJZBsyKfIgKoWG7t2JB1f8m6P/FkH6b5oS4uTM Ud3TBWNRbZspJEsRzbIoPLN2pb/uG4IqhNU61Gw9fYPYkCz9E8otd4pJ9gGmxPd0fDk/VHy7LBEB byZFXJxJ/Hk3+RB7/fYg+IVH+pf7JcBDOahytiTsGgcXb/eDU0mizRv/JL1pCLa59dYnLKwy3euF ukDssQZ45fQvnPSwB9G4kaXJzsLjy4SatwWkQ/p/m+VhWJWj3ygmw2GPQckNBOsVH9skodhTrThe AhybO3MrV4q9e3liy9pBw9lhdFmG+4atbnfSUNtXNJgCqTGoFBJHDkrJvpXhTVNC5ve8/p6P4kSj uvHQ3Fohe2vrNZLFuFKK80/4UZpPCpZPks+r9Cjna21Z71uPIoP7qI5uSmmOMjrLfmysXHxvu3zh x9FkdKaxtiWVH9nIQcLctUdhTIksHgn1UFGJSJ5dLBPLhhkSxVY82BTJG7bftWYCyZ8+leEqTwAf /d5EWHbhzvXMoPH5MH4SlNls+0/Ejv7Wzuro/GricAzUtaeCVpgUjjSD3sI9otBjpKH/+wNDVdBB i92XCGa4xz2Y6AaOGMMt3IZe2C5k31taczAbNnmNLVQ/eFvlaWb6yWu2S2VfwWSxriVshjJ+yReY DNYrvebWQX49Wrk38xEh+b992aBhP637y71mFsE5ighkmVDcZm9xyPLjjZdzdSsQXuGalskdqawD YoVG7fowAbHhkLFqEBmAP7PlhePzxjBVllZKgAhVa1Smc34jzbnA1KlyPIrJHbUwiW5XGjdldTWP lUvbmXE5TfKgVatRui3xWtRLSMAaOzqgCSsyVoOayF9mlCOrHsts8rBo5UMW2RK6cEke88ljrU3S bjWrvv5tPyA7ySw1i78Z8hCUj2PxwD/KxaltpfLxPsN2yudYkDaxbV/weFS3e10gco3Qrymul0Yz mJcapi0zuvs9GK9de0ZB/jUFg9SF3byCIvFpVGM9kRrzUHUcQ2I1yPbS9W/cOjWYs7JaWHIkpK/c 367uTF5dx7I6HSoDtiCv+w5QjYvlLiixVEQsH11CdusTOqEpjkXiyl94LFVHSCVRmbqgZswuV0oB Fy/q92GyxuQ8By8BpbQy6+Mecn23Br5/TWd99x2aV3Bo13pKfecoh3syo2ZOlSTfy7ig4S/VX62Y oESAfUZ68ox8seIj675oQp7ScIiyhRlxSPEZsRti3MdE8FXmNIZd8dn/KXi7SIauV1ScO7SjKN3W EHSFzWk5pq/CrQuz4mmFGMpMTD12WkOkUcrSfIyhhu8Plc7pqNjYz9dSmlHEvjjaO4t64D0OIEaJ ZVm3Lq16F/dAh/WCw1Cw/5GBfOE2rcVBbbjw31nFQlSWbChlWD9OoJQIckL9kDrZ3zEIe09y5481 roasbT5gvekvDBI67/0cSq17IlyhyCMTSfcIgmLMC+SEI8T/8dLT/XbL63daRar2Psfj7HVUXpwp PAT49jIKTe+4Euf/axUkBHFOm8ybm1vzzEd9OJEjC0DGJ7AO9LSKyKe4Lf4ZukFErHdiI5+QOqCr vIRsEk/dg92ZjT93b0aY+rceMthbgLG+t1x57bnXOfRaT9fSCeo2Tv0KzDOZlB8qqzyOce2JK3sM 9grgr2yseRNER3wowEemAH/Nv6coBT5PwEsmWHfN8Bnc/xxzXs85T+KuS5b/sWxhwqiONUutFTvO A1u5pCy9Xfqcc/EBRCCspy/MOq3VNauZKDTDGLuXlYh9HKormvYuCW+g1BZQ9zI6Xz1qMiipdKBI PCYSMzfrA0rPYyLpc5Nb4niLbZS5KMx6hJD+0TqHJG7A0uVTSvnmbcp58OnBcjPy1CPrk6cpgglJ feqW4wbmqRUlQuG1hKchky/tp7UAfOBEXCEJ8XlsKB4ORJz2z7iG/gRPz+NWiG6fWz5fvA6yykyQ MGTwuWaWdR00Jcz+eEe4vjN75h2JY1m286MH0I+Si6D2t036SMo67yKO9zh+hlgUo0s8vigLD1qN FMnsAtYldpbRCmugsqZIm12+z26PT3K6urx6pbR4Gwm1HPzOl9Tk15iyOy7RFxfkv6oOluc3nSu1 EqBDBl8sjc2Djfkadwgy2gjkZtW+ABeAaMgZEEdYH3Dfe9fZpDx9kbKpB6p03t0dn5RE8KRAKMEs W5iNzsLN0Ni3PaY5C0VTUcc6LKGNNlEirFqzwUSjBUzxdITpyapOyOQmWg5gP9Uyn1U8D9WqpHdo ED3RF7Ob9MOGpI9EcqKCcw9rTZp1+fkTLek9JC/CpSl7JyQZM+yaIEHXFGS8x6tWudq+CMezyII0 8RsyfWKBemiERV0h6l6HmoQLouH+jLp6rG8UJhlrHuGqnq4wD2+7yG9GghSImkrI+dazSD9eZytJ vioxSuOBQ8JFcXwwgiYSWf6IqJ1e7MINenXH+drEBaU6/aR37w8D4LnT3J2WCuMV7qk6Lgae2WZV f9bVam3teL7BOUdMD/bjauEMYTqpoyp5wjmk7NYiKzYZcwHEqhtIOsb04Yv5TWqxNu/oSGF2c294 JnFEtuR8ZkWULwwQVv+eEQMoPzgS2OQMLMkLunRg24qKbrJZQdcHZ5GegupVyZKxfwi1l4pG6tar 7E9CVoOAvoGrYqTCMdcYg85p8pdhrgcum5UaWdR3ACOgFnvWfnAcWrZJz+XpHl6o8+V3ZRWU79eQ HePNGEeTYt0Tmbx/+89fAFuVH+ZUj40BZiV727YAIJX+bjuar2mtXJp4wSJn4LPYVqDdBMtRM5tr 4mfkyB/0YLKVZQPfBSGZrtP6s5/vooYeiw3QZRC1I+wGawCocHbl9QD2txiSTOsEbAM0NMJxIyU1 zaAro3MOg+HOj07CsUs+0j5A6AAoWYfoq5sczbX1WtRWNGw/u3oO//kxJ4rZu3wSpulpd3Gdrq+x 7/z9knTAJjVKbyjWkzjNNlr74YrYwoqOJq7dvlvlIUVg75dTPoULtv4iwOdsx3CBeJAmjrh08eNu VxmPONqnQcryqgATxA0LHCVJbtMDmPSLMDw88UG1vvhIwNlckUePlogOkz5CToSZc46OuHiwp8PH XzXqp4zwCjrRAOpm+56hjCszERKcSJBg60sSBgoQxkyETxXKNDxGIY+P3rCoyzJXAL7P2OimJS4E GNfIyiWz482nQs9ssOTDP5mq6zAqlZ7vx7HuA6iBj0fS53NmwLJGbWwNdopeyv4dYL+sQMknJ4ed JOia/0cFvu1u2VuytU9npcvYRSKK9A5foymnd3XihH+4x667ZzHtTHTwS728ZPiRe7U5FGQibpfv p2wp3lZUtYo8Xiqfhq9hoXEA5SRn+1t6DFjLmHhwiYzkwEiZZH+90Jm3jyWo6b91uzEnKKq3jfnK tgWqGGGJFfo2rWWlqEWE1qHByJ2ppYbvrhdPYrI9d+X/0zTV0h0sj50MuorbtEyaOe3TzWB3o+xc vPP0QYfS11DaWD3gazvEQhPpVkxIVwC37sS2u+oWaEGrhAAVo3O6FZAO/fw6R8ezlyuuJeJoEvUC TgRnuPjMjZIEMr6rJqGNTj25MNj7heznfFNTTJwbpJGm/5Kgym21tkGiA+yFIh/IIJWJLKXVMCjJ IAd4x6wOEOfreEr51bXjlwmHndrD7f7AS6y+COAo8RusK7Y3vpbE6aFYHu1JkSiCmTmJgHXu9vEe WkJDonrZUMU6VAZ87Hsx24W8J8aeIGbCiMXNzPP6b059WQhhWhI3XdcfxuBphD2YbtOwsE52LrB/ actfMFzL3okT6zjUmXz+gpBJELrq8XD+rn6tYEJTX3lNQzzF2J37Uj7fz2+fVZAj8JDrx63zNAOc kZlfQBIDEkMxixR7zGimd543KhGR8o1nowG2AzSOA9KhKRBZBWI5TDYfeMSXV/P9HexmpUKtOrGO MhmnFPkLgt4xhQrMzF9340vMcdR2s4etUFvWSCVKUoRYLEmGApBwp5EKXbrHEC98AQZTuKAIOpaw LUUydqT0FPZtSwaNnihd7dmPnPvhGrveivRugfK2ypMb4DMgx/7Q5/g5SvlBGL4kjaNRrz9+JIHr 4OQdlVH7R37eCwIXxf/t7Pw/T65BoDIqjGho59Je3tojyyK92iiXTZNPtYgKCbwaL/mb1r18UEoV R5EjoPJkeqxqDLH0Um72e49ybW0xPKJ92UoLDlykYbZO8tXEfbE9oYlp2fa3Fe5kiwXWYUMC4lsG LtIHoyXTOOJF5TrCEc/xV/HdhyGyOp3pso9VO84uQOcXH3atEM9ttgJD0wctGIs8MAw4J/kOgCJq jBiJfM225PoM79cRFMPumQunTbewWnBj1o/HKR7y8f0E/BQG6UFMvVm77orygW5Whv9sUsC6asKk yLo0YGtrHtKgZeF/eHrRwF+iriptfJ1RnCjT7mehmWsYhriFe54bZz7xjz4J8xL40xSokTjf2bMd BI4OTT22GfDJSzeK9Q6kT3v6mIvgRM7PTBb9o6IVUIZJ/aqwmOeIrHKIU68GKP8UYhFawq9edbPX XGSpW+xPfOraY6gNC820HmHK6Iw2Y3gA3ELLkfFEso6WGwe6lQRBqQ1S9CaP+KzzvPq6MreBmQrb 38Q+gd5B33wgdsfyBSlUDoxl5ILHi4Au4Tme0QE2F71jmMUudGcGER9SpAWdpmSWNg7pkrjQTVYD zk7qQTI/cgiMnuy52KZ6YLnKuuQ0ZoSXZWkOhP4zoJoD+XYdwBA39EqucQACAH8ixgu9HA2OuXYZ 0tCoGkrAlxc8QUFk7RrBdOzq/d5lls1xN1XCFl3sTc/avkZL1ocnpSGrTcPL66SHEufh7SXPazYH PEoabaVmK84/ZW7y2Bh2WemHz2Ws41O7+Q04NezqtdE5OL2ObOlKeFibHV2gPaAPc60q+Uk2mg0r DFrnpLisTVnXsE/acT1lEvW6TfaO+xaokxzYT6ZHKNy+RbvjFGty7G8rOzZmbQAjZM6Tp9Cd2kJL CLQSvla9Bu17BxC9i0Vth5tKPYqkF5T5jjC8c7Um5DaQOW5S3R8fV4rjhw2ijwdulVfSL2Pb3YPp 88qI+RBQqODEqgt76qA5F/+ox/viG0t/vxRCfqM6EPR+6TiFeqc25M8x0WPCM9jw7kF2cYrB6vE0 NNd2gG6qLz1jqYRBzIUUr1jxwbtdT1xQmI8udz7APVuLhYfcSYiQI28GD5p+Pfbg26sJTUen+vuU h5xcWLu79LZtZMGg9Yu1AxaNefLA7L/JN3HgQkgjAPeQIptsc61TApeDAGNpGE3sQ2UxWaJxWOie e/LdrZwajQdJx/B7+sPgqbiIpm+t2HUv8KsuykdhV/LWstAWQ/QsWwtzLVjuPuRvQYJ/o9T3MMpT 1qOrZnnxQLstzzxhWG5NxfSdwGW18U7fb2Z+EKwkMb+UiMLa1roUiFc7tlN38bfLReXfmUDgIu24 Tv/nzl6bHd+n/O08LmyqzbbgBty/E8L3RRGvu71ILFAcs5NKj7sBBOcSRiMpNewjLgNKo+J4Hrpt gfZAonG3TGEjBWGx2mPMgg1At7L6+YwzM6eEI56TyXCybA9dv5xy8W7/sWqCqFA6CrVXcd3M3bvW HVQQfeidfdOKrQ8hCxzyeB2p8jisFsBovt5xvuXFupr60nlOazUFQHWflKgrBcF8kSTBc8u0Yu78 6hSHj9IgbbxiWx2MuzRU70B1TTescZWyIno+gYEO2hp3f91Lbcjo8vsB1ebD3N598uhvlic2lISz PO9hjYg+DwoaCX0daoNlMO4vTPMLBwxXmDH5WKcs2rNrMMf9AfgdK/9BmTNCdEalMlKkdsVqzS95 h/iGCxME55G0n9nrVagQ2l+nkPWnNEb519MEwqnALM6c3u7mK+OiVruuvN+ouapib/f3NjUqLVSw maYEdqp2AwrZ9kiRrNokb5kqUqvv8H10bE7PO6CRY+Y7qnpLn1erBRx+NnmGtDPd4lHP2Nb8kKF7 Tg9uTccOvE8l0KdYUUIhWMx51yqDo87lsz3v3KllyiGNMOr7oU6QnJoz0J1GbuvUOuRzgY5pO2GR 2qLPZUteQHXnonxdTl/xPPRgqoUXCxFtmH1zM74tLlWXWJw0NMvtfcL3XMyoI0l+oU8hiMVhpXfZ C7ngb9zRaw+SaWQeu0J0drqm7M8u3GeCO7mHKQw06molz+9X9H3crGpLGsMvkvfx4a9IZkdB52IE l5oUk0HJGsGxOe6nh0TqOxqpFXwIueGMOo0l9Ei7tTVrMjX/VVCov7QzAIrcAgRYmMLXLfXeYQsd p3gGAYzxpni5wK3BCpfIYuRiryl9dpfDQBe125B5dfoXr3u/HEgPRJnLQaVeMcUIz4ztwssvGZoT JUbALqiF3jOAzld5WaJejoy5iQOp+mfOU6rs7O9Jx+rgDYGfTywUxPfe7/5Xar0qREVZetoblfJR 5opCrs4FaHk9hExufhO+994s7AJmW1fH20XC+C2jy0C0X9p0q9537aqzdiVhF6sRmgzWYWZbeaKg ci9uk2rZVzYc2z8p+WsiFO9pSqbh3WDe5Bue4myvuV1ctcLMiY63CHdPr7TbZaObvhZ7F7c67BnV YDqP4/3chdwUldblCaEvRge+ORLK8cabrbyRPoGB2YUMnoi3qcvAWVbT1nZ+BXlW/TmnmE7msFzX vIYsA8AGnoSXKcsjPCL8tBVvGL0RxWWk1ne+y83U1IoxK0xN82xyQnVbdaTcF0nH1s4AHmJtAlvZ kJlO4kay2s9wQyiYdLjjJx5r23bTVd7xcm3IqLAY/y+IBGL+A9eRK+dPVVP7sXeeu3dsTJ8Asu8n 66b6BrEd+eq0W9JUywY2dfpiafYJwW03IR5KurtGZkhc+avxn9Cnjhh8D8QNUFA6irRn74aV0MyQ XcegfR9tom9qv7kfP8DK+kqIC7WsYm7uTY66ZeIY6ZZD9Bj31g3igvULFvdCIvTFbFm15GQ8LZGG dhKHx1DqeuyeI26hf1I4xFbzOPA4ShX9LvdL3eywGr5wPnLd5tf5iyqBiOIkRuRf2HdwJ7lADC+T H1zsi7dTMJBmF57F7jqJbVbBSj2Nf/EiyYMr4LjDlbeheqSDk6s4pu0EIfkTsoDmejLfD0448bmJ dFarjBS5sgS4T/pR1CkzjiFQjZzNW3ejK/Zpg9p59168LXJVuzGePw1rCDrf/NRYaeQlxvaJErEX mTAAgTXq3jn+assDwz/O65fQmsrX/l4nclFUgqRWvHPd9UZbZqLUS6uBQS1SvBCQtoMcVyo/QwOp I2BdHRtO9nGgvt/3mEJOC1oYd7xlLRXUc7UlkLyhPxjyHyEnlly7W5oqHd0ThEQDxKXyabMJ4fLA ruJaG0zHgbGwYV2+MFCZgu9jUgQYanHolk5EkQhtnICZgpteCI8NFCV3JuqX8ZQznq/xkApE/Hk9 OyPIwcwDVEkpXA7oIramdf+I7mSARHgZHYJuezRj7TNPZf9/rHbOXtNb+0aMoU9VqlItgagJCzV+ xZF+l3fYvOpaW20juQv9L/dPO8KTJFgDQs5UvdjGlfZeXfDeTc/Z6ZKXESnj4M+030gj5TcXQ1No y6+RU0s3O8L8InYg7ILaF4+dQ5JXaeW8y/+VgSkSIH55fSvrheJVI91yiQZKPCXftKL4RZ9X7Y5D CSNh7ST5vsNmJIUGf+oX+wq2PxBKKaJ8d60PGq8Q2C/P5b1zKSHjhl/ENNHz350tnD1dvEo4y22B yJPciD/AJycXJAO1xFFMVLR2B+7oVUdnlgupqcjFIAti8dTvi7ff4ABLTaGYVa+LLDCJMbZ5ubQY Rc45XWQ3YyZCVg8jsmOwju7BRWoWeJkRZC2EIEROmVG0+1baJn+GD4UNTuEH3PwnsWk8azxdlDJx jtScnNZrtbb4I+TjAnIdblwBe103dllHgkTWvR3Gmb5REqB4NagxfL3I1iJa+S+Xt6wrj1HM/spJ c8T+Mt6mDsUgae1OPkAq8YxSMZ4ll6QF8DLBo6CpgHEIoOEbWl4p0BX4wBaML1mmNLXbC5zBIkRd kJhvtBX/LuDn70t2voXZznwkvM4VjPPmrVMCDLIOl1alWtyHCDYAFR6D4tBklO8o1YIEVUhqhS3e EZqA99ftNMrEfWa0VluKkYcKKOi/CDXdASfSk/X7wvMWUJK+fyHUhQ25inLwzfLgJQ2kcC+t594z B7VpW/A01PIOzK1JreO8ql0hcbWTVomMIPQB5Y6Euy5SWw12mDgCf1dHvT1VyG1voxOWvXS9TsPT 8xGzaGOVTHPtBLiTjqRoqgrklFy7kFxaF+Z/4RKTAYyJdQ7pUBKTCxUpaAKd/MZIeCbx7NC1X7nG efTZx99TWh6m7Tag7UfJ6kZz+kQxxuYxCGEpFxKqbJKgWa+2BuN0K+dPn/ZV8J/tZYVt0xgYhBxA noAdwPVAIas9wxph21KQHSzbbA4ISHhNAOlB8JYU2q4nnPKy4lY2fE6dfPjhtLWKUYjtS2v9hVhe hwoJcEvrHUeQ/55jB/2nDJ2udnAKO5xk121NUNO4bjTs8ImF3jkZ297ohZE1a17woULN4glxLn7p 7jTTcIUvXBy0d/4moDOPPoNlayZOmgfslo7Ct6klT+zbz/v+u/6EWHrkEL6Imnl0M2kaqD9AitBJ e5n9VR0Up1ZP8ikjqEsO9kFVbd1933V4V1J0BhrsqEQ4p17LT2e6w9gA+a/vKacN5Ci/SIvFxkl6 1ElI7uEaRtNHtXFFEa8TOeo8lzLTGdH/QVM5ieitfTNsJlyMF35wwOkGfMmL7P3xykqWubU68ZSy no6l7WM8a3Wy5bUHuBqVdAzFHIfKy5FGkUP5wdTvvl0Vgfw4RKDB4Ttyr06Y4EvyNkTYva+HCXwU szqQaEOyvyPJj5tC5m/FkA47Wu23xKJLYlUh/IDch/u+Qy4EMM2kQ2m1jI68NH4KEkbT3SVuQOLU OVmEUgi4PpOj6MaNYFD36Fw+nUQYVBlkj4WbjTeuQZhG3bm6ocRMNDEOfPHnnNPI7euDzCspaEZX 3/amWOvAMx0BQIi6m4XcsuKROsfpztz7rIZkb3IVOuzTUSD+PgJZxv6Qseq7Y/GqCJqS0xqNXk8s QTv2Ut3r5SI+dTbKb/yF5QC2GgSTCrcr8fRMcX4HEQAgwYYA22DHtSW3g+C8Z8J2Jgg8D0njC+ob r7uhQprDCmUqYpMX/30YeCPt2XmbKfhXBCtpyVxgA9Uoa/cdYrdlgnQwjcU4WAmeKYtuqZng1l4W xvdERn2u0F3d31H7GgpyH5nW/YsovuS/uipJxt0OoTQOuisz9e5WoY3hoDkAepf3nnBHlMq4cRJD NkcuOgBTSNkaTgAaNfleGLyWbA55zee8XbgQnhx2TJ3Lu5Zrf8rrXHiySTXiPyW6B8r8xkVNxr8U 1d1pIV9YWUGTQf4Gl/d29IbdzVoQRvZeGR2RVeSjzO93FAxRK33ti5Hs55RYH9d24sV3Kekq5VuU TNMfNDz3EZpRW4hz0gRK9i40/eyy73Ahlr2AB68Mm+9fLc4cHSGbJHVVeHPDwPh43gYBSFG+08NV qAPbIkiYCHS7MJL97coDXMszbxygWAvvaCCx7naRdoTXVWjbGy7ooiohb8Y4JRpKrQP+ChalxbMx r/RDLvIfkXXnNxfPX4iDPxSUhIJTG8jpUO71oxbBqx4R3SiceJlODUIJR3P+DagbJrMHT5RN78bn jHg7qY7Lf+u89JQrdDzoUzyNpuGU48ZJM//9RDfSYi4zdbHbHuCJr5Xgy6he0jviCxlgkPC9nSwu /WBsO4UcN1tOtn0upvabWX79XsELqUXFmqHYtiJBbVm5bxQ9lGS1wJJQDjEZ4jbHr7kNNdVQ3BN9 r+BFA36IUBk7rpH7wPfA9KuoEpTHxAN/7lTzOBBbNyT9JnA8MlUmRECZnyRhVIYDBv3fVS2bhk0S WUeqOqY8fW1tl1aTq+athJeKhfF1VGdtlk/sdpguid5awoflPeWdk6ZbMankPSw9fJ0VFzrk4qJu Rv9aSeBG5NLCpSv3aUw2F/b2plx8ydEaEbpHn5yxKEFAueE3iD43GI3/OP08olPEBemg9Jv0K3oI 7c3NrSOsbjr/qRHZvNOk4Yio6F65DJs4anOl6hEJE/yRNwYgiCUmJhCwgtDcs3jbMar8LjUdmC41 H15/IJN6+z11ZeoX6qdHvpEuWBibPHXtGUd0VUwvk6JQHCtd/mdZSA6CLQqumajiZOIJnhwv0aX4 mQLAdzLJx8PIfz93xUQtbwt97B2CI6Z/zeMmmn0s8QZoaoZlDk7rk0AbeQW0c20DI1YyWEYnms9T VcfCMHjqvfP7iGbxkE++8MKzaTgy/HtGpnW9yJ2XfLhy3K9deITYlihkkBsNXiTnHmI8Bq/7NTkO +RNgBS5645YTKQ8A+hKW3O+4U950sh8/NzWjjRjaiqbXHJ1txNFlM+1g7rA1pMxfjB9MMZxn7ud0 ZW24CpARPtoKXumn76twkiA5dpg5eFZhmn8iQPQwDsJ2r04P45PFwoIAPj6qaqThJkNd6mIxKn/c q/z3eLg+LfIfwHUpR+Ys/RQOeCyxa7X0Ox6vyIvqoKAyYBnPnCdWx5RtjzpVpKEZ65YgBLdY6OAx SjWbGvAqsOCabLhJEH05rcEvcqRpirgDOuVA/XzYmxNZwWLxmdM7cSI/JD2m1RgIJznz/ZEq/5i0 hKgQFWrCWNRAS+WKdR3jAN7OwZrNB4nr6nUZYK9FunjuzKJNc3GsUoYdYRGaGxTE4upEpwiLO4dp 8hFKU3ee/ot4JxfiQumWCvWyrmTLEVneu/R7CurdNr5mBQAHgSsZNKQ6COgnXr5jUbpiGsQidFG6 T8O9PiG5AGCYexHeB07ibIcYjFncRYA6umcthREaj33Ye80/d2M6YbzeFUcVqBczpFwobJ54+vaN 5gbvajaxj57D0NfIXrKuVr5xS1zamgINa9d4cXjSJYtwo8LUHam4a+cA3ED51+81+37RgGBT++UT SX0g3K0sltj1A07LH5f7DtySLJCSCyrrrd7qUUUKmeYSZ7JKnzHcZADkElut8+chrAa5N519w7TX H1B43ZmcTF/3+FmPotfu8zCMyVlPCdRRdN/Em2MhQDNMPN2do5okj8LheEkQy3Mgz32KZS2WJymk AYqPAAWucCpCujRB0UV2mxGDU5OWJTfDrLTU0Hg7i62mZAuCGWEajKH9gkbNaAz9Sc2o/EFu3D4C EEcg4w2hwwLkte7e3aSDHEAWjL868HXepET9DVH46REOzEDpOe3vZ1D4YqCAjwpvj50pKe96QEGw cSOrbR6iBkQwHs4ZXzLLZmIEy4ZbY2K8EQb/V01CRNaLQBEz4V38LjyEg/6lzEjIHPCBROr2FqeJ GGt6X29yR6D18jUTa9dAcMq5O+GlZWP/hy+7SOiaOn17pNXkK2CzKsKq39vgU/mVCHyL/AuFkAuY 6Pj601dA6yyLDbinPZGOeqpwQtJ8LjDxehHesfx/VJ68iQkQOL7A+h5HJpAfTuE5ligti+FfijUG LMwUy4Rg1m19TOT4b/BwBOhQvBhls5j3qNMLD061hFlwIV9BBno16HEOkAsOA/tAO8tK4UCUKYtp z2CtSJk+SFVQ0KuyQosZmriYe6qS6mbPDVm278eJWSHrnL8/4FwPn0x7o1CMrX+v5CfNcpt7IRz/ +krVc7vN5/b/OWiVbIui9OmDDIzD7f0tBnX0zB1UR6duY3JIWytn5DNLk5nSrYQKjD3mdy1YafIG PS8dfX60upi46YDuoAdCPSVYh0byB2RR1Yiri/VcIerdInKJhya+HWH3pdQtCvl8x/OdnDk45+Eq pFWF+WJtI6gPyQAOab4emT2B/eB2YsgjuvEVgYEowQWC6AWKlt25yqDyYccJq5wvhsAEkk6CCcO9 yv7ZLUPHCTa8Pp3bqq7TYOV8Nr4x15vihwQv5wHfvAFOqOmL1NSItcZh35KKdQwQ0vatiduu/wMU +KAsAOx/KwggvvZNQhhN8lLAskscJ5ReDO3LFndrmC+mLPZOn+4H2MlsWrL7MkZvCjJKw4IZ8rQY DqcpkCRs0xsAQ/1V90bweHIjNz8ZVARtcWaG8X2ybsnhWZKbIZqfgPNwCABvoeIGZ/8Xxtt3C8M1 8cX55KPTcWQw2wFYQ4j/8BLlr8WDyHi2ncHu/y5nkmXpmkZMq19yMiu+A5opBPgU5W4YmAqg1j7n B6Jzox9axw0CIlNtuepzZHrBD68ZkCeTmct4kJTvoTnkn3+/kDtpAvWJqrr+bWm1Ejw8tAw9KEPG QwYTBORFV0E9qK2MNvJxyw7p02J+uf0CUARDHJcVyRmGskSU24CoPEeI7oS1WVX3AJh/fnqS7Dbx sdEq3AVn4HKUAVZtb/YnBjnRL/lckh4EgkLhHKUncq18oWkftX0Bt1JQrQjZWdJof+2snXhXEVBE 1GRJXU8wLs5n86STbL+Xttq1hLWj6s5vuZHxTFjFlvuM4KIgNaPJICxHzC5XKAuzTZUDqbfPsYuR bmduC+p/H3FHM8e2EncE73UpGK/syQA86SrrWtfF7bOHX+ybUjyhGt4EP/xudWB7TenKyE1SfGAI e9AUAKXEMFIUtMpv1b33z/FYvpIGjYvIpDrpKFk9JSYojMuZKb9ddXcDcsbVJ3pD4nOjACZV+Gso RtTwYfNegwFjrVaPTE4bi0iAdWD/rCq880xNxKU1ymXlXqnIL+dQaQQVL6vFjv/tTbmQyNr7skzy KTiEdzSotl2dGKtp/TAO94nokuiHpGZOhGhC/cR9QU4gStOC8ztjsv23B6mw1SxaCSMJ+PQ882O+ Qn9mkfUIbHqfSblPbK9i8UoDB5vN+KY660SZgksuseW83R1cMzRu63AezXxp7elv+Mvzx0Sy45mg kiKhf8rIf6Qc39aadFGqpkVpUPihkK6MdWvx7Qu/coEzQq733RYd+l0yXWfzhSoFKLBARA4O/NxS H320DIvgCGjcj0lKpYC9LSbbGgunQGlhY0iO+wDhNtczW0DLalW40c1gd0K2xDuYlOmRpU+W9iYc 42Lcp0zSw0c5vVp2F34gekf2dcII9l95Bzy5yNi0voJOm9PIGnp2qA3hy2uYqm6IhDQv9DB2lFma GSzZFf3iuXfBWg+NL1S5aMhZWU5NmS9u+nd1XUH6TfyWTYI17HJhqje/x/GMVMDqN80vOQkpnizz A50F3H/YF8DE5mf1HEmWsKXWjwHQhnx1Lo1SGQz2Hv7Rmynl7Fp5pbq3IMmjOajMWbAf+r8xvGin t6gNPM93yWlErckKQLI5DNEjk0rz890oR/XvP7eHA40WAFOqwP3q8/ra2L8MeZ4ogrRU3rHD8Gq1 nXAgnyuTgvy1QQb5ZtjtcpC0LIkVUOR+LM0aYY1rNHw7ZGo5GYcWdkTH2D3XCu3Z8VLfux5k2eOE i2goIKa1ODfM2XPkBTj99GFfKARoKpvG6PxHQqAAyG9rKqRF9AQtxjdB8eCmzh/U/01+e/AYkzs6 nOMSgijgZ2XeBJ98VTTQL2MKT72t8MrGxvB5SZx1PX/RQcSXMFX6MyzBMRrgVWYp6MljRsDMN6os Rc8wNOMtWvQBX5PXrnHymFBFkuKP0O/Mjl05LwDtIbSoYtY1Sv3UrRDuFZ38Fbq35VHk6J4z72xh LWriUSrFP+DtnBLWyHhM+W4LNLA3YV4NJkgoTko12l7hbYx2Vl3pizfjE7tPgmzxnwk5EzFSFo8w +8iWCALpNXQBRBsQzeWi+g+5kCNGnU04I/hKiaxYCN9hkHUxK1gUR4OPnFhFyrkcqGi4O7c3FlOh BxxVoupkrFl4wqKY9KIWF4f29w5xwxIEmjtY460oJAncpcnrWo8X1/CSsSAvGPNgtwqul/dWKslq cZlsxR184VRasMGQk/vS9TEHVTJkiJ3ukzXQObZ9pvPepEkjmk/9hD1LkvqULw2fH0twBkvWWnfK yZ+iQ3FKcSLuidUikQNjdP4mXdG3qWdZiolh4tQO9x+2JVmZaDsjtDs9cdueHnnGM6N4U7xghy67 zPkJ4BiZBZTTyHVIWybVNMnWh6ISxjYD6bftzpdEsbR4nDzcwAkFpPTLaSsYL71s5xmoq68XyOub qQO3XFyphdDsyiUN+y2VcuF61TwuzdUjiXXnknZwKFFoF0zrfzGvFJNcflpzyQSFoj3J3aSHDnZQ 9boTl1Y/Y7sK09G3iF8ZprtrjPTlh2bQTa4hqhu9a3hes6VglHMPLuonk9C5/S8kaYQOVoNb5WAF xZ0X3K6TCH6HGLdqfj6HDeUeGM54M8Ze/i7br2oAksRp6FD6wZkmXqC9OBR2LV7d9FWG9oa3HiGs M8SXASBPz2AFScEQfnkE6k65px9hgCwj33yxsLFJeghaSrrErgcnr85oMNwPOFZzwt53mv79jM5T GspeGLzX+t/yTvhXRExtvww7qWmw/XbtPvZ5B/lP/v95XzWNHeuSKsza0/Zjyf/X6CWsvg1o2Ux6 jGteUJDiteT0KwpnpmmZ9bxgMg/KJltim7q2Lpy3V7moUnMA8opHPo4jVBMZ+kdy08mHtYhKZ6A9 0gnJghXsHpJ129VwtIQj9jDausQUv/gYlayBO16jxgF53ekBdqZgltI0SFENMAjq6964IvaL5n3n fFaxEa3B9fYMwFgXa2GA7g3olia6i0oVloQEjGaDJhQ0WJg+irkEG382hK7YnXsQLpPYGKjyUEx+ HxktP+LgKtz7vPS6HJsQlHWKYrXOXemdXtEcezuxx6gqoFHfZ8uS38phDo79ujw0VTWBetjQkGyl xVhhAsJfoUJ2ymJvibLiAw/L6QuqBwUKBlTAnfixTHqe1knASwlIE+GRF+6zwx1G0iE+TbzRhmSc BTBRXX3CKDwPXszSql4EcAmgAv0Q3efPI/HOPwbNQR5vUCcPE97JmCbhugms9UUKevlS7PQ16DX1 rF5lzCz7q/o7zqqVVE34/0LNO+Y7mPRVBSJbosmsuU/2H3YkrJwnaEkPtQfLkukIKAWjvGqtJv4S welv4PGFlP6PGkwGEvs63AHb0Fc6YCitQ3KWFWuNFWB4ayQueFmgyPOHZQY6WXYZFjuh8Fh7914h MwmnVqittQqXFa7SZvIPp/Sn4JGIPptNNIkQWyc1S7Cgdy7iyHPU+sdn8TKs2eiiJN8dAO4JOhag VKFNX9akRVFzzVia1CV+hqGQh4iZJiSdLqanh8FeGCxHmCMzfH4RzzsnBFrQEU2SrXjXYRkZAml0 P0+03ghH/2kx8IDVYkcIMYHaNnt8wT32LpC11UGxSh+w1VCdysriqusDmlLUhWAmvV1Ozl4BbI1Z KHDqkqWY4GQyA1SY5EQfaTWPHg2o1VnnGqPIGt4hXYXO55cxbBYdHvx1zAvqZYxkhl0jn2NT9/+W q0ABYnXGG3mqgzPYELSszpp5/D7zBgDKkNydnA9lJWfvpG6hhTLRytgN7avWr2unOPNZyB3T3ZbZ pRVfCciHoa8EPzi/RNiQQ/IvcSQ/gK47oQzBxvuO8ySXw7DV+lprYdAKQLEYGQkfglfbvG02Pj7k p08PAMPEmu998rMksA3xOD5y0etugi0ykMHLmNQNkVOmU5M+0QcnC8EV0JB45LQUr5Ohf/B/9qGP YeqvIAPWmjHr8GAn/wc9yfVHqfy7oQuBI2Z/JqTw9fSNGCiSMwj3xXe0tFMvVJ+hjhr7K0D9qq1u p/4LH0Ji38POXp2kne7sp5zYC2wEHzqVurV5DdPjmw5N8EWYojtKTVIxIXsA6ddhAX5MWkdwI7Uf C1A4QSxjb4Iyh+2tl3VNx+ImCRTwpjSbpDbelJRfDyvFSVeBd7WWSDWzvMEtn84oNUvg3kUlkHor bKUlUZt/aTxkcgBY2saT7as2KfFrA4IpX1GzvDPRGf0kv+IyGS4j1z5m/7Uu5A7LvtYlM9e0BLT+ M1x8wPCgoONpn6OqvEU50Zi192EH13pz4z5uZ914ODAKVVD5b16k92MfzAaeLHF4Lwoxtj2t0rOj JM6UrN6mGq0Hu0/O+xiS4795QxicG6rBI9CFWEkkm6gJVpShWuX7uKrmdGvkKZdxAxnhrcZ/hysT f/jRiQiZgO1+CFQ12byELS99+JEjxVtr/BtlAxsR0iKbCiucBg+QWBr3wVcICP79oxu8izDGfmb/ YXlIVYY7hqSB83F6LHN0STDbnIa7MojG1HgKs2O4LLjyt670nNLQBBUYcV586rTC1ll2kLCfRncP LTfoj2CVFx80tDTYzIQ3HKuWCbW5t8jKCJiLQib06bVrzgYlki31ZbDUd0synrb0Z+x7XnbbueIY 0whJl1St42lQe+UNqQXePriQFN5mIo+CsZy+TPTbdwNd9NNuArsvsrYUGYceWJAzk4mG0tEXdlER vD1w8clHMXdO1x2D1m+NoPmZt2vO9eAwjJSg8FtDHr6iWuDy5iMH2sfhxbhF+HnqcaLA3N4Fbh80 XTuC29KpvQvadusDNUhX62B0OkWZY4BFmG+An/BOSUNzHYCsiEXlhE34KJTwcJ1QN7R+3JpMwAvR Avdvjrkh8sxvcvJTv5x6BFa7Nj0Eg0BTPZF7I21SDYnVMl3l/8Ku9A0jfsvgRf8xX90Zbi+9zUg2 OH49/4iXqZKppkjurCDjF7q/ft2ala5N6Em7LBimtfulAwXaxYnXXMKOsDKt9D2m3KaRI5G4ngoZ vwtG13liHR52scBcszU1+GTcNBqWWwaPKIvJaW83ia6vmqcrzV9kWQCdRfKwMC74W8I/wMF+Q2u1 xQuRv2DVrJT8i5Vrjj23+8IwdwiBY9HxWiZcF/8ljEzoCHOskVp8Purh2e4hPHhdKJ5JsMk1QklE AypYHUC17j2VtZWYhgC7Xz9594pGsQlUNRcFDDBk63/w7ghE//4q713GBIjU0g2uGY4sMeXNOFsR wYWJm6yRxqYCvcY9QW5UzEOX4u+EnxwbYsXxVxp9xQJfnPYjozYj/2qwvRaTvLdi9LuQRmco0lh4 a0Qn2cTDuA6p/hyooh0r8ySQ5mFfbC8bYou/C0EGUSuns8g+cDxT/TLkHM4Z0RoNISdJqPUQ7q7Z QiR32pEhK4nKdqh0nQsPmDNrbfNR2jLp1hsTw0wJT3Sfo7Uah885gboAnue7eZw6VIN/EINRGL+T 5lNvUgnhE1lHYDR0O4wDYeGF1TsPnaVW6pHGvtKi+qwNXWSSyvZwMxRxRITGx7St1D4pow9U3js4 fPSCMidKKYeD6o2P0mKu1L7uzCNtp2nXH0gSzhZhUsv1S72KiGUV7E6j5vt8MH7t7rRAQ6oaGM9C x3k19EQEBC4AaoUx65qKQYsLqhC6s81v39YSQqYjsYa28XZKZ4W4FdvYcaJZLTM34WiZ018bFto6 2/kcUkTurIQ5BmVHdRxEqbNtfNK/sdLuauN1zNgQYOykREbA8Lquh5PyVoWdLDA6LUsYKjPvVL4G vA2GB9SNL60onCSzwk9Gq6FzZ386ZsqRfiGLzjDA9RxcOEiPcdy0fGw92JpKVMX9jWMVyFguuzI6 Fz66Bnx7ebrJFPY8i7wNIJy5UoH+2WR4b1ERvs0jJh5tB7I5R5ON7kJ8uHz93kPKDGe/FaK4zPfn QYXEeJUuIWdYegrfp8fPY9w4RNWmcmfnRc9cPo0Ub4XirDw/UypKTkovkOHG1pfJHH1vnm+iQMq7 Ru34UtIjLFyUXzb+8VCy7YysRdfyCv4Uh10lDWiyZJv1BwrTk5QHxSYM8z610VHk9ODr4tdcLdzU iePXSEYQISRwbXShSVdrauG9rbYROy62wRkRyYm/WitDt/HN2imxmxDEJ9TUebgAHnXb7XAn5yGn 678gH4nbwhU9uCBN+mE86kMAZzKDbmLCqRqSQP6aE+Nm6c2rPaYoV7sMS2BByrMleR3BDL5v6HRA T3/uwNkKdAAgYaxkH/XFnQVEqGUNYf4L8hcnbMQ2m6MvpyQH6dwnmVV6DBoho1nTqFVWWiJ5/ZHD BiCGnbTuURMQM+E0lL2QsmLCWDsXFyVRA07IbUSrWpH3YvfTHLYMPoqeiFfNmdL+rWrX3yriR0dK lYHwvv3tOs8u+dFSMHMxgJtq1hhJ9wSEG1GrrUglYkoFiqy0OrvoubXQYdfjMboZinZho6JUp4qC up4/lfI/AevBLhAR8OS8FzQ1HQ741/+U9u8dBOAp/UphM6ktvWsga539/+CoPuo57aGiO/WN1fhL /IKkGO3ASFwshee9veGCrxaK34988lI+ylWmW12S4sRfs0GW8z7yrMWv4aIjvJKSmHD44JvDghNn dE/+k0i7NFdT0vLpSF2utH9UhDhdE6ycR3NqrJ39saskm+DArdAWj+RWhEvsD4CDXyD6fXOpK6sC RZM8w8gyyuhsgkepc7zrRySChxQwBKrjl19VX/mOA+g6z6uUZu2Di5r+eHlsqUyFvVNkV3MYwIfc xZt8vg4QS4+RDRQZd+mRZu0/9cLiVm3KwR+zSu8k5vxYIwcoqIfeG3OvTOb1aRwtHEGPymwUcJMI GDFHgnBpcPA74MITBNWHvuNyO3Is9wq+0/a/TWEQioFwZcvnTkUvgMi+zbQgJXeppzpI+It4JVAl i0Tq3lfcWxp+a1Sp5PSYai2roUsK6aVHNiMbFZjLa4hTnPTwEgZiEoOwfL9rc3muKhwG2GY1f16Z l9jRewCejr1BIk41RHSFXgZMZM/JZyORyHFKS4kybzMkqWmZuGOm+8MzvTVhxNCUD3w2O4cRnW42 lxFwm08jyTwr7V2B8af9vgg1jU9gkrAHs9iHZnG7T4HA2iIHPtiVKKT9cP4luCjCHDPo6kItc8oB /SdWJgJJxcyIz0CTZ6WlYIkeF1wJCkyF4juuVyWRwzdA30yjJp56JOrS6iZoVjwS/A2Otc6TCTXO 2AcbgxHCSAYdxr9063XYELBZ3Xs0AXqccPKCvrUO+shWpH4U5pCs67MAi8Yhc9F6gvbAEFaq3S+D p7sSUs8QuNnyCtqVaTc2P0yPkZtT0nSxnOcijXMYAonZD6yd97n7Als2IsbSYKlESvq9lzEgJRBd MLxTcEH2ZlsdfjXvRwxVY/k+S9jtn/Mu/k5cP6FaUAUsiFo0WvcggEjgMeVMMTVDSS+7y5sBFToh E5BZdo3Ub36LYILDwWyQhXGhjiZw/kZYINPB+C2rDDf+ohug9TWm+6WBqvBGw99bJ+zlelkXh3kW E8Ex5ll3Kv+OzWCGrvf7Ht+TRqjBkmFTgM2MiF7a0SdKCYx1yGa5sLRxDNwgXp6/UMGy2HwB/8Rx GwzGFlOMuZQPhQtqB/N95clKVMtOJzRfqIZY7xRf7kGG4p1MJkz2Ye85EkId/hPA4Wk2rclFFfJv lqzZe9amvfqe4o/Q6f4oUklOl/Vlrsmm/acIVIm2dUr6OV8dwz0h+DL2EORV8JFYCp84uYkFQdBT Ul1G6Q7BbnPCeC9hS1uVxjpWaEC78HDwPWVwI+4voha8yeQGDEy+GgFTr+T/VL6zv253dWzizZsW Zo+MogQ2Q+O+ba4oICp9ig1IIApjThvE0RPvGXQaLvEQ5UQt7kw6tVyA4mSUl0uOAEJRv5Z1ieh5 IbnBVhstYwuIiD0EpOyD1w1FylPtsu6SFb67DPe/qIoQ0R4r1wtq4ZvrjHfQGcC4Ho1/2kJ91EFv BzpPuDXXV0MkfYdEgWH+SPTJumuM/uhanmuRXo5wMOpQ5SvjVvWNlbk1QBJMH4ElBaSDRn/Zgp/a CkiSMGDQZ9gbEJwPJZyjRXZi9fwt6vgb121Qd7fISGHE648/oyqpxWZabfWKd9NkXpPsfs88NrpA 8CIjgfmaUCsRMla8eOxhgEtRyDqJIjUjviFvcBNvc3jnfqDwYh6Kp6xwwmDHQA7oA0eCdv8m9Oq5 PFsLqShTGCDwD+97t//8qjZETy9k4OVTbIX4QM1KzY5V1z7mOIYYJjJJ0w3sDz3O1KO0ScPmTMUp BVJ2ODrP47Y2/PUjnwah4GhC2003nPZ+Nu74B68LGQp+s7dOMLsNauBPwpUX+1yH9hKUdqETYAiT 0LcMeL+aiQ3uayw6hQLzQwmSN7SrsvaLAkAh1E/mgZlbOFZ5AKpWAjyQNS+GnIspgONrZTxsBs7p KY+a9ROV8LDI3Hm+G0UEG/PPKu0iYg/Dzcr/N+WDtAk5NDeYjGk0afNhrhY1mfBlMxhNkq8oO6HO VbBpCH/tRKluqATapSrxDvPUwEZJxotAE5MsFEjsUKgUKNtYFyOHAKioQWChkCbH1IoipWnNoPQM BtKZBSYoNQ8fqvz5IB/ryGJ56239WmxQehJcYA+Q0FMm9lqIDep22O/x+xSCw9Q0nofjTOi+X1jl nnu2Rv6WfPsBnyWRS15qP0gyduZSfHVCZiOTvYZGSIORiXlK0KBPBHZeceZDEs36hRB3LBBjGfv6 OJsgNy003Vu70cIADX68zKWZ+Y477JiKpDUnZw8EtfuDx1QudCAq0md7/3O4jrAe9FhR6R7zeNIj JH2xNfX+H6itQcujhn+LZ+JzXtR2uhKKEBa9ynWjJsVzGBgV0Vp/DoDXg38BsaARmSQyyS7y1aHy 2kt5Y/kS3EulWRu8tKAMu98SrwWXfmb91RM6L4uXLxw9poc3UnregBaNjIpHaGBjLJS/cCThxXWK yXzabWul7QoMjwpsnBx3NhGtXsaJwVrGGct/TmFRK068/OXG6OdJSlKTmpau4sRixL6t3d5sMgIr oSgpe23/+zI0YiRv+0XAoWZeVqCJo3xQQUAX8bQzKR0qgHS8vgMBTSNioQJVqXVIkfhB03Es5WlE LwFfELdbut/NYO0U96DIYHp/47ener/Zw++Gfp2JclIJH5mRHs5I70Mk/+ZM0dc+m8Cum8/UTOsW g+3lGAzJ14o00yxf9QGBZK9FJUKWy8TRprYzBBl6c/ieZaeBJxoH5FCTNAdKuFpQColsGCmLB0YY 2KgtHFYmQZ9pIgXapsquzCRkbyhjiLv4juwm/7Nk8dK9u3drmuy+exNqKmdfg6D0jnr779BzkkVN 7RljkG0raJo9mNDvXWVmoy0ZSRpQbx3e8VaMG5jj5Mf7jo+gYoTRbY00A0us8+2bm1Uy0NQ7y38k 5CBetbYkH5dimg97r8oREs8/5HpfT105bYVqfaak/UrvxJi3F1GpuAxY/smzDLt4Cc9JiTKnuNV5 hT1PiZSv8cFWQ24yD8v75eb2hvbkFxWdPOIsrPp9nSEzkAQDp8xBqN6PAl7Zend2HLpm370g28Bf yTX/bMMu0y7MTflK/f40yZBayptkNQgzXLCAISwhtNrYWtWltAel+xr+uh8DRLS3illla6k0h3F+ h0vj9Gqs5HS5alwq0tRot/vUURZ3wvcMLXyL6F2kPY+KmWtK1LuSRNyeVUtGtHHQkj6W3FptZfME RUkj2vDV4iYpW0PKZ8T8nHT/eBrrbdBQSCP06pfewFWf6gW33Pcl5KxlqKCD51Gkm7YqAc/PwDa+ YisWjM1GyLDPFS8jFgkswC8ho3W96EV5lenQJWCOE3ijOTGbAj069EVvaAtFxBrl7czKreF7v2P7 a4rq+Yka8y8d+5EABFxNdI3mMt4JP9uqHwVuzJknNXM6h+caJ9s29ZmS72o7FhfCmqpn6ujFMKsn tUGU0Uxz+sJZ3/zSU9XN7tv3eOUgMOZMFu90DSl5/XiHuRRIlh/Yh5mdpZB+UWo2Q254h5wqkUQt C4VK8/2ORmVqjE5+sBY/DJI0ZewheWDv537IPFIIEgQ+61OcfrLxfKd8N8mPDFHc9CAJ6kN10orw 0C/InaJ8h7ZzwDvAGPgPZOrgK9MW4TOijlp7+7RNXaAlWCT5rIJZq8m/QhoaJRtosb/EBw0AiWdq 6axsu80WfS/6d//V4ZF6ZF9wmu2YPeRI7BYOHcOJ7O2aZtoN2jhhcv0x8zYfpJUVOOZbcRtbZnzN Q5d3vO+SFxTQtvcXdv9B/KC5MG54QwEiaGC6/2CqPCySf98pS2Uej4ZIvnqsj//Js25BJlmdPbkT 47Afviea4xx8lMRquDrxs+xEIkWVuy3oNS3yYOjLLOpisx8mwdqkftFJ8na1ukrDOIJY2uuX/wQF o1+7AZvJ+qpFcfK5HS5a4kvTxz9Uc5SsYKGGgHqG8pozmJ3SeJf1hQA0Ve8VWWqOd8hZZJM3iFyN W2qyJJnrNRz2NlSjpU1/0VxyXcSwV1IuCBw7jOo5emFWQv/S923grMSrOcvJ2fdXXzgxW0xSXC++ N3dQkkDM3HRL5iu4C/yKdeL2oQbb+1xlk6WG/a8dT3iDILE7W6SCoGGXm78VPJLLetEkiocveThD 1D/MfORFlr7PdJRDJFcZ5XT7G7YfP8SGLSh1lzz8KYyV0aBoqar290dJrx1GAbcSIbmdjMjjL4w+ i04/TwKwW+WqzQK3+JQ6llu/ODXunpgOlMn6bEU2bpBSYybplBphEtn9ZDMpLk6UH6P00X07b01G IFub5vbZLp4fBfKtRBLyZETlhTiNZwmyYBd70yuyMTQWzKfzmtmExtHdeuZHy8YaaWrj5u9XL8hz 0g59S0XFw6kV9lgb3XkHpqDc09zmHAcU6k8zZ7liqcNrp2xTzqvi8GO5kdBfb25NGKv5caSHZaFh Jvjqq+3BBMaloWaLi+1tUQavYzwMKbm2WuNh3t0grugIJBvoPPy5euXfzSQyR8Rh8BxKYI8XPJdV KqmD1i6UjDZERILN1jIPSEUFLtly7BGa5wyyS5U1EDa3rSCl12d0715rbSjYgwLhHh0OE9okS31t W4ui99/RCgn0qjIgZI9g2f7uTvDvUAPuOtjjKQlpOz5A5pCUMONqqHgrYlVTJY9+vaXFEjYiEUGD 9Y2NIygOW4aBV4yj64KA+6g0x5n4QdUzYOsZrIJMsoTTFmX+WqeAOXB8ocMjLt3YDgzRS/0hMXGW WC22PfGOq2mr14VkwMXgwYxyRaZkYCLqSlnBq/w6KlqnOQ9P3yygW9MM8YtfWWA+k0oxORxS9aDx dve2Polx/pTC+eL0zRE7b1VCxhV8L7diCRaW8Bk874CBJQLAGiwlI7nSX1fkyGvdLkriOSylPZQ1 O32Wwolwh6HmWxj8FsI6CkjyFSRGELoJJsWdj/yjii7t+iuPqwAgQ+RR+VROdV2Ojdeb6nw8DSua tJpHWh8Q2E7ucvujEfRorAP4xW3URDeOioP50hAlk4nHc23lXwKooygtZp/DN1p3cXfuZf0Mgyuw bqDdZS92E5MowvzLsDFgRv5rNqGmuvhZ18beOOHelGLxy1v0B7mdR/Kt2c5JfoEmEhjlvfwAKMuF LSdKPY+lMUulMMlXhsA/oi6/GHsy8+IoXBYpgE+uOkoco7Hluu2udyDTkRSV7Q1+6EiMHhLsFLUv WYAYNtfs5Szorr7D6s1Bre85ZCqxyfDk/RYM4E9qZjenVemnxNUpqt+rVrqTh3qwJ5F3wZGmfIFd NTBRM2ReA9hGrs5mHrAcnDhrEgezL4qLvO3CuzFhsvuojH5XuhG6SJEzL0C55anv6bB6rPGuz+Jg yLdp4qib7CDa2U8Us1AQJ6tICUnP62InpdXRgVUc9rGoJ4VGzS9N5U1M1ap5Q0oGOgwoHexytVho /ZLPl4mdWzsgDiS2dGaxudLwQqnamPSpa9HxLzuJKI4lWngRo0xGhPxBQXkbTlQjL0hzna7k248d Yo82+UONnI9XUqlasSIrHvB7Ue5P25858I61e8V6zOwj5yXlAdYtAJ+i0/xRsKRA4unIbdTMetSy zc2kq6gDvWSyO4fLg3E5NOfflSyNOi89QwtL70yI1p2diI8iTorcZdTwYTPyPcLGs4RIdXObvls0 LjTUArWOfvrIyIdJt8Wtu9PRXceMPzkMfsuIz4l6wMfV03RStitR0b3SHnFYT5BC/tMW8PX3kCGJ TdgWd6yt69ne6RlbTNucDEZuniEGH/BcvIh5Y5t1nepFH/2/WFZ1dQZwoh1g3+gUIlk5NBkte5Up g4rr9rUjBc1MWjjq1CARpk/X142lHQZZ5Nc+80oCKLbWAasIKobeKIfsaQ3Y5cLjfZH5CXfldhXb tqxuijE7iy1O+9aint91A5NTmI9/hopbch0Tw2rQdQ6cGgTY8WFE3X2X4QjAWvYszS4RmcSP7nTo RQwhamdsikqsqqeiz1GwDhxX5A2SfAnSyH60Z/X7gd2QHujvDRGBZ84QomcCiyRyGs8svvhbuRW2 HAXFeEcmC1meA8vHGUbRGTG28CmSXG/kN/JuXbecufH4Dmu/M1NOrcrkT3nTxkSQBGT9jR7NjSgW tFcyMNJAcOK2yx7LPMlO4PoUC9lcbFr331YtBnFnI/MuQtL3i+f/aH/o/xTasqMg4unL19GO/Irr zZeNH8bUWLq/VHjMN2eC1OP78FOX35KIeg7qjOJuI2mzdsaDvoryUKOgGzXEkLTvfO3pjJm1XATF 45zNubPy0xX/fkaEZpDEiil/mhbeLMxn25ABIGv98VOD5mdoR+f47f04idrs41LuEtXXwYkVnRsa EOGqUpUU3ndosNQO1cy/8qRJ+bzpe6KYWOYVGPoKbTKAlGtcuOpKEragPTy1oVp7gHiRAm3rGmF3 Hpj01J0NF0JzHtN7JvGFUhIMj2GXSHga8tzadOitu6+bSUTRG+zjcq6seXoLMn3Sm1P7u9GoCDja hw+EO6UAH3MPUB80Ze3YHD1cniDvIR5Aenpjo/pEjHM9QlQYGLFBEHqXY+HczTuntmB2ioV7EQKE xTm30oELLcErXM60bqnbgvFv2E5HhH9gXNuaz9S/xLSbJzdDE3gIF4iMxMy70ML5XIkUjjky/2/+ wdFDL39PiS74O7/sBupYUMwyrN7J0anRiAIDGPXt14e+0700LlR7F/FMX/BPx3g/4K8qTIWU868x DY34UCz2FMjFsO2Zrgo1WIgHiqsIXzUVpLQBpqGgp8m+YpjGF3R9hpIuNK+rc8RfC+a2V6AJW448 TpLCFPPjB8jqy2TKkCtk1XPajE7kAILeav6PrZ2reRsEoL1H/zplNQL1cIYi0M45f/ulL0MKjqtK pjAaa2opREDDNmYoXmBenlp5kaFGpRSC+h0OoQndHNLgCiJcSYO6g60lyk6EZ3Y4/TgoM0NUSLNx igdZN3mh/GgB0EcdwswA/rrNB03e5ZaU8c0JXyUF35X5F3a33AYrKgevjIHmoLdDuPdsJOzKi/4j m+6JZimXKQjb3h3ymciFP/1yXpREdg1QA8Q361bl0KhnNaL75I8wItfe5EGxO0s3GQsPZgiz22LR w5VhsKf6nb16ZVQwSkjTLJKfQqnwWCiFMPkukn8H+ebWdULK0kuR5LQLXcmmOio6DHivJRaIjDfP VaFmltyjCAPhdIi/pxG9cVWW2DS6CKP8tnq6MrCC4x9isXdcev5172KW5dIM1Wv+e/A/b5V/tSWo kJ8QGKTd/M0tG6FGXvyqLT/j9Ixz306VCGkP7dU+g9eZ0WXP5NfjVT2x0cRnFRp8xIAMDWUNQYrf CaRoRVQSRGlos5VuNkZpc7xpdV1E0n8te2DYofnIfXf+JTSFgi06YXCiFJiHndj7QYwrPsMNXFk2 qr7pbkIUqrMvIqWq+ZbJmL4tNCYJfG6k+eDA/83U0R47zLJZ0Wc1/QB67RHzkSJk7ttIoub1+qGk wMdWui8itGXbshw9gfYWC4Cts8upGgTr3eFd1vlWdWREYXbsztpGUnT/YaEBuZRVqv6LXkm5Ckc9 J4LfhMIjvxDABBMENnOuJjpLN/vSPN8nD58U8m64wpFHoKHuUm0pFOb3rhx8TL7qoX8cbolUJ4Jc KuhBwTY7jDBwR/FQd1wPVfsufZfrS3Ew/mjZIedVITXgyaluecGTOH8dzesiXZqXVSUeG3qIT90b 91cH8CD5JCB9/+0mjPmbyltbeq+OREcR+Sj8nrL0kLPY/rBa//AvkTssWODawd6GcARxgtGDNgsU LR1EWewx+ZZFp6iajXaotJQ+ZnoeeO3vfB9KY/FXEzwGHzZMj8SjOcj2QITeQ6bHnC1c+JGoJcgE 4I4S9WvmUk/J/is6loBvspI4kjX8bBzr2gKIyRONJKaT2vvCSmmCNvqiL3PSOPFT+fr59I+Ucf5r oifMIbtMlJoBKu4M3OQ7qGSBzmvPP8kot8eGbvAZV/LYhfpBcQmz+3Da5kj1hwlSusa4KU4VJQqF RA8wTJk+zf4PHudcPaasfIdW/XYojtNNsnRFAfw3aAx62ZQeoKlTgLXdcU4UyX7VnlO3C47Yco0q XbA92Q6g3dJhA9rmE5UXbxU30CL/2JGHPXTnbwI8b0atO0h13cEh1tSP+CTZotwfylgHO2pYhdSQ memckAA79Pbbey2uZOlIos4kFGsUHS9t6h3mETLzLwUw78Ib+gApN1QkUkPS8Tlhd9Rb3SCevE+4 9QgKKw+hasecWKXs9/OIo5RXSrXST7EfqRSaCqjIbcbPGEtCaL1GC5Q3HoykeqH/Soc8YzxKxq/z Lc/ew/T5X4N7CoVVXlheMpMo4gWggy+6OYyGgUXhYvskNuiCE+YlOSxqZo9ova64ukRJfCZDQ1Zi yP0xZ9COb+wBqod70AsJJEZaybnRWwmr1cGmD3C8LUSuBUapaxWabSAaoIxLpfOrBBleCDcJ+vbB J76jOWU3HaBn9vcgqtjTOCeDZA8Y6O9HrXSa0RGKOBF4xJrk8K7OR+8M4FFByb3/ZUQWIjBK0Iyi FX5XyrhItueAhcsy7NubQyHdExKKDRngufDPGSvbs2WebZK4GyxWOfiY7+DfXUjjbF+ye0qEUJkH VC/HESGLujicv85r4r/BWSxATSIwZ57Up/JcGU6mR5v3ZD1uUEYFVrammfj+zu6sy324s81J2ZmH i0lkwuo28+wsUv6p3Im9KSAgPpSWkG30+cpwP739owmGPmF6LQp+pkT2aNnmccEMEVr2wgTv/u8i 4xo/RfsXcGelPWqcOfQuj0Ul4OJlGpSdhJCoLyisDcfB3ZtETne4EQgjBrPjQAE8X5u9VEl2gtJU bSFO8SxDRPsD/wGvuHI16fDQJWgdwyi/JrVl6/lJmodpYxw6j4QYFn3Is0s11EyjRzyCroPdvx9c l8vbVlGPq7c8M8qS8zZgwqdLwF+44ZACHObTQ001LG/1qQBrw3/UB0oAh651K2sf2GVvYzG72f2C Z158DmmO3/zX8KmnkfNwaR8QroGA4fGI/MrRl5M1g1hG34DotYWRkeNxG7kOegvx448qR3qUo/ec RiG0eBKw4pm1l8lS+iDIC4ToOFBVahoysbTzTTGkL2s4l/in6OhuAyNRhgBRD/L/xCars37xzTzD pIBHHsK0ij+rZj/BLu3gOHRMnr9sd+c8FwCIcHbBzLNIHSaFIOXdQANTsYRE+FixgzqJCdm20e9h WsMvMOTtfSec/dQSLITI7BcDmPEa1HMcR2J4u8sPTMkKFjaDwUzWT1Uun94JYKvpKudtc9Y/lIaK kc9cvdig2fok8XEB35QndPoSt5lBDNfLBTjoTGLG//fvX4qjqRrwDDJpT2fMu8iTLucIZIXmfw09 VBqQDQPISIfXWzdFTdsP7UN2ahpthWeCgvFk7BoCM39q5Qfw+7Dp1+gHtslQ1hy2GcIfHPKM3rZs v3lRhG34ePGt5zmFhh/1mW2AqdXcVvtPQffA61yOxkCan4tHWRo19D/QX2o8T0QuO9mQGePlBo3V +uxp44+bqZDOA46xD2oaoD7b7YKjflA2iAWqCN4gO640Mzxgu/jbh3aC3Nivsbx78zxr7sSPPsk7 sIu9PKrtVCLPFtBFgB5wGXHk5KJSGsinXODP2tFz0ZtYEuw+yMgTEB58S8w8N8ueE3bzELeRB2Lt pAa5KH/2a3Ht0vZgFjAUnWcpc2/TOigSJq9IhSVWOkJU0TPlqrH4Gg9Ub8Yk6QQMzoSoD0cZ57g+ 0Z7zrDyCY+9Pevn/CR2wRfCy8BXmCe5aWAKqdMTjMS+Emu7zo20BhwEnSxxERtHY5ZCFHZ9sggXR iy5vlRuTpZKYHzUwYgWmfDcrHrno2TTjqi9bKr0VXJzrsonvwSxcZP486ntYJ7ELo24KrZ0R3cDe X/OlhcszQUcvEPcS6u5dYAQfkOKQG9jj6zKpQQCLOzcZTThj57Igvx0I9OoJA/gnepyUEeHw2qwR Fhck/uys+q0KKO6ywPlfWhusqET8Jv5BqEscPfF7UjBX1IJnMfxSkjafaRDkkKIwRn9M1ulee3AX /B+0PVdJ+nGtu+1guYDlLxRQLdO19AIZZI+Y+jPiRZ9lrQmO7QLcQVEZolwELni5SVn+t3e/ss8k kSblPbimcWNr0JSMmoHqUgqrCPucLAIWxZ3pDH408rCNGVXosNK28JOvrtEd2TK5Cu628YYgwNrB wGR4ITYRoZ9fhYKx4yR5TEISV60NpGDWzpCXuaxfXsTvBFyw6XPQdkoLLygX6zPZ3sQ9XKmldTGd e8mtH1PeeGjlh2NfQS5RqMxWSwxn3TbQ01btWlqOEtTd5yWnFuND/l/oArEeBCvxzTejTarb7n4H mRYPG/I0B50FlilKnImuKqvz2Rg8x4KgjZBl5Q/P+5f6M7dn0/4SBVrU93a+7jsVzDOMmcwncxzJ AWtIlHV0NfQCBBrgNg82FThII3KsmeE9JzVlQtL47CiHV36zj54Dgjo8qWnvuE91rg3KtZFJOzVQ TwkRRhfmBrzWqHJnrq5j1aHS/Xm5dPwE6EMZ+sCan5dDTszdQFfQc89YvkjXTPtplfxO0vSJ17TV ps1O52OY0L2tZX8ndCmN/PkQxJt7A8b/HgZepWPUufvTl5zEWLYej5MG2vPZB/HQPo80rYIoQrqq US/WMLfzzRoBkqVaj+PQAbLmv2J4XIIsOZknIYwek4Jbf66+X0Q8y4NGmfLh090nmFB0PxQvKst3 fDbRdhSP8pKW3f1hFTgQ//CG9jsfri3KN6xZ3FyQs4t7AZ8lLG/03uKfEqyakRLLC7WC+hg7wNmD mUBqmleRcG91sRlDpPYmTmxjD75WShZZgrCPLjmv8OC6qEiqtPQERvzwSn0Vae7gmUq6MB7TVrOr +eSB8HQ2FVjZLDZmigWVAsdXn9WYOIRaJ34vWhJ6zkCaQ30oAIi0geEvNEUa3Zahn+LxAa1OCFFV lXDC9UDKZEnyBk6QmiRE4xJ313EUriTwmAbkhNrOFAAkpaOj2XohR0LF5AvauTYv65o2FR0rN16a laxNve9iBfsQUZ91tl1UWmmuKaBKVF8bMK+Eo8GUBeeP3s3JZyn1A6vGW+QaQP6f8L6ztCyXzoBC p+srG0GqLDIUoVnlyEUy2lYpTPqp5gU+pSqOa/wg8Rkb5k66Rkevr2ocX2SOK1wFSfhqdnH9Akuj IHDRMQwhnq2g+iPWM9+PmY2J8t1y3dlruFD90n16qpFGvCGx5RMbSLMhsHm+fzGnWnmF6Bh6xf6p uG6gl8PCMzVmrrxRh43oW1lRfTTt3Dvw+T3YarazQFqsbK1dzl+FvgtZQi64kPfa1y8PBFhDehr2 8vs0B5MsNJcMDhSAMFnzxT58nJmaRLdfkd8xWuYvltkVImox2eShCGKjw75iSKsk8uQc7jWN+vpu UNc9URCWVLDnWdccOPZb8mM5SD1PifjJg/X+pgR4AtvoLXrO6eHF8uI78o9W/UkU+q0arNQOart8 1Z2pRF6O78pxyA6nvOGdxCEOzhjQB+UFyrN7Ls+KRX8edwG5MYS2fUVDa+seumVNOPGvXJFc1oHN 6z/cAkKjO5aGalzFbkUqTcZ83KnGNtl/ZrstHg/Iyztv0qbqPIkIA6Jyg5hRAoEckLZU7nx1MtZe jiZ5PyrtqOEXC/vhxQ4EpVEhtbL7yBvpwVGXLfFTvoIUHi9x0JreHQ35AebT2i18nDKpJ8YU5mWy SKFN7PuUR4I3C/4OAbseEE1btab8FN6ubw0I5366g50rL7HOZzTPZAF33O3M2x+M0bZIIPzbwqur thPzKKqQKwqRoLXAo3vk3iednuJ735TxdTUVx6jOVrCbgBItmBVlOjKR7wDWWx3zrTLh0EafswAz Oi/SNcDUq4/1Tb2GD4UPq40kROPJIE7JcXolasR49EGpNctJzNEqt21lh9YgFqfNRiHGH1oDCzS9 uQfSVHdioacwXRK6HAPDYfZg9h4T2yywXhq05gQYdMUgQ6fRlsoE03dSt9mVeSi8GZ5u1erhVXEB r+dqR76cfFUu7UAADHA67sVwiPJQhDIUoCp1s6BM2nlpj3NOZ9CL3YYMgauHH3FKwOZwiN+Ktsfm lALofqeaO72v1prRPi1AUd4tN3FXbFSWbQdAoQqF5T4ic0KZfmW9xyQLLs2fsfIys95K3GIR+9KK GHUjj8M6HqlTd98GfwtC6u+kIgx0JDzzSzw/emx0GjLHzgagrGwGpUJeWRevIADCAREunqU+ysYp mwMGcw/qVEXb7sYtIo6VEd95ZgiD3WFbL1OPRCnKKwiHtdFyx15jzGg1LyiALnjuWbpUtY4+V0tX wFJeaw+vWVpIsW/6WvtZDIjBUPobRx8Cq1n7I2jM3Zq5vMTu8kUMmycFXRmj5UMw8++W68oQjrPX IXK0guc96OC8b1RdR5RVkfpCO6poIddBawsaPHhLp2WpTBvOFSOWdoXf9a7izsSfVP50OJdVKgNB lk/JOp9OOqaOv60iUF4Rh19ltyhj7Mo7/jSKzatLvNQR+4kEyLl7dLTLo4ESEA1rvqTXnUUQuHAm DtHkWBbmkXxiwCesbyGW+9wA1tdMDSKu1FmrohcPmeVNUaHlnBqKYSyJxuLdKUxfA7A5LXZ7S6uF T3uIfs9ZaRX125mZ9HS5WFkKaAKdeXj3CSobOJDXP7A6OFO/8zVI6kCUrwwp11RTR5rN5WmF2KQY xyDzAv+VuFPXtgt8oycz6C+sq4onPl6hPua7/9zh8nT7uKIgtZyh32JjAHtfncMNuLc/T6Q6rhO7 6PdZ3t6t28MzpN+1l3Bu28Kh0eVIb/DB02K+Bgiv7fiSOns2e1LGDTDW2MrgWs2Ui4Lo8XOu6GRP Hva7nhyQ/c+AO/12tYH0FpWOac8ADYtuvPNset0tsVr36xV0R3O19pkS20Um6Yv2pfR88MzNGhSh Az20kBCK8pTT5yVzzKfV8FhEP53pXA5SaC+BfTQkbIHBLD0MsYxVAplRQYmiDq1S4bpsudJPHh5p LZFCLnIRnTNq33Se+J3Cpql8xwSH3qCGXKpzPOt5qnA7pgsc/xVH3vZX0fquG5jChzrrFbNt+qNS +nezW54Lps4UGkyo70Q91RD5Kt00V19i16aDBFmL5e9OZWl8j0JkjitHnGAQYYwSUHKSioEFoPxT M/0QHDDiDjPEsfEbvLuBi1kRQcf6m6DRZhf3apgQycbEvDSuPN4VPHIVIgvfYb0cDHp9JjFPuhnp h6+OrkoZbi3whPjp2JXqS0M8llaGaKeTjfsZZ83wKHA+Q5oc5ZgFpZuZDrUhRQI5LJiDSF5MBO1E QQjvUpDvTziOauDbVzPXsUTE2I7eZXTH/VgT2e099WPWLucWYWjI77sUNfNLB7xb92vu9Vl/OBJr mHE9TJ/vVQujcoWw2k1yK3C80lXITPp13OdojcEPALb/q2L8Y7IOLg2kuEvMyBLE4ucdhpdXVbuo 36wPExt96jlkdMkWpwNvHwl40bAY5sn1LgHL+I6wlgulna9wAKgUXzHNOm+oUU8h4Tdu6nx8flNi 25FfCIxhv7/dOEZ5RBjBjbY8SXSU/AGDvIrk3I1LZKI2RJzDD+BRlyvc9zi2c0eXKwXMGLzeBabN S/GFLE5iztxZ0XGiGKlQasBn3h81rntd8dHP+ZhEryOiHNyDKwGd+j0sc/oFTY5PvRf/ZFKh3CtT 6NsG7rgZ2Lp6d3JMMUIDsWb1bVjXvinYvbIfCMQlKWP2+g2lBTnorDMiUZj9D/7gxxrn02sCp8bQ KTpsycwnXgsL4spXYqTSDQyVW7f9TWz/JRt9d2/ei/wdI4nHN2mqVJpp1uz5m758RHmRRT768SA5 LBRRNrjtBTFrUESDKrxe1Uk8tNEo6AZ0g55eXyd7ZlUdkflzq6nOG3IkYNSQ1O2JSHTeU/x+ASbV PsJvjqJBRhamAvWAWSELJ08gu2Bv+PbhKdzzuYb1RezgRrIizRgB4EhC0yNzbRV9JV1t79YAdGc/ fkZ/yXgh4j6mjRLuX5/Ush9R2Qjwb2Cubx59bdA+8WZMNd+n1TBtzezoYGzq20NmBV/hUej5csvQ JcfpyjSPA+BODaVUmDYgiMKzEyqmeKhx0DFD4ox7LWTK9En5ABEijiqmF7w9GxpXeodziqBRLd56 9dbNf6xD0tqIkbqIWtdKZBMReEMUk2J5E1dtlT/+LA1nhxwndxN0kNYDlgwPrkxMTEB8ZR5cUQvw 3gnSsNGuWJeXpd28Mhz05fqxGQxooKrQCqpvCzaii0lm3n0Y50FXKYyLy8O1LfnHyu9NhG+07+Kf YJvGjnZxGmCu4lTuy0+2pVFc09QLmrhbUCA5N0KuZv/JOuZMgmMys1x3097mdyI8lT13G84T1f1T t3U/pmyUiRoR8z6UWLOhyKPt3V71l9+BERjJ5T5yFMoyst3qLvWGoTbC8CTYlv69yZ/OidCWmXrd QtGEYX2kV9eHd2SPJilgbNSty1oFuLnqJzrPQzGhpP3dvcIp1ON38ppuKEskllI3cGKe/NZF1BWS bDNFw9UyY8v6H4enMpd3v18k0lfw79SMmDuQazDfCNdlClD/3VuLur47FBP/QdwZR1vsiiNFcQXt BIZRC0Pwrf0SsbqMAeFJp5FCmukWle5M7PdoVrgE2zOY5GqytLl5RICwhDerlScVn1Za/Mg3KR7G DbFWGHwJmEGwWg1bFeV5bAgH/0629gk5mysWoAKZfU4ingP42Ba7s2ej2N3/uDHQx02otBAW+MZA U9/DpM3a8N6UjiEhWOzcRlGeFJrTKwn17GsFDcyV7T5m1rgaPS7jUaKSK0widr9GV1YZDpvw31j1 NkCW8McjL5QY9joGV7M6Ch6os3MoKph1wgTF9i+1/rAKc1nu4Lru4U6zxkhC6uJxd7OVMFUw2pCm tULL2XmkvBIWhOZ3ynAR9gFG1dQVjAlZ3ceOSUOpvgtX/68ZmtWeAoA9fA1Lme0aIEDQEpww6rzl Oq2anM2lhoSJv0tXAdX9zUbUJNkAHnToiwXbqg8Qqi6jVCL3jRRRwMDsVxx7b0eJs4Agm9Nqba8C mvGE7aTbuSVyxei4X2qcc+jp+kfy99XiQ2Zcm/WPAsTanm4OMRQnb2db51cdMt1ymwtxbVf8BwcT NffS2Db+SnzpFylBBtbP/Ha0dMtPSMgeS0pdQ8SOW+EEK8dJ9+gsCZatp4+rB/CQjgKN2qeVnPtc Ib6JdHoXu7fQlPrNg8HpQyo34xZ2VCHW4WJ6tJOeOoonh77EYAMl/j+OCO64K7OZVYRfPH2B/Hvv AA30sEAvB4XvghtRSoGKTceb6hdfvDymvUexjIHOLx16iBxoa7epbRW21BFhiJiEzZ0a3AhwvLN3 puaZr4oqQxyxIlYtuxucunAmIwRomNCHn6weQgt31inVckYQXdwBze03/LPGStGzBP+caM+6Kb2u W1j3DM+zymuZq5/9hhl5DJk76QQFTtwg8bbKg82vSftexQzZFi6GTiJVZDUEcy7J7iH4EJFrf5Fo E2zPOjH4ZzRZYe/DPjuYgJ8UZLQSMy5AwRoeVvfu0ots+5eUdLl0bgavFi7mzWxD+dHTRlIvVlX+ y74y6sQpev+pcvSrjdqTHc7ylcdZmd6GA1yL2KxfVLqevu+aBOBCAf25ymTqIm33SFFY84KADhZO FttcEjdDINYXGa9zn2rnmWMuI3pStZCizjadzJUYUI0N7i6mW2gL1hVU2EGycRG344t8Xv4RwX09 rGQK/D2b7yp0RMyhjNpwfTJ4KSJ5TpRwlVhh4qof0dALruHDSRysiFHSflfvsbDFgGQmLgBppOYJ VKbeTUVmIZTqe7R//Qq8B3uVOpx+bAzyy8lZnYKE8PIli2COeqPBs6xfUgwzKibsOVsyn/PPCswS MRqX1CGAxJbs23OC5yS8E40DT/sxKS92e7NFa4dmtBcybs+e5V0R1a7ys0XUK58Y6MOcoxs//IJ9 0c0gkb+BkF1YQ9QgnGWao0vu0i1C748mrC5r01ufgXEvRTFkx2XPOPAtsoENVyaQsyE6uUiCsfSf SFqkX9PB2s3GGVW93Kth2Rb9ktt4Q3ViOIUUBfPYBdUXeXdLCLF6oEEmHxOu/0WgDXqk7g1BJLFI 5RC6DmvrmskgXZN9vC/pXcfMjZkzykM2GisQuIZYMH/YU8qCZJEWu4kDrY/y3ZCyyMZPBtCovKXg iuIA1B+IeR20nJ9yZ6jQAIw0fb5bGr1Hnc2Q1QHcoA02+UPxTpppYAlQ1vgyJ6+CToE75lPuU7OT b5/HsoxMgDVFX9WiIUdVRByiyWNVIgaAmS1Yz0JEaLVSwjaMECMlEmpJHRmC9Eh2hUT6ECIL6UHp PRUntTUO1Qp3RXcEKAjQ5gy4ChKOujutM163lcAzI54wTWpH9Jx+v4DFpyCdsUqW/rNdjlqHek9g KPSTlFvsZrW+2n5ldM6/VEgr7pf4DEJcub6FUVIsA2R2oqr2cQXlZcQxs6iMH9j9z4+DCaLw7ia4 kZRNJQ9yQ9IhlEOl24VN5/JuTvZuKvkqfLFvdKfoqyxT7DjDK3EWDOtnMEZFuoxfNeu4LFG+3YVh baQ4mV9TdNUQc6iDNZkmd+SUD4TP8h2LoNPS1p9znY3AauAG9cAq+ZCy6kd13A/Gk18eNYyFn0VO pIqNi3aI7+CZhWPq3E9mql+n/ZWWoYgB0SzuJRUj+TlmvfeCOUKQ6kmcuC3+ITcyaG66D6J/l6ik xVuVMcHdbEwFjFnJPnqNFnto92k4cAa8+b/YIILygNwMvLCCfNfE1DvmvU86pHrrxn72oI5/grQz 1j852s57goQTQPA4jfqwBYcxE8dutKKLwyLUtxTkXy9v/SDmSiR5HjCNfGB5c7h8lhQj9Ei9PjgX W9fe18Z9snkDN4J9WGyRIAarnF+c+QWImuhtVmrDqcD7mJcruGj4W1R0b8D2Da9BJmx1O1IT0XDM kPJNo6A4Guy0DzYoFnqEyUXZWuUcxaPbtmXJ7gk2ehtWPWPpCB3H7div3l+EsYsQSmo6Cr4IoSNm KBQey/g9Y5aAUXY0SCphmilCdf7CAw17w/6pZagF1ZNceFqCJqGxwmyIizCOC0jj20v+g7cQAJk7 799pZ/LkCStd8NQeltVkWbXbhhAmEuKToEUCi6GB5O0nNpcMc7ViFiT/HzWJi/6DQMELRRCV7vK/ 2KJ4O/Wo+AYG9Ssob74xrvWXZUDaVNFlsZGZxfLRe7VTGlFxHG8vFGQaoslYLdfsPZVHFRZUi63E esGfDU30JMV0RITMBs7CLjmD/mNVURzxOr8OUwrPJ9n/DkfnKJkve1A6YBGBtLqwZBzO0iG+HzJr 9brJWwBIwcI3jgYfXPU29xcf6nQSYebCNKUzLeHUcv/79g/tbk8PpHagFEwoNfVztUxukx7LTNvW y/+00mzi4CFIyk1G6tiENu0dFK9TxDo1qMNWtU1m4bE3XyeJbJTGgKQ0yoCR62+CNySIB3SoP70y yLxe0NtdmVpRbZTQwH+7ak97Q6df9FFyVkn9RzH6ErlqPFcJSzP+iEkBJ1XI9pge5SDnVFL5Qpa3 yi2dcULOvTX8yxHZ2bVtsKj+QO9lccTYSqcJ/jGsOsT9xo3bJtNOKVIIhmB49802WWljV+WHdR3P qPnvLeXCC+c6MHIzbsmTunAF6WLlSQcQV7IjiDe9AB5KkdbvEbnGkNDzYfaAKaMQ8bVSAMHe6KlI 1gG+a9Mf7eABk579pdozN0/6aNeEHJ4xKqSYEjmfDKbazKBbgeoXWd0oaJ2cJ6briUHQ5FS4NWlL 92osKYc7y1av2zsxGOhfARNpxbMNdAKNOOtH3U4mTY2mEmoHaTPvEAyHsDmyQzzImBMROQEbOPo3 mTrlcZO//w7DU7GV0jVg+ONGDtSTuCyTgB3JVW+2yNp8uyJfGfNYCBbsKNRXu9WeqWSyVTEU8ZQ7 S8PNC/RrUFPuj1M6BZle7k0q/L2Ro2Hnwp12qXAevoHeHsLKKWmfn6UvxGRTGwrrD5/VwW3JjrGe YZvXv3RNYCbDF5H+gxITi6cn3uDu+X9QuE2uyG1cf7Lo5I8Qg4tq/hwa95jPpDzJYZrSZp90YyWR Z4olbkKEdA4yENPPAPrNwXz2dxobVH1HvP3U51HtDyQWcvnQUhSbXEfGtQUToU+W2czI4upkHO5V g5WKpWMOzK2ZYNWigVZtg2IJunZs+q+hb5OVfaFan7Kpj2AXPz+5QPkSW372iS1U3/hwrZB6ooos ms50npbCKTEMYowpBeFMzzVAaVpFUJP2gFNHDhoKA1LdbQb0LxaOUjnbQHwdYq0KzN9qs5Jgt52C xCWCcStKccuOziKvZagBvgjk3cC2FoOfSKtxdgLNA2DhJ0lNslfxHdTfusAKlyWHN9e4vO01Q+Iv ndtEDo98235/hI+FU4tKp1za1KWQT621O8VKHZsur0+jtwYBynwR3dz4HyG8c1xJRNwSbhd0m0ws c0QGcmUgbruEJHCsOUq/UxaRIBDNs0PdY0qs3kp+6srKk218tZ+OS10Oz3VYbWIZjzh9BZinj3hV BSkLrize5cOQVHMGO4cUm5bjATyU0+VpEGVcSKSDUReMvd5aYPTCQiCg89073J3gARnZodQSwoLW 3BsvDJlRYRJyOqpm1CkVeAk6ahI1gYBkoU3ZE6Bsqysc6HiJZpztCMlYxYoUcVT5u+E3o5P14MJD ffbLZjNnVZof60bhe4im2M7z8FzpZpRgRBw3DeulhFiJ3Ob86h+0Yh8ILen+1g2d4EuMizjawRLr fUwYdC88ysz6HHKCDP9ZfUQ+B6JnjXi2UqozEFyeQdwtle5FAnZmFnbweODlfZ32eqfgvf+rWuHX yZ/ElFY2qTMxW+4IC9GYx4ib5eCA+G3OPofE9DhLccawl5qwmqKiyYn6xZCFxpOP9+uMhq8rN+jo CmOWVLaITnbMuRqoEXjcPdCTThezXxSEDvZslG9HBFebiXPA6F4od9qpNE5Zbd0D8FROe14PjOgZ QQG/IuwQHs9y4WviGGxNVAtHKWU5PxYWnCSqGQvLt8sii/Q0GI/svefM40hVTa8hweTD2Zn1iw5H rFLALsC48Qe9KVXRB1xoHI2l3wnzak5NnAx6Abr1bzi9ddQ+yfHa/dqn+QQiXDFPuh+bNm4E3MUO gLMBzKVBhgp1zxjQ1PzsXHJKePcQzKj/KNPf/YdPO87ikGUPnI6No+ycebxhpxYEMWF4APIN9B0Z +eWOdSHxRWzD4Mph2grCqCtIp5DeYPADbCicFtNywYt35uAGiaZ/X4Jg/QEGR7X49N5ZcPzr5TLI HLwifwoyu3GHDnjM1oxxSopmCrBqDuOpfnoOQAAGxhmU8UxhBkSsnhxENj9wFWnn21m2KYuRj4CU huP+j7/NfWZIVqsRjXGmXvnpkqGvL+bFPOyltz1pynSi0FPfq7A20HZR6XNax9XTJUrGnK0KsPl1 MedozW2tqt6B2w/hOF0GihPjNnqb5saLN2/eyXAJz13IWRHHH41OaPN3os/UgZ1SHCFjUdq/Mg8f 2+Dqa3GaH11xdmIzv/PywHgoZ80ggoQOVfmS4FEsImbLQ0CxoD6C9Ow9QbAYBdkqotDLDzpuCtUu 64iXsUJ14HhGDEYA9VOqXxnWni+KNCV7rWmyZBerbg+vpaAX/N1OhbFzxgIZhMv9AuiKElzhjqOQ r11OSq14xO0UhUTc8t7DbYzKud6U0DswK97eyGHSAFgldTy6o/+DuKpgEUbRbO+nRVjFoc5vcFvQ ZFaeYqT5Mc8RbnQDgUwAJIYhDwnz3povv16DRzPF3cX9x7poDnWVvYHzoTH5fpx/JSFYXqGSmEaf 8UKWL294m35mOEtAf76BmPj1mvS9KXzECQvLlRmlBnd8JHvPb7KWm1M0qFkF8sCCgnZKbA0JC5Av nr4P0lM7ZCkDDXVKSZYTQCEty50CcI9UsyuXTObR8wPrF6bZHvTBDZLcykdyOidAy6w65pTolOUx 3aOyvxl4TMB3FOYpLaldjyAZd2tFrlQzjcvEhJxRi6/N6WJ6TLLR1xkp6Ma6lMMzddgQTPox2SeP RYRm8T/6KbGHUL91B+ibzbv7fkphUpgbxv8Ov/OLC/KHawK2o9gj7dTDlnOXbnej1DQ/5LIw0I1C +iXWrq4AzO2oxMp8SudDJ8ze+tfwS/Xbbe6a3VZ1RB8DH+QJ8y8JBZhh1f5EpVYf5v4mYhSNQN1X yX7Y7PpU/j7uUh995UjAXASeNpLi5HxDgJ3kYZ5Nz5F5TBaR9ACi4DxNQQ9P9SmDvU17QPDIvwr2 ZlWK2skSznPujAIIzROVUSnwF7vPzkHYM7UIHw9+vG6mwsEpq3MjYdByou6Xw/sgU90KfMDAIoba mg8GQaf6wGCu5lYIcOaCFTsWjNZZA4ojz2i85WE2AnKITutUpADydsy48ng1akIbL+7ryVOJlBsm Ed+M6O/Cx8vyvCIt/QIdGwuH7x2Dd9MW9d/HYcRTwf4mDAzVVDjMk1FaMonhux6YBUyPQBaJwamI 4Ve5pnbWkF9t2AHhJMySAPBJAip+RwHFNfX6AF1Mb3zNT9aF2BYhqV36uDOE7p+HQlrO0c4XUNp2 bt5vaM6j8/RjJAFOtW8AcsXtPMkISJHzQTMI18fbyMKcyBtwOiT7NNkqzMSfnOXjlLKKIRiSO2iy pn0o2LoNk4d+SXT2bii4ka9+QLQs6DOD2b8OO4x2k/kt+8REq6oXBfwW6qLEEExjI8J/A/n0mthz ZugKQh9MojHVDUStr6BVKHrDEj0cEChaw8MtidYOg/cw1reEgNEa8MxVDAiEuMgCNbzozQ5XFbJs MfsrYNJuTYccoVqYmd2J6pcKgCg5mlkcPi8YgLbBRO1aCmOsK6TQuXXlrQkEet8tuWPPCN6EK+uV 6hvkS5OdmWuOiKuWiWO0w/BB5hRnS/pHdgXjyMjHSPI81j5AI/Qswu/msHAuWsACRtFLLnUZfZ/Y EMHo0aGgWF51aThjmd8QzVCfyUbPgJwUreZe+7MWV/HYhO6+Em8WC6uIDGxaplgv+bFOkw8xruST 4xTMdmAXxtUMcQLeqZVodygbuqIq8YRgGSNQSzyFzQF7DbjDM7wc/+zuwIHjdJ9eE91DcUtGvPG4 C8pSpQNIjOexbo0OJLKvxLVVKl4dqrJfnAK3MRgXrtXXfluL+zxHrLQe46Db8Bj/NWGvIn+bojRl AuM7WfK4SdN14Jq1z5q5CAyooa3S/+NTnr/KLRxDWrBqF1TP0ZLNKJgLolobrZiEohzAxJ16MJK1 Nu/Oa9pfxpaEQ3Cu0wnTEARt3gkCVVPFlgK9l9uXjGCbA21UH0a6JKjhNvgqfR3OLJjKE3AaqkS2 04Ak1qcNtoqM/tuhbSKIUn0Bzom/loGOBuJpBHhOFT44jNMjb3hpQB2zgYtH5YnFGBsNsk0neNhK Goom4OYOV2bQ/k4mE+C4/AkRRb7AeX/PoSFQFLUgq0Fu6cjhq+rlfui/dBN54mnVObT/xjgWFltW tzDaRKoMykv6vz7i3XiK6HWbegrZMNwvl2+B7wIzG2Xeq7L9dtLlrq/9ZoRrH/sd2kHuU/qyqvn+ 0K8IdpWIaejO3AbMrGJq1va37OdHOv8eaogYPdos6rPBpk++IUv20AxvqGdQD2Lgybz/+TL9djgm XrSwaQhLkKo/D2I8tXi1/fpwwPt3xDdB9cabn/jYXt8rYnI/aMsPE2T3iDzXP3k3CpsY5NrbOpoA UoUK2oCPLKAQyp0403Y6om3HBSpUbcXRnq2qgumFFTWWfvXYq1PuGRYBr7WxlTsd8QKLCRHFoPF4 1yQqN6SbCn79k6PsMhDJNscgHtXNXUnani5+gl3roU2I8nA42MUAgHUL+x+aD+sqag2aS8+ljLCb jZBCDfzwvlw8rrGhBmlLilQ3tdHVrrWcSl5bpYIeGGVqUNIbFFZAQHbW3rmDCPecAzN1zxZ08Cib G9rNxnEtRpD0L+G/uGHb5HZ1cScsbL997/tvs3KbV+TTsvAkmrhLZTqH2Xktu0uIijbkvuP2HLP4 /2hbDD+0bq9nl3tuF1k6Hr4VSqBjlbnKHcQwEMaANBPy0gpMbMx39VIMGdoFyl2uHTiwRJDs75RW XVnGL6DvDUslZSBQGfwWZPIqR/yVjLSOIUyu5sYL8mOmOC/LLdUwPj/wce0MRs+8oIgpzMAF4enL aEkPRFFfnKbgKbety7k5m/G+LI3DymIhXC5ziSrBJpSt+jRRqkMfJJegVf/sPT3oP+/HPG+uv5qk BhUITdDOA2RUWpVP9sYrJJ6nrqiAlU1CCdQDLbHDRc/47x6UTcfn4E0PB8PSSw23giGmaUJ02dG/ i46qwH3LdJScdqT6+v6cZlXVyf5WCLS8xkjrca/AHfNL3oprmRC2hUEK17ZnVyZPxxRRGgGq0wGl 6AylJRSayW7eDIPuaRX0Qj2l4xBpbm7j0XNIE4lSAt7URW6jtRC1W1fKKGyUDikoxW+7EKHRFlYn PiCSmlGVzL1JQVCd/LJOXv51VYDQKdSP12BPI8Pquvzh3tx+1eBl4xKlJ9se+K2F34fBEnEYpoIE Q5QIS9IIGIx8/at2RYB3Nkn5dYwKOEV49Cc6/KYAsxgrZC6X5KrblbzTWugH5A6/tnYtgivViayr LQGhXFe1xXT7WuYRTC+m8JaPSf46DNuljHkDzVyemt63c4jd+/YutsxTbq4AY5MlO38zVrlbpZPf Hx1Ct/tqNRxvCieKMv+W2jxdXvjkg0I6h8LHjhbVCIgkjDwNPp8zaUOV2BfD/iNoFc/Y7ywoVi3H C2oj+wdPpZiVrNKMGmKr1/f1f4zHY8JuuYT0x9gv/WwFQgf7dC+OAQfb6/u6IQ74pLaMeuKNOYXn YLgJ96wag1chfesXYsbSLpP9fdRZ1R2xaj0gHk7LdXJVTLG9wwQZJ+BTuL2ao7ImAfULGCTIBjP5 Hmm4S9LUNRpln2o17gwbGU1B0p6UdhEBVlLJ53iYRf7QdkCOWR5/LU6Sc+ZZqWCp/A3j3dz4bZxV cO6wiDz8bIpVFE8X0xqisvdbJdARqKdsXHvc8Ep3PuSXCz7OR8jkUak4qlTDNk3bUOgfClVFSpSR ykiWWIC861YdeM2cG+t4tKIldOk3HT8T8naFjgEWPVhbNUeEMWhoTkf0KlTlthWGj011/H9dW8S5 CiJvyUyVPMPQnlkfl6Am04xW/hwDJgOyNrrGVH28kSOhrBIcKAJra3V6NvQvXPU3xTZAVs7MFztv mzSbdGhFsGC2NneH/SK11W0se/Sw233Y6SHl25MWdCt0n0QRqRME7WmeuY9tPBoYvklo5dmqUwJt 7VJeOxYHV/PB0ncHhDyRR82jKvy5DP2RdaL4XJNSehXgtTpmEu39ng3uXGPAYlAQR/53cmpvCFyT Q+CH4KRoFYc0DYTbdSzJnmhF0mjsLv+VswY45ObfDaJTraX2NBcwVMfj8+rmtrvGBsIuImkK4hDU wWFvf03saXj1PzCT5LqrKNBII6TaYqEtPS2LuNUBjX1P0ux3MDMOGRYl66ast69FSYiLhBVXIFSI +z5Pw8V6/hIvfvTnpp9XKKOPbaz5g8lljzDwhmbcEDrfYGNRI6wJ5wgx4s/Occz+cYNjnqNITgX0 pSEPXgNQfjDnrd2lZTZRtiIG69p/aYGFvM22zTGk5TmtogIBhL9KSherUWaHeov3KwtYrz6T4+Iv Aw5dOpPNsiydRNZnCaWl9Xcsx/e+Cf6csSqrrJspRX9/UTXnqVop8kP90nk/Kt/WsfGLZ9ul+7QK 7xZXWaU53pYGPsOR7ZITagr7OaBqSK46A+vl28FCdYtTrdUzoEE96LUi+hJdhzlzG0pocF210fT+ S+UcjV2m5HQuLAIoYBvtg6I4uKDOKn5+P03hZ0yVWmjJdMZkYGoMFTxQMSVSMU/VPV00oFdgVETp hWwolE5ip093wziPcfxT1vrfxamLyRYuYxaEx9OhR1kID8T5xJKNAW+YzB08XEWWNt2dYPjhob+d uMrtmO4Pd+f10GlhrNK+lAy/i5dimQ+XZv3UzNs8Ewfm7bVjSsSzmRHPeisTw2o2frZ1UfYwHHZ8 9iqanbJobrjpX9JaGNuZPLLe5lIx1K1Mp/HKy6TscNFCugOUHEF/MbulBG76cbKvd/Lk4PRDtlUq 86pIiu7I73GMCri4kYyFO9c77WR5nexAyW/fJFC14gDtfV1lUn4WqRmMJYfB0v3nUcqMyATGExuP vX16cqLaYTShWYiIBTYUmqwLsVsZ7Zx4ffe6ihwFUC773zAcoaKZluSc1WP3ri0160EjMAtwWjOA fhEZzKesPJgx9HDnL9gym5gFqFiWG5DSNOLO6RSLPNUG4gMEMahYYbaBLlivJPWVWdXgxpa0gmfr gI+qDOTr7I1Q0NNMrDZJUZY4YNIPm+Whbvl5u8w0GOPsUt+f3ydHSVjV+QA5gbStLmV1Fpcbbw5t qpAn3z1JANrAuku3nwBw4OOs7G2dK3uYHHHSTKMINrLfMwtrXEn1koeQ43PhE22m/fNSYkS8+LC9 tz0belOXdeun7JAX1NEVL7idxVGGizm+FD89hVRYRcR3eywSRYS6KOKqWm7cvLXbacmaOuVHrDuf jcNuYOcY+RguMpHZZ8nXhWMmznaC1xqifuQeVqY6iUWgbVrslb19RiqBJBTGPd0ZbufbdQPKrDy9 IMAeuUgsgecpDWYVJdsYQFHTrC4P+rzGwUReiufaEoCrGugDc207WmbjMidbYOEeiqIyQzaUmXgH 42Yz7bDVp0iud3ufm95Fw2AGmRipmrEinz1AccaifBf3V5dgm32NgDgDrHEJkCB5/l+bB8sDZYeI bFTxzGrvmk3XQHY4zN27SwXte1qORh+x7P/+SkwIqq3eiTWz+Nv/2HFK2ewM4E043ltW3hogbkn0 YSAjYB64x2nf5vWrvYpPwCBQDbjxwZ4arkCQhbhe5mc9V6k1O0DFjjXTDDti0soNDOrO+jTX/bVa glf8d1XPYfdh+zOENjjQJFujgNaQPObm6/tKV0xmG6Ed2k0qsXos49wU/iLg+3JTmUC0I1y9YgOV eWJ8zy+Lk82UAdm1FtJM9dDdMs9xXk2cSybNZusTxikhpahpW5gjdTZumJPJYX0GE6T0J4SkgKbL IjO0GdB3VH3/Pc7Ri1Jzz0YFem1urXS7TOxXO66ImD5Hu7KUSWmCeUei2yhlEf3WHYhXWBWIc7P2 6eNfPoRtRNoD40alUUqfdOvJ3UgfQ9W94LxkeQ6+ygRujNbXNKqoK8AY6LDU6D+yCZ7QdAEaMRjH /t8aJlf5GT5+IV600KF7udnnqkad14L/hI92zSX8I67CCzEE3Tpt4PjGCw6rq5027EVcUWEuUGp5 SFYL7ViRazTqYN8R76oC7xt01+J06nL+9kLOsLwu/fMken1/62AVomzJgqnlGnMZVHpUwgrkUcu2 oW4JL2dgq5qsuir2NyZ2xowAXI2b0uPZIO6rfZ7VJje0h9p/eQQCbCmL6/r2HtCDl/ePe/i2OxDc 7uEgROJ+vL/LnnwQCMFJ17mv0f1GxQpTX9S/5S8A4arNHStjMrT6lBlMSxOUSXqz7HTboKxrvyMs HqX0/owsUhw/nezXELFR0dl3MzWLD7GcDff1YpxSY4ZA/rOzbFJ7D1uuw8OGarMjtCZgya4eu5Vz XM3C0vaqhIFkx7V+lyXnOIryvHDQrGYxetRawPV0+PdixY5gpSE5cqp4AH5127aNMKFGvbqs9m6H PE4O5KAURnigJ84ackKdiFvW4NyDtulydLhQUZEvtnWHbJAeUeJ5zGxNR7cy01iBgb55FxqJb02s 8CcM/t/2y1YVTfjPAqpxbhSD8d7ZQb9x7n/uQWgL6VshjqzypcwcRiR1gIu2vRfoP18B3uOg4ioH KWQWGC8Db1LF+scUfMpHdw8HtSliGktQlb9IfH3zvKgXOxxUDycmV/cqH3T5ZqoDXIsSp4JKPxG3 A9s6Flnov7BkxTt7Z7dqALjMt83+UitQJwrCZ11NZrLjk///GlJQbDlX6wuWe4JjWMmtgmWRshpy D+aeRh8mN8CKGaLFEn+6zsOMfkoIzB65qQU/O9HiIJxn/uoBLcd9ZkUetGTAwNAClsjXRjDyW+vm PAsCG+G0kmjwCGHTOroQkvjzM/rklqySsMf7cTsp7AvaDFjIMMkawz69T6HPM0D47ZZjCbPZwfc5 vhZzn9X1ebNOM4UCGANtgoL6ZrzHystt4ZfOvEE+6aaeB7J6+pGyLUN11G6fTYtBlJa12FsGpopT /9lA4ZHUCg/o4qL/9VB27IQkFKa9lqrEKQIq7qXYqWqoiH20TmDCjO6olfR2QDHXaZOErJXgUweB CTXYIEfkk9rhg91y3aHhC3v9ulJ2GBRIl3RZJIFn4D2x1Eftpu2sSlxPw4jSc0kHrIPGNiLrMmhd M53oL9peq1hScTLUschtSQN5DTDDiwDih2junYVAP/gkmiAgjd2TjVUnf4WqaBf7Oab4VXBeyDv2 H3HEwYkAfr69XSX46aUv3sfln083na8I/ERtx6rAKrvhJh5umA99lvQk7Jgk3AolOYg3a9d6QgnS biUjnNUFawLaKq3Z+x5jU+f0Ne6Auonxlg9QYxmi2n5USrsjRKx5UTsH2lbtmgdU7P0pZyb3RG4Y o++1cRfmU757gd76j8MchPawkfBqRUzCTicfnhRUqZbegVX4P/Jt4jNMpqLkr82Q1HE9ry8q2mHc PX0XtqutM0BBHGemIx8a49mXE5/76F7jzpQIHPVZPN41XH3/y/Y9LMj+E9EKAQ6GXDjpz7EKNpRg X2QwJ7V8+n8r09ufnk9lS5HKtqkj9m9vCeXrPomi0QYIeWDFsJf9nNjQ2+mY6NYPr4HY5aMxNJtl l28J4zmQcNRKNzWfDP1p0+41/ZPnnnVgdZnC+n6bXfEOM6z0Ll4Sx9VeNBsTP3hBy6z4bLlK4wU6 mgMwb2DEjAuUSlxfpNNaTp8xL+UaWBoCGKe8pz/QAYX9EiurgGl/EFNe6aFaZI+La2GOBCDvYEBE TFHp/uy2e01/Z927alL0SuJ5WotemkcHtLFfQDaC8WQW2xo6weNf4onI6DBEhpiHqtf95xT9f5+F p6qf7RXTNj+wocOlFWG+5f98pNEl0fphq6nYXAsFCaeXmOENAgnatCA4d0WFY4dDec1suvxo1Rl0 2OzfxRcRRxozVVmuRszhc08yJWpn6bNtEc+1UAueS0gkQ5/ri/4cgPZhgp6lgHKawFSzFOxN+LYM CofkhfYmrSlwJhRrXyME5b3ZGULKXxeRiK+t0/M/Ngn0E9SqwsSQb85Yo+USLGw3rx+ZfxOXiGMO ssd2g/H1EjoYcoNPyQX1J9OHqqisOJ2JC5XGiRw0sF6AwnCoZ9SQ+YIgmr6VGPP925SowFEkNHE2 vofVM0y3ws9P9HbiIcxp+t0Hk4ZlguGdSiAMyWd2DWqq3O5r8kIPDT0y8kzOzkzkWW3fs22wENpR GQzNyV6DcXqvw9LWNk1szxgT6wsffxNvBsivBjecmcKH+Ew+inSp8lJWCOtHt4bH2yuwQlGZC3nk vhwT5+48GWsNyV6fWdBOIRdxf2KzZuHpKi8RrGvLFxGGJHGTsUMiQhCNSClwQRkFpXJI+QZX3QjO KmSJ5wy1oKk5BXBn6gIjm/vX6Gjayd7pkEaiyQnNyFTpR6J4dXzPqQCxWOuxc+WHxvzsTXTbUFyd NSlejmDIBm2ApjRu+Q74t8Z3WarcZyjY+Y4V1ziGxTB22JFXx3DkKQ4DhP3B691g4cNVWgKg79w4 byQfFXsyKYl1DisokGY2zfMXF7LGxtYybcBQZZsX4AaBHbv4GEg8jHQI4+ccN3wrSIP1ZAvNB3J7 71dZ5zcPhsBoGNBNKW9JLMPdXzjrvgmlwDSe6DUwpVxoJ4ptBfgjP9bPfuK+Uw0eWgvhTnpb9Dbt K7mpJRp93yYxtPSdlE4Kv+GSYzBk3Fla7W6oPc3rYR0zWJii3WB2nvqpdXSO6cxZoGI8l3PSlnjt 4ij6aPNwZqjHT8BF+dDgHwn2XOM8ybmU7B8SXAY5SCUl5e8eKUSC6TSkMP8RvTUHiIRiB5ObONwR nbi6t3Ya7Kjfb8yX3PS8bgwn+0KETTb+O+QQyiP7+CbLXL9FoJng1WQFijRRHv4HlfXfrtopWcQL 2TgCGG6PYTDOeWYiaaSrrvL3LBKihA3LqO8o9FVNpt3ErLJtrC2htJQRgawO36Etaf/wWEQcinGP U/YKRrQDm+sZuM0OsSDQnzZc3wfKj3FJCUR1nCCgJuyWwq35x9aC9DRPZUptR9qo299IqWctuWZY nLURfsZEtKfvNMenVIcGgFEOnN3nshr8rPFd4vQpplvztArzZLCHADQ75qw2xFAazxmlAaJbwjQl gFvz/Y4DOcDp6fLwIUz4e+YDuWop6MrEOrOwKPUMHyt3YATf1BNB/qNCX7EAhE043Qas+++R1x9Z BmUu7J30Nm4ZlEoPjcDuyWO9HpYCpmiSIFFkuC1G81HI1klGq1c08lxRHpZ3MTSHkh8yvUtQTp4E Xd2GAS04sqCQRc/K7DvpYyPEW2jjkWnfeGKw4FNwPJs6+DEqczfcj71LlUhIxgliGGv7mujG4obK S3KbxGqPNL/i6SaG5KxxoaoR5x3yClue81qBk5oPGpt7DVzjEHRGI4DH+BFAjD6QCCul0SkeNlq8 EKOhUYdI7X/nXLvGn+1Mb9Fp2vEVnr2ujhPdHXx4i+MBM1bf8wgsPhC+Lrk42ArcwrFcti0DSj7E ySTZQMLzY+SglZDrBWbyHKgbYsacK4GglbBfIADhjUVZGVGo5Ds9wWSzUcX555S98cmji3Sa7CSd jAVD5cghVPM92OSkQ/aS+BvZ4JMz7ndYE9AIebBGoAiRMUwUJk/ttTX37jajC3JEZwbQ05plb2ab YQR5KfWDAi/x8W2GxqJ2B0hBVUs04q650ubRb2pitGxoXRdcRNCZFjZ6DO1MT32fl/JwQ8j2Bidr 3PHh35C/7GB7b85GQ4pGThSRUetHtch1ucwmr6sZMIQigmQvoc2aOWfpXInONP9PxPjLkmGCo5/U F9hFroKY+WXwEZaCJhF5wfLleezd5vVN5eIREBTLvLSLx8ELt0IISPXnZNUiG/tLqsJOl9wGB3B3 oiJN87dtg1uN6eOsfcIcFL/UsAaq5qIt+tDZfahm2XwcHOI0n/cbPFgvszKGWJvFXpMzh4JMDQ+A OyTkc4moJeVbcry0gq/VaTA65iMy1gt9V2HWICndkBMuXsbH4Wy6HWyyMonmqLPcs9AWY/6S5Frb 2tAkxQ1rprB+OtgMi5p1x1FuJraJF4n4Rrk3xg3JMthBitT6Onlk+GHWUCfD7HH5f0MFxta49S83 QGqBR947ZoszIDi/8+p5FkFCai4ey2uY/xM7KuVLlcW4Ed+rJkus8XGHioHic7NsdbMnNrZ7Flh3 bvfrfEYt49jGszESDVfSXPJwNYYpoFjcCFXda9KtHUl3L1DZB1NobTOCJOluNt0S4oN8ZHpQpux6 gGixFYAG1XrvZVzxnWaorFuRJbXNUwQHhoVUtpmpafsalXOqGe+8BzZ9HbDS0f9Q+TofZQUFhkWx 8lijCGU/YnJpfEmufG12nJ2nGIoR6hriQbCxHGwbjAPC+KBQMxxt4mJaRiQ9iOPefaYsmI6hrkQw Ric7v2GvfoN1yabk3zM6htzcRtmc4FC3fYRiWO/Z74uy9g+ys+chHf1r2TeI5Kl0/BcN5NiRmYoq ErUmqtjdQssiP282hxr+TPLe27WFVn6TUnvfjoWjp73x2LpgCBWs7eT//ZRe5bX0Sf9/CIh+8y3t PTfY+DHxRujoJbheiqEh7LBNno87iKmS7zJoirvOUXVnmbosMz2RBqwibjX2aV/oIxBqAC2YuaEL CR7tRIt/7FncQsn8c1jnlwFsTZu7rQyaz0u4iFH68vT+xCoXX/0Q8hZENJTnm9XnIV0ynCYXoHn6 +LmWEsgyPwJtUqGqPQR9m+NTkPYjQH4fto77c4lkBmudCfzi1P9DUc8YtNdZ9sa7rzJ6IBwF03vg NMOnAlEMt+JevjEbHRfu5OyOfNspCyDwKuGbRF+yJngOdLf2+ImTBaZ2D0kzmNGDd6X5jQT11Utv 6WVNIjhPcgmSmZAj5s4/CEbkr+iFwaP6i1AVnIxdU49N4dcQQdBZ3mIQ09+zKp03ZW9HTVMJMXMu DTcuPUAu5ufsrpCGMYeKZpNBbw5p2zuLGu3AM2tZcDSIHS6MQ6OvjIrhJa8gAiGCz7SZKyUOWnS9 vf9lyeRzfN9Q/nkCYjAt9ZXe9P0x7G4MTjpyG9ELx1cgD/ViKrAIqbuoR92q4WWqvUUarsbJD72s I1ZrAWectX2WM6aDXCefMFmVZkJHDGPK7rnt3dupbj66/vxkPdM5Z8yv6T5GnCL8y9LRq+0rS046 ngl0c3ABWh4bCDbhMvw8yGtRqLfaLUtzcvWHVxeErk6dx2x4tRhF24blNFc9cLgIKgQS+j5G7H5C jlYGglSKGjVAeoBbZAuaD/y1jKgsq3dvmUWD4bEd/fdYyu6Cb+4aha49GqQL573f2CFQ6Ky1xAcz q4h17dxyVyqrwOKVbZNw11UCtDE5EKFRts43YCKsaaVBEWg6cboCVn4GgseHJCxfvRN66IWKwyqK BoPPQt7BbdTjGP9pgDBVbsn0bpvEq8L/t1TZghrfUzEJlMdm9LUdFb2ULxX62E+QZvzty1RkS/xA wCMBXgXV5dVjK/9dE+txzkt86WmshB63FeBfcXZIog7Y/tMQET9CIkcfhm6YbX6sDCfAZXq1oxq7 vFTCt/aDMF9w8/W1m5Cq99+5oLmUq/PjdhXkh2Pol9jOm5y/eh62KjJ0LagcfDp7RxNOabw5BFOq XVMJvA26+pirGLQNWtXGYs271PBRSAY4pmTXwrQcKkX0zqIFhEFYQxQACxzagIj2U2R6A2alrT+l Pz0HWOphNWuQmO4MzYyE4NYwKYjCWa9sBgwz98zqyHem9GbQ8i5r8idjDB8+q+lcwkgDHHq2aVRA 1NdvTtTU8oU51SDJwfry7WrO+2uDdzrPTek29d5Yxrbx0szJ3pJYVqp9uhObMnMm4uFLfqFZXjDt fQda4XigttsDWTKDQ4VStC/uw6OCTMw/jdXecGF/T9qqx2jRFVivwXT212IYW9n9F8XcQEDKxxgm 0hJw49gycOG66GhV5HmBM7eEL7uYCTpbMP1DLWnm0a0TMC1cbELPgZdDPtOiLWrc0roFwRHoph+u jOePVQROihfQH0W0ri+ITdhKtnAKHlasLggPc62csYHH9WlNGOvPZCh3L4aoqsegZCZm07U00Zmg pv3nxe5wwR1faCaOzAJ5nPG/c7RT8HoIeTa/4khaYAjm6y05R/U87sGqkOCQMUt4CEEYw1qYvFtU s7qgtBdHmzVMkpkR9qXMNdqLJ27p4bPC4T+SmUeCXNViRo1cVFhgtqGe+RDUIGg/8od+CelJ1Rf9 vD3lkklF+Gh6JbAwOrpHhiSvIxR3AZQK8Q98HLzlAfBqboKMo0Lz8/VFMebYAdW7vDHHCVEP6bNg dZszWm8WGAQLr3u5zncuQ586yue6sC2yeu77w2553NsuND2q6MXMwnElklmZwSKVCPsVtBzh12gb N95STwCByTv941v+rP9kut2mEvVEK8/sME8DzqVdgae4o6/Hb19z7EgpPw4fWY5hhCZqGXAijHm7 tdyrgGO0Lblx0FOuMAuRyND5HbIMCjnhkABbKhrc+/MmAGpvu4hM31ri57ZAY1/fAhrA1S8ag5CI LQhgnM1y7Tf50JtPjEMd1rmO86MoJagJlgCsvsulLyPQV54GRNSl5lfaSvz1ki+Fuz/uzDYHABHg 2k4napfQl1CdEgbGJSrmp7MhxxGMpFyBUicSIQzJVjb07abw1s62pOZgEPVmLG2Vnkfvqy3RmiQt xoJbhA/Y9dyCyJ9z7IabKxT8f4vcXSTPClWp9chC8AjcDap5z78uXArW/JmPbtzLuWK5Tm63GFwi DciA6av1SIVdRfsjhA6c83Jvb89xxVsOw6K95t5hwXW72oviMTXkKAwOJgQKuRfbCHsOVF/OMoon MIP8P6osZkfg9/83ACR82+XdsqujMwywcLbeF16lKcpGbPBHX3OkEs7soOTYQQcxgRF5Eo/RJ93E LgqQ8MxyHQ3cyP2DpiYA+tKrTb59TYmi8sV0s47ib5OgJmukP6md8tTwNeC0eAVcmftWlQz+g8aa urJ7qHwBuW87lXSiNZZsWai+pB2LVXpIQBIeuVI8ozoHQDykCftsg+D77mv0otcW9KANQlkSizKN x09+lyzfwdohzwcx454eU6KE2Ho47YKC/N+YmqvKLYcRxGtzLic38CjFfK8fCU8+tBnNsGL+FPwn eWC7rszoXuRU5JtSJjD7vRj5LnRPEltjVXnBjNWDS0FzwqS9d2TANVMXmDdcTM/Yl4Pfhuess8l9 Sx2Hl5Ugizz43C+qyzpluHHE5PTfPumiaI32m3+/9PzzEOffOOvOhlErh9ySZL1qYKuOyy3P/a+H JU0LIWKqM5JZV9YG9CBWOFlxMK+8b3748STmhOkvLTz7Jy1NXb9/vQq4hBkkUD0x22SxnM6zNAPU zWNMWXej/9MmiLj7kVBaYqU3lHYP2AArQVwtS2klZL++Ilb4kYnTFu7Chy2KLJvfPeuTGNziotu+ 6S3iTFQqvV2E2ZKvp0+WAE4VbnbuO5pAR+V0aASQ5MkJTRFJsFaBf1Ec/j5FsQHJ3SfaWok1F9fN ZqWgrWUCg8af1/O5T+VFh2TFUoL8sHr8hCq+VywCgpXCpLhWSkZqGISO9yYnrpeH7gDNCP9dZ1B6 uioHJAvFrUHuNxvbjmxbITyGqeEuimg8Yce7nXuE57rbtaNlmU74S50UdwfYeBWW91/LZfCKM9eB Yru8Z5Ve8uu/9coSVoeTdB+u9tCPdl1Q88qniigY7+HiMhyTzzmcDb2lyrOwR+qAWSoQkPUyfr/n E74pChC+c4cNBr+6NA8MKX5cqA4ME3bNqlA50vTXp2DFdEXOAxCFfuYL4wTL/ik9VMiLSSr+M5gD rfK+C4TM0xpc7jpP2mJixAkwYLpOczri5nOWaI5KbTFNRwpS6W06MzWQb/mDdW1+k2L2xvSSJLMk Q6yuKSzkKCN5ztIlfi+bzOI4BEo56Kl90X3WGwqZ9wrI+lDt/eU9cFxkJb+7X8Y8GbDA+WmRzJ4j cLre33YxtW+J17WH0dauYdMtXYwrcRpB05xbGwgDnvaII7jSYFq0U5GuzwRpVDh8BizZA4h5TaTS Em7FtxcnKOWGWpYF7iKsEx9HaYRAcwd8HtH7FJxwz+2qyInsIjTsQkKhjpaknHCXWICemisiRAnu 1FuwwHBfqOGSThtUa6vS2ginav2QvmpANe2DysE1idaBy85fp5TMDx2HcKcHtR9VVGjynytbZgK0 PzIgan9XnCL5f3za/zHy6aBPZ1c/c9ui2WlbMDGDNyNAfxptx7+M8yV9iU6S6t6k83xsMIS39W1O Bb7n6VBjTofs8Z8QYP88AJwlapjHc4GDEzqSPH+VltgYRPZpN1VD1DPtgusR0LBYpu8cVD1UDMiR 9uhn5I2EpiiNyz1zI9OTMOkWwFdRpz8dXhbKzcjr7OFzW3eRFU0VUdNBiplvL9smkXcZvx/yRDoB W5HAv30kDML4llSBe8MFVyNTSGKuweLqPzkTwvPH9kN6IOfgtC5S+mm+AEhveihx0P+Y6aZ/vDyO 8dUheRxgPNHP1HJ5MLhIsRfr0g+hjl8YvxkYVXISlzDKlsbw2a4+1ui3T/JDnxibEYX0YtnMRGGc HrNvbdivi8fhVLaT+spnT4mmsUnaxYxjpzKzjQoAnl9elgIAdxnsXBAAU2LQ43Q+vNwGL5ZqKg4I WqzV+MNi6ueK48wfCwkn/xDwAdTsWB4BKwd4UHgNelmNgTIR2E52le81lzuCBJu+gpy89vxRDiIh v/BdBlcFIF4IuZU2WMm861rJUg4Ykm7TWCqJi2Z6t7ukCMjIfYtkmBM9km5yL1LjL029pNhe7Aiy ZXE5bS6egT9bQwM/mB5NAzdK/C8m9mplalNN3V5+8WlfR9lvszA8EiCHYCrPgfHKOzqspa0tO9c+ AnFjXRS8bZ4dh22YCzCqCjiAxxVGuMX63qc0RkvaY0I5CcClXjSYN2wlmVlSTEblF16jwRXE5RWb 6DvT7oR6lb4RxV48+CIqUbGdmOi3reOkCE+Mnw+P8aYdBvHiExZHVWAeuFzFeETlCyFGQ5TkBFW+ D9O9yZTaex5iebkJgMvDEg0cQvwNr0KycVGA4mtIXZVwi10C+sZgMvOMeyU0UoXoy468pOrBIzox /NDaCAPsiH6dbsl5ALWxPAkAE3cAjFQgs0sHMghxDsHVbKFyGzTVPIcrVUyZ0iSzxO/wrm5vg1Lu uapI7YheG1mAtIjMp1c93/dnSCKzc++JyW85N9AsgOcD3KLdjLjlRVJEAZYBsmQMqnsJXmw0C7hv V+eOFoVFojyxlffO0pns6hgB/blEIOk/fmnYlXvapa4etCAQTqeLg1IeDugZfByEadSvr7U6wGTg V7hHwd7UuJMuccEcRup55z9ToixNkxlzkKv+leB+Y0TJjLLngtN9ccQnmZStCUfDqW2jj15KIpOo TMG1pycZHjNjYB0TFa+QDwvW41MyRTmsQu79ClSpOXajexMoJCnefhcnKV6579c+3BPf/LuGjsPi PiVuDCjhw89pI26hde6iw+MbzgkSLGe69LKAq35x7Rbs7IyXxHrnE+1SoDR7IcLCrRebbG/2xKfI 0wSDaBRWyoZb78nlluyJgfiiF5vnnVR4CgKbGdX7OwE0b9IeMkxELoFIuctjiAv0MrrjnEuTzf6B B9sDRBxYmAQqjJP6C7SwRH869jGf3NyAHmQRvTS4Rrubx5+pZ1c9697P3itKAQaGOt24+ncm27Gp x9tJoeiAkxyQH55v63pMtwEiIoSCjN4zW2lGclXAqX/iMmn8M84YYw8snM3gajmjioFnCdDV831Z rlAhGdK0l0ckq5b+khrpYICIad/H+TLtwPZUsnI3sOcWV5Bd7+djtLGZqQcFkOakrWwOJ33aompf Q3rIoXDsJlb/pMh/G6fqMhQVL1qTnPuDOA8uml8fIXWnYf9NFCiLafhwWItT31eAk3qOn5rs8gRp gcDbq1FQtwEhZFIQSV3ZnGOcHc6Jr8MablonMP7ehKM3IjgWJ7E5nR7WM3fnr73DwwyaH/qsn8aA 6wLtvCB2xY5d+W3ie+rVW/zt+UiUqR/Z5CURpEJ4FRiQMmvPHqEJCU5rxc6pTbCZSOFXsP/1ZEFB 5yAeB/J27g1oTZ1qazhii/3+YvOFryBYwyA9dUURQu9xHSkfG6tRsW7a6xtFipHOM2+csq2Q7r9/ iE5ReDHWWLqTSm3Qatz9ZcxnAfMsYSJBYXXTIcXjmp1wXuq91ZZmmriGYJzg45ZwKb8HHqXVWiVf vShjyBfX1uTO1L8YG6ArOaYlPEDIKHDF8t397bdCg2FN4M4mMEqvTnUPM1Pi4UAWrs1OodCP/sxP bLbbp8DilqhOZfNm/4y8XEjjtvetM2VLA0CacME+Uzux1rqdIJ22O9E/YLgwBue5NtWKYVVal8He +nMbCgA/o7ubmttOejDaf4zAy83v44kaXidVBAvFrltwFQJQgdAeC6Eh6+8Gnu8CT617MvOYMweL l+weJd6r91PQI5sosWMRfjq/Lzit2LnqIbRcBgm24BsVCK2Uaz7DKVCwaj3smhahJkdvm+5AhGXa 2yh40Me0KET9jvdMUFvjiYf5u9LoE3/32ZrMOTaxHkkWpozkK/fp2ZzLZNLwXkVvh8jRDqVhgFCo D0E82JEm/roP6O+DrBGGI84+RXQLlbclAX1FM+m+UB20NrYCZZ+NlsOUDxVNGMunrpIGf6kv+DN6 Dwhhg1crFyQ+TSpT/tmhQzwZ/yLtQo9zu/VjXraHL4lDea5/fN6oUZ3fprV0mh24MOQU6133gdia l4sIHrywVf0uj/dOzpntnD/156lFiIZIV8rpLYYMEHs+nAW/BZu8K0WNAmve82Em7EhLmZF6bJjz eqZaQ7NzqRR+OHCwVxIcznHpOJ4k2haxl40Ep7LTLVNSGRfu35M+4/oYDt3akyu2EVNQs21jMNzu epZNsZh4+WLcmmgnY+aZ8AiXvAQJEOjYl9ZbwwAoCu1RE/VebdNuj/u1UlFIk0xx/BmRVy6NV8IY eeetU59nrHnY4pyvrokpVDCuieufge3J/NcDHVD4i1jdgxHCF9cZYRaJvz7/l0wh5SWnKBTlOkgm 6HsHkAW7EUmeNXbBIunhniyv6PzaHCwaBOZnUuh6zsiDvwib61TO+8HwpNmkfvE0n7OcZNqq6wov TuZxZcpn6rPkbt9nqsM314B9LLailTlt5SqMiaA+H/8oz7R9++1nBWCHKoKCRouNLB73fUuz6XjW 2yeoBd+L44TOnC0bjzKFCf97vmnqv8flFHqdY02CQSp7zDtbFwSGQJk7kizxOfcw5opDdGCMVHv5 BoBUuXAiWM5OrMZ1bomG2TEm7FSFBAuiYdCa0VmjGK8qT0S5C12cDUpuKzTzhvjPeHiEKqD8pNHW eARfC8J1OGOg+2yo0Qjbi0LlJc79Rlx5xPzMwhF7poqb3wmLBgCiG+ZmyUlZWpsC6KKO8KPPvl/0 ZQPM49usFVTRodlOhwvrhSn1kjKHMjGPtLBwm0KKZb/DGsBypFuSGWbErnhLY9Z7Ye79xWDCpDw3 VaCSn4ev2xDkpCuJPJdqzSXymMeswrpwLC5PzposIgFmYXlxaOf3sCb48MUXWNUr5py6osTNAGCt 2oTucI0Jmzpw5ElcuwAybfEfJbRPYEZBxsLzCsDKOZuoMn7Fh//ctbPVu06f//LKyTU3ZTalosaL HnSOaERf1ioYAUH9c2L3cRvMAaYc1RIw98wCgd5doi3qeAbB8chO9sMzN0rEAIJquj/0q6P1WOlR j4m8t+kB2zHuzoZM1mOY38hNgo5LKyrH9IeabMCKQZfEmjIkTeK2aD5UbsnLBGl7YaUjufpXYpoj pVq9BbVyo5CVUfFR4DUXp6o2kLCum3VO1Q+LiGzNcP6Ew1mi+iUmcf5YEOQrQhs0PMLB4copx9ic UnMVS4AlSkhF+6fy55JL9XEFzzcOyaXeG9rUzkwLsyYYeWEqhHmEsZPCDVBri10CIRcaZxmUb7zI S6+YkOvnkApqLCbwz9IC7RRdpCbK1zsR4wRAKLxtJV3LY8y+LHa7l1yXV3dhKY/ylVy7AqEVKG+Q IJ35xObyhKyoO460bdwuNi6keWpL7fYomZ/o+IY1hJw602al5VCov6mnSSIECyVyIx/KXmCM6kra unfMCPxaWOIkzAErpGaqjvvML+7yh8P/G0136WI4llrBZOYsl3v7VdMaUxXlZD1cUge7EcA1I7O0 mVfljgVS/rpK4JVR2KHjzGFCaDcheZ0X0Cqp6gXRzSoY7VPi91UUzjbBH7FevlmmLG1WawAQmDRV jx601y5n+B9t7VbsWOJ/bh/sQi0WkSjlbDPL12vbJigJSFNMHNCtlx78619pJuoq0nWrWUES7JVa 9jZE7BFFHfzhHJIMi8e3t8u0OXUFrfx/fBqsigrB8pl0EOsUmtAicie1u+NpqSSf7AP8WUxEce0R Xlg1RSlJ0E73KbzNvujDnYhwBsh9V75/JV5D7qs9XT6ojix19Co4BbFOSGSy5Bqw6BeHn9PT30oX /OEIEdB9Y6KJ1R1tGIYWOx/t9+8NkFUBO2C1lV//+4gQyeezNrF0TFmplSJw8ndi7eNp7pyG3mG2 kvodndE75f9dJM0EYd6APAtpAp73fI/gthRDS3jztO+ux+2QywuvcoJBY0z1ybW8dUB1D0n53ONa 68gJ7IGPXO1BhrDXJeZhPgJ1BQT5JcV7y0ZkMuYxDHoloLjV3gNCcBnF23T4pKNgNpJR+XLHZlcO k8Za50IxlmEOrb+2RKy7El+fowsI58lVRlEJ0bXtqk/VBUpAbj/HcJMPscfKIRyPbiaux6bAQMfz /vQ8yB9DmgzTFAhzlUAmJL2RIi6hjaFlkdSUfDmjgijslR1IF4Y07qZUB4llO3ZmzQc9j+H/h5jd hS9TzoAWbUT0yPDCO3h0O4qSDejxoal2QN1/qAh91SGzoxwRWIH/xW0gSrB0qd2W4O18QhqKu3Jk xEY/70tEaSekprpz9rTMSz4M1x4AwBxUOlwOEozZtoEwry8Q1/CY2gum5qdfEURpfNqu7lF1F0Vq 0nItZUqr2xEZPJMPWKwNl+OthNeQOYhUWoxvGLpvETv54j8DqhdRUpX9CbSH7sD1k9SzeUheKXqy KRgyQdMSaxR+jiNSuFiMokSJwwmsdXPdfZDEHMYsSenlprQnf8A96A1sI9pFLxgyHk1pYGurhuD5 AkaO75jGxMeFlGLRzdh0fI4lYkmy+HuWe1pM83uEaNL5ifh5+38qURzAuebrsjwYlz0Hp3aL6X86 eXo9jjyUTb3U/SGMmKjs01nd7cQmTOon0EDXwDn50CM96czYUCjDxUNHTZFuxD+nGysuTKD6oNYc w5EqDSJwZX8cOUPRq5djQ2MngrdfO20bM9jCK32PIjJB9TFQt64CS+UzuONO0KNRGyEoCvaiYlEH 17CG4aydg2feSMEUdhRI9pMC1i06gZxWBn+6wBsmXYuzkaiE/6ComL3FXrEF3vntOwcyOzfzUkKI 2ibR+YJwOkdO4TnWEKHAGfSTy0McuAEQPJsB3aF3EWmJOUzJ9MZLcAeLX3/QxWgEjwio1JtsMl/i vFlTk+azqeRUI1bb1iLnuKwiLDx6q/3NSoiue+a3z/FKywgNDexM3SCebjtnP8U2+KmGEC0jTgzX J+utyDR7GBXviDmWPkeM9sfQfL8YX+W8yp4zsBfzXLfe+Z4wOBeXNdw8ZvfaA2TYJ+gFWO0oKWev aGfY1yCBnHndUrzMWtLoYxdaVL8oy0W/zad8KLhHVdRwipvsghIReU0Px+tIUakzhWy4gYeG4lL4 MI/Z2TuAwMbrxtg9RZXst8Yt6UxPkxzgV55c5OreLKBN8duvwPfFRfqWEnN0louhTnjo/8QH0+I/ xR3RyoSlMXypOqg/815X6vj4BirWRLm+4ONjnUZIC+zKbRQViQzdr6gKbQiLkFQyzdyU/zoBA/bn 7DyCC5xRaI0PU51YYO4t8umeS6qHm1H9Pya3jJSVx91fWxq+UqsKh5UijggxdnF8TBzUUC3zBfrH 50FltR+Ba+eKOoZckNp2ecuorlmvF5ghNcRHSgG4nWBo2aUYvTFRb1I5a8fPZ0B/sndQTmQlQu3Q rvqi5s3SWXcVO/doSqSIT4QkyMOr0qcEtacteIotS1qvKKIkFtg92qOg8sGv8evFhRz/J7hsZFbE /H8myGoxpI/5upSjPHh6Coq2TMv26iIcbIF5HM6m4TIE9ESFb0El1Pw6xqppyxE4WAlHsN0AAHVd DeTJSAmH2TOj595/oYI+S7q7xoBPdPOkjvF2laHG/7ElKfnlQ/P2/W6Bnh2Fyhw8GKJ67ics70sq v/WMJcW9QUHe0kl2nIMwFU2IYbyHIS73BJEl1t50R7LgTJdTjTNptLhYhfz+gsT1UGb8/dEtU6Ac GKf0vYX7Vu3egtndbZbPBIsitZfMLdCuqqyjmUXegqV75h3qxUSAFtwwv8M8EYNp0NKZ8WOmm3mw EQ9wbdljIQkG0VsEHOCRq/dmLuKFRerm4dFxjymsHkzTJP4yp3RA8P5+ta0hPPJ0vBnzudkuoXm7 1VjQtxc4RifVIJtUOjiggWT/6jVl8MWZInQWtHOFR/LTOqcHuMuotNX3xquMb5OTkEfOGCudk4SA rjHAiTeYDc4uJljCdoxAloAvucU/74A+Libj74umXz/klvODNnOId3wEYddg2fKF2F3GoZCddSVM RGXIzq+zMtsO7o2rCOC1C6oUoYCKuTbEoIkehhXAZ8343PwSzqqaKbnxgpvz3v4OWoz8UK4NqOSP UfVcPHnt4VayIl0Igbvk/Jv8tguCaS3ztpRYwlR1TNtofmQmo17yNz24nUI++r/N6NvOFl0KQO/D QaP50Q5x/aHwaOETXHaju91d19c7SJFps3zwmSJTPMk8WeSOzVOGNQ5OxBL4ivTx9A/KBcH3+o5e ykdcCYRF5F30qW/MJqoktxhJLwT2809uNNVLtzYkhEUlBPbB1ktl+QR7iC0ifwI7Y1Fa+/iQvCqm PqpKyXeHiD/UXxw1cXN1klwaTfS59jP/ka5a8q4WR6+C3FNK1cV0bL+hXXgCbTuYJ0Vf2WwKYAzn BAGcqmkYPqYI9cOacAJVGcd6ps7ZlenCk+P5P1wEqcHn6jUjpFu+Wy3GyGJbPM0Sm33eTgJ+cUUf yCFm2HcPsbgSxkkmksj5EODjkvTUHqSTYvvo2M+R02p3R53ghpXZ1BcCVLQgUxtKnuXCJ0sl6ILx 7KmsFVlCgsFo1nrO0RmMFQkR0HNYi2PK877hZYrKtbpu9u52PGeihyYqTrpV463F6jucQISyWlYQ Z1qOSk7EZJH+Yvpk+TcJaS2khAay+vdSIiN5HK8NDQfYVbOi5KzBVrQdFeWQmZl+wwc8FVpGJRuR ivHk0yJzLjnkc2eMQtUNKgj0JBsVvjPX40pntQCtbD3/YZF2TUm7cP/VtpQp2zEpmsTZwO5mTdoX V0pviLF/aIhbwQY+PTxCi6yaQmrbWKqb8uHYZyjkdeMwEucDDLmvhmu194BAah0Kz+yFERH8G3iX nlqI6HRcSM5lepYx+ftrbQcfOLFIBzH1y3AuFrBRV5GfRRLz6oy1c2iwTT10Sg9rAWj09xgX33iE +NcCiLd29PSbvcNpghT/kY0Mj9Nd7qqLRlYr12EIOvfLRyHJXrm//fzZY6CAk+oDt7y6u3t6CBjQ 5FBOXAWL99N8gzHybhLZeGJ8Hv74CMz1UHBQDmTIDvWWF3la18AidXg+JZH1cBfXb6KqZTOiVGWc I5dW6WA2yy5LEcCY+AuWeZGZfILYjJmfrEYh28I897AUxSZh0207fFoJ1Ml3/7DDLU1u7/hB6Kgx MvkjFPCvOmPgl7ylTJsJFGzV3JgUxDJdrJSHu5mvQHKuEp/lP/BWA2tNdk9DZyw+1vykiSdkaano Q24ud6sI9jYGV2vr5ZKIy0kM+MTo7MOCF0kWKKlJCVB7WvOEVQCIThpftlhr7XG4mTgSUHzk27Ne v2u+7VFbpnj1++pf7rBOx6gkX+n+m66kx4KfedUMHlhkn3DY7qjh5LpqbOx8UpeBYttbDUHiYdz8 vxRDde3J+plGo971XnGJY4CY5WjTv/boVWurm/dm1FML+doW6tS9D6FUnsfAEt62wzhhOrIzMHy6 OuNbKyomd6+fm2VnWRNW32i42oIWGTrsSe7MtwrqSrrD2hD7q+GjG6xWTtPvmCmCgOrG8OtE9ac+ JIy7CB8hro5olAU7F8i/ou1g9FgjS/rzN9UE61aHQh5AbsTCKuTsDcRyrYalWYQwMPvviH3mI0Jv mJPrTl/E2K205Z5o1dMwkOhSdugZzBcRmGxA/cbzb20MqPD4DSmhvoICqgus/3EigNf7SBiV9LRO NXPk+mmZ5QE0y4N/IKui7/mhG8PEGZglw3N9vD5hxfi5e1bAEwYK8GsyYYgEAm/Tn1BA0TkERl+y Xu70hKjAgKMwXX0GJrm6Cov4lhrh86dl6Sn4o3fhOkuN9yfoNJjWN2VjuiAP0bNNDptqwVFqVdX9 YOODo51r9BzYehxRwvxOXMrm2HOU6cTqBI16dLHUPaUIcrKcOlTiQeVy39Npyu5UPq2RFS4tYOVx eI6/bIQHM+b4a3ZCKVS5rGLFcSRHDmlF2iuP74ryWkL8WaIAqUx3haB4chqDciiHmyL8KX1+OQJd VxJ+dqLQmsfkQhOy1v8HlAc0V3VrDxKYHSFD77yv54XgBsxKs21rhu3JlliON5nMjVRzy0tyapuv wp9fqhxOOC0zUO6kEi/Dk0uMgi/5Qb0n7zfTAqREXDQRWafFLdhh9kMSJz75DXugIyhgsiyJ5kIu 9Vied8RRLCvMEhbWt3w5aHglUoVUkH4DKBFFHmSF3xPeZyKtVHFkFAy36kQL5GvyB8DGnUdFKXNv eNIe4fh/BP701iTDkXM7gYzS4+N9auJxQdlro//Wxmo8RuQ3Ejo5HlmH3ahPqMAC5EoIA2fAZB5r HOskBr3Yguq8SaXCp2wNZsshn/IMmlyBh6WNlcY4Ki/FmZCq4vBw+aOdlVwFpfcy2fnyZ1QRy8WF mSXTLjHse7NLk4B4Cd3vygpJ7HX0ADv/bUcTWVOgQKCPTJJKKtftRVr/+KXQ3L/TQSjnACCn5dO3 Tp2HMHn08SWdYU3PS9+zGAXqUnWhlDdTK5aVHvYl+Utc3hk/3tIpFiSb+zzMVZRzo5xuoNQjfbpw DX6iqL7FqlaCGFGcRklIxog2ERPzUlgwR+mFJ02CgvjPCrol8gTPXOVXH7gDleLdypKUT2l7qQgB 92lYq90jfPJRXmkfvSy4D62vLsNnR0QBGIwm4jkr+P9cHIFL5+sWy+fqKPQAB2iqozi07fK1BjsH 8VZz7w2Rw1x6dcPEqvftqNylXHTQ29yvUsAXP12JoZUZ+2RvT9eEtDoF+o8urhcYif5dZp9GbWEH zhhEQvV/Vut060DZ19+UbEBLe5JTEgXTGkryvE4KFKJR2ESUw4P19Dd4EBEC3jCKmet9CC2uTGYF I5+rQ5LmJNshUn5KOGNOLyqS//YfpyuLiRVdF1mwiK07UF/YoEsUHuSGPwqbvoQmIg7D/gedKiqn OUs9yOJSlxv2kfpEDRPj4FWpJktyI0Gd4TO8SiUJ7CDsorS3aYJJPpAMoiTOwBvMEeMevhdBnrhd 6q7qvoNJd7Odcq3uhiU0XUs8pSqfH6Ak9Tb/5rw4v/NRINviGVPMHjmlPoae6Q8Q43xmsbP8ABWj aCqOt4t8GP4srPUjCD0ZkAaI6OpF+bLA95MTrNhBYlqKR9Yx3yYDtvMZIkMJxjwz3P8+t67kaRzt 1eLr+dYDcRHeN4stQu+RpfiFyVtvTCrRGpdT94RpYigNxdGjUUzEhVY9xtL9uri0JvKDI0SA0UW/ 6mRdq0yl9ihcWozK5ePfrcNBhmlyER+DwrqoGFe/AE6FwHIV/m4AdQ6tRYKHE8De3zZpN4+Pf2Xk l6qfh9uzkcylGMpEsaQqsawiUhnNrOursH7Qr6l6Qz0/q/wdBM+GB3+OQ83H33XY9n7yCb5CPSy+ 4xF+JM7YvVmQnETpZZqN0jo4zqzHfakctcj3q9oRBd7OAMcv3m46dsTIEcCpYLbhtYldu38B0Q7d oT4kfHLtGJQ8sxYbXHZs6vP9pfpKx3gR6Sk13DNzf0Ypej848KkAaoQAHjG0WgaDG/DKkNBp0s9w HsPBdR0uZFWq+sO1gzq5xlGQYoMZeo54UeYXbPZX5KMatNvqPMtPx4UAFyu7Fw43TBzssavoB8cJ AKhjWQbLFpLzj2oQvlkNwzT1KMNRawvOe1f9VONxegWPDAYgiDUS9RiBLUtTwZW7A8uuyaBOu0NW BIcLBe0/xfUUpBfRtVk+zeZobSjaTfr7HiKnZa7EF0CVS95Aw/zOP1as8EIgWUJ3rvAIrDpXFL6K 1ZtW2JdX49x1/Cfa/5LuIhP4U9CHQGHP+8H1Lm4yPVtAZm9Gj2dV3RswkWh4qL6HyDYZCWiFSxz8 C0gDbGuyqcKnVymexBeIYTRHB5g5Zli6zf6rXvjMJsF6QNnd/2Qr5s4ESMr/f57rauCXnpA2p2/b apHKvp/eIrONrcK7dy/qOrVZRV52ZaMW3WWTIYqPG5crKNbGtdgenuX0wo1KyT66/u/qDjJJy/Ni kdHrryznRwOLz+lzAwkkOD5utVFRAO4m1xEMndAZVgoRAEIymnex1kYbePNpPst3pVMoOa23pXjk W4t+FzdZO9+IUJDYkctLhm1iLoab9nEvbhF7ucZ6Kv0I/Pdx2oi9d3VQYPueIlcpJth15ap5Fvqv gfGte6mpWkK8RPxRI2OLY0KZYAJDMWUHrpZVjkYYhwV5uYxA4vJXFRcACBe9v+9wGb6Z6UtTu5t3 UMwivzonx8Z1vYfLtyp479+ko6QCwnl7k9IvvfHgPXFt1WYEKrOlurZnKSpUpy4QnJ9kZ9qyC0Dg IKzXmLCht77kp42wKILITEEgJLg7fR6Az+nXw/LgsR0t4Mte9oNxDb4zNZC9+oG6tL0lwTFNA/Xn QIU1RD5nokpfbncrN+8zPV+mO2Cn2T78flkvWPWWR/tK6G3gwiDEs4HRjwje+S5ozsPy8vx9zbWu 5kEqhywK9mzbSIwCIFUaB1Q9v3+GImd4yuA9JOIF03hN3JrSj6i1GVMU3ZjRJr9SaFL15igwh19E neW9iuySb5kjozX0liwCq+aFoG+UhOV3DDPHIAq5AaPE62fq0FZYqrx7e2yDFu2DHA3jeOw4fv8M qdCWM7ZtdlOqLg87MzAspI0ergai2uKaFYqaxeZ4RFK8TzBBA0SOMr4Q/Ts+QKjTUD+syhIgqjkk FGlrr1ahCwshR/P3w+qRchKUtG9dCoeXJ6FcxbchEOIdrFiyYOPr97zz32MEESpQwzLxPpFdHt8c dmkNc4fU3bozSwMEuWf93EN3gJs3h+ATtVY3uQiZjbOEckUNauT59RinpbIa9PldJ5Qooe+oD5Hz 7V1rE+GVTD+jfmqsyJecCOwaH0JpyxrV4/b5YjVdHtcC8X5Me7sd6NsNu/RpxtE8HilWh+ysEU8T KxedAr5NauagmbbYmgBX1m6s5tVbgdqi4k2OnVB5WMma/xtiNx9XJgOP25UKVRBD1bNLvX9FE2Ek zflgmh9hJ/KVY3hRipLmxPqdStGar/moxxBzWjUVQxEpjUJEWac3fsbzoHzScN7J0Tvabs+4VJXW lHheKQrlbhLX5HZ9rRd4WUvGRiax1zHJfEHKBfxskBHmtbDfurfNCfZqCUdy7ptt27FxyU6xD2Au LMQ3QWyYFki7ITP5k0gZqsJR+bWb2Jd0PzMzs4/VXsuBljwvKalJJRhx/GmYSj9PD9JCvAvbKQOw GEYHn+B1H95lx9RH0TP357wUAiH4C9KUMOHSL3/tN0Nd+z135a7dA5v0Oqtw4q6N15RAqy58nSNd jolBGPfvJCg3enlBQ/CDILcUkpovkWCY0krzkdzvyuMafGMX9kZNajbVExyl+precrieZwbhU4SE 2TeuuAGv77pobQiSkPAhXHqA/gjdu7tYwBDga2vgEK+05+lB6Z0c7D1X6tbRG5l0dnifD/HVeyHi qFOL7B6OXl+nm/KtyChooTtAzGqbrYqr4OKnS+wHXX0htZ/rvhohbkGdCP/SKqzlLHVevQyRezJE JmBnGbzvBXz4ofSG3UICY6ZV8walb7JgqMrchUzCUQf4dE6tIQMfedVfQp8O+D49yqY2F6aBjTvN UtTnTNeP/+EZtKTwIPe4ne0+SRu1hL9IBEFnz3ivi7mmwnUDokDY2K7tpLKJkK6nyddVo7SvpEWM +ythNe/lwe1hq1CSdKeGaCCAdI1bV+KrtJyIS9Z2Y8l0yYUMF3bpkldyeloU8LsmUSY5cHTgUdUB tRVL+yLysrLDkOJrMPp44ESF4nJE4h/2ESXYjZqW++eTiICbVafr2NDq9U2SK5M4+HV8AMbidw8a V2e0tjCiSVNmWyqFfTMw2TyUVPu8oGaphkKPjgefRcqVERuoS2LJnwWajg4BsqHT8z6zGWyaSJmn ZR4ZhNXfg7FRIFpqRJiIKmeMbpWu5QJyXDBDc8NPCeBl2tbuvVPPwl4PSArM8nP7XzQ1BqosfAxd kRKyYCIlS8LOH8izJZza3DXcuSfPfUZuu1+hMab5QvPDrcBPCpAwv2/nVz7q4tbBlwPdTU/uN0XF f37E1y9uoLS42spThIXrYSMhdrK28fEscVi9QWt4lJUvGFqBky2mpWWpw/QvLDOlkbOHUazyTtFB 9M4pUUj35G6j2k+K6mTMOJOJwXJ0OXksogtMbdYlLTHlu05TzctzriE0IFE47gkoso6ZKSoP6jgm O2QoinwQ1rWyigz8r7cOVrSyP0pmaBMz9YZrhjplQmfecsktOZ2QjXu4HH9/ViPBl3DFGwqwGf4W AA10znvxGUYEe7r6I9OuiU8b0/wvoZRP9pHisaseNadfttTgb0Bzh2Qv/7oTfdW/2aUyomSy/1fF 4D1Yt7Ciyqtlp1fUuKC4TZjkk9IdHpbKl9NiDOcJtshrZ1e7TyjC29fheBrie6nUpW+Su3UKty+x KXXx8FtqtaUVUKTeodQLP8j5ao+Pfo2fLWKMuQXRoc+siVe0fwLipeJcv6owncTjyO8a2QTWdwd8 zSv2lFaYLLKD6CnehnRfuhLvykiVb2x5R7HozcBjSRlqvVW3BmGToSPighdNj3/YKpvIoBBjzVxf dVnwD4hA1DbaQwsdpaYHfhWBRgq5co3LU14rTKDKMso9CyltvfnUZ65iqcFLRws0/+X6EpEsQp+z FrUM+J57cE/q8xWqQUYz7nJ8J6qzG+Xglqty8KNfFRXYUaFWZSBVZWLe4nrFD44Pce3Dbfr3Ea78 seJD4hbvkqrnwWCtIawTa+6LA0Jm98k1+nfvHVaJIb9v3qLIT5zVna1WKnPoIctLSH1WZMruv5+E BLyIs75XjbslL55Ej4Bb0GChtegkmTTs4Unevw+PS/C29gNQCyNH51nRXxQCj5B0Y1SVitrdr24s hoIT82XhE4c3OZH2nVwpwj2TZa7LG0wfQQPxjmbPHewgOjQ7i/o6SkoTNLB1RVzHIF2I98VR5aWv ZPTkUUo4wcqThRIQrNNTnbK5EfDivN/swaXYKKLt832Rkoj7vodHG4mVBSAqvnaqqGO3T7G3jbPr HUX7uM12d8Gdjzk06zYfnixAFdzfcK9IF+kMV5OyHZVmTXPesaQcjHdREP4AZdntwb70U1tsrhH8 bjUybv5rZ+yc05rG6u60QI6iWXpRtiKETq5ApiKzxnVKsjCeIlY6ps4XHAJk81Tk6As89zCn6Rpx iIuR7ypliuk2IersiJpQCKRhpmcHAibw7Kiy+/Oe9MhntcoSomKHC40PxfBZ7p12FK3DKkWAmpyT 3hAv8Ot9wV75ntTTRm7HZPS6yUTcVLMsJIJcWTn/w3yI9CFxicbfDFneQpgGFzbhwtK/lXZIsJGm xU7c+qbJ66nA6zie7dIzEDll+0AGpPqZQgQwYahvhBMhCmnD5F+Fit/IoDcA75ItYrJqrUS8j/jl GTOc0uZfcbN/vf9JTlVFA5E42nlndKyVC25LHNWsEl0htroFl+qSO/aDWBKrBhClrOSXKzdizQbD SUWln+/L67ENXmW9q7MiltILRRgtCmzybMjj5AxwgziCYRJJRlHNj/K7LLimjNQb0ccnBgH9N/wu b4BlnssRUWFbmqonhH7WIo6DOGtNAYfkyUrRXZO1iM5A7xhg9ohfm6QOP13VQYVV1tKKpILGunfn C/jp9vHtltGNaRuRfXYD4n3qrR7MnP5acVymSEa1Adp4FhQk9AKUjfcZNHZw/di41LBr595ziujR X7sdJPFcDBtkLx4gEqgvhVOE373p5Cj3TG8iNFwQiyWiDJZYlrVCyKuYemHXKWDdqtjHYfBLH/Gt JKnfFKVQYT0NYhBKilKH2p1sKu3OA22u+zIwPJ4jpG8kp0IV+SNFqrbH0T5P/YZgoBVJMHWvG3OO RD/l3cJ7FezkLtdemHCkfWqTbPLqtcR3BZAstsM+3lAUmRD82xahRt8GD9ZFyeTj53jR9lyR+SMO PCQx/m7k85wO+dgoTsXTUjRh4HVjvCYzL59ejQm9AtnJSPX1WnDv8wha3ZnurWFydiLybJpDtnux fEnpwGFPVSa5KjIq9DzeM//yhPlYCCa+qUUdo1WOHsieVcXSAEN0suLxSL00AFDzUhlq4TpPc3iL J0bhM/27R1QZTiIVZe/bmnzMQnVtRVzsU53F02Qb6RddOZR7abM8V/+i/zxsegEQ34r821qdp4gN 4qH6hqiP1yyDPdp2RJAd5c5//zDoZW1/gt612G6u/WP94XqSJI599qJkSQHPydBZGVikPkLWM6PU dzlgW5GkYa+iaSPyPTv/TkE8EmfHbjXKdpdDReRLj7khFlLhzB2oFKtQDBITRBDsdSaJX7RsWs7w ycqd72+4Wxp+cJMtjbHo0jHzWTuGBwQYbrnVmM+Nxfzfxq6JQpE73ru1RpMgGGjmt7Njh1s6A7/U H9tlOpEDXWi3snCjwMsUX0ak8fn2kzenYi9skxTbSiHzFF6hh0MmWJoQLWX8djxDKhFSAipiY/5U rSoAGwcQeNDj7iKgrs6QgSeTJsMNGWPCHQfaTq1/p80TXHkXi3BpBYXz0MM0lRQVN4YT/ZExoAhX pY9oFHwVWG69OLdIJz1klnb1VE4LsGakg5s++2/9hkQxBhyOpTpUpNlREsnkH+sMfDy2pGln+SVr gxRl0MdExIeujKe/e/hqQ7kaoExoXttCYeHgGlHut5xEODkUcuLx2nSj5Zlekn42vh0YlS8XMHao JD9ciD3043i0e6jbVhIaehLu2HV7/Je6Fce0+k8bjW4rY1nozjCEu5K4jo+VUtuADSuM9n3RoFJy 24VOdSC5D/+oHmnkJnhj6QhpSiwU/SlLJaTk12qlRzHG20mioYpOJlvpcEFOgMNXx+itntFk171O F9Wb2m7G1BTdJihmkcySBu2fFnSUWp0fKtNEB9Cdrowqack6lIRgZzdW70nJccFZ2DdWQJ5FZYv5 ZE50JS8U9oy6qWFJg8EK6MA5wOpu2E1Mw/syJoXAApszIzTQd+FIlkqtl7uqpWjfXUjNsS6F938L YfgYn1Y1menYg3x/ogUxE7c6L3m50nHeMRt9F8smAlDnZrD78Ivwh+9LWgWNocw+t+jgtSLWHYTv e0eAJZXaPI6VYCaMUgyVY5e9dMzXzNSfBKEY1FO7MOpdpZMADpEBsOOgqxkzs2qHOhkInsxLPWfP nkc2aymSVTHRjUHbiBigMXp6oakhcEicc1TnEXKtu3tWLczTrDpFUL53a6RSGhaEKxYdJjyn2Nqv y5FMslWrHOmjiHd3ici5V4PTOTQvzZbJoMOgVRgPogv5xRybkYbbW/rgBUMkzUiCsZk5uaLHLSwx 1Q53J1B0631jGKFOG6UDRrNCmGhBSmnFWWR7Lnm5cgBMwyTlx14htymyKJGWe6PPMZLHQ6H5h+R1 S6yUeXQaDcgyXue1b/M2UZog3L9Io3jewyFaNfNfaxdFI/7mL8Z8ggburFGH2Z3cgh1Yofo2JGJN yv+g/ALsSD8LqizcZtC9Qw+4hgB7D/0lmwo3qekhwuLI2ulLHciWkPdyDf3jUgfhQ0QESHOs7ArB E/4xVKHrkJMKXP3ioA/hgurflkKxucVqQZi6s1GNemQm5KnfauwpjCfKnGJQ4aIMteygooY4I8Rn nw+dYULyXQFnD4QHNTjopAu0BgqAfHFXB7+wG7zOgHW2zj7EEAh3sSoLnUBQ3jYuGeoFwZQ4rwUE vsGMxueWHO/u4Ft+Z0YJJzj8VQ/Ix0GgoeNgUe+1xAjvoYr/5lTBrPUJZGvappLYhXJFJ52XWZ13 Si4+8uplv5Y2B9I22+Q46m9Cqu80gr+VwOmzWAodDXow/hxoamxlLG3vmUiLldm8uK5TATut5+ma jLGat12N995YNRUzuW6fRWHQHh4H0IYpZRb/v1vx/zCqguNiEAGrzNjngTR3+LEFIhLsW1j0kYo9 EAl8aqznJEk/Rm6F2xcL1EbDXCY1Y0SfGUNMCx+uYhweaQ7mPDB/pPPGR+lkkcTZvPe12I/LG6CP scNbDqyJIuw0g6SD2FbASI8MAMi1ffo7kdVnpiOA/SkSAy/sJoIQ4Kn3z3bz/NTVO/vRUKmPNrjC DP+C+iWOCB7GVd/V5WhJklo5BMpfZvb5Xl0sd+/2mYkdxy/Kw6nm+Xy9tPSnsODzkwc+3W5rtv4u keuZZ9idJSQmAH/lI/nhbKZUBEvA/PHTPO/kO/mbhxjC5yxVyWy3hCVwNccGk72EGQyE2/BlZMUz 1mdJa9MrYo1zzxzXk6NPF0GsljSrUJaDTqvpESrs9EZW1M2EH3sw50BZqdzTLyIAu+7xwIAAnJZX qOQ5FcPIS7rw49EzVGyqHd/LAqLlVnpV2EQUj2I2xdZbT0ELF7Z/sulwosqNCUfFD5StuPptbNy+ pOyXFYy9HlM/UqSkun6hSN0ddMb/bul/pf6l+vgsheXu0HS72t+DxHAFYWqwmsxE20Y27TRSA5Gy UxS+QOuSfC/4TQF1qRpwIrSTR0Pvtczd1P1AUQUzLQ0Xo/4kc+DtnhbywM3AtFNyMxBL03xidgKD u1dO1JGw9o7Y7PK4EGdFtP+vx//7PxfBQu3d0QF0tZWlnZvUjeyRXeKjuNIPbBLdNESPaP3/r+vX awtHIYMdA+MJBLuulh4NZPbdYkUF5uCX+z7iqn2w+A0GNL2/FhSFCNtzsPUjOzJ3AMpiL0rNcuBd 9zqTTfLlVdh1SOxETiSkxMlmyUtBgnSYBd8MTVlE73fWrPVSC2lJ+p+eAffz6brP3Jza8TW49tzK eil0aRBgYaim/XBobTu1EA4cpfspyEO6d5iVSGsNoT+bwlrvlXpgSw0FHmxNTelX1+OsgtawqRqS KYaanBSI38HaIxF8s9vCbqrSepMVFZfItEc4tQaNenGH33ZgHEgzLuyO4xWiVhYhf4B85YrgAhLs hb6jbafLyu7YJkqrJyYdFpzvYyI8OpHib8FNITpd0mSUAsZmmfImzl0GUftyk2v199LtVPFc4tLM dQwdmMTC1vAtXKxTDOYcsSNScFLFO2bMfgwmoJXeXrCkStdotXeGhYCwLKPvlKQ4vmU/To988+8J GvOFGT6XiNLg5Z8W9OGPMUQVNUnz36DmMbFooOYnTZmSPJ2bcLJiYvfBVqilCG18JcEeX+AAHO9g Yve/TsM/6vG/NvL5PZtfZo1i+kQ5six1aYD0yth55wQ/lL49l9N3MR8Ab1x3/ynChmvW2KRIj6Z+ DLZGBv58naoyYplE2yy+IRB7gf+DjvIcU94DK0bMQ8QugtSLUUoELRUtGR1jJKGVgwQDkwX7H9f6 Sr4Z3xGGTH5LDarLu7lI8Lz23FVBXkIg2o2kF1JxribrYN+gy9iEfQPUzNfJbzz2BYP2G6ThjjFO dP1a1nj2w0qkCDRRvUj6+a14ZxihAvZR1IajwH9uw13g0C+wRDjxs5KgZfJ3j79NKTc+rJB3DQJ+ 7AcHL1nCZHQeKftxlr32aQKqGpyjvMNLIK9BxygDYb8VgFo8h5ZWLh21lX7srAjIzypcyvmXqfHL ELne2hgtzpKz1WvyWDVyXPsVELxZ72n7zuRdxAAOCxmlbNdSodSgdGzxljScmtmLj7xG1rb6FyKL ueb7SK70OauFOwU/fVutA9hXGmyDbND/EG5hrS83AV7Ya2fA54RxVhyBm4i9fYX6jdGBUy4ipJ9K dTB7k1gda06hiDg5nKLWVEJxEIz8KI17X6mncJH2H1evX4TQG/k6fwLM5HnyV7ZJpXkjD3mW9Puu kI2fouZAz4xHtUEoxbGQy5LGI9XG2bqCuODTVvCAlu8x7n7L7fxInkD8Phn/hNpQ3oeEOCOq3Iyo JjsJIL+obZ8+Jae32AksKZTt7BJpcoQhWSEv8YnxqjjVf/vV0BwFqYOH4lA3MsjnAJoss4aCsEBn A+ZRajsEdsgWnpbKRrua5gy1UcNh1uGweBalmXA+L2G9XzkhgX3TyoItbTNL3HNUIcf3WsLQxdUh zxifA7dEyUFkG6cLJ7sEh2j+h0ACi2/gaZ3fdCvM2CnKr1tYM7C+uHj89eJIssbphdo6pUZ37CmP 6E6WBAK2tpjESKvffFnSNwuTY7PDsMFVxQI4o7h0aQlQ9MnGS+rUcbBjMSczBy7Sp5fz3awHKTzk /dpEbovSxqIFRr9nCiQoZm3xDkxlfkzMll4AtZQ6lI8Ot7SdOhXUSfC1KQDCoIr+s7aVLH3xBeWv VNLbcMVopv81Ixb7vBUFBBL5+ABVqVv9FppAtNaIrUxfJGsMYcu81gvf8sIiqG9mmCyNkUqasnSh HM2oVaqP14AGK06oTM/ejCDMDQ1lwMF6SzBFl2dok2MpMgCXcPmfMsjRnbKZxJkpFYS+UzkK4RpU 2/Ej8Vhi/iK6pGArjp1oISV5JO0PtITq46TNUfaXClR8v0rTBya2FWMIo0mZLQM7qqDEkWt9rCtJ ruM0Eo6KsWfJ44RiXqjcpa0cDdSocOhxeBoHrfppR8mns4NJJ2K5uvtl4ECNilcKYFGIJaDAZEpR a4g/16HDriT1Gi7smOi6/hLKlbPOUpq+muUhEVexzidofwoONstBIHPDGWH+UWIZ+67dD3+h5x5i 4B2D/0nm8wP9rjVUcpK2fZGUM6CHae9Y2cLkUZjaOlX6VNFjukqj8hncefXAUHw5oG9Ub47rkbVz Pv6nqz/nxyIGE2ApvyrAGiB0Y3I7qvPaSM5vb/4Hsjd1WJM79cluiQvu0xCGnf8XtlQVitaWBi5o bghL8JsfbxdRF/cVY8Y2inguzHmbkbWqNGeF5QeUV2cE5SYfKnvSaWGkTyHDXgmf6F+IAD/dy6sd WydddH8Gk3SZc9VegPrLQKCGnxu4pmwGJ63tBwezfITwbTasQas2A46bhpU7HUPw2z2Iwfvv/mWK vIs/vfq5Kh6j+leK6pxSPNnSjC0ly/cwVRqjMlWPu1BauEYS1VbtS/CRtVnEIJbce8s5rKHRzc5Z WUKD45hsj/VP3xbACRU114r4Wqa8Hdjg4Vae67H9zNArDZJZkTZndn0D5kj2QN+5ZvlkUfFXyb72 iVvgTSvNzlIKf610DxzSJCr4cIvozzbUS8ZgNFfjxNB3RUClVc3jN6VLYDb3BQc1S0/gvfzr74RP QDhO4/1CAKn+/nTXdyn009xqn69F4Poe04G9urSLNNWVpJrXjHOY7JRwvkKbYzDErxouMh1rictU qvBf/83KUlpV4wKAjh8FYa51tw4e7F5b3qM7g+CRMaQ3IGfrTFysQtzZyYSK4OeOVcF4rp2aq7g7 9wUotCv6+bxcHXQQ2D581/WU8k6zwyJAoCsO1sxH6ZxP5pi483zEogIvcSAaOsZ0gWjXq/TJIQyE 9FRODB5TuWOxkqNcG3pxSNdPJuuuDwsXW+67puRjuDmXktZQTFZ7Z9thcdRMGN7K48Tc1qtTrHNs tgrEEL2uiHR+Blq8HPjDoo9qibxghPjt4uXNlVKkcTGA+tfPo+e0Bt6QqEh/nXsFlYdcxY9k1Lsx jRpv0qMScVqDJZhzp0QJKeZS3QekpMf9DB/I3jRNdytutVZxVTNV0UO8bJRk7Ug2eI3tDR2XYDIt 7EBeXulm9o15xpicqGncCVRP9J//iwHcff8gdcg8pCPXkNulKPtdmnHyzFsowisoYJ7WUJ9WFM3e +Rh6fXDRe/X+Eb0MTZgvO4gTkOcU9Th+0ZksQznbOpLRpHRI4bQIls0sSSJEsI+wWuer8uCLZ7be ZjmvJjgEXYEbYfWMs+NDyy4LfAetfeH3RgYc4ruu/oICwXcTZcc5YtmfRhL7bul/+UROClqlBotj +/TdTbq91sE1ftOI091x31oSa5xoCSdzujsG86exGmTL1/CZoFM1e9FUWAMsumIDKBW5e/AXYdnT 20lR1NjrKFAZvAMinKVXzDctJW3/Scksbh/RHwKbr87+HCzLFJaa0ll6mjDR9inpV0T4ii866qLp klZqLa9BeQQL6Am5yLdu4ZUt3IlI8SgrxvEHZ3W3IAdDD2mLeUsz2IuPAmXicPn+k29oMC66d0Zu 10yd3bQBhOZbY+pExz27kEGtog2Ad33lC4KMTDE4YxWoXujWUT1dfZvm7VTwF02cR2jMGUCKHPxu mGVMFoxpr05MD43j+3FMeONs41YHGqLuQydv6+SIcoAoTmOSeqk/WdnSTMxmLJPw/dl2rnwzN6g8 Nghk7LmJccnM0Wt5Q0Xsg2uknqKeFUuhPvWBH+KzMluEf1Hx2mxK+QMjN1aFZBR3Yb0fSlRk7hTN 6I4uYv4u1E4SFEhuL6Q2FqQRggoAmjMEFhbqp5M0NhM9qmeFtnI7bH8b+V3JYgEjEP3/of37urHs Q6Fvdy9xBb98W3T4ASH3zaGdW+vdpc1Vo412btc7iVv3jaN06bjKhR3XxjZgMf+/sRVBpkPZexg6 wzEZBFGGsfmd28DD/BLicr1kVg7kZUYOiA9M6YBoUvWFO7IZS4zdItRLQITNenkrCihtfRBzS6WV 1abxZLpUH52fgXOcj71cD/EnYD6UZnwHFiGD/jEkY4HBh5QGp68xy4B8qEAQu62bxk/w0WRL82o9 G6Youg2MPCv8EOMV6Ql4e6JGDeAauAPS+nSa2Ua6vPI7DbxpiFMqsQWXUIol7AeHhI6VUoGXdQWR v0jaO10Li6eLregx6fkTpKXlIJAVYmBlrpnYFQ9jMb5doePlbT74rgHRBGEN2FBwNGIQY56NFYDs gHNxez/u4RIJQaipxFhsLAFZpTRgthe+fs2HZoHSGjvxAgTzbLa7g+AaZAlA6EEjbzJRRqhhkoqc 45UhIM6blRV7UBqUSl6VtWWSE9wRaPCR+wLE9FERsq0zuTmymNKxht7cmzhdCso8RxLyDLvDlSvj +qoLPPDaY9TbOZ5loFkSs+MgeVyoO2Kkc06ysm2FyP7bFUk1+MZiYZsTXu70ycSCsPjZR+qSkuow VAH8gO5wATgdoenHG0dj9zRWa8Lu+KFw1PcqsysYYQ8dlNcXPi83i6q1LCxussuWC+SzCq48f7HS y9/k/TL3DY31kxdxKoTJQFaAJDg4RYNhH0xrHzxCItxN9WuptpEUaDm96oh/m7koCoJQMG87di7I pVowb10rTy+sfIDdVQb8uQCkmstlk58ID9PPiOt/e3ehaAQN7mlc/ArigzmvI26SAU+SMo+Sv2ZG 0PruHjHoOWIVEyTcnORDD4A61tbzoA78J8g31IBaIewUyZyP3tXFp+mlBYJgcXXFtwASRFeiISPP Xlo41Q2RZk6ZgT63MxgMKs9hx3cOFFBhxVULSGNrCIRjS4ZDgBL9TuBL2vghZlfHR5k7xVtQubW8 J932Za9fkos4AR4ncEWBfTlAy9O0vQxUDszsf8hA3TPddNbzE/86o8MiuJ5eSh9VH+2JV9npionU dQF19y1eDluearm8YvpU2OKuK/8lQrRbuu4gLN65LAW/H5/riXkWcduBUI3a6lqq1Rqk8pHWU86n T7dAFccOW2RJ++lWoGcPT2VYUMl7Jk1YD85XjhlVQ+Th38MHjMSZpIHu8tZXx9NWUjRziSN1md2u e6UtYV5wRAt0zuywMfDHQTKxSzRE6XoP4pmw9qF4c3kZUekeiBWF1Fyn1JDCdopg+JM8JAaHLNnO iBjyUp+x4ByT33MxVv/MQl/hERjUpE1M6WWASsxSEIvjmlFmVarasWxoCREYPiyihh+QG11AfmrJ mznl5bxF30ZBhFkUXjHA+H6yZA82boYCfRgNlyl23n71tK4tE++TcWGun1TqnR4ZAu2LXECMu7WA Cla48trWbFeLrzW2zeCdYtewzRjcPQ2mXOX0pzz5+hnAAHTh7ySxl/AI/51jV3Bdep2zDQw4ogdj XCIJ0EecOsFy88gi8Bjcw/07PBc3ujvoBsGVnLdLOzpVXUNWov3IChtlY+yfApd2gR8tn/aFJsW9 4WIFUqzh8iF9AyPX8IgBQRp6MqQNbw3swvxh3ObITbW1YFFm235jTyR3lZKmJLQiXiMwi6wY4SUX D/LxzmTDW5LpSsmDVdRBEH0FNjg2E8zwe0fVucjleQWtRZCo5NgS/k7+Qg8W+Gz6sqMjVPIAHKh5 e0oAv+rfIey1hgpKbSk3PlBAvuCl4vJ67U4cMmjoMvx4eCocdmcg/AVU1hWB2YTDdenKx7VnIWWZ HZye/kds00HurnQguIijzlSs3xTsgCGnXRt+H1Qvt/8jHa3TbNs/gb6qiWRcNb7/LtojBVI/LxyJ jubJvs+Y/NRyXB8neXwe4f4qXAoP12PPjJ0je0tJ/byQV0Jdmkaijc+26Hy1OxySkuV5Rg6Cvw1j MgbUJ16IrbcqItiwU7wUntdDjzjnQZCKnshkfmqA26h8Ne9vlL0qnjtxXykwtDUOIaTiHyCAaR5U hXSYkNXvW0DMC7khci/oiNeUcnDVUf5Cc2C6B9p5lusUZMerXitlQYMIUEiEU8Nu9ghL1ukmoRDo QM5/i/2ZVpD4dDzhbgJ3XJxCKzGG6km9lO/eEQDF07RY/rCeHL/xI/f7Hz1sc+inY4UqBbzxeBr3 aZP13nocOZIPMPBbmWDdNQ0CBxhfYLmZ7DfzpDvdWvxlPXbtRkVJ65zjdcGvL6AeyeaWLBcu7jLp e7aEcVpLX+jN0TKGpBThDsRD2/gOx5b2mSVE4U31WCqlocU3qDt0jdzaaU8xZw+rDSTElkTetB6q pZyN0DSPaucofNC5LzREayRsd1lZRXXCGkRUodBUCT1OxNMCcMuo4Hr9uuqkzGdHPnWgebJqRuVp rTdKzwKAwlNEqBfe5OhpB5/OiwCrB0gXUwY120AdxHkS19xZ448VpBbtCFl3vfiwndtSxoA+N0Fz HRWemiygn6DkL+BhPALvwxSmBqyS3rcy2CUoy0oSPdpZFTYORSKsh80agXWVmo8gt58rS2B57E/B eLg59GKEnAeb5HvJwRzGDKyCqMtPUkptW48+K0MwsOq7CgXk8n3FWkukI4W+RStIpK6sO1RFgj6V lOg/saTAyy7oz0Ms1U/ur6fB+QRFA/ge5jUJcYluxxjQ1T1kVU0xzGS/543ajFCYfIDtVpa/IoRA qVFH/drecIfM/P0T0cBjsPZWFqT76abhPfKezpQ8AxV5yxcnOwhvIIq3oXLOUUkk/TdzVaTHqJg/ kgvHZKGFarjW2eDja+GxSS9jNDKiLcjP1nkuL2jlzCueN0N4gOgZ5xaViOcqtwOjfzvRwrUBx2qK FDswBJJIVxas7gMmV1CPNcrHfyPnDwP89NkVaGv9ZQpGYyzRJ8PK+dPEOEU/0BqjE9GVL98H+Czz tm4Z8ND/Nmfft9OBZOAOyaQ2f0GW6PWrKIETFZE0v+qn/NVDVrEb7sRPzisplTx1c2ig5BnQVxTW FJeW2vqij+JEotbMDa77KSYBVH42+ANsDRiS6DZ2dfv9CShAXFhyrGuFmGcGwwA5+1BTGAUKLnCq CZa9DH3T4WlawWggASBPQxmNOA6Qfk8+8flYRpIlx8MYyKWWdYvyHd9ECAmNIJs8oInWmyxC1wJv 2BgR9PFPRa5vl0WvUphwSLfRaubF0/oYUIIQg+US4jKnGecohe7why0pH5+76NO/cQiPe99p1M07 +yZDKZ7rSeTcfAdAAj5UoJJ202E6bUPnbftf2QJ3XG8sv88UZ9NNGtBco5Am7dPflF/srpG4Hz5N n50128+cLfYwhEW4ax0NijY9ah6TtBWFAIOGOp/LBd/h7lIx0a26eF23cBDBN6H5iQcdIbO7du11 7aR46zeBDrmKwZHLAKltEyfw/uJeKS1Ct+Y55dxZxxjEDChUfHkKy4g2J/dJybqlx9giezuaI0II 6LI38Av0PRJTyFbM864rGmSTdFyTRps7mnHUmDv4T7t8REgeGw3CeHNK+jiklFFDoIGgfmHGkZXo x+n7E5f82O23gquub6TV9aTfEcAGUVC3dv1fcW7UqfPO03YyYBKhiAUS7SlZvOojMaa9fonr7Rgg m5i8RLWLCrUhhh6vIdPcAZS2RSXqNyRsiMZKcGzg5kqYZ03C0WGV60sX6npUGZLFghi+QktuJ/w6 J4IVWo8c2w43GL9CtC5TSpt1zEEdUOgUSwbf/UHXU4vlCd3DuyBaiI87hn2kpkORQtyXK0cXwAzi Q3X2G3WACmo0hYVBGQmTI1LJwJ4dYymnzxFwkQJgws6woo49wxNWJG+iGOAmCngYu54/k78TJOVh cHmKRGmMMrMS62Lwtbpe75BTnNOmzYyypD7IOJyZk+J3ZloG1iVvYjpIv+aEn1NHtKOJOD/az5bU /p/R/juw0T3zPriHqLUuHtD9oju5vx7a0VtqUfo80GeKdCb+LcF8qzHp2J0TEv47Jn4Xunv5o5N7 Vf/C2wBW1dqfZnkTkWCq+6i1bSqQV9R3NjY8561FLr2cN8T2dTmdvo4SqH9HHErAC30IcJ7E6izH vCq90vXFbdG3AfvkUxKxaXcgaNb+UY3qwAcC9u67zwh5+50CaReUhEaMGcVGnSDnO5iLufFfPVkd S56OFyuU0wq4GeFza5T18UGNztMEtggIOSJIcF5yKEWNW6raxuh9pPhWFSeqGuF7jLNo7EYWVVNQ egesEIi8bz4OqX1rNa4o76yStOPPIWPLZcj/FKcW45/Ch/mEFe3bd/sLeoCcoyBrx7Vbt1jfYtRH yQddhsVfOOW0755Hb1ncIM3tUe8tcE3DTBtVtiDyRGe0Nn4XQEFTX0BjqhE3Glhv1YrHOZ4Aw2WU O0cGh6JOXoM/BD3pYzIzXo2sLX4aLd9ccLfsHF+ZE0LcOBM7iMIkCsMjHWPC+X6IVCNpjfBJuYMP GAdCCqGRjtp6AJP0GnDMHLZv2CyTIWMA795v/kqBXN3tjYmAFXKnZFw5QZznUIXWLE3qk0SR1CYA dV/ErMADRVtIKzO+2wSOXBkJ5BfCatAtEG35RVAcEQJUwT1pdmowSdYMxAUIH8NOJJtsvKMOYSS0 NuGd9AQki4xV8jzqAdbe+REmzL77RJoq68Te3kznWKXIPCde5ilfsiveahgQEBjvLBI8JeynqSag 5bE2aPEFOUj8obnlqGnpsks2mIOBxs84bobozMXhSuqNQuFmEIWJ9rqr6ZDioiIMvWlmxNI8hmy8 4As1udOBkwle9gLs49HRGwAS6/ro2T67feB+I+3biSYjqpxkckVGatRl/MirlzcmOZTjDJWT8oeD TYLDi9XPDEuduReGky5DwU1AYduZKfHIJLKNAt/xB4GtCMXjHys7O6il4EABxqYh+mnoJHfEjQaN 2o6WXiVhpSdxBVhHXJMTF254TnQOH4IuSLL9tHJeZioh87NgxRSetYJcN2hCdHtFNjnEMHAAfE5T UMw3Goqj5AAMvZzYGzmms1TQjK59vONyv8WkhymfeYZu6cctKfKBaUW462cos2p4B3fN1gZdac/E yGWRncrFa+6yWCPq01alV21VZWq8sXnvp6tmlRF8MturJCVu+lyyZebOihBRCcdAJtl1W0IKWvvC jZiVO/5U39AeICY1rmIMo2wL2gogHcFY2jtgRRpW8bdbBvWGORFVK+awj3eJIibz8CN9CmdaXlE0 06BrRwBE1hgrIZcYFQ2wU6yFeGff52QBVGllFwizgHUMDg+xPpkHeAoyvbmWYa5SgpJmwjIsUlvd PTvrhEN27Q/8TFn0HYnCSqw9Qv9xxfvRAVoBjDHpBSTCz25Qn5hAuxoa00rf3DHoiEnEpYce0DAb FMIRrnpqChRPhWuLT0KuV7cyCAjciW9yRiYwV2zTL6GrQCktShojgVKu7jWibc4GvBqHS2uQ6YT+ syZhBiFJbXFO76YX0X/eRD5KYVl9olD4Jeeu6nzjN1D0mIcksOQEqQIEjQKSlCpl5VyWlbqNKCSD Y4GQQ7znjgJXSdPT+GdWhGkoOIcqdaautTXNkhB/PHWmbWPB35KnVRvB5ODW4ppyQtMW65A0MAFK h9MTBmqFg6K/00ODGNg6ymcnaISdlRtXxojOtRyAmSDysrre2LsQIJERd1I7o3/+I1LJjyVV5Taj j9ppxMKB//Q45ysSYraj0JeG/2ynPWlyM8LZQjfI4Ncp7O+EvPHvtCltWxob2S5mS9zwV5oGgACD RpUqXIXZFxT7l2n4cleJ5NNFfkfdwyRNbTRLo2IxETBErRhl0JtHjLekmQFQrkq0Um+Ph6vFYRMi 7aBN12ezWj/gZSwPpb/qdlioM+d2VGwgb9QwEdyacVOhNHc1AX6Qj2LjLzRoVhrMzhP+l5D+c0MK d4hZAQZSETtZECvMeowQ0U1WHnZcz9Pzi6yLPsBDdmSAP5m2jO2Dnmloq3KMthIY5mrDL42b1KgT tSBr4zwi6E0JI1tRXhgeAaGbFbbzAFdGSegzkxfICyAd+j++4YeVmclsV0F2AcvsQPCZ1Ee/9POk wpIcCAkXdkRT7Af8+T74AWqhc0c2SmPRcmzUJ93K1iwB6q/Ov/GN7/xTBhS9TUuSZuT0nhYVXJJ1 pMtiKgAJpBPiLHliNWMyTQko+UGch9/41CvFlpD+PfXZ1ZB0nSLcRGBLpETV2HkRST4h6QmwQpPu ErT2gN+Py45IgdX769bQDKK2cxniHKodhFu7hO9oQbr0voSPSsZrn567qg+Ubl7qvUGGTPBMK9/Y JLYEYP5VTv6QIyyJR/FBuWIOD6FtaFnreYAz3lKFZTqtuj5Pyof4N8QBezEpNyEzoOL4oduoQ0T5 GktFCBhQaFi7dkyYlJ1OA0esFhRQoPf00i5TkInerneZUJl9QhIAMF4Cd+SATW7sybAToqjCh8yu HZIij+Q7lTP3dPKPeYD7fSnmrQpzFmarYzfOGcd6wpa11hW1TyXQ+Z24OsL0dqUF35jW0RZCQY3b oUN019tSjt4jufWUwJ9yYCe7rrfjjG+nYee/Hfn2c7LT3141mGLY/C++OaoqXez1XXn7m2nR91zp qXAbIGlrXWGAXIbsLzx+dbOxTyPaIMy17HqnKXZKZo615i9iX0aBdPqgf8kZP3G9/jjEx9jzgDS2 sB5ikQZTlV1Y4P9j3LQcJ8ipYAgkN1bnQtfEzwgks7rpa1cQKM+z7avmwLTccMhk7YYl1R12AtaO ATm4hDqoatoeu2bb6jQ+eemBFZmnLLmeHs3QyJ0JBxOJYrfnjZtLLBzmkGlyWFu+SkAYYNhDZwPE aXgrPtcw/yy5mssnrf9ue5ZLuiMnoJUCknqAj5MYAt4l5B9psZ6Dij8FXU80XbCBZbgXPq2uwvsJ tVk29RxEc5ugCOe4eX4Uz66g6+hmBfRcUvHL5hbvqymixJ9tPRCAWJFABXpGFdE9ghxrJlLr3U8+ LR7B+IN6S85qMrLrQJdSPaiRH+2ZUpeuEqzqkpNE/iE5/2PW6i5DBDI0y//4tRMWepTELtQFMVyp dHAgoV4yIeryPdliklkdbpjM3e/wzotBklV/FrdaXwE0DzDETD1WG0KKAobjYQ/UDH1S5kknsMu7 oJrl0cEfKI6ytzhCst+eQ0vBsDTaUqWSVBBDCOaQzYG1aFiz8vPXXH5MXy14q7PCJnUKMoHLhR5F fhkqf5lGD+gCpmIPktgwzdJvLM0l1YV6vCrLnpnaP9xHb3ERG4L4f6UNArMYcpAKY+3EObOOEgvY Z07b5GM8Jlue666s+YmQglto8bPxZvqoJvPW1RtM9CMw8+92iow9G1zVUOXkNd5jELylipMdVQT6 a/2oE6eBP3drOWHx8lL394B8w4tTMFLqnfvIQ9TCrHmbxqE/yXt71rEJtw2GbTJVkdC4b9XG+fZY r9B3MpGPtsxJxJoFTKHMuew0VJGpoehPwEPZGV0OumH8ohsPG+xreZfdkXXTGD52Q8sbctEgrLKt sg1JWjlJPLgiCmHfKTYjd5DKeRr4BpvnygeKpO+cXX6T+llXOwYAACLNop1qHcoMqotzBwrF51zE aT3HlpRd0o7o37c+vGb5h1vjApsrxlhHIHIFR0Zbn6CvBRfILbCegZGZ7lbKr5aXgajdmPe68Bhw DQRf+4RNdxJ7qEoRrnk3VtW74td7L70fIOIk46TTtyEPbqT0Wtiir7Ukvr+2GCvPptHqfTpYgKo7 SsVjllQPWBACihTbXAS5SQId4vjrTqnPmAVu0aZmidE3WV4+06+NzR4CZVpGCDVD8ZnLmACU5rUJ hBmRinMU1KmS+Xm2StoeoqJNtVhSlRFxYJDQCDHJY86NOC2JbWIA64YBlVTrrDCDTdVxUGb+uTjC r1uRAtCsRjfKdpOsrD1qgC4aiTZrQvlOxz4anhq1oVyIAEzAt+jyzpanEXLhZEWcefuTX7ag0R8k FEbjQDpCZRAEtADU6G1i7i45gtnjWQUIf0YQMUJSROMlUPMCm0btWIEYL7fXjsF9nxs+DfILdJJ/ a3jQ0HRS400/9Hnv2uukjHsn4J6qpUVSJfv5fqDZa0IK15GQoy7R9CUsRhNk4EtYesz3rOlK/AZt UbmrtPg/F4Hzd9hfSM4OZYVCypByYphSoV7cocav84L+zQUpgDJJwRA+YqUZKtst6yWhntnupq7W TbUPnShcmikcVT6GthUDxaclgwYv/sSl18piLC+uRGjmUcbaUOxwJrARjLgfwlbKQOk9rNjfGunH 4XGZJj51sd8UtH7lDPRTfDLXmXf+PGOjIrvntlCCfiwBZfFkku6T+d7wXSVITR0B+AjpQGLXipql NTqlRRO98LxSd5S7VKxjKMp/sKPQJ0TcKG3nfw3i0+5rfY2WRA/Nh7c+HjkdBFwVNbgRr/ZTOmxL xRuOgQUF7de19s9B/rsIKn3MwQYOsp7fe+40PnWVb5bJgLTY5tXFHKLqVqNRNRzsUHPzOJKIKn1B 43/kwzG/8VsNdACCOx+2p2H1XBoQ18k+xaRSqJUjHcuHMFfVGWKarnv30KQdNUtFln9lsEQRk8UN uDEYCHbGH+PH3S7VtThgLanK0tTlrrygAEzkmN4FeVzLVZjZC658cP5mLDNPrcy8VQhlrKmrqtBr VkkzyPS8e491bhW5K16mk3oLV0sO8S8zjerjmU9+PGdVZGu0AwEPsRxDFZcHHdhDZ4eAFj0/6yBn 5A41rWwe8pHn+ZqsxHX8r8POhx7UGgkDUha3HFnPn08cwTqQqP2W38rG8LIH5WZ2M7U4e0uG0Ge8 bB6uGZRiz0GW/uudQ4KLKwh1zXSDYky7745HIsiUHXMS/LgUIs76qfwHFCG1MkqXNkv+ZebxD7kR qecBjVBRmOkRHLfCdOiWepb40feRFvrTp48zu/+jdB0Qapm8lBxIQ5D+0IlT+pAfJKSghGoiC6zr mhN6dii4gkx0lYkkprjPnRQaeC21EFOfDE973Fl2VB9iXOanOUWUacNP7K8nB1ofASidsUP5sY4x kJVJ4GTQbTiQkFwySO9HnhFu3ncTcXScUcftuFXfXyBLcdjyD+iwtfNxzn0BvDK5pAdvTjTiJmNq XebtFLH+px9fhzoc7mJwv8Z8LFXNfF46KvJ4ynO+FsnssEA08dOXN9Wqv2aUxbMD6qBcRJ4JKx5F kFipF5JLvWnfoMkQ7ZlZ/XBftoLc3i7ps/2kUaMIrXjYkP1bYJZMwKB6J/kcFNbMDaHKM5faP+Sc BIvpiIVBjTF27uMKcacRGIEzwcsyTaskapzyF3oX/Qdb5Z5Fd2eXzUXxZJZQALlN2WnISAInk2yp 4GPFFblegzua4M0CU43MdMgXnM3bYA4Zx3QEfFkCj8+ZnWCfxIA3t9pdm6zswX93D/jTp+xO3W7x lEYPJ3AE0wubvOW+7x1RUgf6rO//fbDeqbNrZm84z9ODB5zF7s1kxAwwcccTmWZpYiSuqCTHaABF xNzooSljD37whfAtght+fmAkEZFgcZJNr8H4RcbX6BvmWrkv39o0yH4SQ/d+FqbAmOWqiYViFRTe 2eeT2Er/fwlvZuaF4Uq68nP6IX/3KKGo3V4Z3qkYV3GClLEj+yEKMO+XhQwCUaImsQFb37Kvt13+ j/XqPF7+GFbpAQz5jpZ++AFiXvXOwr03hi1X9Z+y/vItuThBmF0QQIUHb91JuaNp81isiyZZM5eU O+SCxu/42IjSQJC4rF30wX9N/lQ9KoOwaFHtfG3KtlhIrZol9HjWN7DGErKQz93MR0RGfBEx9i/E k2dcVgWnAsKm2C+vlJXwUS12osgzbp7w1exb93Af1sEVBk62OxBaJ1OAAJiEbwjkiqLTQcmz2NzC YIdTIq5/fPu+fML8aHSIwFtViSeU4MnMJNvkhmkBAhWDFs1JkIfmf7/1D6WXPHOOaRbYP6R7zDTL Vr/7Rm4ATwRPQQQdPWHznNP98mIuVyKJsjfbdAzN6vZxWHUlB7X6Kq/vEgrpVBBkpD/e0brYPVDw JdjSA0ND9Uujxid7RQmQ24ZEfaknpOquq1OlHF0luWk2SXmysEupqRSuLARlRTYpkOxBZJRhc7rM FDdyHCYFGawCeQB+MFp9Cc53LFY4WQMK4c1b1opbjPCKSrIz0E01VtNFW9us4CSVmfVheD4EYEdw iyniyYWxq7RTSc8lhw0/yUNanZLMY6cxuOyKNT2vkfTtA7YTL9C1zh+aoHcvkd6XoCHl7wM6Imr3 3HYrlOBpcCFq5B1e1zvfubA4YLk= `pragma protect end_protected `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif