----------------------------------------------------------------------------------
-- Company: 
-- Creator: Ozgur Sahin, ozgur.sahin[no_spam]@desy,de
-- Engineers: Francesco Costanza, francesco.costanza[no_spam]@cern.ch 
--   			  Ozgur Sahin, ozgur.sahin[no_spam]@desy,de
-- Create Date:    17:20:52 08/14/2013 
-- Design Name: 
-- Module Name:	ngFEC_module - Behavioral 
-- Project Name:	HCAL next Generation Front End Controller
-- Target Devices:	FC7
-- Tool versions: 
-- Description: This is a bridge - translator module between I2C bus/JTAG and the server.
-- It stores the commands for ngFEC and Front End, decode them according to the protocol 
--	then execute or transfer them accordingly.
--
-- Dependencies: 
--
-- Revision:	  (ngFEC User f/w corr. version:)	Log:
-- Revision 0.01 (1.0.0)									File Created
-- Revision 0.10 (1.1.0)									BRAM
-- Revision 0.20 (1.1.1)									IPBUS slave connected to brams
-- Revision 0.30 (1.2.0)									Server - ngFEC communication
-- Revision 0.35 (1.2.0)									ChipScope
-- Revision 0.40 (1.3.0)									server - ngCCM communication 
-- Revision 0.45 (1.3.0)									ngFEC module is divided into 3 modules
-- Revision 0.50 (1.3.0)									Protocol btw server and FE modules (described in Specification of ngCCM - CCMServer Communication) is implemented.
-- Revision 0.90 (1.5.0)									Some major bug fixes - Pre release version
-- Revision 1.00 (1.6.0)									CCMServer Fast Control Commands are implemented
-- Revision 1.10 (1.6.1)									"Sleep" func. is fixed in the buffer-ngCCM com module
-- Revision 1.11 (1.6.4)									A bug in output_bytes register is fixed. Read and write buffers are limited to 1250 (*4) words (bytes)
-- Revision 1.20 (1.7.0)									server - ngCCM communication for JTAG programming with buffers is implemented (FC)
-- Revision 1.21 (2.0.1)									server - ngCCM communication for SFP+ I2C interface is implemented (FC)
-- Revision 1.23 (2.1.4)                           added partition reset
-- Revision 1.24 (2.1.5)                           added partition for BKP command
-- Revision 1.25 (2.1.6)                           improved partition reset
-- Additional Comments: 
--	
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ngFEC_pack.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity	ngFEC_module is
  Port
    ( 
      -- IPbus interface
		ipb_clk_i	:	IN		STD_LOGIC;
		ipb_reset_i	:	IN		STD_LOGIC;
		local_reset_i	:	IN		STD_LOGIC_VECTOR(no_partition-1 downto 0);
		ipb_miso		:	OUT	ipb_rbus;
		ipb_mosi		:	IN		ipb_wbus;
		ngccm_miso	:	IN		ipb_out;
		ngccm_mosi	:	OUT	ipb_in
		);
end		ngFEC_module;
architecture mostly_structural of ngFEC_module is
Component  Module_RAM 
	port( 
		clk		:	in		STD_LOGIC;
	  --Port A
		a_addr	:	in		STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		a_din		:	in		STD_LOGIC_VECTOR (31 downto 0);
		a_wr		:	in		STD_LOGIC_VECTOR (0 downto 0);
		a_dout	:	out	STD_LOGIC_VECTOR (31 downto 0);
	  --Port B
		b_addr	:	in		STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		b_din		:	in		STD_LOGIC_VECTOR (31 downto 0);
		b_wr		:	in		STD_LOGIC_VECTOR (0 downto 0);
		b_dout	:	out	STD_LOGIC_VECTOR (31 downto 0)
--		b_aout	:	out	STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0)  
		);
end Component;
component buffer_server_com
generic (
    partition	:	in		STD_LOGIC_VECTOR);
port(
		ipb_clk_i		:	in		std_logic;
		ipb_reset_i		:	in		std_logic;
		local_reset_i		:	in		std_logic;
		ram_mosi			:	in		ipb_wbus;
		ram_miso			:	out	 ipb_rbus;
		server_addr_o	:	out	STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		server_din_o	:	out	STD_LOGIC_VECTOR (31 downto 0);
		server_wr_o		:	out	STD_LOGIC_VECTOR (0 downto 0);
		server_dout		:	in		STD_LOGIC_VECTOR (31 downto 0);
		input_size		:	out		STD_LOGIC_VECTOR (31 downto 0);
		output_size		:	in		STD_LOGIC_VECTOR (31 downto 0);
		control_reg		:	out		STD_LOGIC_VECTOR (31 downto 0);
		status_reg		:	in		STD_LOGIC_VECTOR (31 downto 0);
		ngccm_state_o  :	out 	state
);
end component;
component buffer_ngccm_com
port(
		ipb_clk_i	:	in		std_logic;
		ipb_reset_i	:	in		std_logic;
		ngccm_addr	:	out	STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		ngccm_din	:	out	STD_LOGIC_VECTOR (31 downto 0);
		ngccm_wr		:	out	STD_LOGIC_VECTOR (0 downto 0);
		ngccm_dout	:	in		STD_LOGIC_VECTOR (31 downto 0);
--		ngccm_aout	:	in		std_logic_vector (BRAM_WORD_SIZE downto 0);		
		input_size	:	in		STD_LOGIC_VECTOR (31 downto 0);
		output_size	:	out	STD_LOGIC_VECTOR (31 downto 0);
		status_reg	:	out	STD_LOGIC_VECTOR (31 downto 0);
		ngccm_state :	in		state;
		ngccm_miso	:	in		ipb_rbus;
		ngccm_mosi	:	out	ipb_wbus;
		partition	:	in		STD_LOGIC_VECTOR (4 downto 0)
);
end component;
component buffer_ngccm_jtag_com
port(
		ipb_clk_i	:	in		std_logic;
		ipb_reset_i	:	in		std_logic;
		ngccm_addr	:	out	STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		ngccm_din	:	out	STD_LOGIC_VECTOR (31 downto 0);
		ngccm_wr		:	out	STD_LOGIC_VECTOR (0 downto 0);
		ngccm_dout	:	in		STD_LOGIC_VECTOR (31 downto 0);
		input_size	:	in		STD_LOGIC_VECTOR (31 downto 0);
		output_size	:	out	STD_LOGIC_VECTOR (31 downto 0);
		status_reg	:	out	STD_LOGIC_VECTOR (31 downto 0);
		ngccm_state :	in		state;
		ngccm_miso	:	in		ipb_rbus;
		ngccm_mosi	:	out	ipb_wbus
);
end component;
signal	control_reg,input_size,output_size,ref_state,status_reg	:	ram_register ;
signal	finish_bit												:	std_logic_vector (no_partition-1 downto 0) := (others => '0');	
signal	server, ngCCM															:	block_ram	:= (others => init_block_ram);
signal	ngccm_state																:	block_state;
signal	ram_miso																	:	ipb_out	:= (others=>init_ipb_rbus);
begin
process(ipb_mosi,ram_miso)
	variable s : std_logic_vector(4 downto 0);
begin
	s := ipb_mosi.ipb_addr(26)&ipb_mosi.ipb_addr(19 downto 16);
	case s is
		when "00000" =>  ipb_miso	<= ram_miso(0);
		when "00001" =>  ipb_miso	<= ram_miso(1);
		when "00010" =>  ipb_miso	<= ram_miso(2);
		when "00011" =>  ipb_miso	<= ram_miso(3);
		when "00100" =>  ipb_miso	<= ram_miso(4);
		when "00101" =>  ipb_miso	<= ram_miso(5);
		when "00110" =>  ipb_miso	<= ram_miso(6);
		when "00111" =>  ipb_miso	<= ram_miso(7);
		when "01000" =>  ipb_miso	<= ram_miso(8);
		when "01001" =>  ipb_miso	<= ram_miso(9);
		when "01010" =>  ipb_miso	<= ram_miso(10);
		when "01011" =>  ipb_miso	<= ram_miso(11);
		when "01111" =>  ipb_miso	<= ram_miso(12);
		when "11111" =>  ipb_miso	<= ram_miso(13);
		when others =>  ipb_miso	<= init_ipb_rbus;
	end case;
end process;
bram_array : for partition in 0 to no_partition-1 generate
	begin
			RAM: Module_RAM 
				Port map(
					clk    => ipb_clk_i,
					a_addr	=>	server(partition).ram_addr,
					a_din		=> server(partition).ram_datain,
					a_wr     =>	server(partition).ram_wr,
					a_dout	=>	server(partition).ram_dataout,
					--Port B
					b_addr	=> ngCCM(partition).ram_addr,
					b_din		=>	ngCCM(partition).ram_datain,
					b_wr		=>	ngCCM(partition).ram_wr,
					b_dout	=>	ngCCM(partition).ram_dataout
					);
			buffer_server: buffer_server_com
				 generic map( partition      => part(partition))
				 port map(
					ipb_clk_i		=>	ipb_clk_i,
					ipb_reset_i		=>	ipb_reset_i,
					local_reset_i => local_reset_i(partition),
					ram_mosi			=>	ipb_mosi,
					ram_miso			=>	ram_miso(partition),
					server_addr_o	=>	server(partition).ram_addr,
					server_din_o	=> server(partition).ram_datain,
					server_wr_o		=>	server(partition).ram_wr,
					server_dout		=>	server(partition).ram_dataout,
					input_size		=>	input_size(partition),
					output_size		=>	output_size(partition),
					control_reg		=>	control_reg(partition),
					ngccm_state_o 	=> ngccm_state(partition),
					status_reg 		=>	status_reg(partition)); 
end generate bram_array;

i2c_comm_gen : for partition in 0 to kNUM_I2C_BUSSES-1 generate
begin		
	--ipbus read and write to buffers		
	buffer_ngccm:buffer_ngccm_com
		port map( 
			ipb_clk_i		=>	ipb_clk_i,
			ipb_reset_i		=>	ipb_reset_i,
			input_size		=>	input_size(partition),
			output_size		=>	output_size(partition),
			status_reg 		=>	status_reg(partition),
			ngccm_addr		=>	ngccm(partition).ram_addr,
			ngccm_din		=> ngccm(partition).ram_datain,
			ngccm_wr			=>	ngccm(partition).ram_wr,
			ngccm_dout		=>	ngccm(partition).ram_dataout,
--			ngccm_aout		=>	ngccm(partition).ram_addrout,
			ngccm_state 	=> ngccm_state(partition),
			ngccm_miso		=> ngccm_miso(partition),
			ngccm_mosi		=> ngccm_mosi(partition),
			partition		=> part(partition));

end generate i2c_comm_gen;

---- JTAG bugger communication
buffer_ngccm_jtag:buffer_ngccm_jtag_com
		port map( 
			ipb_clk_i		=>	ipb_clk_i,
			ipb_reset_i		=>	ipb_reset_i,
			input_size		=>	input_size(JTAG_PARTITION),
			output_size		=>	output_size(JTAG_PARTITION),
			status_reg 		=>	status_reg(JTAG_PARTITION),
			ngccm_addr		=>	ngccm(JTAG_PARTITION).ram_addr,
			ngccm_din		=> ngccm(JTAG_PARTITION).ram_datain,
			ngccm_wr			=>	ngccm(JTAG_PARTITION).ram_wr,
			ngccm_dout		=>	ngccm(JTAG_PARTITION).ram_dataout,
--			ngccm_aout		=>	ngccm(JTAG_PARTITION).ram_addrout,
			ngccm_state 	=> ngccm_state(JTAG_PARTITION),
			ngccm_miso		=> ngccm_miso(JTAG_PARTITION),
			ngccm_mosi		=> ngccm_mosi(JTAG_PARTITION));
			
---- BKP commands, ipbus read and write to buffers		
	bkp_buffer_ngccm:buffer_ngccm_com
		port map( 
			ipb_clk_i		=>	ipb_clk_i,
			ipb_reset_i		=>	ipb_reset_i,
			input_size		=>	input_size(BKP_PARTITION),
			output_size		=>	output_size(BKP_PARTITION),
			status_reg 		=>	status_reg(BKP_PARTITION),
			ngccm_addr		=>	ngccm(BKP_PARTITION).ram_addr,
			ngccm_din		=> ngccm(BKP_PARTITION).ram_datain,
			ngccm_wr			=>	ngccm(BKP_PARTITION).ram_wr,
			ngccm_dout		=>	ngccm(BKP_PARTITION).ram_dataout,
--			ngccm_aout		=>	ngccm(BKP_PARTITION).ram_addrout,
			ngccm_state 	=> ngccm_state(BKP_PARTITION),
			ngccm_miso		=> ngccm_miso(BKP_PARTITION),
			ngccm_mosi		=> ngccm_mosi(BKP_PARTITION),
			partition		=> part(BKP_PARTITION));			
			
end mostly_structural;