--                              -*- Mode: VHDL -*-
-------------------------------------------------------------------------------
-- Title      : Block RAM for storage of JTAG commands and results.
-- Project    : 
-------------------------------------------------------------------------------
-- File       : jtagBram.vhd
-- Author     : Stephen Goadhouse  <sgoadhouse@virginia.edu>
-- Company    : Univ. of Virginia, Physics Dept.
-- Created    : 2012-04-17
-- Last update: 2012-06-22
-- Platform   : 
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: This is a simple Block RAM implementation for storage of
--              commands to the JTAG master and results from the JTAG master.
--              This code mainly comes from Andreas Weschenfelder's
--              jtag_master project on OpenCores.org.
--                  link: http://opencores.org/project,jtag_master
--              Originally started with Andreas' JTAG master but eventually
--              decided that need to start from scratch. Only this Block RAM
--              code remains from his project.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Ver  Author  	Description
-- 2012-04-26  0.1  GOADHOUSE	Created from Andreas Weschenfelder's jtag_master
-- 2012-06-22  1.0  GOADHOUSE	Released
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
--    Original Copyright notice from JTAG_Master:
--    
--    JTAG_Master is free software: you can redistribute it and/or modify
--    it under the terms of the GNU General Public License as published by
--    the Free Software Foundation, either version 3 of the License, or
--    (at your option) any later version.
--
--    JTAG_Master is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with JTAG_Master.  If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY RAM IS
  GENERIC (
    gADDR_BITS : NATURAL := 10;
    gDATA_BITS : NATURAL := 8
    );
  PORT (clk    : IN  STD_LOGIC;
         Write : IN  STD_LOGIC;
         Awr   : IN  STD_LOGIC_VECTOR (gADDR_BITS-1 DOWNTO 0);
         Ard   : IN  STD_LOGIC_VECTOR (gADDR_BITS-1 DOWNTO 0);
         Din   : IN  STD_LOGIC_VECTOR (gDATA_BITS-1 DOWNTO 0);
         Dout  : OUT STD_LOGIC_VECTOR (gDATA_BITS-1 DOWNTO 0)
         );
END RAM;

ARCHITECTURE BlockRAM OF RAM IS
  TYPE   speicher IS ARRAY(0 TO (2**gADDR_BITS)-1) OF STD_LOGIC_VECTOR(gDATA_BITS-1 DOWNTO 0);

  -- SDG: May want to remove the initialization for synthesis but it is useful for now for simulation
  SIGNAL memory : speicher := (
    0 => std_logic_vector(to_unsigned(165,gDATA_BITS)),        -- 165 = x"A5"
    1 => std_logic_vector(to_unsigned(255,gDATA_BITS)),        -- 255 = x"FF"
    others => std_logic_vector(to_unsigned(165,gDATA_BITS)));  -- 165 = x"A5"
  
BEGIN

  PROCESS
  BEGIN
    WAIT UNTIL rising_edge(CLK);
    IF (Write = '1') THEN
      memory(to_integer(UNSIGNED(Awr))) <= Din;
    END IF;
    Dout <= memory(to_integer(UNSIGNED(Ard)));
  END PROCESS;

END BlockRAM;