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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:38:40 12/12/2017 
-- Design Name: 
-- Module Name:    pm - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

entity IPbus_local is
    GENERIC (
      ADDR_MSB          			: INTEGER := 31;
      WAIT_STATES       			: INTEGER := 8;
      WRITE_PULSE_TICKS 			: INTEGER := 2);
    PORT (
      reset_local   					: IN  STD_LOGIC;
      clk_local     					: IN  STD_LOGIC;
      strobe_local  					: OUT STD_LOGIC;
      write_local   					: OUT STD_LOGIC;
      addr_local    					: OUT STD_LOGIC_VECTOR(ADDR_MSB DOWNTO 0);
      DataIn_local  					: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
      DataOut_local 					: IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
      IPbus_clk     					: IN  STD_LOGIC;
      IPbus_strobe  					: IN  STD_LOGIC;
      IPbus_write   					: IN  STD_LOGIC;
      IPbus_ack     					: OUT STD_LOGIC;
      IPbus_addr    					: IN  STD_LOGIC_VECTOR(ADDR_MSB DOWNTO 0);
      IPbus_DataIn  					: IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
      IPbus_DataOut 					: OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
end IPbus_local;

architecture Behavioral of IPbus_local is
signal cycle_cnt : std_logic_vector(3 downto 0) := (others => '0');	
signal toggle_Sync : std_logic_vector(3 downto 0) := (others => '0');	
signal IPbus_ack_i : std_logic := '0';
signal IPbus_cycle : std_logic := '0';
signal toggle : std_logic := '0';
attribute mark_debug : string;
attribute mark_debug of IPbus_strobe, IPbus_cycle, IPbus_write, IPbus_ack_i, strobe_local, write_local: signal is "true";
begin
IPbus_ack <= IPbus_ack_i;
process(IPbus_clk)
begin
	if(IPbus_clk'event and IPbus_clk = '1')then
		if(IPbus_ack_i = '1')then
			IPbus_cycle <= '0';
		elsif(IPbus_strobe = '1')then
			IPbus_cycle <= '1';
		end if;
		if(IPbus_strobe = '1' and IPbus_cycle = '0')then
			toggle <= not toggle;
		end if;
		if(IPbus_cycle = '0')then
			cycle_cnt <= (others => '0');
		else
			cycle_cnt <= cycle_cnt + 1;
		end if;
		if(cycle_cnt = CONV_STD_LOGIC_VECTOR(WAIT_STATES,4))then
			IPbus_ack_i <= '1';
		else
			IPbus_ack_i <= '0';
		end if;
		if(cycle_cnt = CONV_STD_LOGIC_VECTOR(WAIT_STATES-1,4))then
			IPbus_DataOut <= DataOut_local;
		end if;
	end if;
end process;
process(clk_local)
begin
	if(clk_local'event and clk_local = '1')then
		toggle_Sync(3 downto 1) <= toggle_Sync(2 downto 0);
		if(toggle_Sync(1) = toggle_Sync(3))then
			strobe_local <= '0';
		else
			strobe_local <= '1';
		end if;
		if(toggle_Sync(2) = toggle_Sync(3))then
			write_local <= '0';
		else
			write_local <= IPbus_write;
		end if;
		if(toggle_Sync(1) /= toggle_Sync(0))then
			addr_local <= IPbus_addr;
			DataIn_local <= IPbus_DataIn;
		end if;
	end if;
end process;
IPbus_strobe_Sync_inst: xpm_cdc_single
  generic map (
     DEST_SYNC_FF   => 4, -- integer; range: 2-10
     INIT_SYNC_FF   => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values
     SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages
     SRC_INPUT_REG  => 0  -- integer; 0=do not register input, 1=register input
  )
  port map (
     src_clk  => '0',  -- optional; required when SRC_INPUT_REG = 1
     src_in   => toggle,
     dest_clk => clk_local,
     dest_out => toggle_Sync(0)
  );
end Behavioral;