----------------------------------------------------------------------------------
-- Company: DESY
-- Engineer: Francesco Costanza (francesco.costanza@cern.ch)
-- 
-- Create Date:    15:01:33 12/13/2016 
-- Design Name: 
-- Module Name:    delay_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Delay of 'din' by 'shift' cycles of 'clk' 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_counter is
	 Generic ( orbit : INTEGER range 0 to 4095 );
    Port ( din : in  STD_LOGIC;
           shift_i : in  STD_LOGIC_VECTOR (11 downto 0);
           clk_i : in  STD_LOGIC;
           reset_i : in  STD_LOGIC;
           dout : out  STD_LOGIC);
end delay_counter;

architecture Behavioral of delay_counter is
begin
	process(reset_i, clk_i)
	
	variable cnt : integer range 0 TO ORBIT;
	variable en : STD_LOGIC;

	begin
	if reset_i = '1' then
		dout <= '0'; 
		cnt := ORBIT;
		en := '0';
	elsif rising_edge(clk_i) then
		if din = '1' then
			cnt := to_integer(unsigned(shift_i));
			en := '1';
		else
			cnt := cnt - 1;
		end if;
	
		if (cnt = 0 or cnt = ORBIT) and en = '1' then
			dout <= '1';
			en := '0';
		else
			dout <= '0';
		end if;	
	end if;
	end process;
end Behavioral;