---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/26/2020 09:53:46 AM -- Design Name: -- Module Name: mgtX12 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_misc.ALL; library work; use work.ngFEC_pack.all; use work.gbt_bank_package.all; use work.vendor_specific_gbt_bank_package.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; entity mgtX12 is generic (BLK_No : integer := 0); Port ( MGT_RESET : in STD_LOGIC; MGT_RXRESET : in STD_LOGIC_VECTOR (11 downto 0); gtrefclk : in STD_LOGIC; DRPclk : in STD_LOGIC; tx_wordclk : in STD_LOGIC; mgt_en : in STD_LOGIC_VECTOR (11 downto 0); loopback : in STD_LOGIC_VECTOR (2 downto 0); rx_data_good : in STD_LOGIC_VECTOR (11 downto 0); rxn : in STD_LOGIC_VECTOR (11 downto 0); rxp : in STD_LOGIC_VECTOR (11 downto 0); txn : out STD_LOGIC_VECTOR (11 downto 0); txp : out STD_LOGIC_VECTOR (11 downto 0); tx_data : in tx_word_A(11 downto 0); rx_data : out rx_word_A(11 downto 0); rx_wordclk : out STD_LOGIC_VECTOR (11 downto 0); HPTD_reset : in STD_LOGIC_VECTOR (11 downto 0); mgt_reset_tx_done : out STD_LOGIC_VECTOR (11 downto 0); MGT_TXREADY : out std_logic_vector(11 downto 0); MGT_RXREADY : out std_logic_vector(11 downto 0); RX_HEADERFLAG_o : out std_logic_vector(11 downto 0); cpll_locked : out STD_LOGIC_VECTOR (11 downto 0)); end mgtX12; architecture Behavioral of mgtX12 is COMPONENT mgt_HPTD PORT ( gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(19 DOWNTO 0); gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtrefclk0_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); rxpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0); rxpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxslide_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0); txpdelecidlemode_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); cplllock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); HPTD_reset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); mgt_reset_tx_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; COMPONENT mgt_ip_example_init port( clk_freerun_in : in std_logic; reset_all_in : in std_logic; tx_init_done_in : in std_logic; rx_init_done_in : in std_logic; rx_data_good_in : in std_logic; reset_all_out : out std_logic; reset_rx_out : out std_logic; init_done_out : out std_logic; retry_ctr_out : out std_logic_vector(3 downto 0)); END COMPONENT; COMPONENT mgt_ip_example_reset_inv_synchronizer port( clk_in : in std_logic; rst_in : in std_logic; rst_out : out std_logic); END COMPONENT; type array12x2 is array(0 to 11) of std_logic_vector(1 downto 0); signal rxpd : array12x2; signal txpd : array12x2; signal tx_reset_sync : std_logic := '0'; signal rx_usrclk : std_logic_vector(11 downto 0) := (others => '0'); signal userclk_tx_active : std_logic := '0'; signal userclk_tx_reset : std_logic := '0'; signal txoutclk : std_logic_vector(11 downto 0) := (others => '0'); signal txphdlyreset : std_logic_vector(11 downto 0) := (others => '0'); signal txphdlypd : std_logic_vector(11 downto 0) := (others => '0'); signal txphalignen : std_logic_vector(11 downto 0) := (others => '0'); signal txphalign : std_logic_vector(11 downto 0) := (others => '0'); signal txdlyupdown : std_logic_vector(11 downto 0) := (others => '0'); signal txdlysreset : std_logic_vector(11 downto 0) := (others => '0'); signal txdlyovrden : std_logic_vector(11 downto 0) := (others => '0'); signal txdlyhold : std_logic_vector(11 downto 0) := (others => '0'); signal txdlyen : std_logic_vector(11 downto 0) := (others => '0'); signal txdlybypass : std_logic_vector(11 downto 0) := (others => '0'); signal txsyncallin : std_logic_vector(11 downto 0) := (others => '0'); signal txphovrden : std_logic_vector(11 downto 0) := (others => '0'); signal txphinit : std_logic_vector(11 downto 0) := (others => '0'); signal txphdlytstclk : std_logic_vector(11 downto 0) := (others => '0'); signal txsyncin : std_logic_vector(11 downto 0) := (others => '0'); signal txsyncmode : std_logic_vector(11 downto 0) := (others => '0'); signal rxpmaresetdone : std_logic_vector(11 downto 0) := (others => '0'); signal txpmaresetdone : std_logic_vector(11 downto 0) := (others => '0'); signal txphaligndone_in : std_logic_vector(11 downto 0) := (others => '0'); signal txphaligndone_out : std_logic_vector(11 downto 0) := (others => '0'); signal txphinitdone : std_logic_vector(11 downto 0) := (others => '0'); signal txsyncdone : std_logic_vector(11 downto 0) := (others => '0'); signal txsyncout : std_logic_vector(11 downto 0) := (others => '0'); signal txdlysresetdone : std_logic_vector(11 downto 0) := (others => '0'); signal userclk_rx_reset : std_logic_vector(11 downto 0) := (others => '0'); signal userclk_rx_active : std_logic_vector(11 downto 0) := (others => '0'); signal reset_tx_done : std_logic_vector(11 downto 0) := (others => '0'); signal reset_rx_done : std_logic_vector(11 downto 0) := (others => '0'); signal reset_tx_pll_and_datapath : std_logic_vector(11 downto 0) := (others => '0'); signal reset_rx_pll_and_datapath : std_logic_vector(11 downto 0) := (others => '0'); signal reset_tx_datapath : std_logic_vector(11 downto 0) := (others => '0'); signal reset_rx_datapath : std_logic_vector(11 downto 0) := (others => '0'); signal reset_rx_init : std_logic_vector(11 downto 0) := (others => '0'); signal tx_init_done : std_logic_vector(11 downto 0) := (others => '0'); signal reset_all: std_logic_vector(11 downto 0) := (others => '0'); signal reset_all_init: std_logic_vector(11 downto 0) := (others => '0'); signal bitslip_reset : std_logic_vector(11 downto 0) := (others => '0'); signal bitSlipCmd_to_bitSlipCtrller : std_logic_vector(11 downto 0) := (others => '0'); signal rxBitSlip_to_gtx : std_logic_vector(11 downto 0) := (others => '0'); signal rx_headerlocked : std_logic_vector(11 downto 0) := (others => '0'); signal done_from_rxBitSlipControl : std_logic_vector(11 downto 0) := (others => '0'); signal ready_from_bitSlipCtrller : std_logic_vector(11 downto 0) := (others => '0'); signal rx_data_i : rx_word_A(11 downto 0); begin rx_data <= rx_data_i; rx_wordclk <= rx_usrclk; MGT_TXREADY <= tx_init_done; MGT_RXREADY <= reset_rx_done and done_from_rxBitSlipControl; userclk_tx_active <= not or_reduce(mgt_en and not txpmaresetdone); g_mgt_channel : for i in 0 to 11 generate rxpd(i) <= "00" when mgt_en(i) = '1' else "11"; txpd(i) <= "00" when mgt_en(i) = '1' else "11"; reset_all(i) <= MGT_RESET or reset_all_init(i); reset_rx_datapath(i) <= reset_rx_init(i) or MGT_RXRESET(i); userclk_rx_reset(i) <= not rxpmaresetdone(i); tx_init_done(i) <= reset_tx_done(i); txphaligndone_in(i) <= txphaligndone_out(i) or txpd(i)(0); i_init : mgt_ip_example_init port map( clk_freerun_in => DRPclk, reset_all_in => reset_all(i), tx_init_done_in => tx_init_done(i), rx_init_done_in => reset_rx_done(i), rx_data_good_in => rx_data_good(i), reset_all_out => reset_all_init(i), reset_rx_out => reset_rx_init(i), init_done_out => open, retry_ctr_out => open); i_mgt_ip_rx_buf : mgt_HPTD PORT MAP ( gtwiz_userclk_tx_active_in(0) => userclk_tx_active, gtwiz_userclk_rx_reset_in => userclk_rx_reset(i downto i), gtwiz_userclk_rx_srcclk_out => open, gtwiz_userclk_rx_usrclk_out => rx_usrclk(i downto i), gtwiz_userclk_rx_usrclk2_out => open, gtwiz_userclk_rx_active_out => open, gtwiz_reset_clk_freerun_in(0) => tx_wordclk, gtwiz_reset_all_in => reset_all(i downto i), gtwiz_reset_tx_pll_and_datapath_in => "0", gtwiz_reset_tx_datapath_in => "0", gtwiz_reset_rx_pll_and_datapath_in => "0", gtwiz_reset_rx_datapath_in => reset_rx_datapath(i downto i), gtwiz_reset_rx_cdr_stable_out => open, gtwiz_reset_tx_done_out => reset_tx_done(i downto i), gtwiz_reset_rx_done_out => reset_rx_done(i downto i), gtwiz_userdata_tx_in => tx_data(i), gtwiz_userdata_rx_out => rx_data_i(i), gthrxn_in => rxn(i downto i), gthrxp_in => rxp(i downto i), gtrefclk0_in(0) => gtrefclk, loopback_in => loopback, rxpd_in => rxpd(i), rxpolarity_in => rxpolarity(BLK_No*12+i downto BLK_No*12+i), rxslide_in => rxBitSlip_to_gtx(i downto i), txpd_in => txpd(i), txpdelecidlemode_in => txpd(i)(0 downto 0), txpolarity_in => txpolarity(BLK_No*12+i downto BLK_No*12+i), txusrclk_in(0) => tx_wordclk, txusrclk2_in(0) => tx_wordclk, cplllock_out => cpll_locked(i downto i), gthtxn_out => txn(i downto i), gthtxp_out => txp(i downto i), HPTD_reset => HPTD_reset(i downto i), mgt_reset_tx_done => mgt_reset_tx_done(i downto i), gtpowergood_out => open, rxpmaresetdone_out => rxpmaresetdone(i downto i), txpmaresetdone_out => txpmaresetdone(i downto i) ); --====================-- -- RX phase alignment -- --====================-- bitslip_reset(i) <= not reset_rx_done(i); rxBitSlipControl: entity work.mgt_bitslipctrl port map ( RX_RESET_I => bitslip_reset(i), RX_WORDCLK_I => rx_usrclk(i), MGT_CLK_I => DRPclk, RX_BITSLIPCMD_i => bitSlipCmd_to_bitSlipCtrller(i), RX_BITSLIPCMD_o => rxBitSlip_to_gtx(i), RX_HEADERLOCKED_i => rx_headerlocked(i), RX_BITSLIPISEVEN_i => '0', RX_RSTONBITSLIP_o => open, RX_ENRST_i => '0', RX_RSTONEVEN_i => '0', DONE_o => done_from_rxBitSlipControl(i), READY_o => ready_from_bitSlipCtrller(i) ); patternSearch: entity work.mgt_framealigner_pattsearch port map ( RX_RESET_I => bitslip_reset(i), RX_WORDCLK_I => rx_usrclk(i), RX_BITSLIP_CMD_O => bitSlipCmd_to_bitSlipCtrller(i), MGT_BITSLIPDONE_i => ready_from_bitSlipCtrller(i), RX_HEADER_LOCKED_O => rx_headerlocked(i), RX_HEADER_FLAG_O => RX_HEADERFLAG_o(i), RX_BITSLIPISEVEN_o => open, RX_WORD_I => rx_data_i(i) ); end generate g_mgt_channel; end Behavioral;