-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -- Date : Fri Mar 12 21:28:49 2021 -- Host : baby running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_sim_netlist.vhdl -- Design : gig_ethernet_pcs_pma_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku115-flva2104-1-c -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync is port ( reset_out : out STD_LOGIC; rxuserclk2 : in STD_LOGIC; gtwiz_reset_rx_done_out : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync : entity is "gig_ethernet_pcs_pma_0_reset_sync"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => '0', PRE => gtwiz_reset_rx_done_out(0), Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg1, PRE => gtwiz_reset_rx_done_out(0), Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg2, PRE => gtwiz_reset_rx_done_out(0), Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg3, PRE => gtwiz_reset_rx_done_out(0), Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg4, PRE => gtwiz_reset_rx_done_out(0), Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 is port ( gtwiz_reset_rx_done_out_int_reg0 : out STD_LOGIC; reset_out : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 : entity is "gig_ethernet_pcs_pma_0_reset_sync"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; signal rxreset_int : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin gtwiz_reset_rx_done_out_int_reg_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => rxreset_int, I1 => reset_out, O => gtwiz_reset_rx_done_out_int_reg0 ); reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => '0', PRE => SR(0), Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg1, PRE => SR(0), Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg2, PRE => SR(0), Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg3, PRE => SR(0), Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg4, PRE => SR(0), Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rxuserclk2, CE => '1', D => reset_sync_reg5, PRE => '0', Q => rxreset_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 is port ( gtwiz_reset_tx_done_out_int_reg0 : out STD_LOGIC; gtwiz_reset_tx_done_out : in STD_LOGIC_VECTOR ( 0 to 0 ); userclk : in STD_LOGIC; txreset : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 : entity is "gig_ethernet_pcs_pma_0_reset_sync"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; signal txreset_int : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin gtwiz_reset_tx_done_out_int_reg_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => txreset_int, I1 => gtwiz_reset_tx_done_out(0), O => gtwiz_reset_tx_done_out_int_reg0 ); reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => '0', PRE => txreset, Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg1, PRE => txreset, Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg2, PRE => txreset, Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg3, PRE => txreset, Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg4, PRE => txreset, Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg5, PRE => '0', Q => txreset_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 is port ( reset_out : out STD_LOGIC; userclk2 : in STD_LOGIC; enablealign : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 : entity is "gig_ethernet_pcs_pma_0_reset_sync"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => '0', PRE => enablealign, Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg1, PRE => enablealign, Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg2, PRE => enablealign, Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg3, PRE => enablealign, Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg4, PRE => enablealign, Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block is port ( resetdone : out STD_LOGIC; data_in : in STD_LOGIC; userclk2 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block : entity is "gig_ethernet_pcs_pma_0_sync_block"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync5, Q => resetdone, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer is port ( \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC; rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rxresetdone_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 is port ( gtwiz_reset_userclk_tx_active_sync : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[2]\ : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_tx_timer_clr_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC; sm_reset_tx_timer_clr_reg_0 : in STD_LOGIC; plllock_tx_sync : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_1\ : in STD_LOGIC; sm_reset_tx_pll_timer_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 is signal \^gtwiz_reset_userclk_tx_active_sync\ : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_tx_timer_clr_i_2_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin gtwiz_reset_userclk_tx_active_sync <= \^gtwiz_reset_userclk_tx_active_sync\; \FSM_sequential_sm_reset_tx[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"000F000088888888" ) port map ( I0 => \FSM_sequential_sm_reset_tx_reg[0]\, I1 => \^gtwiz_reset_userclk_tx_active_sync\, I2 => \FSM_sequential_sm_reset_tx_reg[0]_0\, I3 => \FSM_sequential_sm_reset_tx_reg[0]_1\, I4 => sm_reset_tx_pll_timer_sat, I5 => Q(0), O => i_in_out_reg_0 ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_userclk_tx_active_in(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^gtwiz_reset_userclk_tx_active_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); sm_reset_tx_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EBEB282B" ) port map ( I0 => sm_reset_tx_timer_clr_i_2_n_0, I1 => Q(2), I2 => Q(1), I3 => Q(0), I4 => sm_reset_tx_timer_clr_reg, O => \FSM_sequential_sm_reset_tx_reg[2]\ ); sm_reset_tx_timer_clr_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"A0C0A0C0F0F000F0" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I1 => \^gtwiz_reset_userclk_tx_active_sync\, I2 => sm_reset_tx_timer_clr_reg_0, I3 => Q(0), I4 => plllock_tx_sync, I5 => Q(2), O => sm_reset_tx_timer_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 is port ( plllock_rx_sync : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_int_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); gtwiz_reset_rx_done_int_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 is signal gtwiz_reset_rx_done_int : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal \^plllock_rx_sync\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin plllock_rx_sync <= \^plllock_rx_sync\; gtwiz_reset_rx_done_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAC0FFFFAAC00000" ) port map ( I0 => \^plllock_rx_sync\, I1 => gtwiz_reset_rx_done_int_reg, I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I3 => Q(0), I4 => gtwiz_reset_rx_done_int, I5 => gtwiz_reset_rx_done_int_reg_0, O => i_in_out_reg_0 ); gtwiz_reset_rx_done_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4C40000040400000" ) port map ( I0 => \^plllock_rx_sync\, I1 => Q(2), I2 => Q(0), I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I4 => Q(1), I5 => gtwiz_reset_rx_done_int_reg, O => gtwiz_reset_rx_done_int ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => cplllock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^plllock_rx_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); sm_reset_rx_timer_clr_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"88880000F5FF5555" ) port map ( I0 => Q(1), I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I2 => \^plllock_rx_sync\, I3 => Q(0), I4 => gtwiz_reset_rx_done_int_reg, I5 => Q(2), O => \FSM_sequential_sm_reset_rx_reg[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 is port ( plllock_tx_sync : out STD_LOGIC; gtwiz_reset_tx_done_int_reg : out STD_LOGIC; i_in_out_reg_0 : out STD_LOGIC; cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_int_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_tx_timer_sat : in STD_LOGIC; gtwiz_reset_tx_done_int_reg_1 : in STD_LOGIC; \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 is signal gtwiz_reset_tx_done_int : STD_LOGIC; signal gtwiz_reset_tx_done_int_i_2_n_0 : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal \^plllock_tx_sync\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin plllock_tx_sync <= \^plllock_tx_sync\; \FSM_sequential_sm_reset_tx[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"00CFA00000000000" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I1 => \^plllock_tx_sync\, I2 => Q(0), I3 => Q(2), I4 => Q(1), I5 => \FSM_sequential_sm_reset_tx_reg[0]\, O => i_in_out_reg_0 ); gtwiz_reset_tx_done_int_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => gtwiz_reset_tx_done_int_i_2_n_0, I1 => gtwiz_reset_tx_done_int, I2 => gtwiz_reset_tx_done_int_reg_0, O => gtwiz_reset_tx_done_int_reg ); gtwiz_reset_tx_done_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444F44444" ) port map ( I0 => Q(0), I1 => \^plllock_tx_sync\, I2 => sm_reset_tx_timer_sat, I3 => gtwiz_reset_tx_done_int_reg_1, I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, I5 => Q(1), O => gtwiz_reset_tx_done_int_i_2_n_0 ); gtwiz_reset_tx_done_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"3000404000004040" ) port map ( I0 => \^plllock_tx_sync\, I1 => Q(1), I2 => Q(2), I3 => \FSM_sequential_sm_reset_tx_reg[0]\, I4 => Q(0), I5 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, O => gtwiz_reset_tx_done_int ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => cplllock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^plllock_tx_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 is port ( \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; sm_reset_rx_cdr_to_sat_reg : out STD_LOGIC; rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sm_reset_rx_cdr_to_clr_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); plllock_rx_sync : in STD_LOGIC; sm_reset_rx_cdr_to_clr : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC; sm_reset_rx_cdr_to_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_out_reg_n_0 : STD_LOGIC; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_rx_cdr_to_clr_i_2_n_0 : STD_LOGIC; signal \^sm_reset_rx_cdr_to_sat_reg\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of rxprogdivreset_out_i_2 : label is "soft_lutpair39"; attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_2 : label is "soft_lutpair39"; begin sm_reset_rx_cdr_to_sat_reg <= \^sm_reset_rx_cdr_to_sat_reg\; \FSM_sequential_sm_reset_rx[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"000A000AC0C000C0" ) port map ( I0 => \^sm_reset_rx_cdr_to_sat_reg\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => Q(1), I3 => Q(0), I4 => plllock_rx_sync, I5 => Q(2), O => \FSM_sequential_sm_reset_rx_reg[1]\ ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rxcdrlock_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => i_in_out_reg_n_0, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); rxprogdivreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => i_in_out_reg_n_0, O => \^sm_reset_rx_cdr_to_sat_reg\ ); sm_reset_rx_cdr_to_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF0800AAAA" ) port map ( I0 => sm_reset_rx_cdr_to_clr_i_2_n_0, I1 => sm_reset_rx_cdr_to_clr_reg, I2 => Q(2), I3 => plllock_rx_sync, I4 => Q(0), I5 => sm_reset_rx_cdr_to_clr, O => \FSM_sequential_sm_reset_rx_reg[2]\ ); sm_reset_rx_cdr_to_clr_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"00EF" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => i_in_out_reg_n_0, I2 => Q(2), I3 => Q(1), O => sm_reset_rx_cdr_to_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 is port ( \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC; txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => txresetdone_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_sequential_sm_reset_all_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \FSM_sequential_sm_reset_all_reg[0]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 is signal gtpowergood_sync : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_all[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AF0FAF00CFFFCFFF" ) port map ( I0 => gtpowergood_sync, I1 => \FSM_sequential_sm_reset_all_reg[0]\, I2 => Q(2), I3 => Q(0), I4 => \FSM_sequential_sm_reset_all_reg[0]_0\, I5 => Q(1), O => E(0) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtpowergood_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtpowergood_sync, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 is port ( gtwiz_reset_rx_datapath_dly : out STD_LOGIC; in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 is signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_rx_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 is port ( D : out STD_LOGIC_VECTOR ( 1 downto 0 ); i_in_out_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); gtwiz_reset_rx_datapath_dly : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 is signal gtwiz_reset_rx_pll_and_datapath_dly : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_rx[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0088FF00FFFFF0" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => gtwiz_reset_rx_pll_and_datapath_dly, I3 => Q(2), I4 => Q(0), I5 => Q(1), O => D(0) ); \FSM_sequential_sm_reset_rx[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFF8F8F000F" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I1 => \FSM_sequential_sm_reset_rx_reg[0]\, I2 => Q(2), I3 => gtwiz_reset_rx_pll_and_datapath_dly, I4 => Q(1), I5 => Q(0), O => D(1) ); \FSM_sequential_sm_reset_rx[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000000E" ) port map ( I0 => gtwiz_reset_rx_pll_and_datapath_dly, I1 => gtwiz_reset_rx_datapath_dly, I2 => Q(2), I3 => Q(1), I4 => Q(0), I5 => \FSM_sequential_sm_reset_rx_reg[0]_0\, O => i_in_out_reg_0 ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_rx_pll_and_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC; gtwiz_reset_tx_pll_and_datapath_dly : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 is signal gtwiz_reset_tx_datapath_dly : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_tx[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF1110" ) port map ( I0 => Q(0), I1 => \FSM_sequential_sm_reset_tx_reg[0]\, I2 => gtwiz_reset_tx_datapath_dly, I3 => gtwiz_reset_tx_pll_and_datapath_dly, I4 => \FSM_sequential_sm_reset_tx_reg[0]_0\, I5 => \FSM_sequential_sm_reset_tx_reg[0]_1\, O => E(0) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_tx_datapath_dly, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 is port ( gtwiz_reset_tx_pll_and_datapath_dly : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); in0 : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 is signal \^gtwiz_reset_tx_pll_and_datapath_dly\ : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[0]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[1]_i_1\ : label is "soft_lutpair38"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin gtwiz_reset_tx_pll_and_datapath_dly <= \^gtwiz_reset_tx_pll_and_datapath_dly\; \FSM_sequential_sm_reset_tx[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1F1E" ) port map ( I0 => Q(1), I1 => Q(2), I2 => Q(0), I3 => \^gtwiz_reset_tx_pll_and_datapath_dly\, O => D(0) ); \FSM_sequential_sm_reset_tx[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0FF1" ) port map ( I0 => Q(2), I1 => \^gtwiz_reset_tx_pll_and_datapath_dly\, I2 => Q(1), I3 => Q(0), O => D(1) ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => in0, Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => \^gtwiz_reset_tx_pll_and_datapath_dly\, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 is port ( \FSM_sequential_sm_reset_rx_reg[0]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sm_reset_rx_timer_clr_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); sm_reset_rx_timer_clr_reg_0 : in STD_LOGIC; gtwiz_reset_rx_any_sync : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_1\ : in STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[0]_2\ : in STD_LOGIC; sm_reset_rx_pll_timer_sat : in STD_LOGIC; sm_reset_rx_timer_sat : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 : entity is "gtwizard_ultrascale_v1_7_9_bit_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 is signal \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ : STD_LOGIC; signal gtwiz_reset_userclk_rx_active_sync : STD_LOGIC; signal i_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of i_in_meta : signal is "true"; signal i_in_sync1 : STD_LOGIC; attribute async_reg of i_in_sync1 : signal is "true"; signal i_in_sync2 : STD_LOGIC; attribute async_reg of i_in_sync2 : signal is "true"; signal i_in_sync3 : STD_LOGIC; attribute async_reg of i_in_sync3 : signal is "true"; signal sm_reset_rx_timer_clr_i_2_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of i_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true; attribute KEEP of i_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true; attribute KEEP of i_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true; attribute KEEP of i_in_sync3_reg : label is "yes"; begin \FSM_sequential_sm_reset_rx[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\, I1 => \FSM_sequential_sm_reset_rx_reg[0]_0\, I2 => \FSM_sequential_sm_reset_rx_reg[0]_1\, O => E(0) ); \FSM_sequential_sm_reset_rx[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2023202000000000" ) port map ( I0 => sm_reset_rx_timer_clr_i_2_n_0, I1 => Q(1), I2 => Q(2), I3 => \FSM_sequential_sm_reset_rx_reg[0]_2\, I4 => sm_reset_rx_pll_timer_sat, I5 => Q(0), O => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ ); i_in_meta_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rxpmaresetdone_out(0), Q => i_in_meta, R => '0' ); i_in_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync3, Q => gtwiz_reset_userclk_rx_active_sync, R => '0' ); i_in_sync1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_meta, Q => i_in_sync1, R => '0' ); i_in_sync2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync1, Q => i_in_sync2, R => '0' ); i_in_sync3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => i_in_sync2, Q => i_in_sync3, R => '0' ); rxuserrdy_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFAAF00000800" ) port map ( I0 => Q(2), I1 => sm_reset_rx_timer_clr_i_2_n_0, I2 => Q(1), I3 => Q(0), I4 => gtwiz_reset_rx_any_sync, I5 => \gen_gtwizard_gthe3.rxuserrdy_int\, O => \FSM_sequential_sm_reset_rx_reg[2]\ ); sm_reset_rx_timer_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FCCCEFFE0CCCE00E" ) port map ( I0 => sm_reset_rx_timer_clr_i_2_n_0, I1 => sm_reset_rx_timer_clr_reg, I2 => Q(0), I3 => Q(2), I4 => Q(1), I5 => sm_reset_rx_timer_clr_reg_0, O => \FSM_sequential_sm_reset_rx_reg[0]\ ); sm_reset_rx_timer_clr_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_rx_timer_clr_reg_0, I1 => sm_reset_rx_timer_sat, I2 => gtwiz_reset_userclk_rx_active_sync, O => sm_reset_rx_timer_clr_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel is port ( cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rst_in0 : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.txprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC; gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel : entity is "gtwizard_ultrascale_v1_7_9_gthe3_channel"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel is signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC; signal 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\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC; signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC; attribute box_type : string; attribute box_type of \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE"; begin cplllock_out(0) <= \^cplllock_out\(0); \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL generic map( ACJTAG_DEBUG_MODE => '0', ACJTAG_MODE => '0', ACJTAG_RESET => '0', ADAPT_CFG0 => X"F800", ADAPT_CFG1 => X"0000", ALIGN_COMMA_DOUBLE => "FALSE", ALIGN_COMMA_ENABLE => B"1111111111", ALIGN_COMMA_WORD => 2, ALIGN_MCOMMA_DET => "TRUE", ALIGN_MCOMMA_VALUE => B"1010000011", ALIGN_PCOMMA_DET => "TRUE", ALIGN_PCOMMA_VALUE => B"0101111100", A_RXOSCALRESET => '0', A_RXPROGDIVRESET => '0', A_TXPROGDIVRESET => '0', CBCC_DATA_SOURCE_SEL => "DECODED", CDR_SWAP_MODE_EN => '0', CHAN_BOND_KEEP_ALIGN => "FALSE", CHAN_BOND_MAX_SKEW => 1, CHAN_BOND_SEQ_1_1 => B"0000000000", CHAN_BOND_SEQ_1_2 => B"0000000000", CHAN_BOND_SEQ_1_3 => B"0000000000", CHAN_BOND_SEQ_1_4 => B"0000000000", CHAN_BOND_SEQ_1_ENABLE => B"1111", CHAN_BOND_SEQ_2_1 => B"0000000000", CHAN_BOND_SEQ_2_2 => B"0000000000", CHAN_BOND_SEQ_2_3 => B"0000000000", CHAN_BOND_SEQ_2_4 => B"0000000000", CHAN_BOND_SEQ_2_ENABLE => B"1111", CHAN_BOND_SEQ_2_USE => "FALSE", CHAN_BOND_SEQ_LEN => 1, CLK_CORRECT_USE => "TRUE", CLK_COR_KEEP_IDLE => "FALSE", CLK_COR_MAX_LAT => 15, CLK_COR_MIN_LAT => 12, CLK_COR_PRECEDENCE => "TRUE", CLK_COR_REPEAT_WAIT => 0, CLK_COR_SEQ_1_1 => B"0110111100", CLK_COR_SEQ_1_2 => B"0001010000", CLK_COR_SEQ_1_3 => B"0000000000", CLK_COR_SEQ_1_4 => B"0000000000", CLK_COR_SEQ_1_ENABLE => B"1111", CLK_COR_SEQ_2_1 => B"0110111100", CLK_COR_SEQ_2_2 => B"0010110101", CLK_COR_SEQ_2_3 => B"0000000000", CLK_COR_SEQ_2_4 => B"0000000000", CLK_COR_SEQ_2_ENABLE => B"1111", CLK_COR_SEQ_2_USE => "TRUE", CLK_COR_SEQ_LEN => 2, CPLL_CFG0 => X"67F8", CPLL_CFG1 => X"A4AC", CPLL_CFG2 => X"0007", CPLL_CFG3 => B"00" & X"0", CPLL_FBDIV => 5, CPLL_FBDIV_45 => 4, CPLL_INIT_CFG0 => X"02B2", CPLL_INIT_CFG1 => X"00", CPLL_LOCK_CFG => X"01E8", CPLL_REFCLK_DIV => 1, DDI_CTRL => B"00", DDI_REALIGN_WAIT => 15, DEC_MCOMMA_DETECT => "TRUE", DEC_PCOMMA_DETECT => "TRUE", DEC_VALID_COMMA_ONLY => "FALSE", DFE_D_X_REL_POS => '0', DFE_VCM_COMP_EN => '0', DMONITOR_CFG0 => B"00" & X"00", DMONITOR_CFG1 => X"00", ES_CLK_PHASE_SEL => '0', ES_CONTROL => B"000000", ES_ERRDET_EN => "FALSE", ES_EYE_SCAN_EN => "FALSE", ES_HORZ_OFFSET => X"000", ES_PMA_CFG => B"0000000000", ES_PRESCALE => B"00000", ES_QUALIFIER0 => X"0000", ES_QUALIFIER1 => X"0000", ES_QUALIFIER2 => X"0000", ES_QUALIFIER3 => X"0000", ES_QUALIFIER4 => X"0000", ES_QUAL_MASK0 => X"0000", ES_QUAL_MASK1 => X"0000", ES_QUAL_MASK2 => X"0000", ES_QUAL_MASK3 => X"0000", ES_QUAL_MASK4 => X"0000", ES_SDATA_MASK0 => X"0000", ES_SDATA_MASK1 => X"0000", ES_SDATA_MASK2 => X"0000", ES_SDATA_MASK3 => X"0000", ES_SDATA_MASK4 => X"0000", EVODD_PHI_CFG => B"00000000000", EYE_SCAN_SWAP_EN => '0', FTS_DESKEW_SEQ_ENABLE => B"1111", FTS_LANE_DESKEW_CFG => B"1111", FTS_LANE_DESKEW_EN => "FALSE", GEARBOX_MODE => B"00000", GM_BIAS_SELECT => '0', LOCAL_MASTER => '1', OOBDIVCTL => B"00", OOB_PWRUP => '0', PCI3_AUTO_REALIGN => "OVR_1K_BLK", PCI3_PIPE_RX_ELECIDLE => '0', PCI3_RX_ASYNC_EBUF_BYPASS => B"00", PCI3_RX_ELECIDLE_EI2_ENABLE => '0', PCI3_RX_ELECIDLE_H2L_COUNT => B"000000", PCI3_RX_ELECIDLE_H2L_DISABLE => B"000", PCI3_RX_ELECIDLE_HI_COUNT => B"000000", PCI3_RX_ELECIDLE_LP4_DISABLE => '0', PCI3_RX_FIFO_DISABLE => '0', PCIE_BUFG_DIV_CTRL => X"1000", PCIE_RXPCS_CFG_GEN3 => X"02A4", PCIE_RXPMA_CFG => X"000A", PCIE_TXPCS_CFG_GEN3 => X"2CA4", PCIE_TXPMA_CFG => X"000A", PCS_PCIE_EN => "FALSE", PCS_RSVD0 => B"0000000000000000", PCS_RSVD1 => B"000", PD_TRANS_TIME_FROM_P2 => X"03C", PD_TRANS_TIME_NONE_P2 => X"19", PD_TRANS_TIME_TO_P2 => X"64", PLL_SEL_MODE_GEN12 => B"00", PLL_SEL_MODE_GEN3 => B"11", PMA_RSV1 => X"F000", PROCESS_PAR => B"010", RATE_SW_USE_DRP => '1', RESET_POWERSAVE_DISABLE => '0', RXBUFRESET_TIME => B"00011", RXBUF_ADDR_MODE => "FULL", RXBUF_EIDLE_HI_CNT => B"1000", RXBUF_EIDLE_LO_CNT => B"0000", RXBUF_EN => "TRUE", RXBUF_RESET_ON_CB_CHANGE => "TRUE", RXBUF_RESET_ON_COMMAALIGN => "FALSE", RXBUF_RESET_ON_EIDLE => "FALSE", RXBUF_RESET_ON_RATE_CHANGE => "TRUE", RXBUF_THRESH_OVFLW => 0, RXBUF_THRESH_OVRD => "FALSE", RXBUF_THRESH_UNDFLW => 0, RXCDRFREQRESET_TIME => B"00001", RXCDRPHRESET_TIME => B"00001", RXCDR_CFG0 => X"0000", RXCDR_CFG0_GEN3 => X"0000", RXCDR_CFG1 => X"0000", RXCDR_CFG1_GEN3 => X"0000", RXCDR_CFG2 => X"0746", RXCDR_CFG2_GEN3 => X"07E6", RXCDR_CFG3 => X"0000", RXCDR_CFG3_GEN3 => X"0000", RXCDR_CFG4 => X"0000", RXCDR_CFG4_GEN3 => X"0000", RXCDR_CFG5 => X"0000", RXCDR_CFG5_GEN3 => X"0000", RXCDR_FR_RESET_ON_EIDLE => '0', RXCDR_HOLD_DURING_EIDLE => '0', RXCDR_LOCK_CFG0 => X"4480", RXCDR_LOCK_CFG1 => X"5FFF", RXCDR_LOCK_CFG2 => X"77C3", RXCDR_PH_RESET_ON_EIDLE => '0', RXCFOK_CFG0 => X"4000", RXCFOK_CFG1 => X"0065", RXCFOK_CFG2 => X"002E", RXDFELPMRESET_TIME => B"0001111", RXDFELPM_KL_CFG0 => X"0000", RXDFELPM_KL_CFG1 => X"0032", RXDFELPM_KL_CFG2 => X"0000", RXDFE_CFG0 => X"0A00", RXDFE_CFG1 => X"0000", RXDFE_GC_CFG0 => X"0000", RXDFE_GC_CFG1 => X"7870", RXDFE_GC_CFG2 => X"0000", RXDFE_H2_CFG0 => X"0000", RXDFE_H2_CFG1 => X"0000", RXDFE_H3_CFG0 => X"4000", RXDFE_H3_CFG1 => X"0000", RXDFE_H4_CFG0 => X"2000", RXDFE_H4_CFG1 => X"0003", RXDFE_H5_CFG0 => X"2000", RXDFE_H5_CFG1 => X"0003", RXDFE_H6_CFG0 => X"2000", RXDFE_H6_CFG1 => X"0000", RXDFE_H7_CFG0 => X"2000", RXDFE_H7_CFG1 => X"0000", RXDFE_H8_CFG0 => X"2000", RXDFE_H8_CFG1 => X"0000", RXDFE_H9_CFG0 => X"2000", RXDFE_H9_CFG1 => X"0000", RXDFE_HA_CFG0 => X"2000", RXDFE_HA_CFG1 => X"0000", RXDFE_HB_CFG0 => X"2000", RXDFE_HB_CFG1 => X"0000", RXDFE_HC_CFG0 => X"0000", RXDFE_HC_CFG1 => X"0000", RXDFE_HD_CFG0 => X"0000", RXDFE_HD_CFG1 => X"0000", RXDFE_HE_CFG0 => X"0000", RXDFE_HE_CFG1 => X"0000", RXDFE_HF_CFG0 => X"0000", RXDFE_HF_CFG1 => X"0000", RXDFE_OS_CFG0 => X"8000", RXDFE_OS_CFG1 => X"0000", RXDFE_UT_CFG0 => X"8000", RXDFE_UT_CFG1 => X"0003", RXDFE_VP_CFG0 => X"AA00", RXDFE_VP_CFG1 => X"0033", RXDLY_CFG => X"001F", RXDLY_LCFG => X"0030", RXELECIDLE_CFG => "Sigcfg_4", RXGBOX_FIFO_INIT_RD_ADDR => 4, RXGEARBOX_EN => "FALSE", RXISCANRESET_TIME => B"00001", RXLPM_CFG => X"0000", RXLPM_GC_CFG => X"1000", RXLPM_KH_CFG0 => X"0000", RXLPM_KH_CFG1 => X"0002", RXLPM_OS_CFG0 => X"8000", RXLPM_OS_CFG1 => X"0002", RXOOB_CFG => B"000000110", RXOOB_CLK_CFG => "PMA", RXOSCALRESET_TIME => B"00011", RXOUT_DIV => 4, RXPCSRESET_TIME => B"00011", RXPHBEACON_CFG => X"0000", RXPHDLY_CFG => X"2020", RXPHSAMP_CFG => X"2100", RXPHSLIP_CFG => X"6622", RXPH_MONITOR_SEL => B"00000", RXPI_CFG0 => B"01", RXPI_CFG1 => B"01", RXPI_CFG2 => B"01", RXPI_CFG3 => B"01", RXPI_CFG4 => '1', RXPI_CFG5 => '1', RXPI_CFG6 => B"011", RXPI_LPM => '0', RXPI_VREFSEL => '0', RXPMACLK_SEL => "DATA", RXPMARESET_TIME => B"00011", RXPRBS_ERR_LOOPBACK => '0', RXPRBS_LINKACQ_CNT => 15, RXSLIDE_AUTO_WAIT => 7, RXSLIDE_MODE => "OFF", RXSYNC_MULTILANE => '0', RXSYNC_OVRD => '0', RXSYNC_SKIP_DA => '0', RX_AFE_CM_EN => '0', RX_BIAS_CFG0 => X"0AB4", RX_BUFFER_CFG => B"000000", RX_CAPFF_SARC_ENB => '0', RX_CLK25_DIV => 5, RX_CLKMUX_EN => '1', RX_CLK_SLIP_OVRD => B"00000", RX_CM_BUF_CFG => B"1010", RX_CM_BUF_PD => '0', RX_CM_SEL => B"11", RX_CM_TRIM => B"1010", RX_CTLE3_LPF => B"00000001", RX_DATA_WIDTH => 20, RX_DDI_SEL => B"000000", RX_DEFER_RESET_BUF_EN => "TRUE", RX_DFELPM_CFG0 => B"0110", RX_DFELPM_CFG1 => '1', RX_DFELPM_KLKH_AGC_STUP_EN => '1', RX_DFE_AGC_CFG0 => B"10", RX_DFE_AGC_CFG1 => B"000", RX_DFE_KL_LPM_KH_CFG0 => B"01", RX_DFE_KL_LPM_KH_CFG1 => B"000", RX_DFE_KL_LPM_KL_CFG0 => B"01", RX_DFE_KL_LPM_KL_CFG1 => B"000", RX_DFE_LPM_HOLD_DURING_EIDLE => '0', RX_DISPERR_SEQ_MATCH => "TRUE", RX_DIVRESET_TIME => B"00001", RX_EN_HI_LR => '0', RX_EYESCAN_VS_CODE => B"0000000", RX_EYESCAN_VS_NEG_DIR => '0', RX_EYESCAN_VS_RANGE => B"00", RX_EYESCAN_VS_UT_SIGN => '0', RX_FABINT_USRCLK_FLOP => '0', RX_INT_DATAWIDTH => 0, RX_PMA_POWER_SAVE => '0', RX_PROGDIV_CFG => 0.000000, RX_SAMPLE_PERIOD => B"111", RX_SIG_VALID_DLY => 11, RX_SUM_DFETAPREP_EN => '0', RX_SUM_IREF_TUNE => B"1100", RX_SUM_RES_CTRL => B"11", RX_SUM_VCMTUNE => B"0000", RX_SUM_VCM_OVWR => '0', RX_SUM_VREF_TUNE => B"000", RX_TUNE_AFE_OS => B"10", RX_WIDEMODE_CDR => '0', RX_XCLK_SEL => "RXDES", SAS_MAX_COM => 64, SAS_MIN_COM => 36, SATA_BURST_SEQ_LEN => B"1110", SATA_BURST_VAL => B"100", SATA_CPLL_CFG => "VCO_3000MHZ", SATA_EIDLE_VAL => B"100", SATA_MAX_BURST => 8, SATA_MAX_INIT => 21, SATA_MAX_WAKE => 7, SATA_MIN_BURST => 4, SATA_MIN_INIT => 12, SATA_MIN_WAKE => 4, SHOW_REALIGN_COMMA => "TRUE", SIM_MODE => "FAST", SIM_RECEIVER_DETECT_PASS => "TRUE", SIM_RESET_SPEEDUP => "TRUE", SIM_TX_EIDLE_DRIVE_LEVEL => '0', SIM_VERSION => 2, TAPDLY_SET_TX => B"00", TEMPERATUR_PAR => B"0010", TERM_RCAL_CFG => B"100001000010000", TERM_RCAL_OVRD => B"000", TRANS_TIME_RATE => X"0E", TST_RSV0 => X"00", TST_RSV1 => X"00", TXBUF_EN => "TRUE", TXBUF_RESET_ON_RATE_CHANGE => "TRUE", TXDLY_CFG => X"0009", TXDLY_LCFG => X"0050", TXDRVBIAS_N => B"1010", TXDRVBIAS_P => B"1010", TXFIFO_ADDR_CFG => "LOW", TXGBOX_FIFO_INIT_RD_ADDR => 4, TXGEARBOX_EN => "FALSE", TXOUT_DIV => 4, TXPCSRESET_TIME => B"00011", TXPHDLY_CFG0 => X"2020", TXPHDLY_CFG1 => X"0075", TXPH_CFG => X"0980", TXPH_MONITOR_SEL => B"00000", TXPI_CFG0 => B"01", TXPI_CFG1 => B"01", TXPI_CFG2 => B"01", TXPI_CFG3 => '1', TXPI_CFG4 => '1', TXPI_CFG5 => B"011", TXPI_GRAY_SEL => '0', TXPI_INVSTROBE_SEL => '1', TXPI_LPM => '0', TXPI_PPMCLK_SEL => "TXUSRCLK2", TXPI_PPM_CFG => B"00000000", TXPI_SYNFREQ_PPM => B"001", TXPI_VREFSEL => '0', TXPMARESET_TIME => B"00011", TXSYNC_MULTILANE => '0', TXSYNC_OVRD => '0', TXSYNC_SKIP_DA => '0', TX_CLK25_DIV => 5, TX_CLKMUX_EN => '1', TX_DATA_WIDTH => 20, TX_DCD_CFG => B"000010", TX_DCD_EN => '0', TX_DEEMPH0 => B"000000", TX_DEEMPH1 => B"000000", TX_DIVRESET_TIME => B"00001", TX_DRIVE_MODE => "DIRECT", TX_EIDLE_ASSERT_DELAY => B"100", TX_EIDLE_DEASSERT_DELAY => B"011", TX_EML_PHI_TUNE => '0', TX_FABINT_USRCLK_FLOP => '0', TX_IDLE_DATA_ZERO => '0', TX_INT_DATAWIDTH => 0, TX_LOOPBACK_DRIVE_HIZ => "FALSE", TX_MAINCURSOR_SEL => '0', TX_MARGIN_FULL_0 => B"1001111", TX_MARGIN_FULL_1 => B"1001110", TX_MARGIN_FULL_2 => B"1001100", TX_MARGIN_FULL_3 => B"1001010", TX_MARGIN_FULL_4 => B"1001000", TX_MARGIN_LOW_0 => B"1000110", TX_MARGIN_LOW_1 => B"1000101", TX_MARGIN_LOW_2 => B"1000011", TX_MARGIN_LOW_3 => B"1000010", TX_MARGIN_LOW_4 => B"1000000", TX_MODE_SEL => B"000", TX_PMADATA_OPT => '0', TX_PMA_POWER_SAVE => '0', TX_PROGCLK_SEL => "CPLL", TX_PROGDIV_CFG => 20.000000, TX_QPI_STATUS_EN => '0', TX_RXDETECT_CFG => B"00" & X"032", TX_RXDETECT_REF => B"100", TX_SAMPLE_PERIOD => B"111", TX_SARC_LPBK_ENB => '0', TX_XCLK_SEL => "TXOUT", USE_PCS_CLK_PHASE_SEL => '0', WB_MODE => B"00" ) port map ( BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\, BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\, BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\, BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\, BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\, BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\, BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\, BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\, BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\, BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\, BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\, BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\, BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\, BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\, BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\, BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\, BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\, BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\, BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\, BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\, BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\, CFGRESET => '0', CLKRSVD0 => '0', CLKRSVD1 => '0', CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\, CPLLLOCK => \^cplllock_out\(0), CPLLLOCKDETCLK => '0', CPLLLOCKEN => '1', CPLLPD => \gen_gtwizard_gthe3.cpllpd_ch_int\, CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\, CPLLREFCLKSEL(2 downto 0) => B"001", CPLLRESET => '0', DMONFIFORESET => '0', DMONITORCLK => '0', DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\, DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\, DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\, DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\, DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\, DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\, DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\, DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\, DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\, DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\, DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\, DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\, DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\, DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\, DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\, DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\, DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\, DRPADDR(8 downto 0) => B"000000000", DRPCLK => drpclk_in(0), DRPDI(15 downto 0) => B"0000000000000000", DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210\, DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211\, DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212\, DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213\, DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214\, DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215\, DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216\, DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\, DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\, DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\, DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\, DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\, DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\, DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\, DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\, DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\, DRPEN => '0', DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\, DRPWE => '0', EVODDPHICALDONE => '0', EVODDPHICALSTART => '0', EVODDPHIDRDEN => '0', EVODDPHIDWREN => '0', EVODDPHIXRDEN => '0', EVODDPHIXWREN => '0', EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\, EYESCANMODE => '0', EYESCANRESET => '0', EYESCANTRIGGER => '0', GTGREFCLK => '0', GTHRXN => gthrxn_in(0), GTHRXP => gthrxp_in(0), GTHTXN => gthtxn_out(0), GTHTXP => gthtxp_out(0), GTNORTHREFCLK0 => '0', GTNORTHREFCLK1 => '0', GTPOWERGOOD => gtpowergood_out(0), GTREFCLK0 => gtrefclk0_in(0), GTREFCLK1 => '0', GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\, GTRESETSEL => '0', GTRSVD(15 downto 0) => B"0000000000000000", GTRXRESET => \gen_gtwizard_gthe3.gtrxreset_int\, GTSOUTHREFCLK0 => '0', GTSOUTHREFCLK1 => '0', GTTXRESET => \gen_gtwizard_gthe3.gttxreset_int\, LOOPBACK(2 downto 0) => B"000", LPBKRXTXSEREN => '0', LPBKTXRXSEREN => '0', PCIEEQRXEQADAPTDONE => '0', PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\, PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\, PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\, PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\, PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\, PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\, PCIERSTIDLE => '0', PCIERSTTXSYNCSTART => '0', PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\, PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\, PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\, PCIEUSERRATEDONE => '0', PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\, PCSRSVDIN(15 downto 0) => B"0000000000000000", PCSRSVDIN2(4 downto 0) => B"00000", PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\, PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\, PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\, PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\, PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\, PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\, PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\, PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\, PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\, PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\, PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\, PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\, PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\, PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\, PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\, PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\, PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\, PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\, PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\, PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\, PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\, PMARSVDIN(4 downto 0) => B"00000", QPLL0CLK => '0', QPLL0REFCLK => '0', QPLL1CLK => '0', QPLL1REFCLK => '0', RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\, RESETOVRD => '0', RSTCLKENTX => '0', RX8B10BEN => '1', RXBUFRESET => '0', RXBUFSTATUS(2) => rxbufstatus_out(0), RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\, RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\, RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\, RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\, RXCDRFREQRESET => '0', RXCDRHOLD => '0', RXCDRLOCK => rxcdrlock_out(0), RXCDROVRDEN => '0', RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\, RXCDRRESET => '0', RXCDRRESETRSV => '0', RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\, RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\, RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\, RXCHBONDEN => '0', RXCHBONDI(4 downto 0) => B"00000", RXCHBONDLEVEL(2 downto 0) => B"000", RXCHBONDMASTER => '0', RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\, RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\, RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\, RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\, RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\, RXCHBONDSLAVE => '0', RXCLKCORCNT(1 downto 0) => rxclkcorcnt_out(1 downto 0), RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\, RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\, RXCOMMADETEN => '1', RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\, RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\, RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\, RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\, RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\, RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\, RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\, RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\, RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\, RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\, RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\, RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\, RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\, RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\, RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\, RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\, RXCTRL0(1 downto 0) => rxctrl0_out(1 downto 0), RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\, RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\, RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\, RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\, RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\, RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\, RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\, RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\, RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\, RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\, RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\, RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\, RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\, RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\, RXCTRL1(1 downto 0) => rxctrl1_out(1 downto 0), RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\, RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\, RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\, RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\, RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\, RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\, RXCTRL2(1 downto 0) => rxctrl2_out(1 downto 0), RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\, RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\, RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\, RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\, RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\, RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\, RXCTRL3(1 downto 0) => rxctrl3_out(1 downto 0), RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\, RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\, RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\, RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\, RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\, RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\, RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\, RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\, RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\, RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\, RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\, RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\, RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\, RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\, RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\, RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\, RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\, RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\, RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\, RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\, RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\, RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\, RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\, RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\, RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\, RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\, RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\, RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\, RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\, RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\, RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\, RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\, RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\, RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\, RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\, RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\, RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\, RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\, RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\, RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\, RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\, RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\, RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\, RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\, RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\, RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\, RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\, RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\, RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\, RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\, RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\, RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\, RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\, RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\, RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\, RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\, RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\, RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\, RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\, RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\, RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\, RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\, RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\, RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\, RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\, RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\, RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\, RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\, RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\, RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\, RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\, RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\, RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\, RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\, RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\, RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\, RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\, RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\, RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\, RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\, RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\, RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\, RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\, RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\, RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\, RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\, RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\, RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\, RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\, RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\, RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\, RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\, RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\, RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\, RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\, RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\, RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\, RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\, RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\, RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\, RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\, RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\, RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\, RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\, RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\, RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\, RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\, RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\, RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\, RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\, RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\, RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\, RXDATA(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0), RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\, RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\, RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\, RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\, RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\, RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\, RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\, RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\, RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\, RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\, RXDFEAGCCTRL(1 downto 0) => B"01", RXDFEAGCHOLD => '0', RXDFEAGCOVRDEN => '0', RXDFELFHOLD => '0', RXDFELFOVRDEN => '0', RXDFELPMRESET => '0', RXDFETAP10HOLD => '0', RXDFETAP10OVRDEN => '0', RXDFETAP11HOLD => '0', RXDFETAP11OVRDEN => '0', RXDFETAP12HOLD => '0', RXDFETAP12OVRDEN => '0', RXDFETAP13HOLD => '0', RXDFETAP13OVRDEN => '0', RXDFETAP14HOLD => '0', RXDFETAP14OVRDEN => '0', RXDFETAP15HOLD => '0', RXDFETAP15OVRDEN => '0', RXDFETAP2HOLD => '0', RXDFETAP2OVRDEN => '0', RXDFETAP3HOLD => '0', RXDFETAP3OVRDEN => '0', RXDFETAP4HOLD => '0', RXDFETAP4OVRDEN => '0', RXDFETAP5HOLD => '0', RXDFETAP5OVRDEN => '0', RXDFETAP6HOLD => '0', RXDFETAP6OVRDEN => '0', RXDFETAP7HOLD => '0', RXDFETAP7OVRDEN => '0', RXDFETAP8HOLD => '0', RXDFETAP8OVRDEN => '0', RXDFETAP9HOLD => '0', RXDFETAP9OVRDEN => '0', RXDFEUTHOLD => '0', RXDFEUTOVRDEN => '0', RXDFEVPHOLD => '0', RXDFEVPOVRDEN => '0', RXDFEVSEN => '0', RXDFEXYDEN => '1', RXDLYBYPASS => '1', RXDLYEN => '0', RXDLYOVRDEN => '0', RXDLYSRESET => '0', RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\, RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\, RXELECIDLEMODE(1 downto 0) => B"11", RXGEARBOXSLIP => '0', RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\, RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\, RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\, RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\, RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\, RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\, RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\, RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\, RXLATCLK => '0', RXLPMEN => '1', RXLPMGCHOLD => '0', RXLPMGCOVRDEN => '0', RXLPMHFHOLD => '0', RXLPMHFOVRDEN => '0', RXLPMLFHOLD => '0', RXLPMLFKLOVRDEN => '0', RXLPMOSHOLD => '0', RXLPMOSOVRDEN => '0', RXMCOMMAALIGNEN => rxmcommaalignen_in(0), RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\, RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\, RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\, RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\, RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\, RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\, RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\, RXMONITORSEL(1 downto 0) => B"00", RXOOBRESET => '0', RXOSCALRESET => '0', RXOSHOLD => '0', RXOSINTCFG(3 downto 0) => B"1101", RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\, RXOSINTEN => '1', RXOSINTHOLD => '0', RXOSINTOVRDEN => '0', RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\, RXOSINTSTROBE => '0', RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\, RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\, RXOSINTTESTOVRDEN => '0', RXOSOVRDEN => '0', RXOUTCLK => rxoutclk_out(0), RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\, RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\, RXOUTCLKSEL(2 downto 0) => B"010", RXPCOMMAALIGNEN => rxmcommaalignen_in(0), RXPCSRESET => '0', RXPD(1) => rxpd_in(0), RXPD(0) => rxpd_in(0), RXPHALIGN => '0', RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\, RXPHALIGNEN => '0', RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\, RXPHDLYPD => '1', RXPHDLYRESET => '0', RXPHOVRDEN => '0', RXPLLCLKSEL(1 downto 0) => B"00", RXPMARESET => '0', RXPMARESETDONE => rxpmaresetdone_out(0), RXPOLARITY => '0', RXPRBSCNTRESET => '0', RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\, RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\, RXPRBSSEL(3 downto 0) => B"0000", RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\, RXPROGDIVRESET => \gen_gtwizard_gthe3.rxprogdivreset_int\, RXQPIEN => '0', RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\, RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\, RXRATE(2 downto 0) => B"000", RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\, RXRATEMODE => '0', RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\, RXRESETDONE => rxresetdone_out(0), RXSLIDE => '0', RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\, RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\, RXSLIPOUTCLK => '0', RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\, RXSLIPPMA => '0', RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\, RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\, RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\, RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\, RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\, RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\, RXSYNCALLIN => '0', RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\, RXSYNCIN => '0', RXSYNCMODE => '0', RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\, RXSYSCLKSEL(1 downto 0) => B"00", RXUSERRDY => \gen_gtwizard_gthe3.rxuserrdy_int\, RXUSRCLK => rxusrclk_in(0), RXUSRCLK2 => rxusrclk_in(0), RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\, SIGVALIDCLK => '0', TSTIN(19 downto 0) => B"00000000000000000000", TX8B10BBYPASS(7 downto 0) => B"00000000", TX8B10BEN => '1', TXBUFDIFFCTRL(2 downto 0) => B"000", TXBUFSTATUS(1) => txbufstatus_out(0), TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\, TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\, TXCOMINIT => '0', TXCOMSAS => '0', TXCOMWAKE => '0', TXCTRL0(15 downto 2) => B"00000000000000", TXCTRL0(1 downto 0) => txctrl0_in(1 downto 0), TXCTRL1(15 downto 2) => B"00000000000000", TXCTRL1(1 downto 0) => txctrl1_in(1 downto 0), TXCTRL2(7 downto 2) => B"000000", TXCTRL2(1 downto 0) => txctrl2_in(1 downto 0), TXDATA(127 downto 16) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", TXDATA(15 downto 0) => gtwiz_userdata_tx_in(15 downto 0), TXDATAEXTENDRSVD(7 downto 0) => B"00000000", TXDEEMPH => '0', TXDETECTRX => '0', TXDIFFCTRL(3 downto 0) => B"1000", TXDIFFPD => '0', TXDLYBYPASS => '1', TXDLYEN => '0', TXDLYHOLD => '0', TXDLYOVRDEN => '0', TXDLYSRESET => '0', TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\, TXDLYUPDOWN => '0', TXELECIDLE => txelecidle_in(0), TXHEADER(5 downto 0) => B"000000", TXINHIBIT => '0', TXLATCLK => '0', TXMAINCURSOR(6 downto 0) => B"1000000", TXMARGIN(2 downto 0) => B"000", TXOUTCLK => txoutclk_out(0), TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\, TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\, TXOUTCLKSEL(2 downto 0) => B"101", TXPCSRESET => '0', TXPD(1) => txelecidle_in(0), TXPD(0) => txelecidle_in(0), TXPDELECIDLEMODE => '0', TXPHALIGN => '0', TXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60\, TXPHALIGNEN => '0', TXPHDLYPD => '1', TXPHDLYRESET => '0', TXPHDLYTSTCLK => '0', TXPHINIT => '0', TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\, TXPHOVRDEN => '0', TXPIPPMEN => '0', TXPIPPMOVRDEN => '0', TXPIPPMPD => '0', TXPIPPMSEL => '0', TXPIPPMSTEPSIZE(4 downto 0) => B"00000", TXPISOPD => '0', TXPLLCLKSEL(1 downto 0) => B"00", TXPMARESET => '0', TXPMARESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62\, TXPOLARITY => '0', TXPOSTCURSOR(4 downto 0) => B"00000", TXPOSTCURSORINV => '0', TXPRBSFORCEERR => '0', TXPRBSSEL(3 downto 0) => B"0000", TXPRECURSOR(4 downto 0) => B"00000", TXPRECURSORINV => '0', TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\, TXPROGDIVRESET => \gen_gtwizard_gthe3.txprogdivreset_int\, TXQPIBIASEN => '0', TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\, TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\, TXQPISTRONGPDOWN => '0', TXQPIWEAKPUP => '0', TXRATE(2 downto 0) => B"000", TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\, TXRATEMODE => '0', TXRESETDONE => txresetdone_out(0), TXSEQUENCE(6 downto 0) => B"0000000", TXSWING => '0', TXSYNCALLIN => '0', TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68\, TXSYNCIN => '0', TXSYNCMODE => '0', TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\, TXSYSCLKSEL(1 downto 0) => B"00", TXUSERRDY => \gen_gtwizard_gthe3.txuserrdy_int\, TXUSRCLK => rxusrclk_in(0), TXUSRCLK2 => rxusrclk_in(0) ); \rst_in_meta_i_1__2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cplllock_out\(0), O => rst_in0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer is port ( gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_sync2_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer : entity is "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal \rst_in_out_i_1__0_n_0\ : STD_LOGIC; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => '1', Q => rst_in_meta ); \rst_in_out_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rst_in_sync2_reg_0, O => \rst_in_out_i_1__0_n_0\ ); rst_in_out_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync3, Q => gtwiz_reset_rx_done_out(0) ); rst_in_sync1_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_meta, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync1, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => \rst_in_out_i_1__0_n_0\, D => rst_in_sync2, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 is port ( gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_sync2_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 : entity is "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_out_i_1_n_0 : STD_LOGIC; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => '1', Q => rst_in_meta ); rst_in_out_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rst_in_sync2_reg_0, O => rst_in_out_i_1_n_0 ); rst_in_out_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync3, Q => gtwiz_reset_tx_done_out(0) ); rst_in_sync1_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_meta, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync1, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rxusrclk_in(0), CE => '1', CLR => rst_in_out_i_1_n_0, D => rst_in_sync2, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer is port ( gtwiz_reset_all_sync : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_all_in(0), Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_all_in(0), Q => gtwiz_reset_all_sync ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_all_in(0), Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_all_in(0), Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_all_in(0), Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 is port ( gtwiz_reset_rx_any_sync : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]_0\ : out STD_LOGIC; \FSM_sequential_sm_reset_rx_reg[1]_1\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : in STD_LOGIC; rxprogdivreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; plllock_rx_sync : in STD_LOGIC; gtrxreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; rst_in_out_reg_0 : in STD_LOGIC; gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 is signal gtrxreset_out_i_2_n_0 : STD_LOGIC; signal gtwiz_reset_rx_any : STD_LOGIC; signal \^gtwiz_reset_rx_any_sync\ : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of gtrxreset_out_i_2 : label is "soft_lutpair40"; attribute SOFT_HLUTNM of pllreset_rx_out_i_1 : label is "soft_lutpair40"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin gtwiz_reset_rx_any_sync <= \^gtwiz_reset_rx_any_sync\; gtrxreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF44884488" ) port map ( I0 => Q(1), I1 => gtrxreset_out_i_2_n_0, I2 => plllock_rx_sync, I3 => Q(0), I4 => gtrxreset_out_reg, I5 => \gen_gtwizard_gthe3.gtrxreset_int\, O => \FSM_sequential_sm_reset_rx_reg[1]_1\ ); gtrxreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^gtwiz_reset_rx_any_sync\, I1 => Q(2), O => gtrxreset_out_i_2_n_0 ); pllreset_rx_out_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FDFF0100" ) port map ( I0 => Q(1), I1 => Q(2), I2 => \^gtwiz_reset_rx_any_sync\, I3 => Q(0), I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, O => \FSM_sequential_sm_reset_rx_reg[1]\ ); rst_in_meta_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => rst_in_out_reg_0, I1 => gtwiz_reset_rx_datapath_in(0), I2 => rst_in_out_reg_1, O => gtwiz_reset_rx_any ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_rx_any, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_rx_any, Q => \^gtwiz_reset_rx_any_sync\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_rx_any, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_rx_any, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_rx_any, Q => rst_in_sync3 ); rxprogdivreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFF00120012" ) port map ( I0 => Q(1), I1 => Q(2), I2 => Q(0), I3 => \^gtwiz_reset_rx_any_sync\, I4 => rxprogdivreset_out_reg, I5 => \gen_gtwizard_gthe3.rxprogdivreset_int\, O => \FSM_sequential_sm_reset_rx_reg[1]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 is signal rst_in0_0 : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin \rst_in_meta_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => gtwiz_reset_rx_datapath_in(0), I1 => rst_in_out_reg_0, O => rst_in0_0 ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in0_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in0_0, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in0_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in0_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in0_0, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_meta_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in_meta_reg_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in_meta_reg_0, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in_meta_reg_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in_meta_reg_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in_meta_reg_0, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 is port ( gtwiz_reset_tx_any_sync : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[1]_0\ : out STD_LOGIC; \FSM_sequential_sm_reset_tx_reg[0]\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_out_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : in STD_LOGIC; plllock_tx_sync : in STD_LOGIC; gttxreset_out_reg : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; txuserrdy_out_reg : in STD_LOGIC; gtwiz_reset_userclk_tx_active_sync : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 is signal gttxreset_out_i_2_n_0 : STD_LOGIC; signal gtwiz_reset_tx_any : STD_LOGIC; signal \^gtwiz_reset_tx_any_sync\ : STD_LOGIC; signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; signal txuserrdy_out_i_2_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of pllreset_tx_out_i_1 : label is "soft_lutpair41"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; attribute SOFT_HLUTNM of txuserrdy_out_i_2 : label is "soft_lutpair41"; begin gtwiz_reset_tx_any_sync <= \^gtwiz_reset_tx_any_sync\; gttxreset_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF44884488" ) port map ( I0 => Q(1), I1 => gttxreset_out_i_2_n_0, I2 => plllock_tx_sync, I3 => Q(0), I4 => gttxreset_out_reg, I5 => \gen_gtwizard_gthe3.gttxreset_int\, O => \FSM_sequential_sm_reset_tx_reg[1]_0\ ); gttxreset_out_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^gtwiz_reset_tx_any_sync\, I1 => Q(2), O => gttxreset_out_i_2_n_0 ); pllreset_tx_out_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FDFF0100" ) port map ( I0 => Q(1), I1 => Q(2), I2 => \^gtwiz_reset_tx_any_sync\, I3 => Q(0), I4 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, O => \FSM_sequential_sm_reset_tx_reg[1]\ ); \rst_in_meta_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => gtwiz_reset_tx_datapath_in(0), I1 => rst_in_out_reg_0, O => gtwiz_reset_tx_any ); rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_tx_any, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_tx_any, Q => \^gtwiz_reset_tx_any_sync\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_tx_any, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_tx_any, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_tx_any, Q => rst_in_sync3 ); txuserrdy_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"DD55DD5588008C00" ) port map ( I0 => txuserrdy_out_i_2_n_0, I1 => txuserrdy_out_reg, I2 => Q(0), I3 => gtwiz_reset_userclk_tx_active_sync, I4 => \^gtwiz_reset_tx_any_sync\, I5 => \gen_gtwizard_gthe3.txuserrdy_int\, O => \FSM_sequential_sm_reset_tx_reg[0]\ ); txuserrdy_out_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0110" ) port map ( I0 => Q(2), I1 => \^gtwiz_reset_tx_any_sync\, I2 => Q(1), I3 => Q(0), O => txuserrdy_out_i_2_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => gtwiz_reset_tx_datapath_in(0), Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => gtwiz_reset_tx_datapath_in(0), Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => gtwiz_reset_tx_datapath_in(0), Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => gtwiz_reset_tx_datapath_in(0), Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => gtwiz_reset_tx_datapath_in(0), Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 is port ( in0 : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in_meta_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in_meta_reg_0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in_meta_reg_0, Q => in0 ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_meta, PRE => rst_in_meta_reg_0, Q => rst_in_sync1 ); rst_in_sync2_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync1, PRE => rst_in_meta_reg_0, Q => rst_in_sync2 ); rst_in_sync3_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync2, PRE => rst_in_meta_reg_0, Q => rst_in_sync3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 is port ( \gen_gtwizard_gthe3.txprogdivreset_int\ : out STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 : entity is "gtwizard_ultrascale_v1_7_9_reset_synchronizer"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 is signal rst_in_meta : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_in_meta : signal is "true"; signal rst_in_sync1 : STD_LOGIC; attribute async_reg of rst_in_sync1 : signal is "true"; signal rst_in_sync2 : STD_LOGIC; attribute async_reg of rst_in_sync2 : signal is "true"; signal rst_in_sync3 : STD_LOGIC; attribute async_reg of rst_in_sync3 : signal is "true"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of rst_in_meta_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true; attribute KEEP of rst_in_sync1_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true; attribute KEEP of rst_in_sync2_reg : label is "yes"; attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true; attribute KEEP of rst_in_sync3_reg : label is "yes"; begin rst_in_meta_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => '0', PRE => rst_in0, Q => rst_in_meta ); rst_in_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => rst_in_sync3, PRE => rst_in0, Q => \gen_gtwizard_gthe3.txprogdivreset_int\ ); rst_in_sync1_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => 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AOOS9E+s0ZqEHeYCt0PDkEWqiRnjDrhbU850u+PwYmOMIFDcxZxrZx9fGoo05454pEanjqaM5S4v VbBto9uMjfJmFMTaSql4Ztc8AatpkjBCGBaURFaZcx3Z4wgnbttxawP/LrqUEZP62feDnwBQvL6I s9E83qpR8Z4KIX6hHma4H6l+QfvS5Kz+YzaShPTwsnNpQWvBx8J3x+xbqxTl5+v9ufiOqW8SoQ/r zya7t2hJsY77aY153+IwA95n4Npw7q2Spju/Au1oahili/NGJ5s16UK4zszYpeJq1H0Q3dDcPraX CcCsnZrJqmBwVbGRrc44ZwaVPj3aLfg+7m99xh7zZwz0G3J5qpYLBi0ejkjJBZMVBje3ooEcGuHB eOaxKCF4u8mCw34ifmXJ4PGaGwNPSs3ZzOMfyr9MqOJfqMp6TVd8h6rzJ3xmLLbLdGjUNpGoSBOf HWGKEc+1b2dz+pyGsqPXD89U9IRw9rLAvusy4wnsLRjLPG7UjK2BLWDDUyHnmytcoytu6TrBZ2Vb MstldXzV/5GL9Zsp4N5ok102t+zOXjokShGQ9IjDUJaS9Dn2TBqmL/DqPdaOI0Tqm2ANHWwEfSeH PpLRtfqMk89pzyezsq863JQQ/PuPtzKtvuTHWEleL8OCVQl+cb6yEpzX+Ri15cLf0DLncA5Ry5Ue T2zkXBgMVAIOtdOJf09wdIFqGC7hPcQWLNSopxVyn59tnSHf7T6wuMJ0AmLKacmTu3+Babrt5i++ vg+KpKgV/1Fx/rInJ/zh9jXLSW4qaJ9w5fH6AcmJgBetqVvUYYK5S7uqkWuswDt2U/Szd6KBKh/d y2guB0goz9Wzkjo5eVGk1U7LCdnckrhPp3fCbHSjhZDXHPA3+Cmx+fFd0hdANuZylZc3la2vn1XQ /fZ+wnXwG6WGQVt0uyqwj14AI5XO8OLhFFa2LdrkzWHldcAdtc6G15wtuBSfDcyQygEyUePpfLUQ UlL8677s5Tm9Z3Nz5ETDUV+OhQ4FGWiKGOakue6FFmixP+J5R41mN3Iq2ivHq1T3Y2ZRySxQc0VP EbzEPkRUXVwFMFgMzqNsaViMvZZHaOUvD0zpZuCXxAeOZKXlmv8fP8cCvxAeFj2U `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper is port ( cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rst_in0 : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : in STD_LOGIC; drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gtrxreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.gttxreset_int\ : in STD_LOGIC; rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.rxprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : in STD_LOGIC; rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.txprogdivreset_int\ : in STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : in STD_LOGIC; gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper : entity is "gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper is begin channel_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel port map ( cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => gtpowergood_out(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_userdata_rx_out(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0), gtwiz_userdata_tx_in(15 downto 0) => gtwiz_userdata_tx_in(15 downto 0), rst_in0 => rst_in0, rxbufstatus_out(0) => rxbufstatus_out(0), rxcdrlock_out(0) => rxcdrlock_out(0), rxclkcorcnt_out(1 downto 0) => rxclkcorcnt_out(1 downto 0), rxctrl0_out(1 downto 0) => rxctrl0_out(1 downto 0), rxctrl1_out(1 downto 0) => rxctrl1_out(1 downto 0), rxctrl2_out(1 downto 0) => rxctrl2_out(1 downto 0), rxctrl3_out(1 downto 0) => rxctrl3_out(1 downto 0), rxmcommaalignen_in(0) => rxmcommaalignen_in(0), rxoutclk_out(0) => rxoutclk_out(0), rxpd_in(0) => rxpd_in(0), rxpmaresetdone_out(0) => rxpmaresetdone_out(0), rxresetdone_out(0) => rxresetdone_out(0), rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => txbufstatus_out(0), txctrl0_in(1 downto 0) => txctrl0_in(1 downto 0), txctrl1_in(1 downto 0) => txctrl1_in(1 downto 0), txctrl2_in(1 downto 0) => txctrl2_in(1 downto 0), txelecidle_in(0) => txelecidle_in(0), txoutclk_out(0) => txoutclk_out(0), txresetdone_out(0) => txresetdone_out(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset is port ( \gen_gtwizard_gthe3.txprogdivreset_int\ : out STD_LOGIC; gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gttxreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.txuserrdy_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.rxprogdivreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.gtrxreset_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.rxuserrdy_int\ : out STD_LOGIC; \gen_gtwizard_gthe3.cpllpd_ch_int\ : out STD_LOGIC; gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rst_in0 : in STD_LOGIC; rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC; gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset : entity is "gtwizard_ultrascale_v1_7_9_gtwiz_reset"; end gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset is signal \FSM_sequential_sm_reset_all[2]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_all[2]_i_4_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_rx[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_rx[2]_i_6_n_0\ : STD_LOGIC; signal \FSM_sequential_sm_reset_tx[2]_i_3_n_0\ : STD_LOGIC; signal bit_synchronizer_gtpowergood_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1 : STD_LOGIC; signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2 : STD_LOGIC; signal bit_synchronizer_plllock_rx_inst_n_1 : STD_LOGIC; signal bit_synchronizer_plllock_rx_inst_n_2 : STD_LOGIC; signal bit_synchronizer_plllock_tx_inst_n_1 : STD_LOGIC; signal bit_synchronizer_plllock_tx_inst_n_2 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_0 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_1 : STD_LOGIC; signal bit_synchronizer_rxcdrlock_inst_n_2 : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.gtrxreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.gttxreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.rxprogdivreset_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.rxuserrdy_int\ : STD_LOGIC; signal \^gen_gtwizard_gthe3.txuserrdy_int\ : STD_LOGIC; signal gttxreset_out_i_3_n_0 : STD_LOGIC; signal gtwiz_reset_all_sync : STD_LOGIC; signal gtwiz_reset_rx_any_sync : STD_LOGIC; signal gtwiz_reset_rx_datapath_dly : STD_LOGIC; signal gtwiz_reset_rx_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_rx_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_datapath_sync : STD_LOGIC; signal gtwiz_reset_rx_done_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_rx_pll_and_datapath_sync : STD_LOGIC; signal gtwiz_reset_tx_any_sync : STD_LOGIC; signal gtwiz_reset_tx_datapath_sync : STD_LOGIC; signal gtwiz_reset_tx_done_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_dly : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 : STD_LOGIC; signal gtwiz_reset_tx_pll_and_datapath_sync : STD_LOGIC; signal gtwiz_reset_userclk_tx_active_sync : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 ); signal plllock_rx_sync : STD_LOGIC; signal plllock_tx_sync : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_1 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_2 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_3 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_1 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_2 : STD_LOGIC; signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_3 : STD_LOGIC; signal sel : STD_LOGIC; signal sm_reset_all : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_all__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_all_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_all_timer_clr_i_2_n_0 : STD_LOGIC; signal sm_reset_all_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_all_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_all_timer_ctr0_n_0 : STD_LOGIC; signal \sm_reset_all_timer_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_all_timer_ctr[1]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_all_timer_ctr[2]_i_1_n_0\ : STD_LOGIC; signal sm_reset_all_timer_sat : STD_LOGIC; signal sm_reset_all_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_rx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_rx_cdr_to_clr : STD_LOGIC; signal sm_reset_rx_cdr_to_clr_i_3_n_0 : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ : STD_LOGIC; signal sm_reset_rx_cdr_to_ctr_reg : STD_LOGIC_VECTOR ( 25 downto 0 ); signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\ : STD_LOGIC; signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\ : STD_LOGIC; signal sm_reset_rx_cdr_to_sat : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_4_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_5_n_0 : STD_LOGIC; signal sm_reset_rx_cdr_to_sat_i_6_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_clr_reg_n_0 : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC; signal sm_reset_rx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); signal sm_reset_rx_pll_timer_sat : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_rx_pll_timer_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_rx_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_rx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_rx_timer_ctr0_n_0 : STD_LOGIC; signal \sm_reset_rx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC; signal \sm_reset_rx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC; signal sm_reset_rx_timer_sat : STD_LOGIC; signal sm_reset_rx_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \sm_reset_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_tx_pll_timer_clr_i_1_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_clr_reg_n_0 : STD_LOGIC; signal \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC; signal \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC; signal sm_reset_tx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); signal sm_reset_tx_pll_timer_sat : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_1_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_2_n_0 : STD_LOGIC; signal sm_reset_tx_pll_timer_sat_i_3_n_0 : STD_LOGIC; signal sm_reset_tx_timer_clr_reg_n_0 : STD_LOGIC; signal sm_reset_tx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sm_reset_tx_timer_sat : STD_LOGIC; signal sm_reset_tx_timer_sat_i_1_n_0 : STD_LOGIC; signal txuserrdy_out_i_3_n_0 : STD_LOGIC; signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[1]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_2\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_3\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_4\ : label is "soft_lutpair54"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[0]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[1]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[2]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[1]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[2]_i_6\ : label is "soft_lutpair42"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[0]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[1]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[2]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_2\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_3\ : label is "soft_lutpair45"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[0]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[1]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[2]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001"; attribute SOFT_HLUTNM of gttxreset_out_i_3 : label is "soft_lutpair48"; attribute SOFT_HLUTNM of gtwiz_reset_rx_datapath_int_i_1 : label is "soft_lutpair51"; attribute SOFT_HLUTNM of gtwiz_reset_tx_pll_and_datapath_int_i_1 : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[1]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[2]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_3 : label is "soft_lutpair42"; attribute ADDER_THRESHOLD : integer; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\ : label is 16; attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\ : label is 16; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of sm_reset_rx_pll_timer_sat_i_2 : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[1]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[2]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of sm_reset_rx_timer_sat_i_1 : label is "soft_lutpair49"; attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_clr_i_1 : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_sat_i_2 : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[1]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[2]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of sm_reset_tx_timer_sat_i_1 : label is "soft_lutpair48"; attribute SOFT_HLUTNM of txuserrdy_out_i_3 : label is "soft_lutpair50"; begin \gen_gtwizard_gthe3.gtrxreset_int\ <= \^gen_gtwizard_gthe3.gtrxreset_int\; \gen_gtwizard_gthe3.gttxreset_int\ <= \^gen_gtwizard_gthe3.gttxreset_int\; \gen_gtwizard_gthe3.rxprogdivreset_int\ <= \^gen_gtwizard_gthe3.rxprogdivreset_int\; \gen_gtwizard_gthe3.rxuserrdy_int\ <= \^gen_gtwizard_gthe3.rxuserrdy_int\; \gen_gtwizard_gthe3.txuserrdy_int\ <= \^gen_gtwizard_gthe3.txuserrdy_int\; \FSM_sequential_sm_reset_all[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00FFF70000FFFFFF" ) port map ( I0 => gtwiz_reset_rx_done_int_reg_n_0, I1 => sm_reset_all_timer_sat, I2 => sm_reset_all_timer_clr_reg_n_0, I3 => sm_reset_all(2), I4 => sm_reset_all(1), I5 => sm_reset_all(0), O => \sm_reset_all__0\(0) ); \FSM_sequential_sm_reset_all[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"34" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(1), I2 => sm_reset_all(0), O => \sm_reset_all__0\(1) ); \FSM_sequential_sm_reset_all[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"4A" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(0), I2 => sm_reset_all(1), O => \sm_reset_all__0\(2) ); \FSM_sequential_sm_reset_all[2]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => sm_reset_all_timer_sat, I1 => gtwiz_reset_rx_done_int_reg_n_0, I2 => sm_reset_all_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_all[2]_i_3_n_0\ ); \FSM_sequential_sm_reset_all[2]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_all_timer_clr_reg_n_0, I1 => sm_reset_all_timer_sat, I2 => gtwiz_reset_tx_done_int_reg_n_0, O => \FSM_sequential_sm_reset_all[2]_i_4_n_0\ ); \FSM_sequential_sm_reset_all_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(0), Q => sm_reset_all(0), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_all_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(1), Q => sm_reset_all(1), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_all_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtpowergood_inst_n_0, D => \sm_reset_all__0\(2), Q => sm_reset_all(2), R => gtwiz_reset_all_sync ); \FSM_sequential_sm_reset_rx[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => sm_reset_rx_timer_sat, I1 => sm_reset_rx_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\ ); \FSM_sequential_sm_reset_rx[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"DDFD8888DDDD8888" ) port map ( I0 => sm_reset_rx(1), I1 => sm_reset_rx(0), I2 => sm_reset_rx_timer_sat, I3 => sm_reset_rx_timer_clr_reg_n_0, I4 => sm_reset_rx(2), I5 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, O => \sm_reset_rx__0\(2) ); \FSM_sequential_sm_reset_rx[2]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"00004000" ) port map ( I0 => sm_reset_rx(0), I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, I2 => sm_reset_rx(1), I3 => sm_reset_rx_timer_sat, I4 => sm_reset_rx_timer_clr_reg_n_0, O => \FSM_sequential_sm_reset_rx[2]_i_6_n_0\ ); \FSM_sequential_sm_reset_rx_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(0), Q => sm_reset_rx(0), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_rx_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(1), Q => sm_reset_rx(1), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_rx_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, D => \sm_reset_rx__0\(2), Q => sm_reset_rx(2), R => gtwiz_reset_rx_any_sync ); \FSM_sequential_sm_reset_tx[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"38" ) port map ( I0 => sm_reset_tx(0), I1 => sm_reset_tx(1), I2 => sm_reset_tx(2), O => \sm_reset_tx__0\(2) ); \FSM_sequential_sm_reset_tx[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), O => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\ ); \FSM_sequential_sm_reset_tx_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(0), Q => sm_reset_tx(0), R => gtwiz_reset_tx_any_sync ); \FSM_sequential_sm_reset_tx_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(1), Q => sm_reset_tx(1), R => gtwiz_reset_tx_any_sync ); \FSM_sequential_sm_reset_tx_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, D => \sm_reset_tx__0\(2), Q => sm_reset_tx(2), R => gtwiz_reset_tx_any_sync ); bit_synchronizer_gtpowergood_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 port map ( E(0) => bit_synchronizer_gtpowergood_inst_n_0, \FSM_sequential_sm_reset_all_reg[0]\ => \FSM_sequential_sm_reset_all[2]_i_3_n_0\, \FSM_sequential_sm_reset_all_reg[0]_0\ => \FSM_sequential_sm_reset_all[2]_i_4_n_0\, Q(2 downto 0) => sm_reset_all(2 downto 0), drpclk_in(0) => drpclk_in(0), gtpowergood_out(0) => gtpowergood_out(0) ); bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_rx_datapath_dly => gtwiz_reset_rx_datapath_dly, in0 => gtwiz_reset_rx_datapath_sync ); bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 port map ( D(1 downto 0) => \sm_reset_rx__0\(1 downto 0), \FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, \FSM_sequential_sm_reset_rx_reg[0]_0\ => \FSM_sequential_sm_reset_rx[2]_i_6_n_0\, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, gtwiz_reset_rx_datapath_dly => gtwiz_reset_rx_datapath_dly, i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2, in0 => gtwiz_reset_rx_pll_and_datapath_sync ); bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 port map ( E(0) => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0, \FSM_sequential_sm_reset_tx_reg[0]\ => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\, \FSM_sequential_sm_reset_tx_reg[0]_0\ => bit_synchronizer_plllock_tx_inst_n_2, \FSM_sequential_sm_reset_tx_reg[0]_1\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2, Q(0) => sm_reset_tx(0), drpclk_in(0) => drpclk_in(0), gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly, in0 => gtwiz_reset_tx_datapath_sync ); bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 port map ( D(1 downto 0) => \sm_reset_tx__0\(1 downto 0), Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly, in0 => gtwiz_reset_tx_pll_and_datapath_sync ); bit_synchronizer_gtwiz_reset_userclk_rx_active_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 port map ( E(0) => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2, \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0, \FSM_sequential_sm_reset_rx_reg[0]_0\ => bit_synchronizer_rxcdrlock_inst_n_1, \FSM_sequential_sm_reset_rx_reg[0]_1\ => bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2, \FSM_sequential_sm_reset_rx_reg[0]_2\ => sm_reset_rx_pll_timer_clr_reg_n_0, \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.rxuserrdy_int\ => \^gen_gtwizard_gthe3.rxuserrdy_int\, gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync, rxpmaresetdone_out(0) => rxpmaresetdone_out(0), sm_reset_rx_pll_timer_sat => sm_reset_rx_pll_timer_sat, sm_reset_rx_timer_clr_reg => bit_synchronizer_plllock_rx_inst_n_2, sm_reset_rx_timer_clr_reg_0 => sm_reset_rx_timer_clr_reg_n_0, sm_reset_rx_timer_sat => sm_reset_rx_timer_sat ); bit_synchronizer_gtwiz_reset_userclk_tx_active_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => txuserrdy_out_i_3_n_0, \FSM_sequential_sm_reset_tx_reg[0]_0\ => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\, \FSM_sequential_sm_reset_tx_reg[0]_1\ => sm_reset_tx_pll_timer_clr_reg_n_0, \FSM_sequential_sm_reset_tx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1, Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, gtwiz_reset_userclk_tx_active_sync => gtwiz_reset_userclk_tx_active_sync, gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2, plllock_tx_sync => plllock_tx_sync, sm_reset_tx_pll_timer_sat => sm_reset_tx_pll_timer_sat, sm_reset_tx_timer_clr_reg => sm_reset_tx_timer_clr_reg_n_0, sm_reset_tx_timer_clr_reg_0 => gttxreset_out_i_3_n_0 ); bit_synchronizer_plllock_rx_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 port map ( \FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_plllock_rx_inst_n_2, Q(2 downto 0) => sm_reset_rx(2 downto 0), cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, gtwiz_reset_rx_done_int_reg => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, gtwiz_reset_rx_done_int_reg_0 => gtwiz_reset_rx_done_int_reg_n_0, i_in_out_reg_0 => bit_synchronizer_plllock_rx_inst_n_1, plllock_rx_sync => plllock_rx_sync ); bit_synchronizer_plllock_tx_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => gttxreset_out_i_3_n_0, Q(2 downto 0) => sm_reset_tx(2 downto 0), cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, gtwiz_reset_tx_done_int_reg => bit_synchronizer_plllock_tx_inst_n_1, gtwiz_reset_tx_done_int_reg_0 => gtwiz_reset_tx_done_int_reg_n_0, gtwiz_reset_tx_done_int_reg_1 => sm_reset_tx_timer_clr_reg_n_0, i_in_out_reg_0 => bit_synchronizer_plllock_tx_inst_n_2, plllock_tx_sync => plllock_tx_sync, sm_reset_tx_timer_sat => sm_reset_tx_timer_sat ); bit_synchronizer_rxcdrlock_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 port map ( \FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, \FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_rxcdrlock_inst_n_1, \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_rxcdrlock_inst_n_0, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), plllock_rx_sync => plllock_rx_sync, rxcdrlock_out(0) => rxcdrlock_out(0), sm_reset_rx_cdr_to_clr => sm_reset_rx_cdr_to_clr, sm_reset_rx_cdr_to_clr_reg => sm_reset_rx_cdr_to_clr_i_3_n_0, sm_reset_rx_cdr_to_sat => sm_reset_rx_cdr_to_sat, sm_reset_rx_cdr_to_sat_reg => bit_synchronizer_rxcdrlock_inst_n_2 ); \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, O => \gen_gtwizard_gthe3.cpllpd_ch_int\ ); gtrxreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3, Q => \^gen_gtwizard_gthe3.gtrxreset_int\, R => '0' ); gttxreset_out_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => sm_reset_tx_timer_sat, I1 => sm_reset_tx_timer_clr_reg_n_0, O => gttxreset_out_i_3_n_0 ); gttxreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2, Q => \^gen_gtwizard_gthe3.gttxreset_int\, R => '0' ); gtwiz_reset_rx_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F740" ) port map ( I0 => sm_reset_all(2), I1 => sm_reset_all(0), I2 => sm_reset_all(1), I3 => gtwiz_reset_rx_datapath_int_reg_n_0, O => gtwiz_reset_rx_datapath_int_i_1_n_0 ); gtwiz_reset_rx_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_rx_datapath_int_i_1_n_0, Q => gtwiz_reset_rx_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); gtwiz_reset_rx_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_plllock_rx_inst_n_1, Q => gtwiz_reset_rx_done_int_reg_n_0, R => gtwiz_reset_rx_any_sync ); gtwiz_reset_rx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F704" ) port map ( I0 => sm_reset_all(0), I1 => sm_reset_all(2), I2 => sm_reset_all(1), I3 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, O => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 ); gtwiz_reset_rx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0, Q => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); gtwiz_reset_tx_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_plllock_tx_inst_n_1, Q => gtwiz_reset_tx_done_int_reg_n_0, R => gtwiz_reset_tx_any_sync ); gtwiz_reset_tx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FB02" ) port map ( I0 => sm_reset_all(0), I1 => sm_reset_all(1), I2 => sm_reset_all(2), I3 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, O => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 ); gtwiz_reset_tx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0, Q => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, R => gtwiz_reset_all_sync ); pllreset_rx_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, R => '0' ); pllreset_tx_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1, Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, R => '0' ); reset_synchronizer_gtwiz_reset_all_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0), gtwiz_reset_all_sync => gtwiz_reset_all_sync ); reset_synchronizer_gtwiz_reset_rx_any_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 port map ( \FSM_sequential_sm_reset_rx_reg[1]\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1, \FSM_sequential_sm_reset_rx_reg[1]_0\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2, \FSM_sequential_sm_reset_rx_reg[1]_1\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3, Q(2 downto 0) => sm_reset_rx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \^gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \^gen_gtwizard_gthe3.rxprogdivreset_int\, gtrxreset_out_reg => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\, gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync, gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), plllock_rx_sync => plllock_rx_sync, rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0, rst_in_out_reg_1 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0, rxprogdivreset_out_reg => bit_synchronizer_rxcdrlock_inst_n_2 ); reset_synchronizer_gtwiz_reset_rx_datapath_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), in0 => gtwiz_reset_rx_datapath_sync, rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0 ); reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 port map ( drpclk_in(0) => drpclk_in(0), in0 => gtwiz_reset_rx_pll_and_datapath_sync, rst_in_meta_reg_0 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 ); reset_synchronizer_gtwiz_reset_tx_any_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 port map ( \FSM_sequential_sm_reset_tx_reg[0]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_3, \FSM_sequential_sm_reset_tx_reg[1]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1, \FSM_sequential_sm_reset_tx_reg[1]_0\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2, Q(2 downto 0) => sm_reset_tx(2 downto 0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \^gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \^gen_gtwizard_gthe3.txuserrdy_int\, gttxreset_out_reg => gttxreset_out_i_3_n_0, gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync, gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0), gtwiz_reset_userclk_tx_active_sync => gtwiz_reset_userclk_tx_active_sync, plllock_tx_sync => plllock_tx_sync, rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0, txuserrdy_out_reg => txuserrdy_out_i_3_n_0 ); reset_synchronizer_gtwiz_reset_tx_datapath_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 port map ( drpclk_in(0) => drpclk_in(0), gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0), in0 => gtwiz_reset_tx_datapath_sync ); reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 port map ( drpclk_in(0) => drpclk_in(0), in0 => gtwiz_reset_tx_pll_and_datapath_sync, rst_in_meta_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 ); reset_synchronizer_rx_done_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer port map ( gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), rst_in_sync2_reg_0 => gtwiz_reset_rx_done_int_reg_n_0, rxusrclk_in(0) => rxusrclk_in(0) ); reset_synchronizer_tx_done_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 port map ( gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), rst_in_sync2_reg_0 => gtwiz_reset_tx_done_int_reg_n_0, rxusrclk_in(0) => rxusrclk_in(0) ); reset_synchronizer_txprogdivreset_inst: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, rst_in0 => rst_in0 ); rxprogdivreset_out_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2, Q => \^gen_gtwizard_gthe3.rxprogdivreset_int\, R => '0' ); rxuserrdy_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1, Q => \^gen_gtwizard_gthe3.rxuserrdy_int\, R => '0' ); sm_reset_all_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EFFA200A" ) port map ( I0 => sm_reset_all_timer_clr_i_2_n_0, I1 => sm_reset_all(1), I2 => sm_reset_all(2), I3 => sm_reset_all(0), I4 => sm_reset_all_timer_clr_reg_n_0, O => sm_reset_all_timer_clr_i_1_n_0 ); sm_reset_all_timer_clr_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000B0003333BB33" ) port map ( I0 => gtwiz_reset_rx_done_int_reg_n_0, I1 => sm_reset_all(2), I2 => gtwiz_reset_tx_done_int_reg_n_0, I3 => sm_reset_all_timer_sat, I4 => sm_reset_all_timer_clr_reg_n_0, I5 => sm_reset_all(1), O => sm_reset_all_timer_clr_i_2_n_0 ); sm_reset_all_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_all_timer_clr_i_1_n_0, Q => sm_reset_all_timer_clr_reg_n_0, S => gtwiz_reset_all_sync ); sm_reset_all_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_all_timer_ctr(2), I1 => sm_reset_all_timer_ctr(0), I2 => sm_reset_all_timer_ctr(1), O => sm_reset_all_timer_ctr0_n_0 ); \sm_reset_all_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_all_timer_ctr(0), O => \sm_reset_all_timer_ctr[0]_i_1_n_0\ ); \sm_reset_all_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_all_timer_ctr(0), I1 => sm_reset_all_timer_ctr(1), O => \sm_reset_all_timer_ctr[1]_i_1_n_0\ ); \sm_reset_all_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_all_timer_ctr(0), I1 => sm_reset_all_timer_ctr(1), I2 => sm_reset_all_timer_ctr(2), O => \sm_reset_all_timer_ctr[2]_i_1_n_0\ ); \sm_reset_all_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[0]_i_1_n_0\, Q => sm_reset_all_timer_ctr(0), R => sm_reset_all_timer_clr_reg_n_0 ); \sm_reset_all_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[1]_i_1_n_0\, Q => sm_reset_all_timer_ctr(1), R => sm_reset_all_timer_clr_reg_n_0 ); \sm_reset_all_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_all_timer_ctr0_n_0, D => \sm_reset_all_timer_ctr[2]_i_1_n_0\, Q => sm_reset_all_timer_ctr(2), R => sm_reset_all_timer_clr_reg_n_0 ); sm_reset_all_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_all_timer_ctr(2), I1 => sm_reset_all_timer_ctr(0), I2 => sm_reset_all_timer_ctr(1), I3 => sm_reset_all_timer_sat, I4 => sm_reset_all_timer_clr_reg_n_0, O => sm_reset_all_timer_sat_i_1_n_0 ); sm_reset_all_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_all_timer_sat_i_1_n_0, Q => sm_reset_all_timer_sat, R => '0' ); sm_reset_rx_cdr_to_clr_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sm_reset_rx_timer_clr_reg_n_0, I1 => sm_reset_rx_timer_sat, I2 => sm_reset_rx(1), O => sm_reset_rx_cdr_to_clr_i_3_n_0 ); sm_reset_rx_cdr_to_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_rxcdrlock_inst_n_0, Q => sm_reset_rx_cdr_to_clr, S => gtwiz_reset_rx_any_sync ); \sm_reset_rx_cdr_to_ctr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(0), I1 => sm_reset_rx_cdr_to_ctr_reg(1), I2 => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\, I3 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\, I4 => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\, I5 => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\, O => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFDFFFFFFFFF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(18), I1 => sm_reset_rx_cdr_to_ctr_reg(19), I2 => sm_reset_rx_cdr_to_ctr_reg(17), I3 => sm_reset_rx_cdr_to_ctr_reg(16), I4 => sm_reset_rx_cdr_to_ctr_reg(14), I5 => sm_reset_rx_cdr_to_ctr_reg(15), O => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFEFFFFFFFF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(24), I1 => sm_reset_rx_cdr_to_ctr_reg(25), I2 => sm_reset_rx_cdr_to_ctr_reg(22), I3 => sm_reset_rx_cdr_to_ctr_reg(23), I4 => sm_reset_rx_cdr_to_ctr_reg(21), I5 => sm_reset_rx_cdr_to_ctr_reg(20), O => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFDFFFFFFFFF" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(12), I1 => sm_reset_rx_cdr_to_ctr_reg(13), I2 => sm_reset_rx_cdr_to_ctr_reg(10), I3 => sm_reset_rx_cdr_to_ctr_reg(11), I4 => sm_reset_rx_cdr_to_ctr_reg(9), I5 => sm_reset_rx_cdr_to_ctr_reg(8), O => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFD" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(6), I1 => sm_reset_rx_cdr_to_ctr_reg(7), I2 => sm_reset_rx_cdr_to_ctr_reg(4), I3 => sm_reset_rx_cdr_to_ctr_reg(5), I4 => sm_reset_rx_cdr_to_ctr_reg(3), I5 => sm_reset_rx_cdr_to_ctr_reg(2), O => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\ ); \sm_reset_rx_cdr_to_ctr[0]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(0), O => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ ); \sm_reset_rx_cdr_to_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(0), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\: unisim.vcomponents.CARRY8 port map ( CI => '0', CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\, DI(7 downto 0) => B"00000001", O(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\, S(7 downto 1) => sm_reset_rx_cdr_to_ctr_reg(7 downto 1), S(0) => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ ); \sm_reset_rx_cdr_to_ctr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(10), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(11), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(12), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(13), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(14), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(15), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(16), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\, CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\, S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(23 downto 16) ); \sm_reset_rx_cdr_to_ctr_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(17), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(18), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(19), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(1), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(20), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(21), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(22), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(23), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(24), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\, CI_TOP => '0', CO(7 downto 1) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\(7 downto 1), CO(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7 downto 2) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\(7 downto 2), O(1) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\, S(7 downto 2) => B"000000", S(1 downto 0) => sm_reset_rx_cdr_to_ctr_reg(25 downto 24) ); \sm_reset_rx_cdr_to_ctr_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(25), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\, Q => sm_reset_rx_cdr_to_ctr_reg(2), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\, Q => sm_reset_rx_cdr_to_ctr_reg(3), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\, Q => sm_reset_rx_cdr_to_ctr_reg(4), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\, Q => sm_reset_rx_cdr_to_ctr_reg(5), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\, Q => sm_reset_rx_cdr_to_ctr_reg(6), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\, Q => sm_reset_rx_cdr_to_ctr_reg(7), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\, Q => sm_reset_rx_cdr_to_ctr_reg(8), R => sm_reset_rx_cdr_to_clr ); \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\: unisim.vcomponents.CARRY8 port map ( CI => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\, CI_TOP => '0', CO(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\, CO(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\, CO(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\, CO(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\, CO(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\, CO(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\, CO(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\, CO(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\, DI(7 downto 0) => B"00000000", O(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\, O(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\, O(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\, O(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\, O(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\, O(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\, O(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\, O(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\, S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(15 downto 8) ); \sm_reset_rx_cdr_to_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\, D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\, Q => sm_reset_rx_cdr_to_ctr_reg(9), R => sm_reset_rx_cdr_to_clr ); sm_reset_rx_cdr_to_sat_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"0E" ) port map ( I0 => sm_reset_rx_cdr_to_sat, I1 => sm_reset_rx_cdr_to_sat_i_2_n_0, I2 => sm_reset_rx_cdr_to_clr, O => sm_reset_rx_cdr_to_sat_i_1_n_0 ); sm_reset_rx_cdr_to_sat_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000008000" ) port map ( I0 => sm_reset_rx_cdr_to_sat_i_3_n_0, I1 => sm_reset_rx_cdr_to_sat_i_4_n_0, I2 => sm_reset_rx_cdr_to_sat_i_5_n_0, I3 => sm_reset_rx_cdr_to_sat_i_6_n_0, I4 => sm_reset_rx_cdr_to_ctr_reg(0), I5 => sm_reset_rx_cdr_to_ctr_reg(1), O => sm_reset_rx_cdr_to_sat_i_2_n_0 ); sm_reset_rx_cdr_to_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(4), I1 => sm_reset_rx_cdr_to_ctr_reg(5), I2 => sm_reset_rx_cdr_to_ctr_reg(2), I3 => sm_reset_rx_cdr_to_ctr_reg(3), I4 => sm_reset_rx_cdr_to_ctr_reg(7), I5 => sm_reset_rx_cdr_to_ctr_reg(6), O => sm_reset_rx_cdr_to_sat_i_3_n_0 ); sm_reset_rx_cdr_to_sat_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000010" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(22), I1 => sm_reset_rx_cdr_to_ctr_reg(23), I2 => sm_reset_rx_cdr_to_ctr_reg(20), I3 => sm_reset_rx_cdr_to_ctr_reg(21), I4 => sm_reset_rx_cdr_to_ctr_reg(25), I5 => sm_reset_rx_cdr_to_ctr_reg(24), O => sm_reset_rx_cdr_to_sat_i_4_n_0 ); sm_reset_rx_cdr_to_sat_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(17), I1 => sm_reset_rx_cdr_to_ctr_reg(16), I2 => sm_reset_rx_cdr_to_ctr_reg(15), I3 => sm_reset_rx_cdr_to_ctr_reg(14), I4 => sm_reset_rx_cdr_to_ctr_reg(19), I5 => sm_reset_rx_cdr_to_ctr_reg(18), O => sm_reset_rx_cdr_to_sat_i_5_n_0 ); sm_reset_rx_cdr_to_sat_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => sm_reset_rx_cdr_to_ctr_reg(10), I1 => sm_reset_rx_cdr_to_ctr_reg(11), I2 => sm_reset_rx_cdr_to_ctr_reg(8), I3 => sm_reset_rx_cdr_to_ctr_reg(9), I4 => sm_reset_rx_cdr_to_ctr_reg(13), I5 => sm_reset_rx_cdr_to_ctr_reg(12), O => sm_reset_rx_cdr_to_sat_i_6_n_0 ); sm_reset_rx_cdr_to_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_cdr_to_sat_i_1_n_0, Q => sm_reset_rx_cdr_to_sat, R => '0' ); sm_reset_rx_pll_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFF3000B" ) port map ( I0 => sm_reset_rx_pll_timer_sat, I1 => sm_reset_rx(0), I2 => sm_reset_rx(1), I3 => sm_reset_rx(2), I4 => sm_reset_rx_pll_timer_clr_reg_n_0, O => sm_reset_rx_pll_timer_clr_i_1_n_0 ); sm_reset_rx_pll_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_pll_timer_clr_i_1_n_0, Q => sm_reset_rx_pll_timer_clr_reg_n_0, S => gtwiz_reset_rx_any_sync ); \sm_reset_rx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(0), O => \p_0_in__1\(0) ); \sm_reset_rx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(1), I1 => sm_reset_rx_pll_timer_ctr_reg(0), O => \p_0_in__1\(1) ); \sm_reset_rx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(1), I1 => sm_reset_rx_pll_timer_ctr_reg(0), I2 => sm_reset_rx_pll_timer_ctr_reg(2), O => \p_0_in__1\(2) ); \sm_reset_rx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(2), I1 => sm_reset_rx_pll_timer_ctr_reg(0), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(3), O => \p_0_in__1\(3) ); \sm_reset_rx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(1), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(2), I4 => sm_reset_rx_pll_timer_ctr_reg(4), O => \p_0_in__1\(4) ); \sm_reset_rx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(4), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(1), I4 => sm_reset_rx_pll_timer_ctr_reg(3), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \p_0_in__1\(5) ); \sm_reset_rx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I1 => sm_reset_rx_pll_timer_ctr_reg(6), O => \p_0_in__1\(6) ); \sm_reset_rx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(6), I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_rx_pll_timer_ctr_reg(7), O => \p_0_in__1\(7) ); \sm_reset_rx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(7), I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_rx_pll_timer_ctr_reg(6), I3 => sm_reset_rx_pll_timer_ctr_reg(8), O => \p_0_in__1\(8) ); \sm_reset_rx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFBF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(0), I4 => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\, O => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ ); \sm_reset_rx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(8), I1 => sm_reset_rx_pll_timer_ctr_reg(6), I2 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\, I3 => sm_reset_rx_pll_timer_ctr_reg(7), I4 => sm_reset_rx_pll_timer_ctr_reg(9), O => \p_0_in__1\(9) ); \sm_reset_rx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEFFFFFFFFF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(8), I1 => sm_reset_rx_pll_timer_ctr_reg(9), I2 => sm_reset_rx_pll_timer_ctr_reg(6), I3 => sm_reset_rx_pll_timer_ctr_reg(7), I4 => sm_reset_rx_pll_timer_ctr_reg(4), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ ); \sm_reset_rx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(4), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(0), I3 => sm_reset_rx_pll_timer_ctr_reg(1), I4 => sm_reset_rx_pll_timer_ctr_reg(3), I5 => sm_reset_rx_pll_timer_ctr_reg(5), O => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ ); \sm_reset_rx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(0), Q => sm_reset_rx_pll_timer_ctr_reg(0), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(1), Q => sm_reset_rx_pll_timer_ctr_reg(1), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(2), Q => sm_reset_rx_pll_timer_ctr_reg(2), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(3), Q => sm_reset_rx_pll_timer_ctr_reg(3), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(4), Q => sm_reset_rx_pll_timer_ctr_reg(4), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(5), Q => sm_reset_rx_pll_timer_ctr_reg(5), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(6), Q => sm_reset_rx_pll_timer_ctr_reg(6), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(7), Q => sm_reset_rx_pll_timer_ctr_reg(7), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(8), Q => sm_reset_rx_pll_timer_ctr_reg(8), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); \sm_reset_rx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\, D => \p_0_in__1\(9), Q => sm_reset_rx_pll_timer_ctr_reg(9), R => sm_reset_rx_pll_timer_clr_reg_n_0 ); sm_reset_rx_pll_timer_sat_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00EA" ) port map ( I0 => sm_reset_rx_pll_timer_sat, I1 => sm_reset_rx_pll_timer_sat_i_2_n_0, I2 => sm_reset_rx_pll_timer_sat_i_3_n_0, I3 => sm_reset_rx_pll_timer_clr_reg_n_0, O => sm_reset_rx_pll_timer_sat_i_1_n_0 ); sm_reset_rx_pll_timer_sat_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(3), I1 => sm_reset_rx_pll_timer_ctr_reg(2), I2 => sm_reset_rx_pll_timer_ctr_reg(1), I3 => sm_reset_rx_pll_timer_ctr_reg(0), O => sm_reset_rx_pll_timer_sat_i_2_n_0 ); sm_reset_rx_pll_timer_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => sm_reset_rx_pll_timer_ctr_reg(6), I1 => sm_reset_rx_pll_timer_ctr_reg(7), I2 => sm_reset_rx_pll_timer_ctr_reg(5), I3 => sm_reset_rx_pll_timer_ctr_reg(4), I4 => sm_reset_rx_pll_timer_ctr_reg(9), I5 => sm_reset_rx_pll_timer_ctr_reg(8), O => sm_reset_rx_pll_timer_sat_i_3_n_0 ); sm_reset_rx_pll_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_pll_timer_sat_i_1_n_0, Q => sm_reset_rx_pll_timer_sat, R => '0' ); sm_reset_rx_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0, Q => sm_reset_rx_timer_clr_reg_n_0, S => gtwiz_reset_rx_any_sync ); sm_reset_rx_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_rx_timer_ctr(2), I1 => sm_reset_rx_timer_ctr(0), I2 => sm_reset_rx_timer_ctr(1), O => sm_reset_rx_timer_ctr0_n_0 ); \sm_reset_rx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_rx_timer_ctr(0), O => \sm_reset_rx_timer_ctr[0]_i_1_n_0\ ); \sm_reset_rx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_rx_timer_ctr(0), I1 => sm_reset_rx_timer_ctr(1), O => \sm_reset_rx_timer_ctr[1]_i_1_n_0\ ); \sm_reset_rx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_rx_timer_ctr(0), I1 => sm_reset_rx_timer_ctr(1), I2 => sm_reset_rx_timer_ctr(2), O => \sm_reset_rx_timer_ctr[2]_i_1_n_0\ ); \sm_reset_rx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[0]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(0), R => sm_reset_rx_timer_clr_reg_n_0 ); \sm_reset_rx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[1]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(1), R => sm_reset_rx_timer_clr_reg_n_0 ); \sm_reset_rx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sm_reset_rx_timer_ctr0_n_0, D => \sm_reset_rx_timer_ctr[2]_i_1_n_0\, Q => sm_reset_rx_timer_ctr(2), R => sm_reset_rx_timer_clr_reg_n_0 ); sm_reset_rx_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_rx_timer_ctr(2), I1 => sm_reset_rx_timer_ctr(0), I2 => sm_reset_rx_timer_ctr(1), I3 => sm_reset_rx_timer_sat, I4 => sm_reset_rx_timer_clr_reg_n_0, O => sm_reset_rx_timer_sat_i_1_n_0 ); sm_reset_rx_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_rx_timer_sat_i_1_n_0, Q => sm_reset_rx_timer_sat, R => '0' ); sm_reset_tx_pll_timer_clr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EFEF1101" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), I2 => sm_reset_tx(0), I3 => sm_reset_tx_pll_timer_sat, I4 => sm_reset_tx_pll_timer_clr_reg_n_0, O => sm_reset_tx_pll_timer_clr_i_1_n_0 ); sm_reset_tx_pll_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_pll_timer_clr_i_1_n_0, Q => sm_reset_tx_pll_timer_clr_reg_n_0, S => gtwiz_reset_tx_any_sync ); \sm_reset_tx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(0), O => \p_0_in__0\(0) ); \sm_reset_tx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(1), I1 => sm_reset_tx_pll_timer_ctr_reg(0), O => \p_0_in__0\(1) ); \sm_reset_tx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(1), I1 => sm_reset_tx_pll_timer_ctr_reg(0), I2 => sm_reset_tx_pll_timer_ctr_reg(2), O => \p_0_in__0\(2) ); \sm_reset_tx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(2), I1 => sm_reset_tx_pll_timer_ctr_reg(0), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(3), O => \p_0_in__0\(3) ); \sm_reset_tx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(1), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(2), I4 => sm_reset_tx_pll_timer_ctr_reg(4), O => \p_0_in__0\(4) ); \sm_reset_tx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(4), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(1), I4 => sm_reset_tx_pll_timer_ctr_reg(3), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \p_0_in__0\(5) ); \sm_reset_tx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I1 => sm_reset_tx_pll_timer_ctr_reg(6), O => \p_0_in__0\(6) ); \sm_reset_tx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(6), I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_tx_pll_timer_ctr_reg(7), O => \p_0_in__0\(7) ); \sm_reset_tx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(7), I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I2 => sm_reset_tx_pll_timer_ctr_reg(6), I3 => sm_reset_tx_pll_timer_ctr_reg(8), O => \p_0_in__0\(8) ); \sm_reset_tx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFBF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(0), I4 => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\, O => sel ); \sm_reset_tx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(8), I1 => sm_reset_tx_pll_timer_ctr_reg(6), I2 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\, I3 => sm_reset_tx_pll_timer_ctr_reg(7), I4 => sm_reset_tx_pll_timer_ctr_reg(9), O => \p_0_in__0\(9) ); \sm_reset_tx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEFFFFFFFFF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(8), I1 => sm_reset_tx_pll_timer_ctr_reg(9), I2 => sm_reset_tx_pll_timer_ctr_reg(6), I3 => sm_reset_tx_pll_timer_ctr_reg(7), I4 => sm_reset_tx_pll_timer_ctr_reg(4), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ ); \sm_reset_tx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(4), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(0), I3 => sm_reset_tx_pll_timer_ctr_reg(1), I4 => sm_reset_tx_pll_timer_ctr_reg(3), I5 => sm_reset_tx_pll_timer_ctr_reg(5), O => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ ); \sm_reset_tx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(0), Q => sm_reset_tx_pll_timer_ctr_reg(0), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(1), Q => sm_reset_tx_pll_timer_ctr_reg(1), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(2), Q => sm_reset_tx_pll_timer_ctr_reg(2), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(3), Q => sm_reset_tx_pll_timer_ctr_reg(3), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(4), Q => sm_reset_tx_pll_timer_ctr_reg(4), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(5), Q => sm_reset_tx_pll_timer_ctr_reg(5), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(6), Q => sm_reset_tx_pll_timer_ctr_reg(6), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(7), Q => sm_reset_tx_pll_timer_ctr_reg(7), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(8), Q => sm_reset_tx_pll_timer_ctr_reg(8), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); \sm_reset_tx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => sel, D => \p_0_in__0\(9), Q => sm_reset_tx_pll_timer_ctr_reg(9), R => sm_reset_tx_pll_timer_clr_reg_n_0 ); sm_reset_tx_pll_timer_sat_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00EA" ) port map ( I0 => sm_reset_tx_pll_timer_sat, I1 => sm_reset_tx_pll_timer_sat_i_2_n_0, I2 => sm_reset_tx_pll_timer_sat_i_3_n_0, I3 => sm_reset_tx_pll_timer_clr_reg_n_0, O => sm_reset_tx_pll_timer_sat_i_1_n_0 ); sm_reset_tx_pll_timer_sat_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(3), I1 => sm_reset_tx_pll_timer_ctr_reg(2), I2 => sm_reset_tx_pll_timer_ctr_reg(1), I3 => sm_reset_tx_pll_timer_ctr_reg(0), O => sm_reset_tx_pll_timer_sat_i_2_n_0 ); sm_reset_tx_pll_timer_sat_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => sm_reset_tx_pll_timer_ctr_reg(6), I1 => sm_reset_tx_pll_timer_ctr_reg(7), I2 => sm_reset_tx_pll_timer_ctr_reg(5), I3 => sm_reset_tx_pll_timer_ctr_reg(4), I4 => sm_reset_tx_pll_timer_ctr_reg(9), I5 => sm_reset_tx_pll_timer_ctr_reg(8), O => sm_reset_tx_pll_timer_sat_i_3_n_0 ); sm_reset_tx_pll_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_pll_timer_sat_i_1_n_0, Q => sm_reset_tx_pll_timer_sat, R => '0' ); sm_reset_tx_timer_clr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => drpclk_in(0), CE => '1', D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1, Q => sm_reset_tx_timer_clr_reg_n_0, S => gtwiz_reset_tx_any_sync ); sm_reset_tx_timer_ctr0: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => sm_reset_tx_timer_ctr(2), I1 => sm_reset_tx_timer_ctr(0), I2 => sm_reset_tx_timer_ctr(1), O => p_0_in ); \sm_reset_tx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sm_reset_tx_timer_ctr(0), O => p_1_in(0) ); \sm_reset_tx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => sm_reset_tx_timer_ctr(0), I1 => sm_reset_tx_timer_ctr(1), O => p_1_in(1) ); \sm_reset_tx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => sm_reset_tx_timer_ctr(0), I1 => sm_reset_tx_timer_ctr(1), I2 => sm_reset_tx_timer_ctr(2), O => p_1_in(2) ); \sm_reset_tx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(0), Q => sm_reset_tx_timer_ctr(0), R => sm_reset_tx_timer_clr_reg_n_0 ); \sm_reset_tx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(1), Q => sm_reset_tx_timer_ctr(1), R => sm_reset_tx_timer_clr_reg_n_0 ); \sm_reset_tx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => p_0_in, D => p_1_in(2), Q => sm_reset_tx_timer_ctr(2), R => sm_reset_tx_timer_clr_reg_n_0 ); sm_reset_tx_timer_sat_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => sm_reset_tx_timer_ctr(2), I1 => sm_reset_tx_timer_ctr(0), I2 => sm_reset_tx_timer_ctr(1), I3 => sm_reset_tx_timer_sat, I4 => sm_reset_tx_timer_clr_reg_n_0, O => sm_reset_tx_timer_sat_i_1_n_0 ); sm_reset_tx_timer_sat_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => sm_reset_tx_timer_sat_i_1_n_0, Q => sm_reset_tx_timer_sat, R => '0' ); txuserrdy_out_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sm_reset_tx(1), I1 => sm_reset_tx(2), I2 => sm_reset_tx_timer_clr_reg_n_0, I3 => sm_reset_tx_timer_sat, O => txuserrdy_out_i_3_n_0 ); txuserrdy_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => drpclk_in(0), CE => '1', D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_3, Q => \^gen_gtwizard_gthe3.txuserrdy_int\, R => '0' ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design 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STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 : entity is "gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 is signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_gtwizard_gthe3.cpllpd_ch_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gtrxreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.gttxreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.rxprogdivreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.rxuserrdy_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.txprogdivreset_int\ : STD_LOGIC; signal \gen_gtwizard_gthe3.txuserrdy_int\ : STD_LOGIC; signal \^gtpowergood_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_in0 : STD_LOGIC; begin cplllock_out(0) <= \^cplllock_out\(0); gtpowergood_out(0) <= \^gtpowergood_out\(0); \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst\: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper port map ( cplllock_out(0) => \^cplllock_out\(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => \^gtpowergood_out\(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_userdata_rx_out(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0), gtwiz_userdata_tx_in(15 downto 0) => gtwiz_userdata_tx_in(15 downto 0), rst_in0 => rst_in0, rxbufstatus_out(0) => rxbufstatus_out(0), rxcdrlock_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4\, rxclkcorcnt_out(1 downto 0) => rxclkcorcnt_out(1 downto 0), rxctrl0_out(1 downto 0) => rxctrl0_out(1 downto 0), rxctrl1_out(1 downto 0) => rxctrl1_out(1 downto 0), rxctrl2_out(1 downto 0) => rxctrl2_out(1 downto 0), rxctrl3_out(1 downto 0) => rxctrl3_out(1 downto 0), rxmcommaalignen_in(0) => rxmcommaalignen_in(0), rxoutclk_out(0) => rxoutclk_out(0), rxpd_in(0) => rxpd_in(0), rxpmaresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6\, rxresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7\, rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => txbufstatus_out(0), txctrl0_in(1 downto 0) => txctrl0_in(1 downto 0), txctrl1_in(1 downto 0) => txctrl1_in(1 downto 0), txctrl2_in(1 downto 0) => txctrl2_in(1 downto 0), txelecidle_in(0) => txelecidle_in(0), txoutclk_out(0) => txoutclk_out(0), txresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9\ ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst\: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, rxresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7\ ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst\: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 port map ( drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, txresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9\ ); \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst\: entity work.gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset port map ( cplllock_out(0) => \^cplllock_out\(0), drpclk_in(0) => drpclk_in(0), \gen_gtwizard_gthe3.cpllpd_ch_int\ => \gen_gtwizard_gthe3.cpllpd_ch_int\, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\, \gen_gtwizard_gthe3.gtrxreset_int\ => \gen_gtwizard_gthe3.gtrxreset_int\, \gen_gtwizard_gthe3.gttxreset_int\ => \gen_gtwizard_gthe3.gttxreset_int\, \gen_gtwizard_gthe3.rxprogdivreset_int\ => \gen_gtwizard_gthe3.rxprogdivreset_int\, \gen_gtwizard_gthe3.rxuserrdy_int\ => \gen_gtwizard_gthe3.rxuserrdy_int\, \gen_gtwizard_gthe3.txprogdivreset_int\ => \gen_gtwizard_gthe3.txprogdivreset_int\, \gen_gtwizard_gthe3.txuserrdy_int\ => \gen_gtwizard_gthe3.txuserrdy_int\, gtpowergood_out(0) => \^gtpowergood_out\(0), gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0), gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), rst_in0 => rst_in0, rxcdrlock_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4\, rxpmaresetdone_out(0) => \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6\, rxusrclk_in(0) => rxusrclk_in(0) ); end STRUCTURE; `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block 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use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top is port ( gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll1lock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_qpll1reset_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gthe3_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe3_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe3_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gthe4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gthe4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_gtye4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gtye4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 ); gtwiz_gtye4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); bgbypassb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgmonitorenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgpdb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bgrcalovrd_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); bgrcalovrdenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpaddr_common_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_common_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpll0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpll1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pmarsvd0_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); pmarsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); qpll0clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0locken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0pd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); qpll0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1locken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1pd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); qpll1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpllrsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); qpllrsvd2_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpllrsvd3_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpllrsvd4_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); rcalenb_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0data_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm0width_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1data_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sdm1width_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tcongpi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconpowerup_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tconrsvdin1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubcfgstreamen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubdo_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubdrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubenable_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubgpi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubintr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubiolmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmcapture_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmdbgrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmdbgupdate_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmregen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmshift_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmsysrst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtck_in : in STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtdi_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdo_common_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_common_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pmarsvdout0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); pmarsvdout1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); qplldmonitor0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); qplldmonitor1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); refclkoutmonitor0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); refclkoutmonitor1_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclk0_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxrecclk1_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxrecclk0sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclk1sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm0finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm0testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm1finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); sdm1testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 ); tcongpo_out : out STD_LOGIC_VECTOR ( 0 to 0 ); tconrsvdout0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdaddr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubden_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdi_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubdwe_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubmdmtdo_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubrsvdout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); ubtxuart_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepdir_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepsq_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cdrstepsx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cfgreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllfreqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllocken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cpllrefclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); cpllreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); dmonfiforeset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drprst_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); elpcaldvorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); elpcalpaorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphicaldone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphicalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphidrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphidwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphixrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); evoddphixwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescantrigger_in : in STD_LOGIC_VECTOR ( 0 to 0 ); freqos_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtgrefclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtnorthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrsvd_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); gtrxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtsouthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); incpctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); looprsvd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); lpbkrxtxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); lpbktxrxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcieeqrxeqadaptdone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcierstidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pciersttxsyncstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserratedone_in : in STD_LOGIC_VECTOR ( 0 to 0 ); pcsrsvdin_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); pcsrsvdin2_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); pmarsvdin_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 ); qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); resetovrd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rstclkentx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxafecfoken_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxbufreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrfreqreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrresetrsv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbonden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondi_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); rxchbondlevel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxchbondmaster_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondslave_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxckcalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxckcalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagcctrl_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagchold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeagcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfcnum_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokfpulse_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfecfokovren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfekhhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfekhovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap10hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap10ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap11hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap11ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap12hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap12ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap13hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap13ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap14hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap14ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap15hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap15ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap2hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap2ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap3hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap3ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap4hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap4ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap5hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap5ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap6hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap6ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap7hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap7ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap8hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap8ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap9hold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfetap9ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeuthold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfeutovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevphold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevpovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfevsen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfexyden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxelecidlemode_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxeqtraining_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmgchold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmgcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmhfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmhfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmlfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmlfklovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxoobreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoscalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintcfg_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxosinten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosinthold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosinttestovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbscntreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxqpien_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslide_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslipoutclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxslippma_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxtermination_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); sigvalidclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tstin_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); tx8b10bbypass_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); tx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txbufdiffctrl_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txcominit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txcomsas_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txcomwake_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); txdata_in : in STD_LOGIC_VECTOR ( 127 downto 0 ); txdataextendrsvd_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); txdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdccreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdeemph_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdetectrx_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txdiffpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txdlyupdown_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txelforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); txinhibit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpstreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpsu2lpexit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txlfpsu3wake_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); txmargin_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txmuxdcdexhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txmuxdcdorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txoneszeros_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txpdelecidlemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphdlytstclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphinit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmpd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmsel_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpippmstepsize_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txpisopd_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txpostcursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbsforceerr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txprecursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpibiasen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpistrongpdown_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txqpiweakpup_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); txratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); txswing_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); bufgtce_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtcemask_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtdiv_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); bufgtreset_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); bufgtrstmask_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); cpllfbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); cpllrefclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorout_out : out STD_LOGIC_VECTOR ( 16 downto 0 ); dmonitoroutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); eyescandataerror_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclkmonitor_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierategen3_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierateidle_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcierateqpllpd_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); pcierateqpllreset_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); pciesynctxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieusergen3rdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserphystatusrst_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcieuserratestart_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pcsrsvdout_out : out STD_LOGIC_VECTOR ( 11 downto 0 ); phystatus_out : out STD_LOGIC_VECTOR ( 0 to 0 ); pinrsrvdas_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); powerpresent_out : out STD_LOGIC_VECTOR ( 0 to 0 ); resetexception_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrphdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanbondseq_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchanrealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxchbondo_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); rxckcaldone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxcominitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcomsasdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxcomwakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdata_out : out STD_LOGIC_VECTOR ( 127 downto 0 ); rxdataextendrsvd_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxelecidle_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxlfpstresetdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxlfpsu2lpexitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxlfpsu3wakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); rxosintdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstarted_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxosintstrobestarted_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxphalignerr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbserr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbslocked_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxrecclkout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxsliderdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslipdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslipoutclkrdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxslippmardy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxvalid_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txcomfinish_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txdccdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txphinitdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_CHANNEL_ENABLE : string; attribute C_CHANNEL_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_COMMON_SCALING_FACTOR : integer; attribute C_COMMON_SCALING_FACTOR of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_CPLL_VCO_FREQUENCY : string; attribute C_CPLL_VCO_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "2500.000000"; attribute C_ENABLE_COMMON_USRCLK : integer; attribute C_ENABLE_COMMON_USRCLK of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_FORCE_COMMONS : integer; attribute C_FORCE_COMMONS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_FREERUN_FREQUENCY : string; attribute C_FREERUN_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "50.000000"; attribute C_GT_REV : integer; attribute C_GT_REV of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 17; attribute C_GT_TYPE : integer; attribute C_GT_TYPE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_INCLUDE_CPLL_CAL : integer; attribute C_INCLUDE_CPLL_CAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_LOCATE_COMMON : integer; attribute C_LOCATE_COMMON of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_LOCATE_RESET_CONTROLLER : integer; attribute C_LOCATE_RESET_CONTROLLER of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_RX_USER_CLOCKING : integer; attribute C_LOCATE_RX_USER_CLOCKING of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_LOCATE_TX_USER_CLOCKING : integer; attribute C_LOCATE_TX_USER_CLOCKING of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer; attribute C_LOCATE_USER_DATA_WIDTH_SIZING of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_PCIE_CORECLK_FREQ : integer; attribute C_PCIE_CORECLK_FREQ of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 250; attribute C_PCIE_ENABLE : integer; attribute C_PCIE_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer; attribute C_RESET_CONTROLLER_INSTANCE_CTRL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RESET_SEQUENCE_INTERVAL : integer; attribute C_RESET_SEQUENCE_INTERVAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFBYPASS_MODE : integer; attribute C_RX_BUFFBYPASS_MODE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_BUFFER_MODE : integer; attribute C_RX_BUFFER_MODE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_DISP : string; attribute C_RX_CB_DISP of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CB_K : string; attribute C_RX_CB_K of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CB_LEN_SEQ : integer; attribute C_RX_CB_LEN_SEQ of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_MAX_LEVEL : integer; attribute C_RX_CB_MAX_LEVEL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_CB_NUM_SEQ : integer; attribute C_RX_CB_NUM_SEQ of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_CB_VAL : string; attribute C_RX_CB_VAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_CC_DISP : string; attribute C_RX_CC_DISP of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "8'b00000000"; attribute C_RX_CC_ENABLE : integer; attribute C_RX_CC_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_CC_K : string; attribute C_RX_CC_K of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "8'b00010001"; attribute C_RX_CC_LEN_SEQ : integer; attribute C_RX_CC_LEN_SEQ of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_RX_CC_NUM_SEQ : integer; attribute C_RX_CC_NUM_SEQ of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_RX_CC_PERIODICITY : integer; attribute C_RX_CC_PERIODICITY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 5000; attribute C_RX_CC_VAL : string; attribute C_RX_CC_VAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100"; attribute C_RX_COMMA_M_ENABLE : integer; attribute C_RX_COMMA_M_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_COMMA_M_VAL : string; attribute C_RX_COMMA_M_VAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "10'b1010000011"; attribute C_RX_COMMA_P_ENABLE : integer; attribute C_RX_COMMA_P_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_COMMA_P_VAL : string; attribute C_RX_COMMA_P_VAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "10'b0101111100"; attribute C_RX_DATA_DECODING : integer; attribute C_RX_DATA_DECODING of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_ENABLE : integer; attribute C_RX_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_INT_DATA_WIDTH : integer; attribute C_RX_INT_DATA_WIDTH of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 20; attribute C_RX_LINE_RATE : string; attribute C_RX_LINE_RATE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "1.250000"; attribute C_RX_MASTER_CHANNEL_IDX : integer; attribute C_RX_MASTER_CHANNEL_IDX of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 96; attribute C_RX_OUTCLK_BUFG_GT_DIV : integer; attribute C_RX_OUTCLK_BUFG_GT_DIV of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_OUTCLK_FREQUENCY : string; attribute C_RX_OUTCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_RX_OUTCLK_SOURCE : integer; attribute C_RX_OUTCLK_SOURCE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_PLL_TYPE : integer; attribute C_RX_PLL_TYPE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_RX_RECCLK_OUTPUT : string; attribute C_RX_RECCLK_OUTPUT of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_REFCLK_FREQUENCY : string; attribute C_RX_REFCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "125.000000"; attribute C_RX_SLIDE_MODE : integer; attribute C_RX_SLIDE_MODE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_CONTENTS : integer; attribute C_RX_USER_CLOCKING_CONTENTS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_RX_USER_CLOCKING_SOURCE : integer; attribute C_RX_USER_CLOCKING_SOURCE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_RX_USER_DATA_WIDTH : integer; attribute C_RX_USER_DATA_WIDTH of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 16; attribute C_RX_USRCLK2_FREQUENCY : string; attribute C_RX_USRCLK2_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_RX_USRCLK_FREQUENCY : string; attribute C_RX_USRCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_SECONDARY_QPLL_ENABLE : integer; attribute C_SECONDARY_QPLL_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "257.812500"; attribute C_SIM_CPLL_CAL_BYPASS : integer; attribute C_SIM_CPLL_CAL_BYPASS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TOTAL_NUM_CHANNELS : integer; attribute C_TOTAL_NUM_CHANNELS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TOTAL_NUM_COMMONS : integer; attribute C_TOTAL_NUM_COMMONS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer; attribute C_TOTAL_NUM_COMMONS_EXAMPLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TXPROGDIV_FREQ_ENABLE : integer; attribute C_TXPROGDIV_FREQ_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TXPROGDIV_FREQ_SOURCE : integer; attribute C_TXPROGDIV_FREQ_SOURCE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_TXPROGDIV_FREQ_VAL : string; attribute C_TXPROGDIV_FREQ_VAL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "125.000000"; attribute C_TX_BUFFBYPASS_MODE : integer; attribute C_TX_BUFFBYPASS_MODE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TX_BUFFER_MODE : integer; attribute C_TX_BUFFER_MODE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TX_DATA_ENCODING : integer; attribute C_TX_DATA_ENCODING of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TX_ENABLE : integer; attribute C_TX_ENABLE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TX_INT_DATA_WIDTH : integer; attribute C_TX_INT_DATA_WIDTH of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 20; attribute C_TX_LINE_RATE : string; attribute C_TX_LINE_RATE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "1.250000"; attribute C_TX_MASTER_CHANNEL_IDX : integer; attribute C_TX_MASTER_CHANNEL_IDX of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 96; attribute C_TX_OUTCLK_BUFG_GT_DIV : integer; attribute C_TX_OUTCLK_BUFG_GT_DIV of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_TX_OUTCLK_FREQUENCY : string; attribute C_TX_OUTCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_TX_OUTCLK_SOURCE : integer; attribute C_TX_OUTCLK_SOURCE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 4; attribute C_TX_PLL_TYPE : integer; attribute C_TX_PLL_TYPE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 2; attribute C_TX_REFCLK_FREQUENCY : string; attribute C_TX_REFCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "125.000000"; attribute C_TX_USER_CLOCKING_CONTENTS : integer; attribute C_TX_USER_CLOCKING_CONTENTS of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 1; attribute C_TX_USER_CLOCKING_SOURCE : integer; attribute C_TX_USER_CLOCKING_SOURCE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute C_TX_USER_DATA_WIDTH : integer; attribute C_TX_USER_DATA_WIDTH of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 16; attribute C_TX_USRCLK2_FREQUENCY : string; attribute C_TX_USRCLK2_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_TX_USRCLK_FREQUENCY : string; attribute C_TX_USRCLK_FREQUENCY of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "62.500000"; attribute C_USER_GTPOWERGOOD_DELAY_EN : integer; attribute C_USER_GTPOWERGOOD_DELAY_EN of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top : entity is "gig_ethernet_pcs_pma_0_gt_gtwizard_top"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top is signal \\ : STD_LOGIC; signal \^rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \^rxctrl0_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl1_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl2_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl3_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 to 1 ); begin bufgtce_out(2) <= \\; bufgtce_out(1) <= \\; bufgtce_out(0) <= \\; bufgtcemask_out(2) <= \\; bufgtcemask_out(1) <= \\; bufgtcemask_out(0) <= \\; bufgtdiv_out(8) <= \\; bufgtdiv_out(7) <= \\; bufgtdiv_out(6) <= \\; bufgtdiv_out(5) <= \\; bufgtdiv_out(4) <= \\; bufgtdiv_out(3) <= \\; bufgtdiv_out(2) <= \\; bufgtdiv_out(1) <= \\; bufgtdiv_out(0) <= \\; bufgtreset_out(2) <= \\; bufgtreset_out(1) <= \\; bufgtreset_out(0) <= \\; bufgtrstmask_out(2) <= \\; bufgtrstmask_out(1) <= \\; bufgtrstmask_out(0) <= \\; cpllfbclklost_out(0) <= \\; cpllrefclklost_out(0) <= \\; dmonitorout_out(16) <= \\; dmonitorout_out(15) <= \\; dmonitorout_out(14) <= \\; dmonitorout_out(13) <= \\; dmonitorout_out(12) <= \\; dmonitorout_out(11) <= \\; dmonitorout_out(10) <= \\; dmonitorout_out(9) <= \\; dmonitorout_out(8) <= \\; dmonitorout_out(7) <= \\; dmonitorout_out(6) <= \\; dmonitorout_out(5) <= \\; dmonitorout_out(4) <= \\; dmonitorout_out(3) <= \\; dmonitorout_out(2) <= \\; dmonitorout_out(1) <= \\; dmonitorout_out(0) <= \\; dmonitoroutclk_out(0) <= \\; drpdo_common_out(15) <= \\; drpdo_common_out(14) <= \\; drpdo_common_out(13) <= \\; drpdo_common_out(12) <= \\; drpdo_common_out(11) <= \\; drpdo_common_out(10) <= \\; drpdo_common_out(9) <= \\; drpdo_common_out(8) <= \\; drpdo_common_out(7) <= \\; drpdo_common_out(6) <= \\; drpdo_common_out(5) <= \\; drpdo_common_out(4) <= \\; drpdo_common_out(3) <= \\; drpdo_common_out(2) <= \\; drpdo_common_out(1) <= \\; drpdo_common_out(0) <= \\; drpdo_out(15) <= \\; drpdo_out(14) <= \\; drpdo_out(13) <= \\; drpdo_out(12) <= \\; drpdo_out(11) <= \\; drpdo_out(10) <= \\; drpdo_out(9) <= \\; drpdo_out(8) <= \\; drpdo_out(7) <= \\; drpdo_out(6) <= \\; drpdo_out(5) <= \\; drpdo_out(4) <= \\; drpdo_out(3) <= \\; drpdo_out(2) <= \\; drpdo_out(1) <= \\; drpdo_out(0) <= \\; drprdy_common_out(0) <= \\; drprdy_out(0) <= \\; eyescandataerror_out(0) <= \\; gtrefclkmonitor_out(0) <= \\; gtwiz_buffbypass_rx_done_out(0) <= \\; gtwiz_buffbypass_rx_error_out(0) <= \\; gtwiz_buffbypass_tx_done_out(0) <= \\; gtwiz_buffbypass_tx_error_out(0) <= \\; gtwiz_reset_qpll0reset_out(0) <= \\; gtwiz_reset_qpll1reset_out(0) <= \\; gtwiz_reset_rx_cdr_stable_out(0) <= \\; gtwiz_userclk_rx_active_out(0) <= \\; gtwiz_userclk_rx_srcclk_out(0) <= \\; gtwiz_userclk_rx_usrclk2_out(0) <= \\; gtwiz_userclk_rx_usrclk_out(0) <= \\; gtwiz_userclk_tx_active_out(0) <= \\; gtwiz_userclk_tx_srcclk_out(0) <= \\; gtwiz_userclk_tx_usrclk2_out(0) <= \\; gtwiz_userclk_tx_usrclk_out(0) <= \\; gtytxn_out(0) <= \\; gtytxp_out(0) <= \\; pcierategen3_out(0) <= \\; pcierateidle_out(0) <= \\; pcierateqpllpd_out(1) <= \\; pcierateqpllpd_out(0) <= \\; pcierateqpllreset_out(1) <= \\; pcierateqpllreset_out(0) <= \\; pciesynctxsyncdone_out(0) <= \\; pcieusergen3rdy_out(0) <= \\; pcieuserphystatusrst_out(0) <= \\; pcieuserratestart_out(0) <= \\; pcsrsvdout_out(11) <= \\; pcsrsvdout_out(10) <= \\; pcsrsvdout_out(9) <= \\; pcsrsvdout_out(8) <= \\; pcsrsvdout_out(7) <= \\; pcsrsvdout_out(6) <= \\; pcsrsvdout_out(5) <= \\; pcsrsvdout_out(4) <= \\; pcsrsvdout_out(3) <= \\; pcsrsvdout_out(2) <= \\; pcsrsvdout_out(1) <= \\; pcsrsvdout_out(0) <= \\; phystatus_out(0) <= \\; pinrsrvdas_out(7) <= \\; pinrsrvdas_out(6) <= \\; pinrsrvdas_out(5) <= \\; pinrsrvdas_out(4) <= \\; pinrsrvdas_out(3) <= \\; pinrsrvdas_out(2) <= \\; pinrsrvdas_out(1) <= \\; pinrsrvdas_out(0) <= \\; pmarsvdout0_out(7) <= \\; pmarsvdout0_out(6) <= \\; pmarsvdout0_out(5) <= \\; pmarsvdout0_out(4) <= \\; pmarsvdout0_out(3) <= \\; pmarsvdout0_out(2) <= \\; pmarsvdout0_out(1) <= \\; pmarsvdout0_out(0) <= \\; pmarsvdout1_out(7) <= \\; pmarsvdout1_out(6) <= \\; pmarsvdout1_out(5) <= \\; pmarsvdout1_out(4) <= \\; pmarsvdout1_out(3) <= \\; pmarsvdout1_out(2) <= \\; pmarsvdout1_out(1) <= \\; pmarsvdout1_out(0) <= \\; powerpresent_out(0) <= \\; qpll0fbclklost_out(0) <= \\; qpll0lock_out(0) <= \\; qpll0outclk_out(0) <= \\; qpll0outrefclk_out(0) <= \\; qpll0refclklost_out(0) <= \\; qpll1fbclklost_out(0) <= \\; qpll1lock_out(0) <= \\; qpll1outclk_out(0) <= \\; qpll1outrefclk_out(0) <= \\; qpll1refclklost_out(0) <= \\; qplldmonitor0_out(7) <= \\; qplldmonitor0_out(6) <= \\; qplldmonitor0_out(5) <= \\; qplldmonitor0_out(4) <= \\; qplldmonitor0_out(3) <= \\; qplldmonitor0_out(2) <= \\; qplldmonitor0_out(1) <= \\; qplldmonitor0_out(0) <= \\; qplldmonitor1_out(7) <= \\; qplldmonitor1_out(6) <= \\; qplldmonitor1_out(5) <= \\; qplldmonitor1_out(4) <= \\; qplldmonitor1_out(3) <= \\; qplldmonitor1_out(2) <= \\; qplldmonitor1_out(1) <= \\; qplldmonitor1_out(0) <= \\; refclkoutmonitor0_out(0) <= \\; refclkoutmonitor1_out(0) <= \\; resetexception_out(0) <= \\; rxbufstatus_out(2) <= \^rxbufstatus_out\(2); rxbufstatus_out(1) <= \\; rxbufstatus_out(0) <= \\; rxbyteisaligned_out(0) <= \\; rxbyterealign_out(0) <= \\; rxcdrlock_out(0) <= \\; rxcdrphdone_out(0) <= \\; rxchanbondseq_out(0) <= \\; rxchanisaligned_out(0) <= \\; rxchanrealign_out(0) <= \\; rxchbondo_out(4) <= \\; rxchbondo_out(3) <= \\; rxchbondo_out(2) <= \\; rxchbondo_out(1) <= \\; rxchbondo_out(0) <= \\; rxckcaldone_out(0) <= \\; rxcominitdet_out(0) <= \\; rxcommadet_out(0) <= \\; rxcomsasdet_out(0) <= \\; rxcomwakedet_out(0) <= \\; rxctrl0_out(15) <= \\; rxctrl0_out(14) <= \\; rxctrl0_out(13) <= \\; rxctrl0_out(12) <= \\; rxctrl0_out(11) <= \\; rxctrl0_out(10) <= \\; rxctrl0_out(9) <= \\; rxctrl0_out(8) <= \\; rxctrl0_out(7) <= \\; rxctrl0_out(6) <= \\; rxctrl0_out(5) <= \\; rxctrl0_out(4) <= \\; rxctrl0_out(3) <= \\; rxctrl0_out(2) <= \\; rxctrl0_out(1 downto 0) <= \^rxctrl0_out\(1 downto 0); rxctrl1_out(15) <= \\; rxctrl1_out(14) <= \\; rxctrl1_out(13) <= \\; rxctrl1_out(12) <= \\; rxctrl1_out(11) <= \\; rxctrl1_out(10) <= \\; rxctrl1_out(9) <= \\; rxctrl1_out(8) <= \\; rxctrl1_out(7) <= \\; rxctrl1_out(6) <= \\; rxctrl1_out(5) <= \\; rxctrl1_out(4) <= \\; rxctrl1_out(3) <= \\; rxctrl1_out(2) <= \\; rxctrl1_out(1 downto 0) <= \^rxctrl1_out\(1 downto 0); rxctrl2_out(7) <= \\; rxctrl2_out(6) <= \\; rxctrl2_out(5) <= \\; rxctrl2_out(4) <= \\; rxctrl2_out(3) <= \\; rxctrl2_out(2) <= \\; rxctrl2_out(1 downto 0) <= \^rxctrl2_out\(1 downto 0); rxctrl3_out(7) <= \\; rxctrl3_out(6) <= \\; rxctrl3_out(5) <= \\; rxctrl3_out(4) <= \\; rxctrl3_out(3) <= \\; rxctrl3_out(2) <= \\; rxctrl3_out(1 downto 0) <= \^rxctrl3_out\(1 downto 0); rxdata_out(127) <= \\; rxdata_out(126) <= \\; rxdata_out(125) <= \\; rxdata_out(124) <= \\; rxdata_out(123) <= \\; rxdata_out(122) <= \\; rxdata_out(121) <= \\; rxdata_out(120) <= \\; rxdata_out(119) <= \\; rxdata_out(118) <= \\; rxdata_out(117) <= \\; rxdata_out(116) <= \\; rxdata_out(115) <= \\; rxdata_out(114) <= \\; rxdata_out(113) <= \\; rxdata_out(112) <= \\; rxdata_out(111) <= \\; rxdata_out(110) <= \\; rxdata_out(109) <= \\; rxdata_out(108) <= \\; rxdata_out(107) <= \\; rxdata_out(106) <= \\; rxdata_out(105) <= \\; rxdata_out(104) <= \\; rxdata_out(103) <= \\; rxdata_out(102) <= \\; rxdata_out(101) <= \\; rxdata_out(100) <= \\; rxdata_out(99) <= \\; rxdata_out(98) <= \\; rxdata_out(97) <= \\; rxdata_out(96) <= \\; rxdata_out(95) <= \\; rxdata_out(94) <= \\; rxdata_out(93) <= \\; rxdata_out(92) <= \\; rxdata_out(91) <= \\; rxdata_out(90) <= \\; rxdata_out(89) <= \\; rxdata_out(88) <= \\; rxdata_out(87) <= \\; rxdata_out(86) <= \\; rxdata_out(85) <= \\; rxdata_out(84) <= \\; rxdata_out(83) <= \\; rxdata_out(82) <= \\; rxdata_out(81) <= \\; rxdata_out(80) <= \\; rxdata_out(79) <= \\; rxdata_out(78) <= \\; rxdata_out(77) <= \\; rxdata_out(76) <= \\; rxdata_out(75) <= \\; rxdata_out(74) <= \\; rxdata_out(73) <= \\; rxdata_out(72) <= \\; rxdata_out(71) <= \\; rxdata_out(70) <= \\; rxdata_out(69) <= \\; rxdata_out(68) <= \\; rxdata_out(67) <= \\; rxdata_out(66) <= \\; rxdata_out(65) <= \\; rxdata_out(64) <= \\; rxdata_out(63) <= \\; rxdata_out(62) <= \\; rxdata_out(61) <= \\; rxdata_out(60) <= \\; rxdata_out(59) <= \\; rxdata_out(58) <= \\; rxdata_out(57) <= \\; rxdata_out(56) <= \\; rxdata_out(55) <= \\; rxdata_out(54) <= \\; rxdata_out(53) <= \\; rxdata_out(52) <= \\; rxdata_out(51) <= \\; rxdata_out(50) <= \\; rxdata_out(49) <= \\; rxdata_out(48) <= \\; rxdata_out(47) <= \\; rxdata_out(46) <= \\; rxdata_out(45) <= \\; rxdata_out(44) <= \\; rxdata_out(43) <= \\; rxdata_out(42) <= \\; rxdata_out(41) <= \\; rxdata_out(40) <= \\; rxdata_out(39) <= \\; rxdata_out(38) <= \\; rxdata_out(37) <= \\; rxdata_out(36) <= \\; rxdata_out(35) <= \\; rxdata_out(34) <= \\; rxdata_out(33) <= \\; rxdata_out(32) <= \\; rxdata_out(31) <= \\; rxdata_out(30) <= \\; rxdata_out(29) <= \\; rxdata_out(28) <= \\; rxdata_out(27) <= \\; rxdata_out(26) <= \\; rxdata_out(25) <= \\; rxdata_out(24) <= \\; rxdata_out(23) <= \\; rxdata_out(22) <= \\; rxdata_out(21) <= \\; rxdata_out(20) <= \\; rxdata_out(19) <= \\; rxdata_out(18) <= \\; rxdata_out(17) <= \\; rxdata_out(16) <= \\; rxdata_out(15) <= \\; rxdata_out(14) <= \\; rxdata_out(13) <= \\; rxdata_out(12) <= \\; rxdata_out(11) <= \\; rxdata_out(10) <= \\; rxdata_out(9) <= \\; rxdata_out(8) <= \\; rxdata_out(7) <= \\; rxdata_out(6) <= \\; rxdata_out(5) <= \\; rxdata_out(4) <= \\; rxdata_out(3) <= \\; rxdata_out(2) <= \\; rxdata_out(1) <= \\; rxdata_out(0) <= \\; rxdataextendrsvd_out(7) <= \\; rxdataextendrsvd_out(6) <= \\; rxdataextendrsvd_out(5) <= \\; rxdataextendrsvd_out(4) <= \\; rxdataextendrsvd_out(3) <= \\; rxdataextendrsvd_out(2) <= \\; rxdataextendrsvd_out(1) <= \\; rxdataextendrsvd_out(0) <= \\; rxdatavalid_out(1) <= \\; rxdatavalid_out(0) <= \\; rxdlysresetdone_out(0) <= \\; rxelecidle_out(0) <= \\; rxheader_out(5) <= \\; rxheader_out(4) <= \\; rxheader_out(3) <= \\; rxheader_out(2) <= \\; rxheader_out(1) <= \\; rxheader_out(0) <= \\; rxheadervalid_out(1) <= \\; rxheadervalid_out(0) <= \\; rxlfpstresetdet_out(0) <= \\; rxlfpsu2lpexitdet_out(0) <= \\; rxlfpsu3wakedet_out(0) <= \\; rxmonitorout_out(6) <= \\; rxmonitorout_out(5) <= \\; rxmonitorout_out(4) <= \\; rxmonitorout_out(3) <= \\; rxmonitorout_out(2) <= \\; rxmonitorout_out(1) <= \\; rxmonitorout_out(0) <= \\; rxosintdone_out(0) <= \\; rxosintstarted_out(0) <= \\; rxosintstrobedone_out(0) <= \\; rxosintstrobestarted_out(0) <= \\; rxoutclkfabric_out(0) <= \\; rxoutclkpcs_out(0) <= \\; rxphaligndone_out(0) <= \\; rxphalignerr_out(0) <= \\; rxpmaresetdone_out(0) <= \\; rxprbserr_out(0) <= \\; rxprbslocked_out(0) <= \\; rxprgdivresetdone_out(0) <= \\; rxqpisenn_out(0) <= \\; rxqpisenp_out(0) <= \\; rxratedone_out(0) <= \\; rxrecclk0_sel_out(1) <= \\; rxrecclk0_sel_out(0) <= \\; rxrecclk0sel_out(0) <= \\; rxrecclk1_sel_out(1) <= \\; rxrecclk1_sel_out(0) <= \\; rxrecclk1sel_out(0) <= \\; rxrecclkout_out(0) <= \\; rxresetdone_out(0) <= \\; rxsliderdy_out(0) <= \\; rxslipdone_out(0) <= \\; rxslipoutclkrdy_out(0) <= \\; rxslippmardy_out(0) <= \\; rxstartofseq_out(1) <= \\; rxstartofseq_out(0) <= \\; rxstatus_out(2) <= \\; rxstatus_out(1) <= \\; rxstatus_out(0) <= \\; rxsyncdone_out(0) <= \\; rxsyncout_out(0) <= \\; rxvalid_out(0) <= \\; sdm0finalout_out(0) <= \\; sdm0testdata_out(0) <= \\; sdm1finalout_out(0) <= \\; sdm1testdata_out(0) <= \\; tcongpo_out(0) <= \\; tconrsvdout0_out(0) <= \\; txbufstatus_out(1) <= \^txbufstatus_out\(1); txbufstatus_out(0) <= \\; txcomfinish_out(0) <= \\; txdccdone_out(0) <= \\; txdlysresetdone_out(0) <= \\; txoutclkfabric_out(0) <= \\; txoutclkpcs_out(0) <= \\; txphaligndone_out(0) <= \\; txphinitdone_out(0) <= \\; txpmaresetdone_out(0) <= \\; txprgdivresetdone_out(0) <= \\; txqpisenn_out(0) <= \\; txqpisenp_out(0) <= \\; txratedone_out(0) <= \\; txresetdone_out(0) <= \\; txsyncdone_out(0) <= \\; txsyncout_out(0) <= \\; ubdaddr_out(0) <= \\; ubden_out(0) <= \\; ubdi_out(0) <= \\; ubdwe_out(0) <= \\; ubmdmtdo_out(0) <= \\; ubrsvdout_out(0) <= \\; ubtxuart_out(0) <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); \gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst\: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 port map ( cplllock_out(0) => cplllock_out(0), drpclk_in(0) => drpclk_in(0), gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtpowergood_out(0) => gtpowergood_out(0), gtrefclk0_in(0) => gtrefclk0_in(0), gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0), gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), gtwiz_userdata_rx_out(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0), gtwiz_userdata_tx_in(15 downto 0) => gtwiz_userdata_tx_in(15 downto 0), rxbufstatus_out(0) => \^rxbufstatus_out\(2), rxclkcorcnt_out(1 downto 0) => rxclkcorcnt_out(1 downto 0), rxctrl0_out(1 downto 0) => \^rxctrl0_out\(1 downto 0), rxctrl1_out(1 downto 0) => \^rxctrl1_out\(1 downto 0), rxctrl2_out(1 downto 0) => \^rxctrl2_out\(1 downto 0), rxctrl3_out(1 downto 0) => \^rxctrl3_out\(1 downto 0), rxmcommaalignen_in(0) => rxmcommaalignen_in(0), rxoutclk_out(0) => rxoutclk_out(0), rxpd_in(0) => rxpd_in(1), rxusrclk_in(0) => rxusrclk_in(0), txbufstatus_out(0) => \^txbufstatus_out\(1), txctrl0_in(1 downto 0) => txctrl0_in(1 downto 0), txctrl1_in(1 downto 0) => txctrl1_in(1 downto 0), txctrl2_in(1 downto 0) => txctrl2_in(1 downto 0), txelecidle_in(0) => txelecidle_in(0), txoutclk_out(0) => txoutclk_out(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt is port ( gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); cpllrefclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescanreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); eyescantrigger_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); pcsrsvdin_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); rx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxbufreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxlpmen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbscntreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); rxrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); tx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txctrl0_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl1_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); txctrl2_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txinhibit_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); txpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txprbsforceerr_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 ); txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); dmonitorout_out : out STD_LOGIC_VECTOR ( 16 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 ); eyescandataerror_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxctrl0_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl1_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); rxctrl2_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxctrl3_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxprbserr_out : out STD_LOGIC_VECTOR ( 0 to 0 ); rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt : entity is "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt : entity is "gig_ethernet_pcs_pma_0_gt"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt : entity is "yes"; attribute x_core_info : string; attribute x_core_info of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt : entity is "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt is signal \\ : STD_LOGIC; signal \^rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \^rxctrl0_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl1_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl2_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^rxctrl3_out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_inst_bufgtce_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtcemask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtdiv_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_inst_bufgtreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_bufgtrstmask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_cpllfbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_cpllrefclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); signal NLW_inst_dmonitoroutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_drpdo_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_inst_drpdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_inst_drprdy_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_drprdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtrefclkmonitor_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtytxn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_gtytxp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierategen3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierateidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcierateqpllpd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_pcierateqpllreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_pciesynctxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieusergen3rdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieuserphystatusrst_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcieuserratestart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pcsrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_phystatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_pinrsrvdas_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_pmarsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_pmarsvdout1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_powerpresent_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll0refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qpll1refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_qplldmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_qplldmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_refclkoutmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_refclkoutmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_resetexception_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcdrlock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcdrphdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanbondseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchanrealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxchbondo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_inst_rxckcaldone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcominitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcomsasdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxcomwakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 ); signal NLW_inst_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 ); signal NLW_inst_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_inst_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_inst_rxdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 ); signal NLW_inst_rxdataextendrsvd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_rxdatavalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxelecidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxheader_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_rxheadervalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxlfpstresetdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 ); signal NLW_inst_rxosintdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstrobedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxosintstrobestarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxphalignerr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxpmaresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprbslocked_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclk0_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxrecclk0sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclk1_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxrecclk1sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxrecclkout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxsliderdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslipdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslipoutclkrdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxslippmardy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxstartofseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_rxstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_rxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_rxvalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm0finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm0testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm1finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_sdm1testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_tcongpo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_tconrsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txcomfinish_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txdccdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txphinitdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txpmaresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_txsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubden_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdi_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubdwe_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubmdmtdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_ubtxuart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_CHANNEL_ENABLE : string; attribute C_CHANNEL_ENABLE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_COMMON_SCALING_FACTOR : integer; attribute C_COMMON_SCALING_FACTOR of inst : label is 1; attribute C_CPLL_VCO_FREQUENCY : string; attribute C_CPLL_VCO_FREQUENCY of inst : label is "2500.000000"; attribute C_ENABLE_COMMON_USRCLK : integer; attribute C_ENABLE_COMMON_USRCLK of inst : label is 0; attribute C_FORCE_COMMONS : integer; attribute C_FORCE_COMMONS of inst : label is 0; attribute C_FREERUN_FREQUENCY : string; attribute C_FREERUN_FREQUENCY of inst : label is "50.000000"; attribute C_GT_REV : integer; attribute C_GT_REV of inst : label is 17; attribute C_GT_TYPE : integer; attribute C_GT_TYPE of inst : label is 0; attribute C_INCLUDE_CPLL_CAL : integer; attribute C_INCLUDE_CPLL_CAL of inst : label is 2; attribute C_LOCATE_COMMON : integer; attribute C_LOCATE_COMMON of inst : label is 0; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer; attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of inst : label is 2; attribute C_LOCATE_RESET_CONTROLLER : integer; attribute C_LOCATE_RESET_CONTROLLER of inst : label is 0; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of inst : label is 0; attribute C_LOCATE_RX_USER_CLOCKING : integer; attribute C_LOCATE_RX_USER_CLOCKING of inst : label is 1; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer; attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of inst : label is 0; attribute C_LOCATE_TX_USER_CLOCKING : integer; attribute C_LOCATE_TX_USER_CLOCKING of inst : label is 1; attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer; attribute C_LOCATE_USER_DATA_WIDTH_SIZING of inst : label is 0; attribute C_PCIE_CORECLK_FREQ : integer; attribute C_PCIE_CORECLK_FREQ of inst : label is 250; attribute C_PCIE_ENABLE : integer; attribute C_PCIE_ENABLE of inst : label is 0; attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer; attribute C_RESET_CONTROLLER_INSTANCE_CTRL of inst : label is 0; attribute C_RESET_SEQUENCE_INTERVAL : integer; attribute C_RESET_SEQUENCE_INTERVAL of inst : label is 0; attribute C_RX_BUFFBYPASS_MODE : integer; attribute C_RX_BUFFBYPASS_MODE of inst : label is 0; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0; attribute C_RX_BUFFER_MODE : integer; attribute C_RX_BUFFER_MODE of inst : label is 1; attribute C_RX_CB_DISP : string; attribute C_RX_CB_DISP of inst : label is "8'b00000000"; attribute C_RX_CB_K : string; attribute C_RX_CB_K of inst : label is "8'b00000000"; attribute C_RX_CB_LEN_SEQ : integer; attribute C_RX_CB_LEN_SEQ of inst : label is 1; attribute C_RX_CB_MAX_LEVEL : integer; attribute C_RX_CB_MAX_LEVEL of inst : label is 1; attribute C_RX_CB_NUM_SEQ : integer; attribute C_RX_CB_NUM_SEQ of inst : label is 0; attribute C_RX_CB_VAL : string; attribute C_RX_CB_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_CC_DISP : string; attribute C_RX_CC_DISP of inst : label is "8'b00000000"; attribute C_RX_CC_ENABLE : integer; attribute C_RX_CC_ENABLE of inst : label is 1; attribute C_RX_CC_K : string; attribute C_RX_CC_K of inst : label is "8'b00010001"; attribute C_RX_CC_LEN_SEQ : integer; attribute C_RX_CC_LEN_SEQ of inst : label is 2; attribute C_RX_CC_NUM_SEQ : integer; attribute C_RX_CC_NUM_SEQ of inst : label is 2; attribute C_RX_CC_PERIODICITY : integer; attribute C_RX_CC_PERIODICITY of inst : label is 5000; attribute C_RX_CC_VAL : string; attribute C_RX_CC_VAL of inst : label is "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100"; attribute C_RX_COMMA_M_ENABLE : integer; attribute C_RX_COMMA_M_ENABLE of inst : label is 1; attribute C_RX_COMMA_M_VAL : string; attribute C_RX_COMMA_M_VAL of inst : label is "10'b1010000011"; attribute C_RX_COMMA_P_ENABLE : integer; attribute C_RX_COMMA_P_ENABLE of inst : label is 1; attribute C_RX_COMMA_P_VAL : string; attribute C_RX_COMMA_P_VAL of inst : label is "10'b0101111100"; attribute C_RX_DATA_DECODING : integer; attribute C_RX_DATA_DECODING of inst : label is 1; attribute C_RX_ENABLE : integer; attribute C_RX_ENABLE of inst : label is 1; attribute C_RX_INT_DATA_WIDTH : integer; attribute C_RX_INT_DATA_WIDTH of inst : label is 20; attribute C_RX_LINE_RATE : string; attribute C_RX_LINE_RATE of inst : label is "1.250000"; attribute C_RX_MASTER_CHANNEL_IDX : integer; attribute C_RX_MASTER_CHANNEL_IDX of inst : label is 96; attribute C_RX_OUTCLK_BUFG_GT_DIV : integer; attribute C_RX_OUTCLK_BUFG_GT_DIV of inst : label is 1; attribute C_RX_OUTCLK_FREQUENCY : string; attribute C_RX_OUTCLK_FREQUENCY of inst : label is "62.500000"; attribute C_RX_OUTCLK_SOURCE : integer; attribute C_RX_OUTCLK_SOURCE of inst : label is 1; attribute C_RX_PLL_TYPE : integer; attribute C_RX_PLL_TYPE of inst : label is 2; attribute C_RX_RECCLK_OUTPUT : string; attribute C_RX_RECCLK_OUTPUT of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_RX_REFCLK_FREQUENCY : string; attribute C_RX_REFCLK_FREQUENCY of inst : label is "125.000000"; attribute C_RX_SLIDE_MODE : integer; attribute C_RX_SLIDE_MODE of inst : label is 0; attribute C_RX_USER_CLOCKING_CONTENTS : integer; attribute C_RX_USER_CLOCKING_CONTENTS of inst : label is 0; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1; attribute C_RX_USER_CLOCKING_SOURCE : integer; attribute C_RX_USER_CLOCKING_SOURCE of inst : label is 0; attribute C_RX_USER_DATA_WIDTH : integer; attribute C_RX_USER_DATA_WIDTH of inst : label is 16; attribute C_RX_USRCLK2_FREQUENCY : string; attribute C_RX_USRCLK2_FREQUENCY of inst : label is "62.500000"; attribute C_RX_USRCLK_FREQUENCY : string; attribute C_RX_USRCLK_FREQUENCY of inst : label is "62.500000"; attribute C_SECONDARY_QPLL_ENABLE : integer; attribute C_SECONDARY_QPLL_ENABLE of inst : label is 0; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string; attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of inst : label is "257.812500"; attribute C_SIM_CPLL_CAL_BYPASS : integer; attribute C_SIM_CPLL_CAL_BYPASS of inst : label is 1; attribute C_TOTAL_NUM_CHANNELS : integer; attribute C_TOTAL_NUM_CHANNELS of inst : label is 1; attribute C_TOTAL_NUM_COMMONS : integer; attribute C_TOTAL_NUM_COMMONS of inst : label is 0; attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer; attribute C_TOTAL_NUM_COMMONS_EXAMPLE of inst : label is 0; attribute C_TXPROGDIV_FREQ_ENABLE : integer; attribute C_TXPROGDIV_FREQ_ENABLE of inst : label is 1; attribute C_TXPROGDIV_FREQ_SOURCE : integer; attribute C_TXPROGDIV_FREQ_SOURCE of inst : label is 2; attribute C_TXPROGDIV_FREQ_VAL : string; attribute C_TXPROGDIV_FREQ_VAL of inst : label is "125.000000"; attribute C_TX_BUFFBYPASS_MODE : integer; attribute C_TX_BUFFBYPASS_MODE of inst : label is 0; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer; attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0; attribute C_TX_BUFFER_MODE : integer; attribute C_TX_BUFFER_MODE of inst : label is 1; attribute C_TX_DATA_ENCODING : integer; attribute C_TX_DATA_ENCODING of inst : label is 1; attribute C_TX_ENABLE : integer; attribute C_TX_ENABLE of inst : label is 1; attribute C_TX_INT_DATA_WIDTH : integer; attribute C_TX_INT_DATA_WIDTH of inst : label is 20; attribute C_TX_LINE_RATE : string; attribute C_TX_LINE_RATE of inst : label is "1.250000"; attribute C_TX_MASTER_CHANNEL_IDX : integer; attribute C_TX_MASTER_CHANNEL_IDX of inst : label is 96; attribute C_TX_OUTCLK_BUFG_GT_DIV : integer; attribute C_TX_OUTCLK_BUFG_GT_DIV of inst : label is 2; attribute C_TX_OUTCLK_FREQUENCY : string; attribute C_TX_OUTCLK_FREQUENCY of inst : label is "62.500000"; attribute C_TX_OUTCLK_SOURCE : integer; attribute C_TX_OUTCLK_SOURCE of inst : label is 4; attribute C_TX_PLL_TYPE : integer; attribute C_TX_PLL_TYPE of inst : label is 2; attribute C_TX_REFCLK_FREQUENCY : string; attribute C_TX_REFCLK_FREQUENCY of inst : label is "125.000000"; attribute C_TX_USER_CLOCKING_CONTENTS : integer; attribute C_TX_USER_CLOCKING_CONTENTS of inst : label is 0; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer; attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer; attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer; attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1; attribute C_TX_USER_CLOCKING_SOURCE : integer; attribute C_TX_USER_CLOCKING_SOURCE of inst : label is 0; attribute C_TX_USER_DATA_WIDTH : integer; attribute C_TX_USER_DATA_WIDTH of inst : label is 16; attribute C_TX_USRCLK2_FREQUENCY : string; attribute C_TX_USRCLK2_FREQUENCY of inst : label is "62.500000"; attribute C_TX_USRCLK_FREQUENCY : string; attribute C_TX_USRCLK_FREQUENCY of inst : label is "62.500000"; attribute C_USER_GTPOWERGOOD_DELAY_EN : integer; attribute C_USER_GTPOWERGOOD_DELAY_EN of inst : label is 0; begin dmonitorout_out(16) <= \\; dmonitorout_out(15) <= \\; dmonitorout_out(14) <= \\; dmonitorout_out(13) <= \\; dmonitorout_out(12) <= \\; dmonitorout_out(11) <= \\; dmonitorout_out(10) <= \\; dmonitorout_out(9) <= \\; dmonitorout_out(8) <= \\; dmonitorout_out(7) <= \\; dmonitorout_out(6) <= \\; dmonitorout_out(5) <= \\; dmonitorout_out(4) <= \\; dmonitorout_out(3) <= \\; dmonitorout_out(2) <= \\; dmonitorout_out(1) <= \\; dmonitorout_out(0) <= \\; drpdo_out(15) <= \\; drpdo_out(14) <= \\; drpdo_out(13) <= \\; drpdo_out(12) <= \\; drpdo_out(11) <= \\; drpdo_out(10) <= \\; drpdo_out(9) <= \\; drpdo_out(8) <= \\; drpdo_out(7) <= \\; drpdo_out(6) <= \\; drpdo_out(5) <= \\; drpdo_out(4) <= \\; drpdo_out(3) <= \\; drpdo_out(2) <= \\; drpdo_out(1) <= \\; drpdo_out(0) <= \\; drprdy_out(0) <= \\; eyescandataerror_out(0) <= \\; gtwiz_reset_rx_cdr_stable_out(0) <= \\; rxbufstatus_out(2) <= \^rxbufstatus_out\(2); rxbufstatus_out(1) <= \\; rxbufstatus_out(0) <= \\; rxbyteisaligned_out(0) <= \\; rxbyterealign_out(0) <= \\; rxcommadet_out(0) <= \\; rxctrl0_out(15) <= \\; rxctrl0_out(14) <= \\; rxctrl0_out(13) <= \\; rxctrl0_out(12) <= \\; rxctrl0_out(11) <= \\; rxctrl0_out(10) <= \\; rxctrl0_out(9) <= \\; rxctrl0_out(8) <= \\; rxctrl0_out(7) <= \\; rxctrl0_out(6) <= \\; rxctrl0_out(5) <= \\; rxctrl0_out(4) <= \\; rxctrl0_out(3) <= \\; rxctrl0_out(2) <= \\; rxctrl0_out(1 downto 0) <= \^rxctrl0_out\(1 downto 0); rxctrl1_out(15) <= \\; rxctrl1_out(14) <= \\; rxctrl1_out(13) <= \\; rxctrl1_out(12) <= \\; rxctrl1_out(11) <= \\; rxctrl1_out(10) <= \\; rxctrl1_out(9) <= \\; rxctrl1_out(8) <= \\; rxctrl1_out(7) <= \\; rxctrl1_out(6) <= \\; rxctrl1_out(5) <= \\; rxctrl1_out(4) <= \\; rxctrl1_out(3) <= \\; rxctrl1_out(2) <= \\; rxctrl1_out(1 downto 0) <= \^rxctrl1_out\(1 downto 0); rxctrl2_out(7) <= \\; rxctrl2_out(6) <= \\; rxctrl2_out(5) <= \\; rxctrl2_out(4) <= \\; rxctrl2_out(3) <= \\; rxctrl2_out(2) <= \\; rxctrl2_out(1 downto 0) <= \^rxctrl2_out\(1 downto 0); rxctrl3_out(7) <= \\; rxctrl3_out(6) <= \\; rxctrl3_out(5) <= \\; rxctrl3_out(4) <= \\; rxctrl3_out(3) <= \\; rxctrl3_out(2) <= \\; rxctrl3_out(1 downto 0) <= \^rxctrl3_out\(1 downto 0); rxpmaresetdone_out(0) <= \\; rxprbserr_out(0) <= \\; rxresetdone_out(0) <= \\; txbufstatus_out(1) <= \^txbufstatus_out\(1); txbufstatus_out(0) <= \\; txpmaresetdone_out(0) <= \\; txprgdivresetdone_out(0) <= \\; txresetdone_out(0) <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); inst: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top port map ( bgbypassb_in(0) => '1', bgmonitorenb_in(0) => '1', bgpdb_in(0) => '1', bgrcalovrd_in(4 downto 0) => B"11111", bgrcalovrdenb_in(0) => '1', bufgtce_out(2 downto 0) => NLW_inst_bufgtce_out_UNCONNECTED(2 downto 0), bufgtcemask_out(2 downto 0) => NLW_inst_bufgtcemask_out_UNCONNECTED(2 downto 0), bufgtdiv_out(8 downto 0) => NLW_inst_bufgtdiv_out_UNCONNECTED(8 downto 0), bufgtreset_out(2 downto 0) => NLW_inst_bufgtreset_out_UNCONNECTED(2 downto 0), bufgtrstmask_out(2 downto 0) => NLW_inst_bufgtrstmask_out_UNCONNECTED(2 downto 0), cdrstepdir_in(0) => '0', cdrstepsq_in(0) => '0', cdrstepsx_in(0) => '0', cfgreset_in(0) => '0', clkrsvd0_in(0) => '0', clkrsvd1_in(0) => '0', cpllfbclklost_out(0) => NLW_inst_cpllfbclklost_out_UNCONNECTED(0), cpllfreqlock_in(0) => '0', cplllock_out(0) => cplllock_out(0), cplllockdetclk_in(0) => '0', cplllocken_in(0) => '1', cpllpd_in(0) => '0', cpllrefclklost_out(0) => NLW_inst_cpllrefclklost_out_UNCONNECTED(0), cpllrefclksel_in(2 downto 0) => B"001", cpllreset_in(0) => '0', dmonfiforeset_in(0) => '0', dmonitorclk_in(0) => '0', dmonitorout_out(16 downto 0) => NLW_inst_dmonitorout_out_UNCONNECTED(16 downto 0), dmonitoroutclk_out(0) => NLW_inst_dmonitoroutclk_out_UNCONNECTED(0), drpaddr_common_in(8 downto 0) => B"000000000", drpaddr_in(8 downto 0) => B"000000000", drpclk_common_in(0) => '0', drpclk_in(0) => drpclk_in(0), drpdi_common_in(15 downto 0) => B"0000000000000000", drpdi_in(15 downto 0) => B"0000000000000000", drpdo_common_out(15 downto 0) => NLW_inst_drpdo_common_out_UNCONNECTED(15 downto 0), drpdo_out(15 downto 0) => NLW_inst_drpdo_out_UNCONNECTED(15 downto 0), drpen_common_in(0) => '0', drpen_in(0) => '0', drprdy_common_out(0) => NLW_inst_drprdy_common_out_UNCONNECTED(0), drprdy_out(0) => NLW_inst_drprdy_out_UNCONNECTED(0), drprst_in(0) => '0', drpwe_common_in(0) => '0', drpwe_in(0) => '0', elpcaldvorwren_in(0) => '0', elpcalpaorwren_in(0) => '0', evoddphicaldone_in(0) => '0', evoddphicalstart_in(0) => '0', evoddphidrden_in(0) => '0', evoddphidwren_in(0) => '0', evoddphixrden_in(0) => '0', evoddphixwren_in(0) => '0', eyescandataerror_out(0) => NLW_inst_eyescandataerror_out_UNCONNECTED(0), eyescanmode_in(0) => '0', eyescanreset_in(0) => '0', eyescantrigger_in(0) => '0', freqos_in(0) => '0', gtgrefclk0_in(0) => '0', gtgrefclk1_in(0) => '0', gtgrefclk_in(0) => '0', gthrxn_in(0) => gthrxn_in(0), gthrxp_in(0) => gthrxp_in(0), gthtxn_out(0) => gthtxn_out(0), gthtxp_out(0) => gthtxp_out(0), gtnorthrefclk00_in(0) => '0', gtnorthrefclk01_in(0) => '0', gtnorthrefclk0_in(0) => '0', gtnorthrefclk10_in(0) => '0', gtnorthrefclk11_in(0) => '0', gtnorthrefclk1_in(0) => '0', gtpowergood_out(0) => gtpowergood_out(0), gtrefclk00_in(0) => '0', gtrefclk01_in(0) => '0', gtrefclk0_in(0) => gtrefclk0_in(0), gtrefclk10_in(0) => '0', gtrefclk11_in(0) => '0', gtrefclk1_in(0) => '0', gtrefclkmonitor_out(0) => NLW_inst_gtrefclkmonitor_out_UNCONNECTED(0), gtresetsel_in(0) => '0', gtrsvd_in(15 downto 0) => B"0000000000000000", gtrxreset_in(0) => '0', gtrxresetsel_in(0) => '0', gtsouthrefclk00_in(0) => '0', gtsouthrefclk01_in(0) => '0', gtsouthrefclk0_in(0) => '0', gtsouthrefclk10_in(0) => '0', gtsouthrefclk11_in(0) => '0', gtsouthrefclk1_in(0) => '0', gttxreset_in(0) => '0', gttxresetsel_in(0) => '0', gtwiz_buffbypass_rx_done_out(0) => NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED(0), gtwiz_buffbypass_rx_error_out(0) => NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED(0), gtwiz_buffbypass_rx_reset_in(0) => '0', gtwiz_buffbypass_rx_start_user_in(0) => '0', gtwiz_buffbypass_tx_done_out(0) => NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED(0), gtwiz_buffbypass_tx_error_out(0) => NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED(0), gtwiz_buffbypass_tx_reset_in(0) => '0', gtwiz_buffbypass_tx_start_user_in(0) => '0', gtwiz_gthe3_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gthe3_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gthe3_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_gthe4_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gthe4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gthe4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_gtye4_cpll_cal_bufg_ce_in(0) => '0', gtwiz_gtye4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000", gtwiz_gtye4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000", gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0), gtwiz_reset_clk_freerun_in(0) => '0', gtwiz_reset_qpll0lock_in(0) => '0', gtwiz_reset_qpll0reset_out(0) => NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED(0), gtwiz_reset_qpll1lock_in(0) => '0', gtwiz_reset_qpll1reset_out(0) => NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED(0), gtwiz_reset_rx_cdr_stable_out(0) => NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0), gtwiz_reset_rx_done_in(0) => '0', gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0), gtwiz_reset_rx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0), gtwiz_reset_tx_done_in(0) => '0', gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0), gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_userclk_rx_active_in(0) => '0', gtwiz_userclk_rx_active_out(0) => NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED(0), gtwiz_userclk_rx_reset_in(0) => '0', gtwiz_userclk_rx_srcclk_out(0) => NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED(0), gtwiz_userclk_rx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED(0), gtwiz_userclk_rx_usrclk_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED(0), gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0), gtwiz_userclk_tx_active_out(0) => NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED(0), gtwiz_userclk_tx_reset_in(0) => '0', gtwiz_userclk_tx_srcclk_out(0) => NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED(0), gtwiz_userclk_tx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED(0), gtwiz_userclk_tx_usrclk_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED(0), gtwiz_userdata_rx_out(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0), gtwiz_userdata_tx_in(15 downto 0) => gtwiz_userdata_tx_in(15 downto 0), gtyrxn_in(0) => '0', gtyrxp_in(0) => '0', gtytxn_out(0) => NLW_inst_gtytxn_out_UNCONNECTED(0), gtytxp_out(0) => NLW_inst_gtytxp_out_UNCONNECTED(0), incpctrl_in(0) => '0', loopback_in(2 downto 0) => B"000", looprsvd_in(0) => '0', lpbkrxtxseren_in(0) => '0', lpbktxrxseren_in(0) => '0', pcieeqrxeqadaptdone_in(0) => '0', pcierategen3_out(0) => NLW_inst_pcierategen3_out_UNCONNECTED(0), pcierateidle_out(0) => NLW_inst_pcierateidle_out_UNCONNECTED(0), pcierateqpll0_in(0) => '0', pcierateqpll1_in(0) => '0', pcierateqpllpd_out(1 downto 0) => NLW_inst_pcierateqpllpd_out_UNCONNECTED(1 downto 0), pcierateqpllreset_out(1 downto 0) => NLW_inst_pcierateqpllreset_out_UNCONNECTED(1 downto 0), pcierstidle_in(0) => '0', pciersttxsyncstart_in(0) => '0', pciesynctxsyncdone_out(0) => NLW_inst_pciesynctxsyncdone_out_UNCONNECTED(0), pcieusergen3rdy_out(0) => NLW_inst_pcieusergen3rdy_out_UNCONNECTED(0), pcieuserphystatusrst_out(0) => NLW_inst_pcieuserphystatusrst_out_UNCONNECTED(0), pcieuserratedone_in(0) => '0', pcieuserratestart_out(0) => NLW_inst_pcieuserratestart_out_UNCONNECTED(0), pcsrsvdin2_in(4 downto 0) => B"00000", pcsrsvdin_in(15 downto 0) => B"0000000000000000", pcsrsvdout_out(11 downto 0) => NLW_inst_pcsrsvdout_out_UNCONNECTED(11 downto 0), phystatus_out(0) => NLW_inst_phystatus_out_UNCONNECTED(0), pinrsrvdas_out(7 downto 0) => NLW_inst_pinrsrvdas_out_UNCONNECTED(7 downto 0), pmarsvd0_in(7 downto 0) => B"00000000", pmarsvd1_in(7 downto 0) => B"00000000", pmarsvdin_in(4 downto 0) => B"00000", pmarsvdout0_out(7 downto 0) => NLW_inst_pmarsvdout0_out_UNCONNECTED(7 downto 0), pmarsvdout1_out(7 downto 0) => NLW_inst_pmarsvdout1_out_UNCONNECTED(7 downto 0), powerpresent_out(0) => NLW_inst_powerpresent_out_UNCONNECTED(0), qpll0clk_in(0) => '0', qpll0clkrsvd0_in(0) => '0', qpll0clkrsvd1_in(0) => '0', qpll0fbclklost_out(0) => NLW_inst_qpll0fbclklost_out_UNCONNECTED(0), qpll0fbdiv_in(0) => '0', qpll0freqlock_in(0) => '0', qpll0lock_out(0) => NLW_inst_qpll0lock_out_UNCONNECTED(0), qpll0lockdetclk_in(0) => '0', qpll0locken_in(0) => '0', qpll0outclk_out(0) => NLW_inst_qpll0outclk_out_UNCONNECTED(0), qpll0outrefclk_out(0) => NLW_inst_qpll0outrefclk_out_UNCONNECTED(0), qpll0pd_in(0) => '1', qpll0refclk_in(0) => '0', qpll0refclklost_out(0) => NLW_inst_qpll0refclklost_out_UNCONNECTED(0), qpll0refclksel_in(2 downto 0) => B"001", qpll0reset_in(0) => '1', qpll1clk_in(0) => '0', qpll1clkrsvd0_in(0) => '0', qpll1clkrsvd1_in(0) => '0', qpll1fbclklost_out(0) => NLW_inst_qpll1fbclklost_out_UNCONNECTED(0), qpll1fbdiv_in(0) => '0', qpll1freqlock_in(0) => '0', qpll1lock_out(0) => NLW_inst_qpll1lock_out_UNCONNECTED(0), qpll1lockdetclk_in(0) => '0', qpll1locken_in(0) => '0', qpll1outclk_out(0) => NLW_inst_qpll1outclk_out_UNCONNECTED(0), qpll1outrefclk_out(0) => NLW_inst_qpll1outrefclk_out_UNCONNECTED(0), qpll1pd_in(0) => '1', qpll1refclk_in(0) => '0', qpll1refclklost_out(0) => NLW_inst_qpll1refclklost_out_UNCONNECTED(0), qpll1refclksel_in(2 downto 0) => B"001", qpll1reset_in(0) => '1', qplldmonitor0_out(7 downto 0) => NLW_inst_qplldmonitor0_out_UNCONNECTED(7 downto 0), qplldmonitor1_out(7 downto 0) => NLW_inst_qplldmonitor1_out_UNCONNECTED(7 downto 0), qpllrsvd1_in(7 downto 0) => B"00000000", qpllrsvd2_in(4 downto 0) => B"00000", qpllrsvd3_in(4 downto 0) => B"00000", qpllrsvd4_in(7 downto 0) => B"00000000", rcalenb_in(0) => '1', refclkoutmonitor0_out(0) => NLW_inst_refclkoutmonitor0_out_UNCONNECTED(0), refclkoutmonitor1_out(0) => NLW_inst_refclkoutmonitor1_out_UNCONNECTED(0), resetexception_out(0) => NLW_inst_resetexception_out_UNCONNECTED(0), resetovrd_in(0) => '0', rstclkentx_in(0) => '0', rx8b10ben_in(0) => '1', rxafecfoken_in(0) => '0', rxbufreset_in(0) => '0', rxbufstatus_out(2) => \^rxbufstatus_out\(2), rxbufstatus_out(1 downto 0) => NLW_inst_rxbufstatus_out_UNCONNECTED(1 downto 0), rxbyteisaligned_out(0) => NLW_inst_rxbyteisaligned_out_UNCONNECTED(0), rxbyterealign_out(0) => NLW_inst_rxbyterealign_out_UNCONNECTED(0), rxcdrfreqreset_in(0) => '0', rxcdrhold_in(0) => '0', rxcdrlock_out(0) => NLW_inst_rxcdrlock_out_UNCONNECTED(0), rxcdrovrden_in(0) => '0', rxcdrphdone_out(0) => NLW_inst_rxcdrphdone_out_UNCONNECTED(0), rxcdrreset_in(0) => '0', rxcdrresetrsv_in(0) => '0', rxchanbondseq_out(0) => NLW_inst_rxchanbondseq_out_UNCONNECTED(0), rxchanisaligned_out(0) => NLW_inst_rxchanisaligned_out_UNCONNECTED(0), rxchanrealign_out(0) => NLW_inst_rxchanrealign_out_UNCONNECTED(0), rxchbonden_in(0) => '0', rxchbondi_in(4 downto 0) => B"00000", rxchbondlevel_in(2 downto 0) => B"000", rxchbondmaster_in(0) => '0', rxchbondo_out(4 downto 0) => NLW_inst_rxchbondo_out_UNCONNECTED(4 downto 0), rxchbondslave_in(0) => '0', rxckcaldone_out(0) => NLW_inst_rxckcaldone_out_UNCONNECTED(0), rxckcalreset_in(0) => '0', rxckcalstart_in(0) => '0', rxclkcorcnt_out(1 downto 0) => rxclkcorcnt_out(1 downto 0), rxcominitdet_out(0) => NLW_inst_rxcominitdet_out_UNCONNECTED(0), rxcommadet_out(0) => NLW_inst_rxcommadet_out_UNCONNECTED(0), rxcommadeten_in(0) => '1', rxcomsasdet_out(0) => NLW_inst_rxcomsasdet_out_UNCONNECTED(0), rxcomwakedet_out(0) => NLW_inst_rxcomwakedet_out_UNCONNECTED(0), rxctrl0_out(15 downto 2) => NLW_inst_rxctrl0_out_UNCONNECTED(15 downto 2), rxctrl0_out(1 downto 0) => \^rxctrl0_out\(1 downto 0), rxctrl1_out(15 downto 2) => NLW_inst_rxctrl1_out_UNCONNECTED(15 downto 2), rxctrl1_out(1 downto 0) => \^rxctrl1_out\(1 downto 0), rxctrl2_out(7 downto 2) => NLW_inst_rxctrl2_out_UNCONNECTED(7 downto 2), rxctrl2_out(1 downto 0) => \^rxctrl2_out\(1 downto 0), rxctrl3_out(7 downto 2) => NLW_inst_rxctrl3_out_UNCONNECTED(7 downto 2), rxctrl3_out(1 downto 0) => \^rxctrl3_out\(1 downto 0), rxdata_out(127 downto 0) => NLW_inst_rxdata_out_UNCONNECTED(127 downto 0), rxdataextendrsvd_out(7 downto 0) => NLW_inst_rxdataextendrsvd_out_UNCONNECTED(7 downto 0), rxdatavalid_out(1 downto 0) => NLW_inst_rxdatavalid_out_UNCONNECTED(1 downto 0), rxdccforcestart_in(0) => '0', rxdfeagcctrl_in(1 downto 0) => B"01", rxdfeagchold_in(0) => '0', rxdfeagcovrden_in(0) => '0', rxdfecfokfcnum_in(0) => '0', rxdfecfokfen_in(0) => '0', rxdfecfokfpulse_in(0) => '0', rxdfecfokhold_in(0) => '0', rxdfecfokovren_in(0) => '0', rxdfekhhold_in(0) => '0', rxdfekhovrden_in(0) => '0', rxdfelfhold_in(0) => '0', rxdfelfovrden_in(0) => '0', rxdfelpmreset_in(0) => '0', rxdfetap10hold_in(0) => '0', rxdfetap10ovrden_in(0) => '0', rxdfetap11hold_in(0) => '0', rxdfetap11ovrden_in(0) => '0', rxdfetap12hold_in(0) => '0', rxdfetap12ovrden_in(0) => '0', rxdfetap13hold_in(0) => '0', rxdfetap13ovrden_in(0) => '0', rxdfetap14hold_in(0) => '0', rxdfetap14ovrden_in(0) => '0', rxdfetap15hold_in(0) => '0', rxdfetap15ovrden_in(0) => '0', rxdfetap2hold_in(0) => '0', rxdfetap2ovrden_in(0) => '0', rxdfetap3hold_in(0) => '0', rxdfetap3ovrden_in(0) => '0', rxdfetap4hold_in(0) => '0', rxdfetap4ovrden_in(0) => '0', rxdfetap5hold_in(0) => '0', rxdfetap5ovrden_in(0) => '0', rxdfetap6hold_in(0) => '0', rxdfetap6ovrden_in(0) => '0', rxdfetap7hold_in(0) => '0', rxdfetap7ovrden_in(0) => '0', rxdfetap8hold_in(0) => '0', rxdfetap8ovrden_in(0) => '0', rxdfetap9hold_in(0) => '0', rxdfetap9ovrden_in(0) => '0', rxdfeuthold_in(0) => '0', rxdfeutovrden_in(0) => '0', rxdfevphold_in(0) => '0', rxdfevpovrden_in(0) => '0', rxdfevsen_in(0) => '0', rxdfexyden_in(0) => '1', rxdlybypass_in(0) => '1', rxdlyen_in(0) => '0', rxdlyovrden_in(0) => '0', rxdlysreset_in(0) => '0', rxdlysresetdone_out(0) => NLW_inst_rxdlysresetdone_out_UNCONNECTED(0), rxelecidle_out(0) => NLW_inst_rxelecidle_out_UNCONNECTED(0), rxelecidlemode_in(1 downto 0) => B"11", rxeqtraining_in(0) => '0', rxgearboxslip_in(0) => '0', rxheader_out(5 downto 0) => NLW_inst_rxheader_out_UNCONNECTED(5 downto 0), rxheadervalid_out(1 downto 0) => NLW_inst_rxheadervalid_out_UNCONNECTED(1 downto 0), rxlatclk_in(0) => '0', rxlfpstresetdet_out(0) => NLW_inst_rxlfpstresetdet_out_UNCONNECTED(0), rxlfpsu2lpexitdet_out(0) => NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED(0), rxlfpsu3wakedet_out(0) => NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED(0), rxlpmen_in(0) => '1', rxlpmgchold_in(0) => '0', rxlpmgcovrden_in(0) => '0', rxlpmhfhold_in(0) => '0', rxlpmhfovrden_in(0) => '0', rxlpmlfhold_in(0) => '0', rxlpmlfklovrden_in(0) => '0', rxlpmoshold_in(0) => '0', rxlpmosovrden_in(0) => '0', rxmcommaalignen_in(0) => rxmcommaalignen_in(0), rxmonitorout_out(6 downto 0) => NLW_inst_rxmonitorout_out_UNCONNECTED(6 downto 0), rxmonitorsel_in(1 downto 0) => B"00", rxoobreset_in(0) => '0', rxoscalreset_in(0) => '0', rxoshold_in(0) => '0', rxosintcfg_in(3 downto 0) => B"1101", rxosintdone_out(0) => NLW_inst_rxosintdone_out_UNCONNECTED(0), rxosinten_in(0) => '1', rxosinthold_in(0) => '0', rxosintovrden_in(0) => '0', rxosintstarted_out(0) => NLW_inst_rxosintstarted_out_UNCONNECTED(0), rxosintstrobe_in(0) => '0', rxosintstrobedone_out(0) => NLW_inst_rxosintstrobedone_out_UNCONNECTED(0), rxosintstrobestarted_out(0) => NLW_inst_rxosintstrobestarted_out_UNCONNECTED(0), rxosinttestovrden_in(0) => '0', rxosovrden_in(0) => '0', rxoutclk_out(0) => rxoutclk_out(0), rxoutclkfabric_out(0) => NLW_inst_rxoutclkfabric_out_UNCONNECTED(0), rxoutclkpcs_out(0) => NLW_inst_rxoutclkpcs_out_UNCONNECTED(0), rxoutclksel_in(2 downto 0) => B"010", rxpcommaalignen_in(0) => '0', rxpcsreset_in(0) => '0', rxpd_in(1) => rxpd_in(1), rxpd_in(0) => '0', rxphalign_in(0) => '0', rxphaligndone_out(0) => NLW_inst_rxphaligndone_out_UNCONNECTED(0), rxphalignen_in(0) => '0', rxphalignerr_out(0) => NLW_inst_rxphalignerr_out_UNCONNECTED(0), rxphdlypd_in(0) => '1', rxphdlyreset_in(0) => '0', rxphovrden_in(0) => '0', rxpllclksel_in(1 downto 0) => B"00", rxpmareset_in(0) => '0', rxpmaresetdone_out(0) => NLW_inst_rxpmaresetdone_out_UNCONNECTED(0), rxpolarity_in(0) => '0', rxprbscntreset_in(0) => '0', rxprbserr_out(0) => NLW_inst_rxprbserr_out_UNCONNECTED(0), rxprbslocked_out(0) => NLW_inst_rxprbslocked_out_UNCONNECTED(0), rxprbssel_in(3 downto 0) => B"0000", rxprgdivresetdone_out(0) => NLW_inst_rxprgdivresetdone_out_UNCONNECTED(0), rxprogdivreset_in(0) => '0', rxqpien_in(0) => '0', rxqpisenn_out(0) => NLW_inst_rxqpisenn_out_UNCONNECTED(0), rxqpisenp_out(0) => NLW_inst_rxqpisenp_out_UNCONNECTED(0), rxrate_in(2 downto 0) => B"000", rxratedone_out(0) => NLW_inst_rxratedone_out_UNCONNECTED(0), rxratemode_in(0) => '0', rxrecclk0_sel_out(1 downto 0) => NLW_inst_rxrecclk0_sel_out_UNCONNECTED(1 downto 0), rxrecclk0sel_out(0) => NLW_inst_rxrecclk0sel_out_UNCONNECTED(0), rxrecclk1_sel_out(1 downto 0) => NLW_inst_rxrecclk1_sel_out_UNCONNECTED(1 downto 0), rxrecclk1sel_out(0) => NLW_inst_rxrecclk1sel_out_UNCONNECTED(0), rxrecclkout_out(0) => NLW_inst_rxrecclkout_out_UNCONNECTED(0), rxresetdone_out(0) => NLW_inst_rxresetdone_out_UNCONNECTED(0), rxslide_in(0) => '0', rxsliderdy_out(0) => NLW_inst_rxsliderdy_out_UNCONNECTED(0), rxslipdone_out(0) => NLW_inst_rxslipdone_out_UNCONNECTED(0), rxslipoutclk_in(0) => '0', rxslipoutclkrdy_out(0) => NLW_inst_rxslipoutclkrdy_out_UNCONNECTED(0), rxslippma_in(0) => '0', rxslippmardy_out(0) => NLW_inst_rxslippmardy_out_UNCONNECTED(0), rxstartofseq_out(1 downto 0) => NLW_inst_rxstartofseq_out_UNCONNECTED(1 downto 0), rxstatus_out(2 downto 0) => NLW_inst_rxstatus_out_UNCONNECTED(2 downto 0), rxsyncallin_in(0) => '0', rxsyncdone_out(0) => NLW_inst_rxsyncdone_out_UNCONNECTED(0), rxsyncin_in(0) => '0', rxsyncmode_in(0) => '0', rxsyncout_out(0) => NLW_inst_rxsyncout_out_UNCONNECTED(0), rxsysclksel_in(1 downto 0) => B"00", rxtermination_in(0) => '0', rxuserrdy_in(0) => '1', rxusrclk2_in(0) => '0', rxusrclk_in(0) => rxusrclk_in(0), rxvalid_out(0) => NLW_inst_rxvalid_out_UNCONNECTED(0), sdm0data_in(0) => '0', sdm0finalout_out(0) => NLW_inst_sdm0finalout_out_UNCONNECTED(0), sdm0reset_in(0) => '0', sdm0testdata_out(0) => NLW_inst_sdm0testdata_out_UNCONNECTED(0), sdm0toggle_in(0) => '0', sdm0width_in(0) => '0', sdm1data_in(0) => '0', sdm1finalout_out(0) => NLW_inst_sdm1finalout_out_UNCONNECTED(0), sdm1reset_in(0) => '0', sdm1testdata_out(0) => NLW_inst_sdm1testdata_out_UNCONNECTED(0), sdm1toggle_in(0) => '0', sdm1width_in(0) => '0', sigvalidclk_in(0) => '0', tcongpi_in(0) => '0', tcongpo_out(0) => NLW_inst_tcongpo_out_UNCONNECTED(0), tconpowerup_in(0) => '0', tconreset_in(0) => '0', tconrsvdin1_in(0) => '0', tconrsvdout0_out(0) => NLW_inst_tconrsvdout0_out_UNCONNECTED(0), tstin_in(19 downto 0) => B"00000000000000000000", tx8b10bbypass_in(7 downto 0) => B"00000000", tx8b10ben_in(0) => '1', txbufdiffctrl_in(2 downto 0) => B"000", txbufstatus_out(1) => \^txbufstatus_out\(1), txbufstatus_out(0) => NLW_inst_txbufstatus_out_UNCONNECTED(0), txcomfinish_out(0) => NLW_inst_txcomfinish_out_UNCONNECTED(0), txcominit_in(0) => '0', txcomsas_in(0) => '0', txcomwake_in(0) => '0', txctrl0_in(15 downto 2) => B"00000000000000", txctrl0_in(1 downto 0) => txctrl0_in(1 downto 0), txctrl1_in(15 downto 2) => B"00000000000000", txctrl1_in(1 downto 0) => txctrl1_in(1 downto 0), txctrl2_in(7 downto 2) => B"000000", txctrl2_in(1 downto 0) => txctrl2_in(1 downto 0), txdata_in(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", txdataextendrsvd_in(7 downto 0) => B"00000000", txdccdone_out(0) => NLW_inst_txdccdone_out_UNCONNECTED(0), txdccforcestart_in(0) => '0', txdccreset_in(0) => '0', txdeemph_in(0) => '0', txdetectrx_in(0) => '0', txdiffctrl_in(3 downto 0) => B"1000", txdiffpd_in(0) => '0', txdlybypass_in(0) => '1', txdlyen_in(0) => '0', txdlyhold_in(0) => '0', txdlyovrden_in(0) => '0', txdlysreset_in(0) => '0', txdlysresetdone_out(0) => NLW_inst_txdlysresetdone_out_UNCONNECTED(0), txdlyupdown_in(0) => '0', txelecidle_in(0) => txelecidle_in(0), txelforcestart_in(0) => '0', txheader_in(5 downto 0) => B"000000", txinhibit_in(0) => '0', txlatclk_in(0) => '0', txlfpstreset_in(0) => '0', txlfpsu2lpexit_in(0) => '0', txlfpsu3wake_in(0) => '0', txmaincursor_in(6 downto 0) => B"1000000", txmargin_in(2 downto 0) => B"000", txmuxdcdexhold_in(0) => '0', txmuxdcdorwren_in(0) => '0', txoneszeros_in(0) => '0', txoutclk_out(0) => txoutclk_out(0), txoutclkfabric_out(0) => NLW_inst_txoutclkfabric_out_UNCONNECTED(0), txoutclkpcs_out(0) => NLW_inst_txoutclkpcs_out_UNCONNECTED(0), txoutclksel_in(2 downto 0) => B"101", txpcsreset_in(0) => '0', txpd_in(1 downto 0) => B"00", txpdelecidlemode_in(0) => '0', txphalign_in(0) => '0', txphaligndone_out(0) => NLW_inst_txphaligndone_out_UNCONNECTED(0), txphalignen_in(0) => '0', txphdlypd_in(0) => '1', txphdlyreset_in(0) => '0', txphdlytstclk_in(0) => '0', txphinit_in(0) => '0', txphinitdone_out(0) => NLW_inst_txphinitdone_out_UNCONNECTED(0), txphovrden_in(0) => '0', txpippmen_in(0) => '0', txpippmovrden_in(0) => '0', txpippmpd_in(0) => '0', txpippmsel_in(0) => '0', txpippmstepsize_in(4 downto 0) => B"00000", txpisopd_in(0) => '0', txpllclksel_in(1 downto 0) => B"00", txpmareset_in(0) => '0', txpmaresetdone_out(0) => NLW_inst_txpmaresetdone_out_UNCONNECTED(0), txpolarity_in(0) => '0', txpostcursor_in(4 downto 0) => B"00000", txpostcursorinv_in(0) => '0', txprbsforceerr_in(0) => '0', txprbssel_in(3 downto 0) => B"0000", txprecursor_in(4 downto 0) => B"00000", txprecursorinv_in(0) => '0', txprgdivresetdone_out(0) => NLW_inst_txprgdivresetdone_out_UNCONNECTED(0), txprogdivreset_in(0) => '0', txqpibiasen_in(0) => '0', txqpisenn_out(0) => NLW_inst_txqpisenn_out_UNCONNECTED(0), txqpisenp_out(0) => NLW_inst_txqpisenp_out_UNCONNECTED(0), txqpistrongpdown_in(0) => '0', txqpiweakpup_in(0) => '0', txrate_in(2 downto 0) => B"000", txratedone_out(0) => NLW_inst_txratedone_out_UNCONNECTED(0), txratemode_in(0) => '0', txresetdone_out(0) => NLW_inst_txresetdone_out_UNCONNECTED(0), txsequence_in(6 downto 0) => B"0000000", txswing_in(0) => '0', txsyncallin_in(0) => '0', txsyncdone_out(0) => NLW_inst_txsyncdone_out_UNCONNECTED(0), txsyncin_in(0) => '0', txsyncmode_in(0) => '0', txsyncout_out(0) => NLW_inst_txsyncout_out_UNCONNECTED(0), txsysclksel_in(1 downto 0) => B"00", txuserrdy_in(0) => '1', txusrclk2_in(0) => '0', txusrclk_in(0) => '0', ubcfgstreamen_in(0) => '0', ubdaddr_out(0) => NLW_inst_ubdaddr_out_UNCONNECTED(0), ubden_out(0) => NLW_inst_ubden_out_UNCONNECTED(0), ubdi_out(0) => NLW_inst_ubdi_out_UNCONNECTED(0), ubdo_in(0) => '0', ubdrdy_in(0) => '0', ubdwe_out(0) => NLW_inst_ubdwe_out_UNCONNECTED(0), ubenable_in(0) => '0', ubgpi_in(0) => '0', ubintr_in(0) => '0', ubiolmbrst_in(0) => '0', ubmbrst_in(0) => '0', ubmdmcapture_in(0) => '0', ubmdmdbgrst_in(0) => '0', ubmdmdbgupdate_in(0) => '0', ubmdmregen_in(0) => '0', ubmdmshift_in(0) => '0', ubmdmsysrst_in(0) => '0', ubmdmtck_in(0) => '0', ubmdmtdi_in(0) => '0', ubmdmtdo_out(0) => NLW_inst_ubmdmtdo_out_UNCONNECTED(0), ubrsvdout_out(0) => NLW_inst_ubrsvdout_out_UNCONNECTED(0), ubtxuart_out(0) => NLW_inst_ubtxuart_out_UNCONNECTED(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver is port ( cplllock : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; gtpowergood : out STD_LOGIC; rxoutclk : out STD_LOGIC; txoutclk : out STD_LOGIC; rxchariscomma : out STD_LOGIC; rxcharisk : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \rxdata_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdisperr : out STD_LOGIC; rxnotintable : out STD_LOGIC; rxbuferr : out STD_LOGIC; txbuferr : out STD_LOGIC; data_in : out STD_LOGIC; mmcm_reset : out STD_LOGIC; userclk2 : in STD_LOGIC; enablealign : in STD_LOGIC; userclk : in STD_LOGIC; txreset : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); mmcm_locked : in STD_LOGIC; pma_reset : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gtrefclk : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ); powerdown : in STD_LOGIC; txchardispval_reg_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); txchardispmode_reg_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); txcharisk_reg_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver : entity is "gig_ethernet_pcs_pma_0_transceiver"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver is signal \^cplllock\ : STD_LOGIC; signal encommaalign_int : STD_LOGIC; signal gig_ethernet_pcs_pma_0_gt_i_n_118 : STD_LOGIC; signal gig_ethernet_pcs_pma_0_gt_i_n_58 : STD_LOGIC; signal gtwiz_reset_rx_done_out_int : STD_LOGIC; signal gtwiz_reset_rx_done_out_int_reg : STD_LOGIC; signal gtwiz_reset_rx_done_out_int_reg0 : STD_LOGIC; signal gtwiz_reset_rx_done_out_reg : STD_LOGIC; signal gtwiz_reset_tx_done_out_int : STD_LOGIC; signal gtwiz_reset_tx_done_out_int_reg : STD_LOGIC; signal gtwiz_reset_tx_done_out_int_reg0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \p_1_in__1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \p_1_in__2\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal rxchariscomma_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxchariscomma_i_1_n_0 : STD_LOGIC; signal \rxchariscomma_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxcharisk_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxcharisk_i_1_n_0 : STD_LOGIC; signal \rxcharisk_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_reg : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxctrl0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxctrl1_out : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxctrl2_out : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxctrl3_out : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxdata[0]_i_1_n_0\ : STD_LOGIC; signal \rxdata[1]_i_1_n_0\ : STD_LOGIC; signal \rxdata[2]_i_1_n_0\ : STD_LOGIC; signal \rxdata[3]_i_1_n_0\ : STD_LOGIC; signal \rxdata[4]_i_1_n_0\ : STD_LOGIC; signal \rxdata[5]_i_1_n_0\ : STD_LOGIC; signal \rxdata[6]_i_1_n_0\ : STD_LOGIC; signal \rxdata[7]_i_1_n_0\ : STD_LOGIC; signal rxdata_double : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdata_int : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdata_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdisperr_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdisperr_i_1_n_0 : STD_LOGIC; signal \rxdisperr_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxnotintable_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxnotintable_i_1_n_0 : STD_LOGIC; signal \rxnotintable_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxpowerdown : STD_LOGIC; signal rxpowerdown_double : STD_LOGIC; signal \rxpowerdown_reg__0\ : STD_LOGIC; signal toggle : STD_LOGIC; signal toggle_i_1_n_0 : STD_LOGIC; signal txbufstatus_reg : STD_LOGIC_VECTOR ( 1 to 1 ); signal txchardispmode_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispmode_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispval_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispval_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txcharisk_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txcharisk_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txdata_double : STD_LOGIC_VECTOR ( 15 downto 0 ); signal txdata_int : STD_LOGIC_VECTOR ( 15 downto 0 ); signal txpowerdown : STD_LOGIC; signal txpowerdown_double : STD_LOGIC; signal \txpowerdown_reg__0\ : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of gig_ethernet_pcs_pma_0_gt_i : label is "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of gig_ethernet_pcs_pma_0_gt_i : label is "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_0_gt_i : label is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of rxchariscomma_i_1 : label is "soft_lutpair67"; attribute SOFT_HLUTNM of rxcharisk_i_1 : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \rxdata[0]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \rxdata[1]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \rxdata[2]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \rxdata[3]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \rxdata[4]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \rxdata[5]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \rxdata[6]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \rxdata[7]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of rxdisperr_i_1 : label is "soft_lutpair68"; attribute SOFT_HLUTNM of rxnotintable_i_1 : label is "soft_lutpair68"; begin cplllock <= \^cplllock\; SYNC_ASYNC_RESET_GT_RX: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync port map ( gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out_int, reset_out => gtwiz_reset_rx_done_out_reg, rxuserclk2 => rxuserclk2 ); SYNC_ASYNC_RESET_RX: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 port map ( SR(0) => SR(0), gtwiz_reset_rx_done_out_int_reg0 => gtwiz_reset_rx_done_out_int_reg0, reset_out => gtwiz_reset_rx_done_out_reg, rxuserclk2 => rxuserclk2 ); SYNC_ASYNC_RESET_TX: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 port map ( gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out_int, gtwiz_reset_tx_done_out_int_reg0 => gtwiz_reset_tx_done_out_int_reg0, txreset => txreset, userclk => userclk ); data_sync1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => gtwiz_reset_tx_done_out_int, I1 => gtwiz_reset_rx_done_out_int, O => data_in ); gig_ethernet_pcs_pma_0_gt_i: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt port map ( cplllock_out(0) => \^cplllock\, cpllrefclksel_in(2 downto 0) => B"001", dmonitorout_out(16 downto 0) => NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED(16 downto 0), drpaddr_in(8 downto 0) => B"000000000", drpclk_in(0) => independent_clock_bufg, drpdi_in(15 downto 0) => B"0000000000000000", drpdo_out(15 downto 0) => NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED(15 downto 0), drpen_in(0) => '0', drprdy_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED(0), drpwe_in(0) => '0', eyescandataerror_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED(0), eyescanreset_in(0) => '0', eyescantrigger_in(0) => '0', gthrxn_in(0) => rxn, gthrxp_in(0) => rxp, gthtxn_out(0) => txn, gthtxp_out(0) => txp, gtpowergood_out(0) => gtpowergood, gtrefclk0_in(0) => gtrefclk, gtrefclk1_in(0) => '0', gtwiz_reset_all_in(0) => pma_reset, gtwiz_reset_clk_freerun_in(0) => '0', gtwiz_reset_rx_cdr_stable_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED(0), gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_done_out_int_reg, gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out_int, gtwiz_reset_rx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_done_out_int_reg, gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out_int, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_userclk_rx_active_in(0) => '0', gtwiz_userclk_tx_active_in(0) => mmcm_locked, gtwiz_userdata_rx_out(15 downto 0) => rxdata_int(15 downto 0), gtwiz_userdata_tx_in(15 downto 0) => txdata_int(15 downto 0), loopback_in(2 downto 0) => B"000", pcsrsvdin_in(15 downto 0) => B"0000000000000000", rx8b10ben_in(0) => '1', rxbufreset_in(0) => '0', rxbufstatus_out(2) => gig_ethernet_pcs_pma_0_gt_i_n_58, rxbufstatus_out(1 downto 0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED(1 downto 0), rxbyteisaligned_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED(0), rxbyterealign_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED(0), rxcdrhold_in(0) => '0', rxclkcorcnt_out(1 downto 0) => rxclkcorcnt_int(1 downto 0), rxcommadet_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED(0), rxcommadeten_in(0) => '1', rxctrl0_out(15 downto 2) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED(15 downto 2), rxctrl0_out(1 downto 0) => rxctrl0_out(1 downto 0), rxctrl1_out(15 downto 2) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED(15 downto 2), rxctrl1_out(1 downto 0) => rxctrl1_out(1 downto 0), rxctrl2_out(7 downto 2) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED(7 downto 2), rxctrl2_out(1 downto 0) => rxctrl2_out(1 downto 0), rxctrl3_out(7 downto 2) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED(7 downto 2), rxctrl3_out(1 downto 0) => rxctrl3_out(1 downto 0), rxdfelpmreset_in(0) => '0', rxlpmen_in(0) => '1', rxmcommaalignen_in(0) => encommaalign_int, rxoutclk_out(0) => rxoutclk, rxpcommaalignen_in(0) => '0', rxpcsreset_in(0) => '0', rxpd_in(1) => rxpowerdown, rxpd_in(0) => '0', rxpmareset_in(0) => '0', rxpmaresetdone_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED(0), rxpolarity_in(0) => '0', rxprbscntreset_in(0) => '0', rxprbserr_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED(0), rxprbssel_in(3 downto 0) => B"0000", rxrate_in(2 downto 0) => B"000", rxresetdone_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED(0), rxusrclk2_in(0) => '0', rxusrclk_in(0) => userclk, tx8b10ben_in(0) => '1', txbufstatus_out(1) => gig_ethernet_pcs_pma_0_gt_i_n_118, txbufstatus_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED(0), txctrl0_in(15 downto 2) => B"00000000000000", txctrl0_in(1 downto 0) => txchardispval_int(1 downto 0), txctrl1_in(15 downto 2) => B"00000000000000", txctrl1_in(1 downto 0) => txchardispmode_int(1 downto 0), txctrl2_in(7 downto 2) => B"000000", txctrl2_in(1 downto 0) => txcharisk_int(1 downto 0), txdiffctrl_in(3 downto 0) => B"1000", txelecidle_in(0) => txpowerdown, txinhibit_in(0) => '0', txoutclk_out(0) => txoutclk, txpcsreset_in(0) => '0', txpd_in(1 downto 0) => B"00", txpmareset_in(0) => '0', txpmaresetdone_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED(0), txpolarity_in(0) => '0', txpostcursor_in(4 downto 0) => B"00000", txprbsforceerr_in(0) => '0', txprbssel_in(3 downto 0) => B"0000", txprecursor_in(4 downto 0) => B"00000", txprgdivresetdone_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED(0), txresetdone_out(0) => NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED(0), txusrclk2_in(0) => '0', txusrclk_in(0) => '0' ); gtwiz_reset_rx_done_out_int_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rxuserclk2, CE => '1', D => gtwiz_reset_rx_done_out_int_reg0, Q => gtwiz_reset_rx_done_out_int_reg, R => '0' ); gtwiz_reset_tx_done_out_int_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => gtwiz_reset_tx_done_out_int_reg0, Q => gtwiz_reset_tx_done_out_int_reg, R => '0' ); mmcm_reset_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cplllock\, O => mmcm_reset ); reclock_encommaalign: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 port map ( enablealign => enablealign, reset_out => encommaalign_int, userclk2 => userclk2 ); rxbuferr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_0_in, Q => rxbuferr, R => '0' ); \rxbufstatus_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => gig_ethernet_pcs_pma_0_gt_i_n_58, Q => p_0_in, R => '0' ); \rxchariscomma_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxchariscomma_reg__0\(0), Q => rxchariscomma_double(0), R => SR(0) ); \rxchariscomma_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxchariscomma_reg__0\(1), Q => rxchariscomma_double(1), R => SR(0) ); rxchariscomma_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxchariscomma_double(1), I1 => toggle, I2 => rxchariscomma_double(0), O => rxchariscomma_i_1_n_0 ); rxchariscomma_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxchariscomma_i_1_n_0, Q => rxchariscomma, R => SR(0) ); \rxchariscomma_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl2_out(0), Q => \rxchariscomma_reg__0\(0), R => '0' ); \rxchariscomma_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl2_out(1), Q => \rxchariscomma_reg__0\(1), R => '0' ); \rxcharisk_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxcharisk_reg__0\(0), Q => rxcharisk_double(0), R => SR(0) ); \rxcharisk_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxcharisk_reg__0\(1), Q => rxcharisk_double(1), R => SR(0) ); rxcharisk_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxcharisk_double(1), I1 => toggle, I2 => rxcharisk_double(0), O => rxcharisk_i_1_n_0 ); rxcharisk_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxcharisk_i_1_n_0, Q => rxcharisk, R => SR(0) ); \rxcharisk_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl0_out(0), Q => \rxcharisk_reg__0\(0), R => '0' ); \rxcharisk_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl0_out(1), Q => \rxcharisk_reg__0\(1), R => '0' ); \rxclkcorcnt_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxclkcorcnt_reg(0), Q => rxclkcorcnt_double(0), R => SR(0) ); \rxclkcorcnt_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxclkcorcnt_reg(1), Q => rxclkcorcnt_double(1), R => SR(0) ); \rxclkcorcnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxclkcorcnt_double(0), Q => Q(0), R => SR(0) ); \rxclkcorcnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxclkcorcnt_double(1), Q => Q(1), R => SR(0) ); \rxclkcorcnt_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxclkcorcnt_int(0), Q => rxclkcorcnt_reg(0), R => '0' ); \rxclkcorcnt_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxclkcorcnt_int(1), Q => rxclkcorcnt_reg(1), R => '0' ); \rxdata[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(8), I1 => toggle, I2 => rxdata_double(0), O => \rxdata[0]_i_1_n_0\ ); \rxdata[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(9), I1 => toggle, I2 => rxdata_double(1), O => \rxdata[1]_i_1_n_0\ ); \rxdata[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(10), I1 => toggle, I2 => rxdata_double(2), O => \rxdata[2]_i_1_n_0\ ); \rxdata[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(11), I1 => toggle, I2 => rxdata_double(3), O => \rxdata[3]_i_1_n_0\ ); \rxdata[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(12), I1 => toggle, I2 => rxdata_double(4), O => \rxdata[4]_i_1_n_0\ ); \rxdata[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(13), I1 => toggle, I2 => rxdata_double(5), O => \rxdata[5]_i_1_n_0\ ); \rxdata[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(14), I1 => toggle, I2 => rxdata_double(6), O => \rxdata[6]_i_1_n_0\ ); \rxdata[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(15), I1 => toggle, I2 => rxdata_double(7), O => \rxdata[7]_i_1_n_0\ ); \rxdata_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(0), Q => rxdata_double(0), R => SR(0) ); \rxdata_double_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(10), Q => rxdata_double(10), R => SR(0) ); \rxdata_double_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(11), Q => rxdata_double(11), R => SR(0) ); \rxdata_double_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(12), Q => rxdata_double(12), R => SR(0) ); \rxdata_double_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(13), Q => rxdata_double(13), R => SR(0) ); \rxdata_double_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(14), Q => rxdata_double(14), R => SR(0) ); \rxdata_double_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(15), Q => rxdata_double(15), R => SR(0) ); \rxdata_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(1), Q => rxdata_double(1), R => SR(0) ); \rxdata_double_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(2), Q => rxdata_double(2), R => SR(0) ); \rxdata_double_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(3), Q => rxdata_double(3), R => SR(0) ); \rxdata_double_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(4), Q => rxdata_double(4), R => SR(0) ); \rxdata_double_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(5), Q => rxdata_double(5), R => SR(0) ); \rxdata_double_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(6), Q => rxdata_double(6), R => SR(0) ); \rxdata_double_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(7), Q => rxdata_double(7), R => SR(0) ); \rxdata_double_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(8), Q => rxdata_double(8), R => SR(0) ); \rxdata_double_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(9), Q => rxdata_double(9), R => SR(0) ); \rxdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[0]_i_1_n_0\, Q => \rxdata_reg[7]_0\(0), R => SR(0) ); \rxdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[1]_i_1_n_0\, Q => \rxdata_reg[7]_0\(1), R => SR(0) ); \rxdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[2]_i_1_n_0\, Q => \rxdata_reg[7]_0\(2), R => SR(0) ); \rxdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[3]_i_1_n_0\, Q => \rxdata_reg[7]_0\(3), R => SR(0) ); \rxdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[4]_i_1_n_0\, Q => \rxdata_reg[7]_0\(4), R => SR(0) ); \rxdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[5]_i_1_n_0\, Q => \rxdata_reg[7]_0\(5), R => SR(0) ); \rxdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[6]_i_1_n_0\, Q => \rxdata_reg[7]_0\(6), R => SR(0) ); \rxdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[7]_i_1_n_0\, Q => \rxdata_reg[7]_0\(7), R => SR(0) ); \rxdata_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(0), Q => rxdata_reg(0), R => '0' ); \rxdata_reg_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(10), Q => rxdata_reg(10), R => '0' ); \rxdata_reg_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(11), Q => rxdata_reg(11), R => '0' ); \rxdata_reg_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(12), Q => rxdata_reg(12), R => '0' ); \rxdata_reg_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(13), Q => rxdata_reg(13), R => '0' ); \rxdata_reg_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(14), Q => rxdata_reg(14), R => '0' ); \rxdata_reg_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(15), Q => rxdata_reg(15), R => '0' ); \rxdata_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(1), Q => rxdata_reg(1), R => '0' ); \rxdata_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(2), Q => rxdata_reg(2), R => '0' ); \rxdata_reg_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(3), Q => rxdata_reg(3), R => '0' ); \rxdata_reg_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(4), Q => rxdata_reg(4), R => '0' ); \rxdata_reg_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(5), Q => rxdata_reg(5), R => '0' ); \rxdata_reg_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(6), Q => rxdata_reg(6), R => '0' ); \rxdata_reg_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(7), Q => rxdata_reg(7), R => '0' ); \rxdata_reg_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(8), Q => rxdata_reg(8), R => '0' ); \rxdata_reg_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(9), Q => rxdata_reg(9), R => '0' ); \rxdisperr_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxdisperr_reg__0\(0), Q => rxdisperr_double(0), R => SR(0) ); \rxdisperr_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxdisperr_reg__0\(1), Q => rxdisperr_double(1), R => SR(0) ); rxdisperr_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdisperr_double(1), I1 => toggle, I2 => rxdisperr_double(0), O => rxdisperr_i_1_n_0 ); rxdisperr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxdisperr_i_1_n_0, Q => rxdisperr, R => SR(0) ); \rxdisperr_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl1_out(0), Q => \rxdisperr_reg__0\(0), R => '0' ); \rxdisperr_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl1_out(1), Q => \rxdisperr_reg__0\(1), R => '0' ); \rxnotintable_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxnotintable_reg__0\(0), Q => rxnotintable_double(0), R => SR(0) ); \rxnotintable_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxnotintable_reg__0\(1), Q => rxnotintable_double(1), R => SR(0) ); rxnotintable_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxnotintable_double(1), I1 => toggle, I2 => rxnotintable_double(0), O => rxnotintable_i_1_n_0 ); rxnotintable_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxnotintable_i_1_n_0, Q => rxnotintable, R => SR(0) ); \rxnotintable_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl3_out(0), Q => \rxnotintable_reg__0\(0), R => '0' ); \rxnotintable_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxctrl3_out(1), Q => \rxnotintable_reg__0\(1), R => '0' ); rxpowerdown_double_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => toggle, D => \rxpowerdown_reg__0\, Q => rxpowerdown_double, R => SR(0) ); rxpowerdown_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => rxpowerdown_double, Q => rxpowerdown, R => '0' ); rxpowerdown_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => powerdown, Q => \rxpowerdown_reg__0\, R => SR(0) ); toggle_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => toggle, O => toggle_i_1_n_0 ); toggle_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => toggle_i_1_n_0, Q => toggle, R => '0' ); txbuferr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txbufstatus_reg(1), Q => txbuferr, R => '0' ); \txbufstatus_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => gig_ethernet_pcs_pma_0_gt_i_n_118, Q => txbufstatus_reg(1), R => '0' ); \txchardispmode_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(0), Q => txchardispmode_double(0), R => txreset ); \txchardispmode_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => txchardispmode_reg_reg_0(0), Q => txchardispmode_double(1), R => txreset ); \txchardispmode_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispmode_double(0), Q => txchardispmode_int(0), R => '0' ); \txchardispmode_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispmode_double(1), Q => txchardispmode_int(1), R => '0' ); txchardispmode_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txchardispmode_reg_reg_0(0), Q => \p_1_in__1\(0), R => txreset ); \txchardispval_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__0\(0), Q => txchardispval_double(0), R => txreset ); \txchardispval_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => txchardispval_reg_reg_0(0), Q => txchardispval_double(1), R => txreset ); \txchardispval_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispval_double(0), Q => txchardispval_int(0), R => '0' ); \txchardispval_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispval_double(1), Q => txchardispval_int(1), R => '0' ); txchardispval_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txchardispval_reg_reg_0(0), Q => \p_1_in__0\(0), R => txreset ); \txcharisk_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__2\(0), Q => txcharisk_double(0), R => txreset ); \txcharisk_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => txcharisk_reg_reg_0(0), Q => txcharisk_double(1), R => txreset ); \txcharisk_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txcharisk_double(0), Q => txcharisk_int(0), R => '0' ); \txcharisk_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txcharisk_double(1), Q => txcharisk_int(1), R => '0' ); txcharisk_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txcharisk_reg_reg_0(0), Q => \p_1_in__2\(0), R => txreset ); \txdata_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(0), Q => txdata_double(0), R => txreset ); \txdata_double_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(2), Q => txdata_double(10), R => txreset ); \txdata_double_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(3), Q => txdata_double(11), R => txreset ); \txdata_double_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(4), Q => txdata_double(12), R => txreset ); \txdata_double_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(5), Q => txdata_double(13), R => txreset ); \txdata_double_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(6), Q => txdata_double(14), R => txreset ); \txdata_double_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(7), Q => txdata_double(15), R => txreset ); \txdata_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(1), Q => txdata_double(1), R => txreset ); \txdata_double_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(2), Q => txdata_double(2), R => txreset ); \txdata_double_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(3), Q => txdata_double(3), R => txreset ); \txdata_double_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(4), Q => txdata_double(4), R => txreset ); \txdata_double_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(5), Q => txdata_double(5), R => txreset ); \txdata_double_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(6), Q => txdata_double(6), R => txreset ); \txdata_double_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(7), Q => txdata_double(7), R => txreset ); \txdata_double_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(0), Q => txdata_double(8), R => txreset ); \txdata_double_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(1), Q => txdata_double(9), R => txreset ); \txdata_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(0), Q => txdata_int(0), R => '0' ); \txdata_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(10), Q => txdata_int(10), R => '0' ); \txdata_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(11), Q => txdata_int(11), R => '0' ); \txdata_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(12), Q => txdata_int(12), R => '0' ); \txdata_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(13), Q => txdata_int(13), R => '0' ); \txdata_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(14), Q => txdata_int(14), R => '0' ); \txdata_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(15), Q => txdata_int(15), R => '0' ); \txdata_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(1), Q => txdata_int(1), R => '0' ); \txdata_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(2), Q => txdata_int(2), R => '0' ); \txdata_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(3), Q => txdata_int(3), R => '0' ); \txdata_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(4), Q => txdata_int(4), R => '0' ); \txdata_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(5), Q => txdata_int(5), R => '0' ); \txdata_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(6), Q => txdata_int(6), R => '0' ); \txdata_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(7), Q => txdata_int(7), R => '0' ); \txdata_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(8), Q => txdata_int(8), R => '0' ); \txdata_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(9), Q => txdata_int(9), R => '0' ); \txdata_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(0), Q => p_1_in(0), R => txreset ); \txdata_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(1), Q => p_1_in(1), R => txreset ); \txdata_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(2), Q => p_1_in(2), R => txreset ); \txdata_reg_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(3), Q => p_1_in(3), R => txreset ); \txdata_reg_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(4), Q => p_1_in(4), R => txreset ); \txdata_reg_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(5), Q => p_1_in(5), R => txreset ); \txdata_reg_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(6), Q => p_1_in(6), R => txreset ); \txdata_reg_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(7), Q => p_1_in(7), R => txreset ); txpowerdown_double_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \txpowerdown_reg__0\, Q => txpowerdown_double, R => txreset ); txpowerdown_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => txpowerdown_double, Q => txpowerdown, R => '0' ); txpowerdown_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => powerdown, Q => \txpowerdown_reg__0\, R => txreset ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block is port ( gtrefclk : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; txoutclk : out STD_LOGIC; rxoutclk : out STD_LOGIC; resetdone : out STD_LOGIC; cplllock : out STD_LOGIC; mmcm_reset : out STD_LOGIC; mmcm_locked : in STD_LOGIC; userclk : in STD_LOGIC; userclk2 : in STD_LOGIC; rxuserclk : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; pma_reset : in STD_LOGIC; gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; gmii_isolate : out STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 4 downto 0 ); status_vector : out STD_LOGIC_VECTOR ( 15 downto 0 ); reset : in STD_LOGIC; gtpowergood : out STD_LOGIC; signal_detect : in STD_LOGIC ); attribute EXAMPLE_SIMULATION : integer; attribute EXAMPLE_SIMULATION of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block : entity is "gig_ethernet_pcs_pma_0_block"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block : entity is "yes"; end gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block; architecture STRUCTURE of gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block is signal \\ : STD_LOGIC; signal enablealign : STD_LOGIC; signal mgt_rx_reset : STD_LOGIC; signal mgt_tx_reset : STD_LOGIC; signal powerdown : STD_LOGIC; signal \^resetdone\ : STD_LOGIC; signal resetdone_i : STD_LOGIC; signal rxbuferr : STD_LOGIC; signal rxchariscomma : STD_LOGIC; signal rxcharisk : STD_LOGIC; signal rxclkcorcnt : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdata : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rxdisperr : STD_LOGIC; signal rxnotintable : STD_LOGIC; signal \^status_vector\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal txbuferr : STD_LOGIC; signal txchardispmode : STD_LOGIC; signal txchardispval : STD_LOGIC; signal txcharisk : STD_LOGIC; signal txdata : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 7 ); signal NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute B_SHIFTER_ADDR : string; attribute B_SHIFTER_ADDR of gig_ethernet_pcs_pma_0_core : label is "10'b0101010000"; attribute C_1588 : integer; attribute C_1588 of gig_ethernet_pcs_pma_0_core : label is 0; attribute C_2_5G : string; attribute C_2_5G of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of gig_ethernet_pcs_pma_0_core : label is "gig_ethernet_pcs_pma_0"; attribute C_DYNAMIC_SWITCHING : string; attribute C_DYNAMIC_SWITCHING of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_ELABORATION_TRANSIENT_DIR : string; attribute C_ELABORATION_TRANSIENT_DIR of gig_ethernet_pcs_pma_0_core : label is "BlankString"; attribute C_FAMILY : string; attribute C_FAMILY of gig_ethernet_pcs_pma_0_core : label is "kintexu"; attribute C_HAS_AN : string; attribute C_HAS_AN of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_HAS_AXIL : string; attribute C_HAS_AXIL of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_HAS_MDIO : string; attribute C_HAS_MDIO of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_HAS_TEMAC : string; attribute C_HAS_TEMAC of gig_ethernet_pcs_pma_0_core : label is "TRUE"; attribute C_IS_SGMII : string; attribute C_IS_SGMII of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_RX_GMII_CLK : string; attribute C_RX_GMII_CLK of gig_ethernet_pcs_pma_0_core : label is "TXOUTCLK"; attribute C_SGMII_FABRIC_BUFFER : string; attribute C_SGMII_FABRIC_BUFFER of gig_ethernet_pcs_pma_0_core : label is "TRUE"; attribute C_SGMII_PHY_MODE : string; attribute C_SGMII_PHY_MODE of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_USE_LVDS : string; attribute C_USE_LVDS of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_USE_TBI : string; attribute C_USE_TBI of gig_ethernet_pcs_pma_0_core : label is "FALSE"; attribute C_USE_TRANSCEIVER : string; attribute C_USE_TRANSCEIVER of gig_ethernet_pcs_pma_0_core : label is "TRUE"; attribute GT_RX_BYTE_WIDTH : integer; attribute GT_RX_BYTE_WIDTH of gig_ethernet_pcs_pma_0_core : label is 1; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of gig_ethernet_pcs_pma_0_core : label is "soft"; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_0_core : label is "yes"; attribute is_du_within_envelope : string; attribute is_du_within_envelope of gig_ethernet_pcs_pma_0_core : label is "true"; begin resetdone <= \^resetdone\; status_vector(15) <= \\; status_vector(14) <= \\; status_vector(13) <= \\; status_vector(12) <= \\; status_vector(11) <= \\; status_vector(10) <= \\; status_vector(9) <= \\; status_vector(8) <= \\; status_vector(7) <= \\; status_vector(6 downto 0) <= \^status_vector\(6 downto 0); GND: unisim.vcomponents.GND port map ( G => \\ ); gig_ethernet_pcs_pma_0_core: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_v16_2_1 port map ( an_adv_config_val => '0', an_adv_config_vector(15 downto 0) => B"0000000000000000", an_enable => NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED, an_interrupt => NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED, an_restart_config => '0', basex_or_sgmii => '0', configuration_valid => '0', configuration_vector(4) => '0', configuration_vector(3 downto 1) => configuration_vector(3 downto 1), configuration_vector(0) => '0', correction_timer(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", dcm_locked => mmcm_locked, drp_daddr(9 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED(9 downto 0), drp_dclk => '0', drp_den => NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED, drp_di(15 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED(15 downto 0), drp_do(15 downto 0) => B"0000000000000000", drp_drdy => '0', drp_dwe => NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED, drp_gnt => '0', drp_req => NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED, en_cdet => NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED, enablealign => enablealign, ewrap => NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED, gmii_isolate => gmii_isolate, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), gtx_clk => '0', link_timer_basex(9 downto 0) => B"0000000000", link_timer_sgmii(9 downto 0) => B"0000000000", link_timer_value(9 downto 0) => B"0000000000", loc_ref => NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED, mdc => '0', mdio_in => '0', mdio_out => NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED, mdio_tri => NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED, mgt_rx_reset => mgt_rx_reset, mgt_tx_reset => mgt_tx_reset, phyad(4 downto 0) => B"00000", pma_rx_clk0 => '0', pma_rx_clk1 => '0', powerdown => powerdown, reset => reset, reset_done => \^resetdone\, rx_code_group0(9 downto 0) => B"0000000000", rx_code_group1(9 downto 0) => B"0000000000", rx_gt_nominal_latency(15 downto 0) => B"0000000010111100", rxbufstatus(1) => rxbuferr, rxbufstatus(0) => '0', rxchariscomma(0) => rxchariscomma, rxcharisk(0) => rxcharisk, rxclkcorcnt(2) => '0', rxclkcorcnt(1 downto 0) => rxclkcorcnt(1 downto 0), rxdata(7 downto 0) => rxdata(7 downto 0), rxdisperr(0) => rxdisperr, rxnotintable(0) => rxnotintable, rxphy_correction_timer(63 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED(63 downto 0), rxphy_ns_field(31 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED(31 downto 0), rxphy_s_field(47 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED(47 downto 0), rxrecclk => '0', rxrundisp(0) => '0', s_axi_aclk => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arready => NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED, s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awready => NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED, s_axi_awvalid => '0', s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED, s_axi_rdata(31 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED(31 downto 0), s_axi_resetn => '0', s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED, s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_wready => NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED, s_axi_wvalid => '0', signal_detect => signal_detect, speed_is_100 => '0', speed_is_10_100 => '0', speed_selection(1 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED(1 downto 0), status_vector(15 downto 7) => NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED(15 downto 7), status_vector(6 downto 0) => \^status_vector\(6 downto 0), systemtimer_ns_field(31 downto 0) => B"00000000000000000000000000000000", systemtimer_s_field(47 downto 0) => B"000000000000000000000000000000000000000000000000", tx_code_group(9 downto 0) => NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED(9 downto 0), txbuferr => txbuferr, txchardispmode => txchardispmode, txchardispval => txchardispval, txcharisk => txcharisk, txdata(7 downto 0) => txdata(7 downto 0), userclk => '0', userclk2 => userclk2 ); sync_block_reset_done: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block port map ( data_in => resetdone_i, resetdone => \^resetdone\, userclk2 => userclk2 ); transceiver_inst: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver port map ( D(7 downto 0) => txdata(7 downto 0), Q(1 downto 0) => rxclkcorcnt(1 downto 0), SR(0) => mgt_rx_reset, cplllock => cplllock, data_in => resetdone_i, enablealign => enablealign, gtpowergood => gtpowergood, gtrefclk => gtrefclk, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, powerdown => powerdown, rxbuferr => rxbuferr, rxchariscomma => rxchariscomma, rxcharisk => rxcharisk, \rxdata_reg[7]_0\(7 downto 0) => rxdata(7 downto 0), rxdisperr => rxdisperr, rxn => rxn, rxnotintable => rxnotintable, rxoutclk => rxoutclk, rxp => rxp, rxuserclk2 => rxuserclk2, txbuferr => txbuferr, txchardispmode_reg_reg_0(0) => txchardispmode, txchardispval_reg_reg_0(0) => txchardispval, txcharisk_reg_reg_0(0) => txcharisk, txn => txn, txoutclk => txoutclk, txp => txp, txreset => mgt_tx_reset, userclk => userclk, userclk2 => userclk2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity gig_ethernet_pcs_pma_0 is port ( gtrefclk : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; resetdone : out STD_LOGIC; cplllock : out STD_LOGIC; mmcm_reset : out STD_LOGIC; txoutclk : out STD_LOGIC; rxoutclk : out STD_LOGIC; userclk : in STD_LOGIC; userclk2 : in STD_LOGIC; rxuserclk : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; pma_reset : in STD_LOGIC; mmcm_locked : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; gmii_isolate : out STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 4 downto 0 ); status_vector : out STD_LOGIC_VECTOR ( 15 downto 0 ); reset : in STD_LOGIC; gtpowergood : out STD_LOGIC; signal_detect : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of gig_ethernet_pcs_pma_0 : entity is true; attribute EXAMPLE_SIMULATION : integer; attribute EXAMPLE_SIMULATION of gig_ethernet_pcs_pma_0 : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of gig_ethernet_pcs_pma_0 : entity is "gig_ethernet_pcs_pma_v16_2_1,Vivado 2020.2"; end gig_ethernet_pcs_pma_0; architecture STRUCTURE of gig_ethernet_pcs_pma_0 is signal \\ : STD_LOGIC; signal \^status_vector\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal NLW_U0_status_vector_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 7 ); attribute EXAMPLE_SIMULATION of U0 : label is 0; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin status_vector(15) <= \\; status_vector(14) <= \\; status_vector(13) <= \\; status_vector(12) <= \\; status_vector(11) <= \\; status_vector(10) <= \\; status_vector(9) <= \\; status_vector(8) <= \\; status_vector(7) <= \\; status_vector(6 downto 0) <= \^status_vector\(6 downto 0); GND: unisim.vcomponents.GND port map ( G => \\ ); U0: entity work.gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block port map ( configuration_vector(4) => '0', configuration_vector(3 downto 1) => configuration_vector(3 downto 1), configuration_vector(0) => '0', cplllock => cplllock, gmii_isolate => gmii_isolate, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), gtpowergood => gtpowergood, gtrefclk => gtrefclk, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, reset => reset, resetdone => resetdone, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, rxuserclk => '0', rxuserclk2 => rxuserclk2, signal_detect => signal_detect, status_vector(15 downto 7) => NLW_U0_status_vector_UNCONNECTED(15 downto 7), status_vector(6 downto 0) => \^status_vector\(6 downto 0), txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk, userclk2 => userclk2 ); end STRUCTURE;