// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 // Date : Fri Mar 12 21:28:49 2021 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim // d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_sim_netlist.v // Design : gig_ethernet_pcs_pma_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xcku115-flva2104-1-c // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "gig_ethernet_pcs_pma_v16_2_1,Vivado 2020.2" *) (* NotValidForBitStream *) module gig_ethernet_pcs_pma_0 (gtrefclk, txp, txn, rxp, rxn, resetdone, cplllock, mmcm_reset, txoutclk, rxoutclk, userclk, userclk2, rxuserclk, rxuserclk2, pma_reset, mmcm_locked, independent_clock_bufg, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, gtpowergood, signal_detect); input gtrefclk; output txp; output txn; input rxp; input rxn; output resetdone; output cplllock; output mmcm_reset; output txoutclk; output rxoutclk; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input pma_reset; input mmcm_locked; input independent_clock_bufg; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; output gtpowergood; input signal_detect; wire \ ; wire [4:0]configuration_vector; wire cplllock; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gtpowergood; wire gtrefclk; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire reset; wire resetdone; wire rxn; wire rxoutclk; wire rxp; wire rxuserclk2; wire signal_detect; wire [6:0]\^status_vector ; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; wire [15:7]NLW_U0_status_vector_UNCONNECTED; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; GND GND (.G(\ )); (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block U0 (.configuration_vector({1'b0,configuration_vector[3:1],1'b0}), .cplllock(cplllock), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gtpowergood(gtpowergood), .gtrefclk(gtrefclk), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .reset(reset), .resetdone(resetdone), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .rxuserclk(1'b0), .rxuserclk2(rxuserclk2), .signal_detect(signal_detect), .status_vector({NLW_U0_status_vector_UNCONNECTED[15:7],\^status_vector }), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk), .userclk2(userclk2)); endmodule (* EXAMPLE_SIMULATION = "0" *) (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_block" *) (* downgradeipidentifiedwarnings = "yes" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_block (gtrefclk, txp, txn, rxp, rxn, txoutclk, rxoutclk, resetdone, cplllock, mmcm_reset, mmcm_locked, userclk, userclk2, rxuserclk, rxuserclk2, independent_clock_bufg, pma_reset, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, gtpowergood, signal_detect); input gtrefclk; output txp; output txn; input rxp; input rxn; output txoutclk; output rxoutclk; output resetdone; output cplllock; output mmcm_reset; input mmcm_locked; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input independent_clock_bufg; input pma_reset; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; output gtpowergood; input signal_detect; wire \ ; wire [4:0]configuration_vector; wire cplllock; wire enablealign; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gtpowergood; wire gtrefclk; wire independent_clock_bufg; wire mgt_rx_reset; wire mgt_tx_reset; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire powerdown; wire reset; wire resetdone; wire resetdone_i; wire rxbuferr; wire rxchariscomma; wire rxcharisk; wire [1:0]rxclkcorcnt; wire [7:0]rxdata; wire rxdisperr; wire rxn; wire rxnotintable; wire rxoutclk; wire rxp; wire rxuserclk2; wire signal_detect; wire [6:0]\^status_vector ; wire txbuferr; wire txchardispmode; wire txchardispval; wire txcharisk; wire [7:0]txdata; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; wire NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED; wire [15:0]NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED; wire [63:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED; wire [47:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED; wire [15:7]NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; GND GND (.G(\ )); (* B_SHIFTER_ADDR = "10'b0101010000" *) (* C_1588 = "0" *) (* C_2_5G = "FALSE" *) (* C_COMPONENT_NAME = "gig_ethernet_pcs_pma_0" *) (* C_DYNAMIC_SWITCHING = "FALSE" *) (* C_ELABORATION_TRANSIENT_DIR = "BlankString" *) (* C_FAMILY = "kintexu" *) (* C_HAS_AN = "FALSE" *) (* C_HAS_AXIL = "FALSE" *) (* C_HAS_MDIO = "FALSE" *) (* C_HAS_TEMAC = "TRUE" *) (* C_IS_SGMII = "FALSE" *) (* C_RX_GMII_CLK = "TXOUTCLK" *) (* C_SGMII_FABRIC_BUFFER = "TRUE" *) (* C_SGMII_PHY_MODE = "FALSE" *) (* C_USE_LVDS = "FALSE" *) (* C_USE_TBI = "FALSE" *) (* C_USE_TRANSCEIVER = "TRUE" *) (* GT_RX_BYTE_WIDTH = "1" *) (* KEEP_HIERARCHY = "soft" *) (* downgradeipidentifiedwarnings = "yes" *) (* is_du_within_envelope = "true" *) gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_v16_2_1 gig_ethernet_pcs_pma_0_core (.an_adv_config_val(1'b0), .an_adv_config_vector({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .an_enable(NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED), .an_interrupt(NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED), .an_restart_config(1'b0), .basex_or_sgmii(1'b0), .configuration_valid(1'b0), .configuration_vector({1'b0,configuration_vector[3:1],1'b0}), .correction_timer({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .dcm_locked(mmcm_locked), .drp_daddr(NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED[9:0]), .drp_dclk(1'b0), .drp_den(NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED), .drp_di(NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED[15:0]), .drp_do({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drp_drdy(1'b0), .drp_dwe(NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED), .drp_gnt(1'b0), .drp_req(NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED), .en_cdet(NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED), .enablealign(enablealign), .ewrap(NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gtx_clk(1'b0), .link_timer_basex({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_sgmii({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_value({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .loc_ref(NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED), .mdc(1'b0), .mdio_in(1'b0), .mdio_out(NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED), .mdio_tri(NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED), .mgt_rx_reset(mgt_rx_reset), .mgt_tx_reset(mgt_tx_reset), .phyad({1'b0,1'b0,1'b0,1'b0,1'b0}), .pma_rx_clk0(1'b0), .pma_rx_clk1(1'b0), .powerdown(powerdown), .reset(reset), .reset_done(resetdone), .rx_code_group0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_code_group1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_gt_nominal_latency({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0}), .rxbufstatus({rxbuferr,1'b0}), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .rxclkcorcnt({1'b0,rxclkcorcnt}), .rxdata(rxdata), .rxdisperr(rxdisperr), .rxnotintable(rxnotintable), .rxphy_correction_timer(NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED[63:0]), .rxphy_ns_field(NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED[31:0]), .rxphy_s_field(NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED[47:0]), .rxrecclk(1'b0), .rxrundisp(1'b0), .s_axi_aclk(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED), .s_axi_awvalid(1'b0), .s_axi_bready(1'b0), .s_axi_bresp(NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED[31:0]), .s_axi_resetn(1'b0), .s_axi_rready(1'b0), .s_axi_rresp(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED), .s_axi_wvalid(1'b0), .signal_detect(signal_detect), .speed_is_100(1'b0), .speed_is_10_100(1'b0), .speed_selection(NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED[1:0]), .status_vector({NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED[15:7],\^status_vector }), .systemtimer_ns_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .systemtimer_s_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx_code_group(NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED[9:0]), .txbuferr(txbuferr), .txchardispmode(txchardispmode), .txchardispval(txchardispval), .txcharisk(txcharisk), .txdata(txdata), .userclk(1'b0), .userclk2(userclk2)); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block sync_block_reset_done (.data_in(resetdone_i), .resetdone(resetdone), .userclk2(userclk2)); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver transceiver_inst (.D(txdata), .Q(rxclkcorcnt), .SR(mgt_rx_reset), .cplllock(cplllock), .data_in(resetdone_i), .enablealign(enablealign), .gtpowergood(gtpowergood), .gtrefclk(gtrefclk), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .powerdown(powerdown), .rxbuferr(rxbuferr), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .\rxdata_reg[7]_0 (rxdata), .rxdisperr(rxdisperr), .rxn(rxn), .rxnotintable(rxnotintable), .rxoutclk(rxoutclk), .rxp(rxp), .rxuserclk2(rxuserclk2), .txbuferr(txbuferr), .txchardispmode_reg_reg_0(txchardispmode), .txchardispval_reg_reg_0(txchardispval), .txcharisk_reg_reg_0(txcharisk), .txn(txn), .txoutclk(txoutclk), .txp(txp), .txreset(mgt_tx_reset), .userclk(userclk), .userclk2(userclk2)); endmodule (* CHECK_LICENSE_TYPE = "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}" *) (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_gt" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt (gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, cpllrefclksel_in, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drpwe_in, eyescanreset_in, eyescantrigger_in, gthrxn_in, gthrxp_in, gtrefclk0_in, gtrefclk1_in, loopback_in, pcsrsvdin_in, rx8b10ben_in, rxbufreset_in, rxcdrhold_in, rxcommadeten_in, rxdfelpmreset_in, rxlpmen_in, rxmcommaalignen_in, rxpcommaalignen_in, rxpcsreset_in, rxpd_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxrate_in, rxusrclk_in, rxusrclk2_in, tx8b10ben_in, txctrl0_in, txctrl1_in, txctrl2_in, txdiffctrl_in, txelecidle_in, txinhibit_in, txpcsreset_in, txpd_in, txpmareset_in, txpolarity_in, txpostcursor_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txusrclk_in, txusrclk2_in, cplllock_out, dmonitorout_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxbufstatus_out, rxbyteisaligned_out, rxbyterealign_out, rxclkcorcnt_out, rxcommadet_out, rxctrl0_out, rxctrl1_out, rxctrl2_out, rxctrl3_out, rxoutclk_out, rxpmaresetdone_out, rxprbserr_out, rxresetdone_out, txbufstatus_out, txoutclk_out, txpmaresetdone_out, txprgdivresetdone_out, txresetdone_out); input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [15:0]gtwiz_userdata_tx_in; output [15:0]gtwiz_userdata_rx_out; input [2:0]cpllrefclksel_in; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [0:0]gtrefclk1_in; input [2:0]loopback_in; input [15:0]pcsrsvdin_in; input [0:0]rx8b10ben_in; input [0:0]rxbufreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcommadeten_in; input [0:0]rxdfelpmreset_in; input [0:0]rxlpmen_in; input [0:0]rxmcommaalignen_in; input [0:0]rxpcommaalignen_in; input [0:0]rxpcsreset_in; input [1:0]rxpd_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [2:0]rxrate_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]tx8b10ben_in; input [15:0]txctrl0_in; input [15:0]txctrl1_in; input [7:0]txctrl2_in; input [3:0]txdiffctrl_in; input [0:0]txelecidle_in; input [0:0]txinhibit_in; input [0:0]txpcsreset_in; input [1:0]txpd_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [0:0]cplllock_out; output [16:0]dmonitorout_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [2:0]rxbufstatus_out; output [0:0]rxbyteisaligned_out; output [0:0]rxbyterealign_out; output [1:0]rxclkcorcnt_out; output [0:0]rxcommadet_out; output [15:0]rxctrl0_out; output [15:0]rxctrl1_out; output [7:0]rxctrl2_out; output [7:0]rxctrl3_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxresetdone_out; output [1:0]txbufstatus_out; output [0:0]txoutclk_out; output [0:0]txpmaresetdone_out; output [0:0]txprgdivresetdone_out; output [0:0]txresetdone_out; wire \ ; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire [2:2]\^rxbufstatus_out ; wire [1:0]rxclkcorcnt_out; wire [1:0]\^rxctrl0_out ; wire [1:0]\^rxctrl1_out ; wire [1:0]\^rxctrl2_out ; wire [1:0]\^rxctrl3_out ; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [1:0]rxpd_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [15:0]txctrl0_in; wire [15:0]txctrl1_in; wire [7:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [2:0]NLW_inst_bufgtce_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtcemask_out_UNCONNECTED; wire [8:0]NLW_inst_bufgtdiv_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtreset_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtrstmask_out_UNCONNECTED; wire [0:0]NLW_inst_cpllfbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_cpllrefclklost_out_UNCONNECTED; wire [16:0]NLW_inst_dmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_dmonitoroutclk_out_UNCONNECTED; wire [15:0]NLW_inst_drpdo_common_out_UNCONNECTED; wire [15:0]NLW_inst_drpdo_out_UNCONNECTED; wire [0:0]NLW_inst_drprdy_common_out_UNCONNECTED; wire [0:0]NLW_inst_drprdy_out_UNCONNECTED; wire [0:0]NLW_inst_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_inst_gtrefclkmonitor_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxn_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxp_out_UNCONNECTED; wire [0:0]NLW_inst_pcierategen3_out_UNCONNECTED; wire [0:0]NLW_inst_pcierateidle_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllpd_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllreset_out_UNCONNECTED; wire [0:0]NLW_inst_pciesynctxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_pcieusergen3rdy_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserphystatusrst_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserratestart_out_UNCONNECTED; wire [11:0]NLW_inst_pcsrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_phystatus_out_UNCONNECTED; wire [7:0]NLW_inst_pinrsrvdas_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout0_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout1_out_UNCONNECTED; wire [0:0]NLW_inst_powerpresent_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0refclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1refclklost_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor0_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor0_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_resetexception_out_UNCONNECTED; wire [1:0]NLW_inst_rxbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyteisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyterealign_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrlock_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrphdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanbondseq_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanrealign_out_UNCONNECTED; wire [4:0]NLW_inst_rxchbondo_out_UNCONNECTED; wire [0:0]NLW_inst_rxckcaldone_out_UNCONNECTED; wire [0:0]NLW_inst_rxcominitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcommadet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomsasdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomwakedet_out_UNCONNECTED; wire [15:2]NLW_inst_rxctrl0_out_UNCONNECTED; wire [15:2]NLW_inst_rxctrl1_out_UNCONNECTED; wire [7:2]NLW_inst_rxctrl2_out_UNCONNECTED; wire [7:2]NLW_inst_rxctrl3_out_UNCONNECTED; wire [127:0]NLW_inst_rxdata_out_UNCONNECTED; wire [7:0]NLW_inst_rxdataextendrsvd_out_UNCONNECTED; wire [1:0]NLW_inst_rxdatavalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxelecidle_out_UNCONNECTED; wire [5:0]NLW_inst_rxheader_out_UNCONNECTED; wire [1:0]NLW_inst_rxheadervalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpstresetdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED; wire [6:0]NLW_inst_rxmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobedone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobestarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_rxphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_rxphalignerr_out_UNCONNECTED; wire [0:0]NLW_inst_rxpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbslocked_out_UNCONNECTED; wire [0:0]NLW_inst_rxprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_rxratedone_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk0_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk0sel_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk1_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk1sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclkout_out_UNCONNECTED; wire [0:0]NLW_inst_rxresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsliderdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipoutclkrdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslippmardy_out_UNCONNECTED; wire [1:0]NLW_inst_rxstartofseq_out_UNCONNECTED; wire [2:0]NLW_inst_rxstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_rxvalid_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0testdata_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1testdata_out_UNCONNECTED; wire [0:0]NLW_inst_tcongpo_out_UNCONNECTED; wire [0:0]NLW_inst_tconrsvdout0_out_UNCONNECTED; wire [0:0]NLW_inst_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_txcomfinish_out_UNCONNECTED; wire [0:0]NLW_inst_txdccdone_out_UNCONNECTED; wire [0:0]NLW_inst_txdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_txphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_txphinitdone_out_UNCONNECTED; wire [0:0]NLW_inst_txpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_txratedone_out_UNCONNECTED; wire [0:0]NLW_inst_txresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_ubdaddr_out_UNCONNECTED; wire [0:0]NLW_inst_ubden_out_UNCONNECTED; wire [0:0]NLW_inst_ubdi_out_UNCONNECTED; wire [0:0]NLW_inst_ubdwe_out_UNCONNECTED; wire [0:0]NLW_inst_ubmdmtdo_out_UNCONNECTED; wire [0:0]NLW_inst_ubrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_ubtxuart_out_UNCONNECTED; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign drpdo_out[15] = \ ; assign drpdo_out[14] = \ ; assign drpdo_out[13] = \ ; assign drpdo_out[12] = \ ; assign drpdo_out[11] = \ ; assign drpdo_out[10] = \ ; assign drpdo_out[9] = \ ; assign drpdo_out[8] = \ ; assign drpdo_out[7] = \ ; assign drpdo_out[6] = \ ; assign drpdo_out[5] = \ ; assign drpdo_out[4] = \ ; assign drpdo_out[3] = \ ; assign drpdo_out[2] = \ ; assign drpdo_out[1] = \ ; assign drpdo_out[0] = \ ; assign drprdy_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxbyteisaligned_out[0] = \ ; assign rxbyterealign_out[0] = \ ; assign rxcommadet_out[0] = \ ; assign rxctrl0_out[15] = \ ; assign rxctrl0_out[14] = \ ; assign rxctrl0_out[13] = \ ; assign rxctrl0_out[12] = \ ; assign rxctrl0_out[11] = \ ; assign rxctrl0_out[10] = \ ; assign rxctrl0_out[9] = \ ; assign rxctrl0_out[8] = \ ; assign rxctrl0_out[7] = \ ; assign rxctrl0_out[6] = \ ; assign rxctrl0_out[5] = \ ; assign rxctrl0_out[4] = \ ; assign rxctrl0_out[3] = \ ; assign rxctrl0_out[2] = \ ; assign rxctrl0_out[1:0] = \^rxctrl0_out [1:0]; assign rxctrl1_out[15] = \ ; assign rxctrl1_out[14] = \ ; assign rxctrl1_out[13] = \ ; assign rxctrl1_out[12] = \ ; assign rxctrl1_out[11] = \ ; assign rxctrl1_out[10] = \ ; assign rxctrl1_out[9] = \ ; assign rxctrl1_out[8] = \ ; assign rxctrl1_out[7] = \ ; assign rxctrl1_out[6] = \ ; assign rxctrl1_out[5] = \ ; assign rxctrl1_out[4] = \ ; assign rxctrl1_out[3] = \ ; assign rxctrl1_out[2] = \ ; assign rxctrl1_out[1:0] = \^rxctrl1_out [1:0]; assign rxctrl2_out[7] = \ ; assign rxctrl2_out[6] = \ ; assign rxctrl2_out[5] = \ ; assign rxctrl2_out[4] = \ ; assign rxctrl2_out[3] = \ ; assign rxctrl2_out[2] = \ ; assign rxctrl2_out[1:0] = \^rxctrl2_out [1:0]; assign rxctrl3_out[7] = \ ; assign rxctrl3_out[6] = \ ; assign rxctrl3_out[5] = \ ; assign rxctrl3_out[4] = \ ; assign rxctrl3_out[3] = \ ; assign rxctrl3_out[2] = \ ; assign rxctrl3_out[1:0] = \^rxctrl3_out [1:0]; assign rxpmaresetdone_out[0] = \ ; assign rxprbserr_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txpmaresetdone_out[0] = \ ; assign txprgdivresetdone_out[0] = \ ; assign txresetdone_out[0] = \ ; GND GND (.G(\ )); (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "1" *) (* C_RX_CC_K = "8'b00010001" *) (* C_RX_CC_LEN_SEQ = "2" *) (* C_RX_CC_NUM_SEQ = "2" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100" *) (* C_RX_COMMA_M_ENABLE = "1" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "1" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "1" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "20" *) (* C_RX_LINE_RATE = "1.250000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "62.500000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "16" *) (* C_RX_USRCLK2_FREQUENCY = "62.500000" *) (* C_RX_USRCLK_FREQUENCY = "62.500000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "1" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "125.000000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "1" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "20" *) (* C_TX_LINE_RATE = "1.250000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "2" *) (* C_TX_OUTCLK_FREQUENCY = "62.500000" *) (* C_TX_OUTCLK_SOURCE = "4" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "16" *) (* C_TX_USRCLK2_FREQUENCY = "62.500000" *) (* C_TX_USRCLK_FREQUENCY = "62.500000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top inst (.bgbypassb_in(1'b1), .bgmonitorenb_in(1'b1), .bgpdb_in(1'b1), .bgrcalovrd_in({1'b1,1'b1,1'b1,1'b1,1'b1}), .bgrcalovrdenb_in(1'b1), .bufgtce_out(NLW_inst_bufgtce_out_UNCONNECTED[2:0]), .bufgtcemask_out(NLW_inst_bufgtcemask_out_UNCONNECTED[2:0]), .bufgtdiv_out(NLW_inst_bufgtdiv_out_UNCONNECTED[8:0]), .bufgtreset_out(NLW_inst_bufgtreset_out_UNCONNECTED[2:0]), .bufgtrstmask_out(NLW_inst_bufgtrstmask_out_UNCONNECTED[2:0]), .cdrstepdir_in(1'b0), .cdrstepsq_in(1'b0), .cdrstepsx_in(1'b0), .cfgreset_in(1'b0), .clkrsvd0_in(1'b0), .clkrsvd1_in(1'b0), .cpllfbclklost_out(NLW_inst_cpllfbclklost_out_UNCONNECTED[0]), .cpllfreqlock_in(1'b0), .cplllock_out(cplllock_out), .cplllockdetclk_in(1'b0), .cplllocken_in(1'b1), .cpllpd_in(1'b0), .cpllrefclklost_out(NLW_inst_cpllrefclklost_out_UNCONNECTED[0]), .cpllrefclksel_in({1'b0,1'b0,1'b1}), .cpllreset_in(1'b0), .dmonfiforeset_in(1'b0), .dmonitorclk_in(1'b0), .dmonitorout_out(NLW_inst_dmonitorout_out_UNCONNECTED[16:0]), .dmonitoroutclk_out(NLW_inst_dmonitoroutclk_out_UNCONNECTED[0]), .drpaddr_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpaddr_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpclk_common_in(1'b0), .drpclk_in(drpclk_in), .drpdi_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdi_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdo_common_out(NLW_inst_drpdo_common_out_UNCONNECTED[15:0]), .drpdo_out(NLW_inst_drpdo_out_UNCONNECTED[15:0]), .drpen_common_in(1'b0), .drpen_in(1'b0), .drprdy_common_out(NLW_inst_drprdy_common_out_UNCONNECTED[0]), .drprdy_out(NLW_inst_drprdy_out_UNCONNECTED[0]), .drprst_in(1'b0), .drpwe_common_in(1'b0), .drpwe_in(1'b0), .elpcaldvorwren_in(1'b0), .elpcalpaorwren_in(1'b0), .evoddphicaldone_in(1'b0), .evoddphicalstart_in(1'b0), .evoddphidrden_in(1'b0), .evoddphidwren_in(1'b0), .evoddphixrden_in(1'b0), .evoddphixwren_in(1'b0), .eyescandataerror_out(NLW_inst_eyescandataerror_out_UNCONNECTED[0]), .eyescanmode_in(1'b0), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .freqos_in(1'b0), .gtgrefclk0_in(1'b0), .gtgrefclk1_in(1'b0), .gtgrefclk_in(1'b0), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtnorthrefclk00_in(1'b0), .gtnorthrefclk01_in(1'b0), .gtnorthrefclk0_in(1'b0), .gtnorthrefclk10_in(1'b0), .gtnorthrefclk11_in(1'b0), .gtnorthrefclk1_in(1'b0), .gtpowergood_out(gtpowergood_out), .gtrefclk00_in(1'b0), .gtrefclk01_in(1'b0), .gtrefclk0_in(gtrefclk0_in), .gtrefclk10_in(1'b0), .gtrefclk11_in(1'b0), .gtrefclk1_in(1'b0), .gtrefclkmonitor_out(NLW_inst_gtrefclkmonitor_out_UNCONNECTED[0]), .gtresetsel_in(1'b0), .gtrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtrxreset_in(1'b0), .gtrxresetsel_in(1'b0), .gtsouthrefclk00_in(1'b0), .gtsouthrefclk01_in(1'b0), .gtsouthrefclk0_in(1'b0), .gtsouthrefclk10_in(1'b0), .gtsouthrefclk11_in(1'b0), .gtsouthrefclk1_in(1'b0), .gttxreset_in(1'b0), .gttxresetsel_in(1'b0), .gtwiz_buffbypass_rx_done_out(NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_error_out(NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_reset_in(1'b0), .gtwiz_buffbypass_rx_start_user_in(1'b0), .gtwiz_buffbypass_tx_done_out(NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_error_out(NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_reset_in(1'b0), .gtwiz_buffbypass_tx_start_user_in(1'b0), .gtwiz_gthe3_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe3_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe3_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gtye4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_qpll0lock_in(1'b0), .gtwiz_reset_qpll0reset_out(NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED[0]), .gtwiz_reset_qpll1lock_in(1'b0), .gtwiz_reset_qpll1reset_out(NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED[0]), .gtwiz_reset_rx_cdr_stable_out(NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_in(1'b0), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(1'b0), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_in(1'b0), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(1'b0), .gtwiz_userclk_rx_active_out(NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED[0]), .gtwiz_userclk_rx_reset_in(1'b0), .gtwiz_userclk_rx_srcclk_out(NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk2_out(NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk_out(NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userclk_tx_active_out(NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED[0]), .gtwiz_userclk_tx_reset_in(1'b0), .gtwiz_userclk_tx_srcclk_out(NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk2_out(NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk_out(NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED[0]), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .gtyrxn_in(1'b0), .gtyrxp_in(1'b0), .gtytxn_out(NLW_inst_gtytxn_out_UNCONNECTED[0]), .gtytxp_out(NLW_inst_gtytxp_out_UNCONNECTED[0]), .incpctrl_in(1'b0), .loopback_in({1'b0,1'b0,1'b0}), .looprsvd_in(1'b0), .lpbkrxtxseren_in(1'b0), .lpbktxrxseren_in(1'b0), .pcieeqrxeqadaptdone_in(1'b0), .pcierategen3_out(NLW_inst_pcierategen3_out_UNCONNECTED[0]), .pcierateidle_out(NLW_inst_pcierateidle_out_UNCONNECTED[0]), .pcierateqpll0_in(1'b0), .pcierateqpll1_in(1'b0), .pcierateqpllpd_out(NLW_inst_pcierateqpllpd_out_UNCONNECTED[1:0]), .pcierateqpllreset_out(NLW_inst_pcierateqpllreset_out_UNCONNECTED[1:0]), .pcierstidle_in(1'b0), .pciersttxsyncstart_in(1'b0), .pciesynctxsyncdone_out(NLW_inst_pciesynctxsyncdone_out_UNCONNECTED[0]), .pcieusergen3rdy_out(NLW_inst_pcieusergen3rdy_out_UNCONNECTED[0]), .pcieuserphystatusrst_out(NLW_inst_pcieuserphystatusrst_out_UNCONNECTED[0]), .pcieuserratedone_in(1'b0), .pcieuserratestart_out(NLW_inst_pcieuserratestart_out_UNCONNECTED[0]), .pcsrsvdin2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdout_out(NLW_inst_pcsrsvdout_out_UNCONNECTED[11:0]), .phystatus_out(NLW_inst_phystatus_out_UNCONNECTED[0]), .pinrsrvdas_out(NLW_inst_pinrsrvdas_out_UNCONNECTED[7:0]), .pmarsvd0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdout0_out(NLW_inst_pmarsvdout0_out_UNCONNECTED[7:0]), .pmarsvdout1_out(NLW_inst_pmarsvdout1_out_UNCONNECTED[7:0]), .powerpresent_out(NLW_inst_powerpresent_out_UNCONNECTED[0]), .qpll0clk_in(1'b0), .qpll0clkrsvd0_in(1'b0), .qpll0clkrsvd1_in(1'b0), .qpll0fbclklost_out(NLW_inst_qpll0fbclklost_out_UNCONNECTED[0]), .qpll0fbdiv_in(1'b0), .qpll0freqlock_in(1'b0), .qpll0lock_out(NLW_inst_qpll0lock_out_UNCONNECTED[0]), .qpll0lockdetclk_in(1'b0), .qpll0locken_in(1'b0), .qpll0outclk_out(NLW_inst_qpll0outclk_out_UNCONNECTED[0]), .qpll0outrefclk_out(NLW_inst_qpll0outrefclk_out_UNCONNECTED[0]), .qpll0pd_in(1'b1), .qpll0refclk_in(1'b0), .qpll0refclklost_out(NLW_inst_qpll0refclklost_out_UNCONNECTED[0]), .qpll0refclksel_in({1'b0,1'b0,1'b1}), .qpll0reset_in(1'b1), .qpll1clk_in(1'b0), .qpll1clkrsvd0_in(1'b0), .qpll1clkrsvd1_in(1'b0), .qpll1fbclklost_out(NLW_inst_qpll1fbclklost_out_UNCONNECTED[0]), .qpll1fbdiv_in(1'b0), .qpll1freqlock_in(1'b0), .qpll1lock_out(NLW_inst_qpll1lock_out_UNCONNECTED[0]), .qpll1lockdetclk_in(1'b0), .qpll1locken_in(1'b0), .qpll1outclk_out(NLW_inst_qpll1outclk_out_UNCONNECTED[0]), .qpll1outrefclk_out(NLW_inst_qpll1outrefclk_out_UNCONNECTED[0]), .qpll1pd_in(1'b1), .qpll1refclk_in(1'b0), .qpll1refclklost_out(NLW_inst_qpll1refclklost_out_UNCONNECTED[0]), .qpll1refclksel_in({1'b0,1'b0,1'b1}), .qpll1reset_in(1'b1), .qplldmonitor0_out(NLW_inst_qplldmonitor0_out_UNCONNECTED[7:0]), .qplldmonitor1_out(NLW_inst_qplldmonitor1_out_UNCONNECTED[7:0]), .qpllrsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd3_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd4_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rcalenb_in(1'b1), .refclkoutmonitor0_out(NLW_inst_refclkoutmonitor0_out_UNCONNECTED[0]), .refclkoutmonitor1_out(NLW_inst_refclkoutmonitor1_out_UNCONNECTED[0]), .resetexception_out(NLW_inst_resetexception_out_UNCONNECTED[0]), .resetovrd_in(1'b0), .rstclkentx_in(1'b0), .rx8b10ben_in(1'b1), .rxafecfoken_in(1'b0), .rxbufreset_in(1'b0), .rxbufstatus_out({\^rxbufstatus_out ,NLW_inst_rxbufstatus_out_UNCONNECTED[1:0]}), .rxbyteisaligned_out(NLW_inst_rxbyteisaligned_out_UNCONNECTED[0]), .rxbyterealign_out(NLW_inst_rxbyterealign_out_UNCONNECTED[0]), .rxcdrfreqreset_in(1'b0), .rxcdrhold_in(1'b0), .rxcdrlock_out(NLW_inst_rxcdrlock_out_UNCONNECTED[0]), .rxcdrovrden_in(1'b0), .rxcdrphdone_out(NLW_inst_rxcdrphdone_out_UNCONNECTED[0]), .rxcdrreset_in(1'b0), .rxcdrresetrsv_in(1'b0), .rxchanbondseq_out(NLW_inst_rxchanbondseq_out_UNCONNECTED[0]), .rxchanisaligned_out(NLW_inst_rxchanisaligned_out_UNCONNECTED[0]), .rxchanrealign_out(NLW_inst_rxchanrealign_out_UNCONNECTED[0]), .rxchbonden_in(1'b0), .rxchbondi_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .rxchbondlevel_in({1'b0,1'b0,1'b0}), .rxchbondmaster_in(1'b0), .rxchbondo_out(NLW_inst_rxchbondo_out_UNCONNECTED[4:0]), .rxchbondslave_in(1'b0), .rxckcaldone_out(NLW_inst_rxckcaldone_out_UNCONNECTED[0]), .rxckcalreset_in(1'b0), .rxckcalstart_in(1'b0), .rxclkcorcnt_out(rxclkcorcnt_out), .rxcominitdet_out(NLW_inst_rxcominitdet_out_UNCONNECTED[0]), .rxcommadet_out(NLW_inst_rxcommadet_out_UNCONNECTED[0]), .rxcommadeten_in(1'b1), .rxcomsasdet_out(NLW_inst_rxcomsasdet_out_UNCONNECTED[0]), .rxcomwakedet_out(NLW_inst_rxcomwakedet_out_UNCONNECTED[0]), .rxctrl0_out({NLW_inst_rxctrl0_out_UNCONNECTED[15:2],\^rxctrl0_out }), .rxctrl1_out({NLW_inst_rxctrl1_out_UNCONNECTED[15:2],\^rxctrl1_out }), .rxctrl2_out({NLW_inst_rxctrl2_out_UNCONNECTED[7:2],\^rxctrl2_out }), .rxctrl3_out({NLW_inst_rxctrl3_out_UNCONNECTED[7:2],\^rxctrl3_out }), .rxdata_out(NLW_inst_rxdata_out_UNCONNECTED[127:0]), .rxdataextendrsvd_out(NLW_inst_rxdataextendrsvd_out_UNCONNECTED[7:0]), .rxdatavalid_out(NLW_inst_rxdatavalid_out_UNCONNECTED[1:0]), .rxdccforcestart_in(1'b0), .rxdfeagcctrl_in({1'b0,1'b1}), .rxdfeagchold_in(1'b0), .rxdfeagcovrden_in(1'b0), .rxdfecfokfcnum_in(1'b0), .rxdfecfokfen_in(1'b0), .rxdfecfokfpulse_in(1'b0), .rxdfecfokhold_in(1'b0), .rxdfecfokovren_in(1'b0), .rxdfekhhold_in(1'b0), .rxdfekhovrden_in(1'b0), .rxdfelfhold_in(1'b0), .rxdfelfovrden_in(1'b0), .rxdfelpmreset_in(1'b0), .rxdfetap10hold_in(1'b0), .rxdfetap10ovrden_in(1'b0), .rxdfetap11hold_in(1'b0), .rxdfetap11ovrden_in(1'b0), .rxdfetap12hold_in(1'b0), .rxdfetap12ovrden_in(1'b0), .rxdfetap13hold_in(1'b0), .rxdfetap13ovrden_in(1'b0), .rxdfetap14hold_in(1'b0), .rxdfetap14ovrden_in(1'b0), .rxdfetap15hold_in(1'b0), .rxdfetap15ovrden_in(1'b0), .rxdfetap2hold_in(1'b0), .rxdfetap2ovrden_in(1'b0), .rxdfetap3hold_in(1'b0), .rxdfetap3ovrden_in(1'b0), .rxdfetap4hold_in(1'b0), .rxdfetap4ovrden_in(1'b0), .rxdfetap5hold_in(1'b0), .rxdfetap5ovrden_in(1'b0), .rxdfetap6hold_in(1'b0), .rxdfetap6ovrden_in(1'b0), .rxdfetap7hold_in(1'b0), .rxdfetap7ovrden_in(1'b0), .rxdfetap8hold_in(1'b0), .rxdfetap8ovrden_in(1'b0), .rxdfetap9hold_in(1'b0), .rxdfetap9ovrden_in(1'b0), .rxdfeuthold_in(1'b0), .rxdfeutovrden_in(1'b0), .rxdfevphold_in(1'b0), .rxdfevpovrden_in(1'b0), .rxdfevsen_in(1'b0), .rxdfexyden_in(1'b1), .rxdlybypass_in(1'b1), .rxdlyen_in(1'b0), .rxdlyovrden_in(1'b0), .rxdlysreset_in(1'b0), .rxdlysresetdone_out(NLW_inst_rxdlysresetdone_out_UNCONNECTED[0]), .rxelecidle_out(NLW_inst_rxelecidle_out_UNCONNECTED[0]), .rxelecidlemode_in({1'b1,1'b1}), .rxeqtraining_in(1'b0), .rxgearboxslip_in(1'b0), .rxheader_out(NLW_inst_rxheader_out_UNCONNECTED[5:0]), .rxheadervalid_out(NLW_inst_rxheadervalid_out_UNCONNECTED[1:0]), .rxlatclk_in(1'b0), .rxlfpstresetdet_out(NLW_inst_rxlfpstresetdet_out_UNCONNECTED[0]), .rxlfpsu2lpexitdet_out(NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED[0]), .rxlfpsu3wakedet_out(NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED[0]), .rxlpmen_in(1'b1), .rxlpmgchold_in(1'b0), .rxlpmgcovrden_in(1'b0), .rxlpmhfhold_in(1'b0), .rxlpmhfovrden_in(1'b0), .rxlpmlfhold_in(1'b0), .rxlpmlfklovrden_in(1'b0), .rxlpmoshold_in(1'b0), .rxlpmosovrden_in(1'b0), .rxmcommaalignen_in(rxmcommaalignen_in), .rxmonitorout_out(NLW_inst_rxmonitorout_out_UNCONNECTED[6:0]), .rxmonitorsel_in({1'b0,1'b0}), .rxoobreset_in(1'b0), .rxoscalreset_in(1'b0), .rxoshold_in(1'b0), .rxosintcfg_in({1'b1,1'b1,1'b0,1'b1}), .rxosintdone_out(NLW_inst_rxosintdone_out_UNCONNECTED[0]), .rxosinten_in(1'b1), .rxosinthold_in(1'b0), .rxosintovrden_in(1'b0), .rxosintstarted_out(NLW_inst_rxosintstarted_out_UNCONNECTED[0]), .rxosintstrobe_in(1'b0), .rxosintstrobedone_out(NLW_inst_rxosintstrobedone_out_UNCONNECTED[0]), .rxosintstrobestarted_out(NLW_inst_rxosintstrobestarted_out_UNCONNECTED[0]), .rxosinttestovrden_in(1'b0), .rxosovrden_in(1'b0), .rxoutclk_out(rxoutclk_out), .rxoutclkfabric_out(NLW_inst_rxoutclkfabric_out_UNCONNECTED[0]), .rxoutclkpcs_out(NLW_inst_rxoutclkpcs_out_UNCONNECTED[0]), .rxoutclksel_in({1'b0,1'b1,1'b0}), .rxpcommaalignen_in(1'b0), .rxpcsreset_in(1'b0), .rxpd_in({rxpd_in[1],1'b0}), .rxphalign_in(1'b0), .rxphaligndone_out(NLW_inst_rxphaligndone_out_UNCONNECTED[0]), .rxphalignen_in(1'b0), .rxphalignerr_out(NLW_inst_rxphalignerr_out_UNCONNECTED[0]), .rxphdlypd_in(1'b1), .rxphdlyreset_in(1'b0), .rxphovrden_in(1'b0), .rxpllclksel_in({1'b0,1'b0}), .rxpmareset_in(1'b0), .rxpmaresetdone_out(NLW_inst_rxpmaresetdone_out_UNCONNECTED[0]), .rxpolarity_in(1'b0), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_inst_rxprbserr_out_UNCONNECTED[0]), .rxprbslocked_out(NLW_inst_rxprbslocked_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxprgdivresetdone_out(NLW_inst_rxprgdivresetdone_out_UNCONNECTED[0]), .rxprogdivreset_in(1'b0), .rxqpien_in(1'b0), .rxqpisenn_out(NLW_inst_rxqpisenn_out_UNCONNECTED[0]), .rxqpisenp_out(NLW_inst_rxqpisenp_out_UNCONNECTED[0]), .rxrate_in({1'b0,1'b0,1'b0}), .rxratedone_out(NLW_inst_rxratedone_out_UNCONNECTED[0]), .rxratemode_in(1'b0), .rxrecclk0_sel_out(NLW_inst_rxrecclk0_sel_out_UNCONNECTED[1:0]), .rxrecclk0sel_out(NLW_inst_rxrecclk0sel_out_UNCONNECTED[0]), .rxrecclk1_sel_out(NLW_inst_rxrecclk1_sel_out_UNCONNECTED[1:0]), .rxrecclk1sel_out(NLW_inst_rxrecclk1sel_out_UNCONNECTED[0]), .rxrecclkout_out(NLW_inst_rxrecclkout_out_UNCONNECTED[0]), .rxresetdone_out(NLW_inst_rxresetdone_out_UNCONNECTED[0]), .rxslide_in(1'b0), .rxsliderdy_out(NLW_inst_rxsliderdy_out_UNCONNECTED[0]), .rxslipdone_out(NLW_inst_rxslipdone_out_UNCONNECTED[0]), .rxslipoutclk_in(1'b0), .rxslipoutclkrdy_out(NLW_inst_rxslipoutclkrdy_out_UNCONNECTED[0]), .rxslippma_in(1'b0), .rxslippmardy_out(NLW_inst_rxslippmardy_out_UNCONNECTED[0]), .rxstartofseq_out(NLW_inst_rxstartofseq_out_UNCONNECTED[1:0]), .rxstatus_out(NLW_inst_rxstatus_out_UNCONNECTED[2:0]), .rxsyncallin_in(1'b0), .rxsyncdone_out(NLW_inst_rxsyncdone_out_UNCONNECTED[0]), .rxsyncin_in(1'b0), .rxsyncmode_in(1'b0), .rxsyncout_out(NLW_inst_rxsyncout_out_UNCONNECTED[0]), .rxsysclksel_in({1'b0,1'b0}), .rxtermination_in(1'b0), .rxuserrdy_in(1'b1), .rxusrclk2_in(1'b0), .rxusrclk_in(rxusrclk_in), .rxvalid_out(NLW_inst_rxvalid_out_UNCONNECTED[0]), .sdm0data_in(1'b0), .sdm0finalout_out(NLW_inst_sdm0finalout_out_UNCONNECTED[0]), .sdm0reset_in(1'b0), .sdm0testdata_out(NLW_inst_sdm0testdata_out_UNCONNECTED[0]), .sdm0toggle_in(1'b0), .sdm0width_in(1'b0), .sdm1data_in(1'b0), .sdm1finalout_out(NLW_inst_sdm1finalout_out_UNCONNECTED[0]), .sdm1reset_in(1'b0), .sdm1testdata_out(NLW_inst_sdm1testdata_out_UNCONNECTED[0]), .sdm1toggle_in(1'b0), .sdm1width_in(1'b0), .sigvalidclk_in(1'b0), .tcongpi_in(1'b0), .tcongpo_out(NLW_inst_tcongpo_out_UNCONNECTED[0]), .tconpowerup_in(1'b0), .tconreset_in(1'b0), .tconrsvdin1_in(1'b0), .tconrsvdout0_out(NLW_inst_tconrsvdout0_out_UNCONNECTED[0]), .tstin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10bbypass_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10ben_in(1'b1), .txbufdiffctrl_in({1'b0,1'b0,1'b0}), .txbufstatus_out({\^txbufstatus_out ,NLW_inst_txbufstatus_out_UNCONNECTED[0]}), .txcomfinish_out(NLW_inst_txcomfinish_out_UNCONNECTED[0]), .txcominit_in(1'b0), .txcomsas_in(1'b0), .txcomwake_in(1'b0), .txctrl0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl0_in[1:0]}), .txctrl1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl1_in[1:0]}), .txctrl2_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl2_in[1:0]}), .txdata_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdataextendrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdccdone_out(NLW_inst_txdccdone_out_UNCONNECTED[0]), .txdccforcestart_in(1'b0), .txdccreset_in(1'b0), .txdeemph_in(1'b0), .txdetectrx_in(1'b0), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txdiffpd_in(1'b0), .txdlybypass_in(1'b1), .txdlyen_in(1'b0), .txdlyhold_in(1'b0), .txdlyovrden_in(1'b0), .txdlysreset_in(1'b0), .txdlysresetdone_out(NLW_inst_txdlysresetdone_out_UNCONNECTED[0]), .txdlyupdown_in(1'b0), .txelecidle_in(txelecidle_in), .txelforcestart_in(1'b0), .txheader_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txinhibit_in(1'b0), .txlatclk_in(1'b0), .txlfpstreset_in(1'b0), .txlfpsu2lpexit_in(1'b0), .txlfpsu3wake_in(1'b0), .txmaincursor_in({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txmargin_in({1'b0,1'b0,1'b0}), .txmuxdcdexhold_in(1'b0), .txmuxdcdorwren_in(1'b0), .txoneszeros_in(1'b0), .txoutclk_out(txoutclk_out), .txoutclkfabric_out(NLW_inst_txoutclkfabric_out_UNCONNECTED[0]), .txoutclkpcs_out(NLW_inst_txoutclkpcs_out_UNCONNECTED[0]), .txoutclksel_in({1'b1,1'b0,1'b1}), .txpcsreset_in(1'b0), .txpd_in({1'b0,1'b0}), .txpdelecidlemode_in(1'b0), .txphalign_in(1'b0), .txphaligndone_out(NLW_inst_txphaligndone_out_UNCONNECTED[0]), .txphalignen_in(1'b0), .txphdlypd_in(1'b1), .txphdlyreset_in(1'b0), .txphdlytstclk_in(1'b0), .txphinit_in(1'b0), .txphinitdone_out(NLW_inst_txphinitdone_out_UNCONNECTED[0]), .txphovrden_in(1'b0), .txpippmen_in(1'b0), .txpippmovrden_in(1'b0), .txpippmpd_in(1'b0), .txpippmsel_in(1'b0), .txpippmstepsize_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpisopd_in(1'b0), .txpllclksel_in({1'b0,1'b0}), .txpmareset_in(1'b0), .txpmaresetdone_out(NLW_inst_txpmaresetdone_out_UNCONNECTED[0]), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpostcursorinv_in(1'b0), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprecursorinv_in(1'b0), .txprgdivresetdone_out(NLW_inst_txprgdivresetdone_out_UNCONNECTED[0]), .txprogdivreset_in(1'b0), .txqpibiasen_in(1'b0), .txqpisenn_out(NLW_inst_txqpisenn_out_UNCONNECTED[0]), .txqpisenp_out(NLW_inst_txqpisenp_out_UNCONNECTED[0]), .txqpistrongpdown_in(1'b0), .txqpiweakpup_in(1'b0), .txrate_in({1'b0,1'b0,1'b0}), .txratedone_out(NLW_inst_txratedone_out_UNCONNECTED[0]), .txratemode_in(1'b0), .txresetdone_out(NLW_inst_txresetdone_out_UNCONNECTED[0]), .txsequence_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txswing_in(1'b0), .txsyncallin_in(1'b0), .txsyncdone_out(NLW_inst_txsyncdone_out_UNCONNECTED[0]), .txsyncin_in(1'b0), .txsyncmode_in(1'b0), .txsyncout_out(NLW_inst_txsyncout_out_UNCONNECTED[0]), .txsysclksel_in({1'b0,1'b0}), .txuserrdy_in(1'b1), .txusrclk2_in(1'b0), .txusrclk_in(1'b0), .ubcfgstreamen_in(1'b0), .ubdaddr_out(NLW_inst_ubdaddr_out_UNCONNECTED[0]), .ubden_out(NLW_inst_ubden_out_UNCONNECTED[0]), .ubdi_out(NLW_inst_ubdi_out_UNCONNECTED[0]), .ubdo_in(1'b0), .ubdrdy_in(1'b0), .ubdwe_out(NLW_inst_ubdwe_out_UNCONNECTED[0]), .ubenable_in(1'b0), .ubgpi_in(1'b0), .ubintr_in(1'b0), .ubiolmbrst_in(1'b0), .ubmbrst_in(1'b0), .ubmdmcapture_in(1'b0), .ubmdmdbgrst_in(1'b0), .ubmdmdbgupdate_in(1'b0), .ubmdmregen_in(1'b0), .ubmdmshift_in(1'b0), .ubmdmsysrst_in(1'b0), .ubmdmtck_in(1'b0), .ubmdmtdi_in(1'b0), .ubmdmtdo_out(NLW_inst_ubmdmtdo_out_UNCONNECTED[0]), .ubrsvdout_out(NLW_inst_ubrsvdout_out_UNCONNECTED[0]), .ubtxuart_out(NLW_inst_ubtxuart_out_UNCONNECTED[0])); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txresetdone_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxmcommaalignen_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, txelecidle_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txresetdone_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxmcommaalignen_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxpmaresetdone_out; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [0:0]txresetdone_out; gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel channel_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(rxcdrlock_out), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(rxctrl0_out), .rxctrl1_out(rxctrl1_out), .rxctrl2_out(rxctrl2_out), .rxctrl3_out(rxctrl3_out), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in), .rxpmaresetdone_out(rxpmaresetdone_out), .rxresetdone_out(rxresetdone_out), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txctrl0_in(txctrl0_in), .txctrl1_in(txctrl1_in), .txctrl2_in(txctrl2_in), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out), .txresetdone_out(txresetdone_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxoutclk_out, txoutclk_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, rxmcommaalignen_in, rxusrclk_in, txelecidle_in, gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in, gtwiz_userclk_tx_active_in, gtwiz_reset_all_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_datapath_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxoutclk_out; output [0:0]txoutclk_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [0:0]rxmcommaalignen_in; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(rxctrl0_out), .rxctrl1_out(rxctrl1_out), .rxctrl2_out(rxctrl2_out), .rxctrl3_out(rxctrl3_out), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in), .rxpmaresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 ), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txctrl0_in(txctrl0_in), .txctrl1_in(txctrl1_in), .txctrl2_in(txctrl2_in), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 )); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 )); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 )); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gtpowergood_out(gtpowergood_out), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .rst_in0(rst_in0), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ), .rxpmaresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ), .rxusrclk_in(rxusrclk_in)); endmodule (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "1" *) (* C_RX_CC_K = "8'b00010001" *) (* C_RX_CC_LEN_SEQ = "2" *) (* C_RX_CC_NUM_SEQ = "2" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100" *) (* C_RX_COMMA_M_ENABLE = "1" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "1" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "1" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "20" *) (* C_RX_LINE_RATE = "1.250000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "62.500000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "16" *) (* C_RX_USRCLK2_FREQUENCY = "62.500000" *) (* C_RX_USRCLK_FREQUENCY = "62.500000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "1" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "125.000000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "1" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "20" *) (* C_TX_LINE_RATE = "1.250000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "2" *) (* C_TX_OUTCLK_FREQUENCY = "62.500000" *) (* C_TX_OUTCLK_SOURCE = "4" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "16" *) (* C_TX_USRCLK2_FREQUENCY = "62.500000" *) (* C_TX_USRCLK_FREQUENCY = "62.500000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_gt_gtwizard_top" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_top (gtwiz_userclk_tx_reset_in, gtwiz_userclk_tx_active_in, gtwiz_userclk_tx_srcclk_out, gtwiz_userclk_tx_usrclk_out, gtwiz_userclk_tx_usrclk2_out, gtwiz_userclk_tx_active_out, gtwiz_userclk_rx_reset_in, gtwiz_userclk_rx_active_in, gtwiz_userclk_rx_srcclk_out, gtwiz_userclk_rx_usrclk_out, gtwiz_userclk_rx_usrclk2_out, gtwiz_userclk_rx_active_out, gtwiz_buffbypass_tx_reset_in, gtwiz_buffbypass_tx_start_user_in, gtwiz_buffbypass_tx_done_out, gtwiz_buffbypass_tx_error_out, gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_tx_done_in, gtwiz_reset_rx_done_in, gtwiz_reset_qpll0lock_in, gtwiz_reset_qpll1lock_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_reset_qpll0reset_out, gtwiz_reset_qpll1reset_out, gtwiz_gthe3_cpll_cal_txoutclk_period_in, gtwiz_gthe3_cpll_cal_cnt_tol_in, gtwiz_gthe3_cpll_cal_bufg_ce_in, gtwiz_gthe4_cpll_cal_txoutclk_period_in, gtwiz_gthe4_cpll_cal_cnt_tol_in, gtwiz_gthe4_cpll_cal_bufg_ce_in, gtwiz_gtye4_cpll_cal_txoutclk_period_in, gtwiz_gtye4_cpll_cal_cnt_tol_in, gtwiz_gtye4_cpll_cal_bufg_ce_in, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, bgbypassb_in, bgmonitorenb_in, bgpdb_in, bgrcalovrd_in, bgrcalovrdenb_in, drpaddr_common_in, drpclk_common_in, drpdi_common_in, drpen_common_in, drpwe_common_in, gtgrefclk0_in, gtgrefclk1_in, gtnorthrefclk00_in, gtnorthrefclk01_in, gtnorthrefclk10_in, gtnorthrefclk11_in, gtrefclk00_in, gtrefclk01_in, gtrefclk10_in, gtrefclk11_in, gtsouthrefclk00_in, gtsouthrefclk01_in, gtsouthrefclk10_in, gtsouthrefclk11_in, pcierateqpll0_in, pcierateqpll1_in, pmarsvd0_in, pmarsvd1_in, qpll0clkrsvd0_in, qpll0clkrsvd1_in, qpll0fbdiv_in, qpll0lockdetclk_in, qpll0locken_in, qpll0pd_in, qpll0refclksel_in, qpll0reset_in, qpll1clkrsvd0_in, qpll1clkrsvd1_in, qpll1fbdiv_in, qpll1lockdetclk_in, qpll1locken_in, qpll1pd_in, qpll1refclksel_in, qpll1reset_in, qpllrsvd1_in, qpllrsvd2_in, qpllrsvd3_in, qpllrsvd4_in, rcalenb_in, sdm0data_in, sdm0reset_in, sdm0toggle_in, sdm0width_in, sdm1data_in, sdm1reset_in, sdm1toggle_in, sdm1width_in, tcongpi_in, tconpowerup_in, tconreset_in, tconrsvdin1_in, ubcfgstreamen_in, ubdo_in, ubdrdy_in, ubenable_in, ubgpi_in, ubintr_in, ubiolmbrst_in, ubmbrst_in, ubmdmcapture_in, ubmdmdbgrst_in, ubmdmdbgupdate_in, ubmdmregen_in, ubmdmshift_in, ubmdmsysrst_in, ubmdmtck_in, ubmdmtdi_in, drpdo_common_out, drprdy_common_out, pmarsvdout0_out, pmarsvdout1_out, qpll0fbclklost_out, qpll0lock_out, qpll0outclk_out, qpll0outrefclk_out, qpll0refclklost_out, qpll1fbclklost_out, qpll1lock_out, qpll1outclk_out, qpll1outrefclk_out, qpll1refclklost_out, qplldmonitor0_out, qplldmonitor1_out, refclkoutmonitor0_out, refclkoutmonitor1_out, rxrecclk0_sel_out, rxrecclk1_sel_out, rxrecclk0sel_out, rxrecclk1sel_out, sdm0finalout_out, sdm0testdata_out, sdm1finalout_out, sdm1testdata_out, tcongpo_out, tconrsvdout0_out, ubdaddr_out, ubden_out, ubdi_out, ubdwe_out, ubmdmtdo_out, ubrsvdout_out, ubtxuart_out, cdrstepdir_in, cdrstepsq_in, cdrstepsx_in, cfgreset_in, clkrsvd0_in, clkrsvd1_in, cpllfreqlock_in, cplllockdetclk_in, cplllocken_in, cpllpd_in, cpllrefclksel_in, cpllreset_in, dmonfiforeset_in, dmonitorclk_in, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drprst_in, drpwe_in, elpcaldvorwren_in, elpcalpaorwren_in, evoddphicaldone_in, evoddphicalstart_in, evoddphidrden_in, evoddphidwren_in, evoddphixrden_in, evoddphixwren_in, eyescanmode_in, eyescanreset_in, eyescantrigger_in, freqos_in, gtgrefclk_in, gthrxn_in, gthrxp_in, gtnorthrefclk0_in, gtnorthrefclk1_in, gtrefclk0_in, gtrefclk1_in, gtresetsel_in, gtrsvd_in, gtrxreset_in, gtrxresetsel_in, gtsouthrefclk0_in, gtsouthrefclk1_in, gttxreset_in, gttxresetsel_in, incpctrl_in, gtyrxn_in, gtyrxp_in, loopback_in, looprsvd_in, lpbkrxtxseren_in, lpbktxrxseren_in, pcieeqrxeqadaptdone_in, pcierstidle_in, pciersttxsyncstart_in, pcieuserratedone_in, pcsrsvdin_in, pcsrsvdin2_in, pmarsvdin_in, qpll0clk_in, qpll0freqlock_in, qpll0refclk_in, qpll1clk_in, qpll1freqlock_in, qpll1refclk_in, resetovrd_in, rstclkentx_in, rx8b10ben_in, rxafecfoken_in, rxbufreset_in, rxcdrfreqreset_in, rxcdrhold_in, rxcdrovrden_in, rxcdrreset_in, rxcdrresetrsv_in, rxchbonden_in, rxchbondi_in, rxchbondlevel_in, rxchbondmaster_in, rxchbondslave_in, rxckcalreset_in, rxckcalstart_in, rxcommadeten_in, rxdfeagcctrl_in, rxdccforcestart_in, rxdfeagchold_in, rxdfeagcovrden_in, rxdfecfokfcnum_in, rxdfecfokfen_in, rxdfecfokfpulse_in, rxdfecfokhold_in, rxdfecfokovren_in, rxdfekhhold_in, rxdfekhovrden_in, rxdfelfhold_in, rxdfelfovrden_in, rxdfelpmreset_in, rxdfetap10hold_in, rxdfetap10ovrden_in, rxdfetap11hold_in, rxdfetap11ovrden_in, rxdfetap12hold_in, rxdfetap12ovrden_in, rxdfetap13hold_in, rxdfetap13ovrden_in, rxdfetap14hold_in, rxdfetap14ovrden_in, rxdfetap15hold_in, rxdfetap15ovrden_in, rxdfetap2hold_in, rxdfetap2ovrden_in, rxdfetap3hold_in, rxdfetap3ovrden_in, rxdfetap4hold_in, rxdfetap4ovrden_in, rxdfetap5hold_in, rxdfetap5ovrden_in, rxdfetap6hold_in, rxdfetap6ovrden_in, rxdfetap7hold_in, rxdfetap7ovrden_in, rxdfetap8hold_in, rxdfetap8ovrden_in, rxdfetap9hold_in, rxdfetap9ovrden_in, rxdfeuthold_in, rxdfeutovrden_in, rxdfevphold_in, rxdfevpovrden_in, rxdfevsen_in, rxdfexyden_in, rxdlybypass_in, rxdlyen_in, rxdlyovrden_in, rxdlysreset_in, rxelecidlemode_in, rxeqtraining_in, rxgearboxslip_in, rxlatclk_in, rxlpmen_in, rxlpmgchold_in, rxlpmgcovrden_in, rxlpmhfhold_in, rxlpmhfovrden_in, rxlpmlfhold_in, rxlpmlfklovrden_in, rxlpmoshold_in, rxlpmosovrden_in, rxmcommaalignen_in, rxmonitorsel_in, rxoobreset_in, rxoscalreset_in, rxoshold_in, rxosintcfg_in, rxosinten_in, rxosinthold_in, rxosintovrden_in, rxosintstrobe_in, rxosinttestovrden_in, rxosovrden_in, rxoutclksel_in, rxpcommaalignen_in, rxpcsreset_in, rxpd_in, rxphalign_in, rxphalignen_in, rxphdlypd_in, rxphdlyreset_in, rxphovrden_in, rxpllclksel_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxprogdivreset_in, rxqpien_in, rxrate_in, rxratemode_in, rxslide_in, rxslipoutclk_in, rxslippma_in, rxsyncallin_in, rxsyncin_in, rxsyncmode_in, rxsysclksel_in, rxtermination_in, rxuserrdy_in, rxusrclk_in, rxusrclk2_in, sigvalidclk_in, tstin_in, tx8b10bbypass_in, tx8b10ben_in, txbufdiffctrl_in, txcominit_in, txcomsas_in, txcomwake_in, txctrl0_in, txctrl1_in, txctrl2_in, txdata_in, txdataextendrsvd_in, txdccforcestart_in, txdccreset_in, txdeemph_in, txdetectrx_in, txdiffctrl_in, txdiffpd_in, txdlybypass_in, txdlyen_in, txdlyhold_in, txdlyovrden_in, txdlysreset_in, txdlyupdown_in, txelecidle_in, txelforcestart_in, txheader_in, txinhibit_in, txlatclk_in, txlfpstreset_in, txlfpsu2lpexit_in, txlfpsu3wake_in, txmaincursor_in, txmargin_in, txmuxdcdexhold_in, txmuxdcdorwren_in, txoneszeros_in, txoutclksel_in, txpcsreset_in, txpd_in, txpdelecidlemode_in, txphalign_in, txphalignen_in, txphdlypd_in, txphdlyreset_in, txphdlytstclk_in, txphinit_in, txphovrden_in, txpippmen_in, txpippmovrden_in, txpippmpd_in, txpippmsel_in, txpippmstepsize_in, txpisopd_in, txpllclksel_in, txpmareset_in, txpolarity_in, txpostcursor_in, txpostcursorinv_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txprecursorinv_in, txprogdivreset_in, txqpibiasen_in, txqpistrongpdown_in, txqpiweakpup_in, txrate_in, txratemode_in, txsequence_in, txswing_in, txsyncallin_in, txsyncin_in, txsyncmode_in, txsysclksel_in, txuserrdy_in, txusrclk_in, txusrclk2_in, bufgtce_out, bufgtcemask_out, bufgtdiv_out, bufgtreset_out, bufgtrstmask_out, cpllfbclklost_out, cplllock_out, cpllrefclklost_out, dmonitorout_out, dmonitoroutclk_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, gtrefclkmonitor_out, gtytxn_out, gtytxp_out, pcierategen3_out, pcierateidle_out, pcierateqpllpd_out, pcierateqpllreset_out, pciesynctxsyncdone_out, pcieusergen3rdy_out, pcieuserphystatusrst_out, pcieuserratestart_out, pcsrsvdout_out, phystatus_out, pinrsrvdas_out, powerpresent_out, resetexception_out, rxbufstatus_out, rxbyteisaligned_out, rxbyterealign_out, rxcdrlock_out, rxcdrphdone_out, rxchanbondseq_out, rxchanisaligned_out, rxchanrealign_out, rxchbondo_out, rxckcaldone_out, rxclkcorcnt_out, rxcominitdet_out, rxcommadet_out, rxcomsasdet_out, rxcomwakedet_out, rxctrl0_out, rxctrl1_out, rxctrl2_out, rxctrl3_out, rxdata_out, rxdataextendrsvd_out, rxdatavalid_out, rxdlysresetdone_out, rxelecidle_out, rxheader_out, rxheadervalid_out, rxlfpstresetdet_out, rxlfpsu2lpexitdet_out, rxlfpsu3wakedet_out, rxmonitorout_out, rxosintdone_out, rxosintstarted_out, rxosintstrobedone_out, rxosintstrobestarted_out, rxoutclk_out, rxoutclkfabric_out, rxoutclkpcs_out, rxphaligndone_out, rxphalignerr_out, rxpmaresetdone_out, rxprbserr_out, rxprbslocked_out, rxprgdivresetdone_out, rxqpisenn_out, rxqpisenp_out, rxratedone_out, rxrecclkout_out, rxresetdone_out, rxsliderdy_out, rxslipdone_out, rxslipoutclkrdy_out, rxslippmardy_out, rxstartofseq_out, rxstatus_out, rxsyncdone_out, rxsyncout_out, rxvalid_out, txbufstatus_out, txcomfinish_out, txdccdone_out, txdlysresetdone_out, txoutclk_out, txoutclkfabric_out, txoutclkpcs_out, txphaligndone_out, txphinitdone_out, txpmaresetdone_out, txprgdivresetdone_out, txqpisenn_out, txqpisenp_out, txratedone_out, txresetdone_out, txsyncdone_out, txsyncout_out); input [0:0]gtwiz_userclk_tx_reset_in; input [0:0]gtwiz_userclk_tx_active_in; output [0:0]gtwiz_userclk_tx_srcclk_out; output [0:0]gtwiz_userclk_tx_usrclk_out; output [0:0]gtwiz_userclk_tx_usrclk2_out; output [0:0]gtwiz_userclk_tx_active_out; input [0:0]gtwiz_userclk_rx_reset_in; input [0:0]gtwiz_userclk_rx_active_in; output [0:0]gtwiz_userclk_rx_srcclk_out; output [0:0]gtwiz_userclk_rx_usrclk_out; output [0:0]gtwiz_userclk_rx_usrclk2_out; output [0:0]gtwiz_userclk_rx_active_out; input [0:0]gtwiz_buffbypass_tx_reset_in; input [0:0]gtwiz_buffbypass_tx_start_user_in; output [0:0]gtwiz_buffbypass_tx_done_out; output [0:0]gtwiz_buffbypass_tx_error_out; input [0:0]gtwiz_buffbypass_rx_reset_in; input [0:0]gtwiz_buffbypass_rx_start_user_in; output [0:0]gtwiz_buffbypass_rx_done_out; output [0:0]gtwiz_buffbypass_rx_error_out; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; input [0:0]gtwiz_reset_tx_done_in; input [0:0]gtwiz_reset_rx_done_in; input [0:0]gtwiz_reset_qpll0lock_in; input [0:0]gtwiz_reset_qpll1lock_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output [0:0]gtwiz_reset_qpll0reset_out; output [0:0]gtwiz_reset_qpll1reset_out; input [17:0]gtwiz_gthe3_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe3_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe3_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gthe4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe4_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gtye4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gtye4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gtye4_cpll_cal_bufg_ce_in; input [15:0]gtwiz_userdata_tx_in; output [15:0]gtwiz_userdata_rx_out; input [0:0]bgbypassb_in; input [0:0]bgmonitorenb_in; input [0:0]bgpdb_in; input [4:0]bgrcalovrd_in; input [0:0]bgrcalovrdenb_in; input [8:0]drpaddr_common_in; input [0:0]drpclk_common_in; input [15:0]drpdi_common_in; input [0:0]drpen_common_in; input [0:0]drpwe_common_in; input [0:0]gtgrefclk0_in; input [0:0]gtgrefclk1_in; input [0:0]gtnorthrefclk00_in; input [0:0]gtnorthrefclk01_in; input [0:0]gtnorthrefclk10_in; input [0:0]gtnorthrefclk11_in; input [0:0]gtrefclk00_in; input [0:0]gtrefclk01_in; input [0:0]gtrefclk10_in; input [0:0]gtrefclk11_in; input [0:0]gtsouthrefclk00_in; input [0:0]gtsouthrefclk01_in; input [0:0]gtsouthrefclk10_in; input [0:0]gtsouthrefclk11_in; input [0:0]pcierateqpll0_in; input [0:0]pcierateqpll1_in; input [7:0]pmarsvd0_in; input [7:0]pmarsvd1_in; input [0:0]qpll0clkrsvd0_in; input [0:0]qpll0clkrsvd1_in; input [0:0]qpll0fbdiv_in; input [0:0]qpll0lockdetclk_in; input [0:0]qpll0locken_in; input [0:0]qpll0pd_in; input [2:0]qpll0refclksel_in; input [0:0]qpll0reset_in; input [0:0]qpll1clkrsvd0_in; input [0:0]qpll1clkrsvd1_in; input [0:0]qpll1fbdiv_in; input [0:0]qpll1lockdetclk_in; input [0:0]qpll1locken_in; input [0:0]qpll1pd_in; input [2:0]qpll1refclksel_in; input [0:0]qpll1reset_in; input [7:0]qpllrsvd1_in; input [4:0]qpllrsvd2_in; input [4:0]qpllrsvd3_in; input [7:0]qpllrsvd4_in; input [0:0]rcalenb_in; input [0:0]sdm0data_in; input [0:0]sdm0reset_in; input [0:0]sdm0toggle_in; input [0:0]sdm0width_in; input [0:0]sdm1data_in; input [0:0]sdm1reset_in; input [0:0]sdm1toggle_in; input [0:0]sdm1width_in; input [0:0]tcongpi_in; input [0:0]tconpowerup_in; input [0:0]tconreset_in; input [0:0]tconrsvdin1_in; input [0:0]ubcfgstreamen_in; input [0:0]ubdo_in; input [0:0]ubdrdy_in; input [0:0]ubenable_in; input [0:0]ubgpi_in; input [0:0]ubintr_in; input [0:0]ubiolmbrst_in; input [0:0]ubmbrst_in; input [0:0]ubmdmcapture_in; input [0:0]ubmdmdbgrst_in; input [0:0]ubmdmdbgupdate_in; input [0:0]ubmdmregen_in; input [0:0]ubmdmshift_in; input [0:0]ubmdmsysrst_in; input [0:0]ubmdmtck_in; input [0:0]ubmdmtdi_in; output [15:0]drpdo_common_out; output [0:0]drprdy_common_out; output [7:0]pmarsvdout0_out; output [7:0]pmarsvdout1_out; output [0:0]qpll0fbclklost_out; output [0:0]qpll0lock_out; output [0:0]qpll0outclk_out; output [0:0]qpll0outrefclk_out; output [0:0]qpll0refclklost_out; output [0:0]qpll1fbclklost_out; output [0:0]qpll1lock_out; output [0:0]qpll1outclk_out; output [0:0]qpll1outrefclk_out; output [0:0]qpll1refclklost_out; output [7:0]qplldmonitor0_out; output [7:0]qplldmonitor1_out; output [0:0]refclkoutmonitor0_out; output [0:0]refclkoutmonitor1_out; output [1:0]rxrecclk0_sel_out; output [1:0]rxrecclk1_sel_out; output [0:0]rxrecclk0sel_out; output [0:0]rxrecclk1sel_out; output [0:0]sdm0finalout_out; output [0:0]sdm0testdata_out; output [0:0]sdm1finalout_out; output [0:0]sdm1testdata_out; output [0:0]tcongpo_out; output [0:0]tconrsvdout0_out; output [0:0]ubdaddr_out; output [0:0]ubden_out; output [0:0]ubdi_out; output [0:0]ubdwe_out; output [0:0]ubmdmtdo_out; output [0:0]ubrsvdout_out; output [0:0]ubtxuart_out; input [0:0]cdrstepdir_in; input [0:0]cdrstepsq_in; input [0:0]cdrstepsx_in; input [0:0]cfgreset_in; input [0:0]clkrsvd0_in; input [0:0]clkrsvd1_in; input [0:0]cpllfreqlock_in; input [0:0]cplllockdetclk_in; input [0:0]cplllocken_in; input [0:0]cpllpd_in; input [2:0]cpllrefclksel_in; input [0:0]cpllreset_in; input [0:0]dmonfiforeset_in; input [0:0]dmonitorclk_in; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drprst_in; input [0:0]drpwe_in; input [0:0]elpcaldvorwren_in; input [0:0]elpcalpaorwren_in; input [0:0]evoddphicaldone_in; input [0:0]evoddphicalstart_in; input [0:0]evoddphidrden_in; input [0:0]evoddphidwren_in; input [0:0]evoddphixrden_in; input [0:0]evoddphixwren_in; input [0:0]eyescanmode_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]freqos_in; input [0:0]gtgrefclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtnorthrefclk0_in; input [0:0]gtnorthrefclk1_in; input [0:0]gtrefclk0_in; input [0:0]gtrefclk1_in; input [0:0]gtresetsel_in; input [15:0]gtrsvd_in; input [0:0]gtrxreset_in; input [0:0]gtrxresetsel_in; input [0:0]gtsouthrefclk0_in; input [0:0]gtsouthrefclk1_in; input [0:0]gttxreset_in; input [0:0]gttxresetsel_in; input [0:0]incpctrl_in; input [0:0]gtyrxn_in; input [0:0]gtyrxp_in; input [2:0]loopback_in; input [0:0]looprsvd_in; input [0:0]lpbkrxtxseren_in; input [0:0]lpbktxrxseren_in; input [0:0]pcieeqrxeqadaptdone_in; input [0:0]pcierstidle_in; input [0:0]pciersttxsyncstart_in; input [0:0]pcieuserratedone_in; input [15:0]pcsrsvdin_in; input [4:0]pcsrsvdin2_in; input [4:0]pmarsvdin_in; input [0:0]qpll0clk_in; input [0:0]qpll0freqlock_in; input [0:0]qpll0refclk_in; input [0:0]qpll1clk_in; input [0:0]qpll1freqlock_in; input [0:0]qpll1refclk_in; input [0:0]resetovrd_in; input [0:0]rstclkentx_in; input [0:0]rx8b10ben_in; input [0:0]rxafecfoken_in; input [0:0]rxbufreset_in; input [0:0]rxcdrfreqreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcdrovrden_in; input [0:0]rxcdrreset_in; input [0:0]rxcdrresetrsv_in; input [0:0]rxchbonden_in; input [4:0]rxchbondi_in; input [2:0]rxchbondlevel_in; input [0:0]rxchbondmaster_in; input [0:0]rxchbondslave_in; input [0:0]rxckcalreset_in; input [0:0]rxckcalstart_in; input [0:0]rxcommadeten_in; input [1:0]rxdfeagcctrl_in; input [0:0]rxdccforcestart_in; input [0:0]rxdfeagchold_in; input [0:0]rxdfeagcovrden_in; input [0:0]rxdfecfokfcnum_in; input [0:0]rxdfecfokfen_in; input [0:0]rxdfecfokfpulse_in; input [0:0]rxdfecfokhold_in; input [0:0]rxdfecfokovren_in; input [0:0]rxdfekhhold_in; input [0:0]rxdfekhovrden_in; input [0:0]rxdfelfhold_in; input [0:0]rxdfelfovrden_in; input [0:0]rxdfelpmreset_in; input [0:0]rxdfetap10hold_in; input [0:0]rxdfetap10ovrden_in; input [0:0]rxdfetap11hold_in; input [0:0]rxdfetap11ovrden_in; input [0:0]rxdfetap12hold_in; input [0:0]rxdfetap12ovrden_in; input [0:0]rxdfetap13hold_in; input [0:0]rxdfetap13ovrden_in; input [0:0]rxdfetap14hold_in; input [0:0]rxdfetap14ovrden_in; input [0:0]rxdfetap15hold_in; input [0:0]rxdfetap15ovrden_in; input [0:0]rxdfetap2hold_in; input [0:0]rxdfetap2ovrden_in; input [0:0]rxdfetap3hold_in; input [0:0]rxdfetap3ovrden_in; input [0:0]rxdfetap4hold_in; input [0:0]rxdfetap4ovrden_in; input [0:0]rxdfetap5hold_in; input [0:0]rxdfetap5ovrden_in; input [0:0]rxdfetap6hold_in; input [0:0]rxdfetap6ovrden_in; input [0:0]rxdfetap7hold_in; input [0:0]rxdfetap7ovrden_in; input [0:0]rxdfetap8hold_in; input [0:0]rxdfetap8ovrden_in; input [0:0]rxdfetap9hold_in; input [0:0]rxdfetap9ovrden_in; input [0:0]rxdfeuthold_in; input [0:0]rxdfeutovrden_in; input [0:0]rxdfevphold_in; input [0:0]rxdfevpovrden_in; input [0:0]rxdfevsen_in; input [0:0]rxdfexyden_in; input [0:0]rxdlybypass_in; input [0:0]rxdlyen_in; input [0:0]rxdlyovrden_in; input [0:0]rxdlysreset_in; input [1:0]rxelecidlemode_in; input [0:0]rxeqtraining_in; input [0:0]rxgearboxslip_in; input [0:0]rxlatclk_in; input [0:0]rxlpmen_in; input [0:0]rxlpmgchold_in; input [0:0]rxlpmgcovrden_in; input [0:0]rxlpmhfhold_in; input [0:0]rxlpmhfovrden_in; input [0:0]rxlpmlfhold_in; input [0:0]rxlpmlfklovrden_in; input [0:0]rxlpmoshold_in; input [0:0]rxlpmosovrden_in; input [0:0]rxmcommaalignen_in; input [1:0]rxmonitorsel_in; input [0:0]rxoobreset_in; input [0:0]rxoscalreset_in; input [0:0]rxoshold_in; input [3:0]rxosintcfg_in; input [0:0]rxosinten_in; input [0:0]rxosinthold_in; input [0:0]rxosintovrden_in; input [0:0]rxosintstrobe_in; input [0:0]rxosinttestovrden_in; input [0:0]rxosovrden_in; input [2:0]rxoutclksel_in; input [0:0]rxpcommaalignen_in; input [0:0]rxpcsreset_in; input [1:0]rxpd_in; input [0:0]rxphalign_in; input [0:0]rxphalignen_in; input [0:0]rxphdlypd_in; input [0:0]rxphdlyreset_in; input [0:0]rxphovrden_in; input [1:0]rxpllclksel_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [0:0]rxprogdivreset_in; input [0:0]rxqpien_in; input [2:0]rxrate_in; input [0:0]rxratemode_in; input [0:0]rxslide_in; input [0:0]rxslipoutclk_in; input [0:0]rxslippma_in; input [0:0]rxsyncallin_in; input [0:0]rxsyncin_in; input [0:0]rxsyncmode_in; input [1:0]rxsysclksel_in; input [0:0]rxtermination_in; input [0:0]rxuserrdy_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]sigvalidclk_in; input [19:0]tstin_in; input [7:0]tx8b10bbypass_in; input [0:0]tx8b10ben_in; input [2:0]txbufdiffctrl_in; input [0:0]txcominit_in; input [0:0]txcomsas_in; input [0:0]txcomwake_in; input [15:0]txctrl0_in; input [15:0]txctrl1_in; input [7:0]txctrl2_in; input [127:0]txdata_in; input [7:0]txdataextendrsvd_in; input [0:0]txdccforcestart_in; input [0:0]txdccreset_in; input [0:0]txdeemph_in; input [0:0]txdetectrx_in; input [3:0]txdiffctrl_in; input [0:0]txdiffpd_in; input [0:0]txdlybypass_in; input [0:0]txdlyen_in; input [0:0]txdlyhold_in; input [0:0]txdlyovrden_in; input [0:0]txdlysreset_in; input [0:0]txdlyupdown_in; input [0:0]txelecidle_in; input [0:0]txelforcestart_in; input [5:0]txheader_in; input [0:0]txinhibit_in; input [0:0]txlatclk_in; input [0:0]txlfpstreset_in; input [0:0]txlfpsu2lpexit_in; input [0:0]txlfpsu3wake_in; input [6:0]txmaincursor_in; input [2:0]txmargin_in; input [0:0]txmuxdcdexhold_in; input [0:0]txmuxdcdorwren_in; input [0:0]txoneszeros_in; input [2:0]txoutclksel_in; input [0:0]txpcsreset_in; input [1:0]txpd_in; input [0:0]txpdelecidlemode_in; input [0:0]txphalign_in; input [0:0]txphalignen_in; input [0:0]txphdlypd_in; input [0:0]txphdlyreset_in; input [0:0]txphdlytstclk_in; input [0:0]txphinit_in; input [0:0]txphovrden_in; input [0:0]txpippmen_in; input [0:0]txpippmovrden_in; input [0:0]txpippmpd_in; input [0:0]txpippmsel_in; input [4:0]txpippmstepsize_in; input [0:0]txpisopd_in; input [1:0]txpllclksel_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txpostcursorinv_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [0:0]txprecursorinv_in; input [0:0]txprogdivreset_in; input [0:0]txqpibiasen_in; input [0:0]txqpistrongpdown_in; input [0:0]txqpiweakpup_in; input [2:0]txrate_in; input [0:0]txratemode_in; input [6:0]txsequence_in; input [0:0]txswing_in; input [0:0]txsyncallin_in; input [0:0]txsyncin_in; input [0:0]txsyncmode_in; input [1:0]txsysclksel_in; input [0:0]txuserrdy_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [2:0]bufgtce_out; output [2:0]bufgtcemask_out; output [8:0]bufgtdiv_out; output [2:0]bufgtreset_out; output [2:0]bufgtrstmask_out; output [0:0]cpllfbclklost_out; output [0:0]cplllock_out; output [0:0]cpllrefclklost_out; output [16:0]dmonitorout_out; output [0:0]dmonitoroutclk_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]gtrefclkmonitor_out; output [0:0]gtytxn_out; output [0:0]gtytxp_out; output [0:0]pcierategen3_out; output [0:0]pcierateidle_out; output [1:0]pcierateqpllpd_out; output [1:0]pcierateqpllreset_out; output [0:0]pciesynctxsyncdone_out; output [0:0]pcieusergen3rdy_out; output [0:0]pcieuserphystatusrst_out; output [0:0]pcieuserratestart_out; output [11:0]pcsrsvdout_out; output [0:0]phystatus_out; output [7:0]pinrsrvdas_out; output [0:0]powerpresent_out; output [0:0]resetexception_out; output [2:0]rxbufstatus_out; output [0:0]rxbyteisaligned_out; output [0:0]rxbyterealign_out; output [0:0]rxcdrlock_out; output [0:0]rxcdrphdone_out; output [0:0]rxchanbondseq_out; output [0:0]rxchanisaligned_out; output [0:0]rxchanrealign_out; output [4:0]rxchbondo_out; output [0:0]rxckcaldone_out; output [1:0]rxclkcorcnt_out; output [0:0]rxcominitdet_out; output [0:0]rxcommadet_out; output [0:0]rxcomsasdet_out; output [0:0]rxcomwakedet_out; output [15:0]rxctrl0_out; output [15:0]rxctrl1_out; output [7:0]rxctrl2_out; output [7:0]rxctrl3_out; output [127:0]rxdata_out; output [7:0]rxdataextendrsvd_out; output [1:0]rxdatavalid_out; output [0:0]rxdlysresetdone_out; output [0:0]rxelecidle_out; output [5:0]rxheader_out; output [1:0]rxheadervalid_out; output [0:0]rxlfpstresetdet_out; output [0:0]rxlfpsu2lpexitdet_out; output [0:0]rxlfpsu3wakedet_out; output [6:0]rxmonitorout_out; output [0:0]rxosintdone_out; output [0:0]rxosintstarted_out; output [0:0]rxosintstrobedone_out; output [0:0]rxosintstrobestarted_out; output [0:0]rxoutclk_out; output [0:0]rxoutclkfabric_out; output [0:0]rxoutclkpcs_out; output [0:0]rxphaligndone_out; output [0:0]rxphalignerr_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxprbslocked_out; output [0:0]rxprgdivresetdone_out; output [0:0]rxqpisenn_out; output [0:0]rxqpisenp_out; output [0:0]rxratedone_out; output [0:0]rxrecclkout_out; output [0:0]rxresetdone_out; output [0:0]rxsliderdy_out; output [0:0]rxslipdone_out; output [0:0]rxslipoutclkrdy_out; output [0:0]rxslippmardy_out; output [1:0]rxstartofseq_out; output [2:0]rxstatus_out; output [0:0]rxsyncdone_out; output [0:0]rxsyncout_out; output [0:0]rxvalid_out; output [1:0]txbufstatus_out; output [0:0]txcomfinish_out; output [0:0]txdccdone_out; output [0:0]txdlysresetdone_out; output [0:0]txoutclk_out; output [0:0]txoutclkfabric_out; output [0:0]txoutclkpcs_out; output [0:0]txphaligndone_out; output [0:0]txphinitdone_out; output [0:0]txpmaresetdone_out; output [0:0]txprgdivresetdone_out; output [0:0]txqpisenn_out; output [0:0]txqpisenp_out; output [0:0]txratedone_out; output [0:0]txresetdone_out; output [0:0]txsyncdone_out; output [0:0]txsyncout_out; wire \ ; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire [2:2]\^rxbufstatus_out ; wire [1:0]rxclkcorcnt_out; wire [1:0]\^rxctrl0_out ; wire [1:0]\^rxctrl1_out ; wire [1:0]\^rxctrl2_out ; wire [1:0]\^rxctrl3_out ; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [1:0]rxpd_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [15:0]txctrl0_in; wire [15:0]txctrl1_in; wire [7:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; assign bufgtce_out[2] = \ ; assign bufgtce_out[1] = \ ; assign bufgtce_out[0] = \ ; assign bufgtcemask_out[2] = \ ; assign bufgtcemask_out[1] = \ ; assign bufgtcemask_out[0] = \ ; assign bufgtdiv_out[8] = \ ; assign bufgtdiv_out[7] = \ ; assign bufgtdiv_out[6] = \ ; assign bufgtdiv_out[5] = \ ; assign bufgtdiv_out[4] = \ ; assign bufgtdiv_out[3] = \ ; assign bufgtdiv_out[2] = \ ; assign bufgtdiv_out[1] = \ ; assign bufgtdiv_out[0] = \ ; assign bufgtreset_out[2] = \ ; assign bufgtreset_out[1] = \ ; assign bufgtreset_out[0] = \ ; assign bufgtrstmask_out[2] = \ ; assign bufgtrstmask_out[1] = \ ; assign bufgtrstmask_out[0] = \ ; assign cpllfbclklost_out[0] = \ ; assign cpllrefclklost_out[0] = \ ; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign dmonitoroutclk_out[0] = \ ; assign drpdo_common_out[15] = \ ; assign drpdo_common_out[14] = \ ; assign drpdo_common_out[13] = \ ; assign drpdo_common_out[12] = \ ; assign drpdo_common_out[11] = \ ; assign drpdo_common_out[10] = \ ; assign drpdo_common_out[9] = \ ; assign drpdo_common_out[8] = \ ; assign drpdo_common_out[7] = \ ; assign drpdo_common_out[6] = \ ; assign drpdo_common_out[5] = \ ; assign drpdo_common_out[4] = \ ; assign drpdo_common_out[3] = \ ; assign drpdo_common_out[2] = \ ; assign drpdo_common_out[1] = \ ; assign drpdo_common_out[0] = \ ; assign drpdo_out[15] = \ ; assign drpdo_out[14] = \ ; assign drpdo_out[13] = \ ; assign drpdo_out[12] = \ ; assign drpdo_out[11] = \ ; assign drpdo_out[10] = \ ; assign drpdo_out[9] = \ ; assign drpdo_out[8] = \ ; assign drpdo_out[7] = \ ; assign drpdo_out[6] = \ ; assign drpdo_out[5] = \ ; assign drpdo_out[4] = \ ; assign drpdo_out[3] = \ ; assign drpdo_out[2] = \ ; assign drpdo_out[1] = \ ; assign drpdo_out[0] = \ ; assign drprdy_common_out[0] = \ ; assign drprdy_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtrefclkmonitor_out[0] = \ ; assign gtwiz_buffbypass_rx_done_out[0] = \ ; assign gtwiz_buffbypass_rx_error_out[0] = \ ; assign gtwiz_buffbypass_tx_done_out[0] = \ ; assign gtwiz_buffbypass_tx_error_out[0] = \ ; assign gtwiz_reset_qpll0reset_out[0] = \ ; assign gtwiz_reset_qpll1reset_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign gtwiz_userclk_rx_active_out[0] = \ ; assign gtwiz_userclk_rx_srcclk_out[0] = \ ; assign gtwiz_userclk_rx_usrclk2_out[0] = \ ; assign gtwiz_userclk_rx_usrclk_out[0] = \ ; assign gtwiz_userclk_tx_active_out[0] = \ ; assign gtwiz_userclk_tx_srcclk_out[0] = \ ; assign gtwiz_userclk_tx_usrclk2_out[0] = \ ; assign gtwiz_userclk_tx_usrclk_out[0] = \ ; assign gtytxn_out[0] = \ ; assign gtytxp_out[0] = \ ; assign pcierategen3_out[0] = \ ; assign pcierateidle_out[0] = \ ; assign pcierateqpllpd_out[1] = \ ; assign pcierateqpllpd_out[0] = \ ; assign pcierateqpllreset_out[1] = \ ; assign pcierateqpllreset_out[0] = \ ; assign pciesynctxsyncdone_out[0] = \ ; assign pcieusergen3rdy_out[0] = \ ; assign pcieuserphystatusrst_out[0] = \ ; assign pcieuserratestart_out[0] = \ ; assign pcsrsvdout_out[11] = \ ; assign pcsrsvdout_out[10] = \ ; assign pcsrsvdout_out[9] = \ ; assign pcsrsvdout_out[8] = \ ; assign pcsrsvdout_out[7] = \ ; assign pcsrsvdout_out[6] = \ ; assign pcsrsvdout_out[5] = \ ; assign pcsrsvdout_out[4] = \ ; assign pcsrsvdout_out[3] = \ ; assign pcsrsvdout_out[2] = \ ; assign pcsrsvdout_out[1] = \ ; assign pcsrsvdout_out[0] = \ ; assign phystatus_out[0] = \ ; assign pinrsrvdas_out[7] = \ ; assign pinrsrvdas_out[6] = \ ; assign pinrsrvdas_out[5] = \ ; assign pinrsrvdas_out[4] = \ ; assign pinrsrvdas_out[3] = \ ; assign pinrsrvdas_out[2] = \ ; assign pinrsrvdas_out[1] = \ ; assign pinrsrvdas_out[0] = \ ; assign pmarsvdout0_out[7] = \ ; assign pmarsvdout0_out[6] = \ ; assign pmarsvdout0_out[5] = \ ; assign pmarsvdout0_out[4] = \ ; assign pmarsvdout0_out[3] = \ ; assign pmarsvdout0_out[2] = \ ; assign pmarsvdout0_out[1] = \ ; assign pmarsvdout0_out[0] = \ ; assign pmarsvdout1_out[7] = \ ; assign pmarsvdout1_out[6] = \ ; assign pmarsvdout1_out[5] = \ ; assign pmarsvdout1_out[4] = \ ; assign pmarsvdout1_out[3] = \ ; assign pmarsvdout1_out[2] = \ ; assign pmarsvdout1_out[1] = \ ; assign pmarsvdout1_out[0] = \ ; assign powerpresent_out[0] = \ ; assign qpll0fbclklost_out[0] = \ ; assign qpll0lock_out[0] = \ ; assign qpll0outclk_out[0] = \ ; assign qpll0outrefclk_out[0] = \ ; assign qpll0refclklost_out[0] = \ ; assign qpll1fbclklost_out[0] = \ ; assign qpll1lock_out[0] = \ ; assign qpll1outclk_out[0] = \ ; assign qpll1outrefclk_out[0] = \ ; assign qpll1refclklost_out[0] = \ ; assign qplldmonitor0_out[7] = \ ; assign qplldmonitor0_out[6] = \ ; assign qplldmonitor0_out[5] = \ ; assign qplldmonitor0_out[4] = \ ; assign qplldmonitor0_out[3] = \ ; assign qplldmonitor0_out[2] = \ ; assign qplldmonitor0_out[1] = \ ; assign qplldmonitor0_out[0] = \ ; assign qplldmonitor1_out[7] = \ ; assign qplldmonitor1_out[6] = \ ; assign qplldmonitor1_out[5] = \ ; assign qplldmonitor1_out[4] = \ ; assign qplldmonitor1_out[3] = \ ; assign qplldmonitor1_out[2] = \ ; assign qplldmonitor1_out[1] = \ ; assign qplldmonitor1_out[0] = \ ; assign refclkoutmonitor0_out[0] = \ ; assign refclkoutmonitor1_out[0] = \ ; assign resetexception_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxbyteisaligned_out[0] = \ ; assign rxbyterealign_out[0] = \ ; assign rxcdrlock_out[0] = \ ; assign rxcdrphdone_out[0] = \ ; assign rxchanbondseq_out[0] = \ ; assign rxchanisaligned_out[0] = \ ; assign rxchanrealign_out[0] = \ ; assign rxchbondo_out[4] = \ ; assign rxchbondo_out[3] = \ ; assign rxchbondo_out[2] = \ ; assign rxchbondo_out[1] = \ ; assign rxchbondo_out[0] = \ ; assign rxckcaldone_out[0] = \ ; assign rxcominitdet_out[0] = \ ; assign rxcommadet_out[0] = \ ; assign rxcomsasdet_out[0] = \ ; assign rxcomwakedet_out[0] = \ ; assign rxctrl0_out[15] = \ ; assign rxctrl0_out[14] = \ ; assign rxctrl0_out[13] = \ ; assign rxctrl0_out[12] = \ ; assign rxctrl0_out[11] = \ ; assign rxctrl0_out[10] = \ ; assign rxctrl0_out[9] = \ ; assign rxctrl0_out[8] = \ ; assign rxctrl0_out[7] = \ ; assign rxctrl0_out[6] = \ ; assign rxctrl0_out[5] = \ ; assign rxctrl0_out[4] = \ ; assign rxctrl0_out[3] = \ ; assign rxctrl0_out[2] = \ ; assign rxctrl0_out[1:0] = \^rxctrl0_out [1:0]; assign rxctrl1_out[15] = \ ; assign rxctrl1_out[14] = \ ; assign rxctrl1_out[13] = \ ; assign rxctrl1_out[12] = \ ; assign rxctrl1_out[11] = \ ; assign rxctrl1_out[10] = \ ; assign rxctrl1_out[9] = \ ; assign rxctrl1_out[8] = \ ; assign rxctrl1_out[7] = \ ; assign rxctrl1_out[6] = \ ; assign rxctrl1_out[5] = \ ; assign rxctrl1_out[4] = \ ; assign rxctrl1_out[3] = \ ; assign rxctrl1_out[2] = \ ; assign rxctrl1_out[1:0] = \^rxctrl1_out [1:0]; assign rxctrl2_out[7] = \ ; assign rxctrl2_out[6] = \ ; assign rxctrl2_out[5] = \ ; assign rxctrl2_out[4] = \ ; assign rxctrl2_out[3] = \ ; assign rxctrl2_out[2] = \ ; assign rxctrl2_out[1:0] = \^rxctrl2_out [1:0]; assign rxctrl3_out[7] = \ ; assign rxctrl3_out[6] = \ ; assign rxctrl3_out[5] = \ ; assign rxctrl3_out[4] = \ ; assign rxctrl3_out[3] = \ ; assign rxctrl3_out[2] = \ ; assign rxctrl3_out[1:0] = \^rxctrl3_out [1:0]; assign rxdata_out[127] = \ ; assign rxdata_out[126] = \ ; assign rxdata_out[125] = \ ; assign rxdata_out[124] = \ ; assign rxdata_out[123] = \ ; assign rxdata_out[122] = \ ; assign rxdata_out[121] = \ ; assign rxdata_out[120] = \ ; assign rxdata_out[119] = \ ; assign rxdata_out[118] = \ ; assign rxdata_out[117] = \ ; assign rxdata_out[116] = \ ; assign rxdata_out[115] = \ ; assign rxdata_out[114] = \ ; assign rxdata_out[113] = \ ; assign rxdata_out[112] = \ ; assign rxdata_out[111] = \ ; assign rxdata_out[110] = \ ; assign rxdata_out[109] = \ ; assign rxdata_out[108] = \ ; assign rxdata_out[107] = \ ; assign rxdata_out[106] = \ ; assign rxdata_out[105] = \ ; assign rxdata_out[104] = \ ; assign rxdata_out[103] = \ ; assign rxdata_out[102] = \ ; assign rxdata_out[101] = \ ; assign rxdata_out[100] = \ ; assign rxdata_out[99] = \ ; assign rxdata_out[98] = \ ; assign rxdata_out[97] = \ ; assign rxdata_out[96] = \ ; assign rxdata_out[95] = \ ; assign rxdata_out[94] = \ ; assign rxdata_out[93] = \ ; assign rxdata_out[92] = \ ; assign rxdata_out[91] = \ ; assign rxdata_out[90] = \ ; assign rxdata_out[89] = \ ; assign rxdata_out[88] = \ ; assign rxdata_out[87] = \ ; assign rxdata_out[86] = \ ; assign rxdata_out[85] = \ ; assign rxdata_out[84] = \ ; assign rxdata_out[83] = \ ; assign rxdata_out[82] = \ ; assign rxdata_out[81] = \ ; assign rxdata_out[80] = \ ; assign rxdata_out[79] = \ ; assign rxdata_out[78] = \ ; assign rxdata_out[77] = \ ; assign rxdata_out[76] = \ ; assign rxdata_out[75] = \ ; assign rxdata_out[74] = \ ; assign rxdata_out[73] = \ ; assign rxdata_out[72] = \ ; assign rxdata_out[71] = \ ; assign rxdata_out[70] = \ ; assign rxdata_out[69] = \ ; assign rxdata_out[68] = \ ; assign rxdata_out[67] = \ ; assign rxdata_out[66] = \ ; assign rxdata_out[65] = \ ; assign rxdata_out[64] = \ ; assign rxdata_out[63] = \ ; assign rxdata_out[62] = \ ; assign rxdata_out[61] = \ ; assign rxdata_out[60] = \ ; assign rxdata_out[59] = \ ; assign rxdata_out[58] = \ ; assign rxdata_out[57] = \ ; assign rxdata_out[56] = \ ; assign rxdata_out[55] = \ ; assign rxdata_out[54] = \ ; assign rxdata_out[53] = \ ; assign rxdata_out[52] = \ ; assign rxdata_out[51] = \ ; assign rxdata_out[50] = \ ; assign rxdata_out[49] = \ ; assign rxdata_out[48] = \ ; assign rxdata_out[47] = \ ; assign rxdata_out[46] = \ ; assign rxdata_out[45] = \ ; assign rxdata_out[44] = \ ; assign rxdata_out[43] = \ ; assign rxdata_out[42] = \ ; assign rxdata_out[41] = \ ; assign rxdata_out[40] = \ ; assign rxdata_out[39] = \ ; assign rxdata_out[38] = \ ; assign rxdata_out[37] = \ ; assign rxdata_out[36] = \ ; assign rxdata_out[35] = \ ; assign rxdata_out[34] = \ ; assign rxdata_out[33] = \ ; assign rxdata_out[32] = \ ; assign rxdata_out[31] = \ ; assign rxdata_out[30] = \ ; assign rxdata_out[29] = \ ; assign rxdata_out[28] = \ ; assign rxdata_out[27] = \ ; assign rxdata_out[26] = \ ; assign rxdata_out[25] = \ ; assign rxdata_out[24] = \ ; assign rxdata_out[23] = \ ; assign rxdata_out[22] = \ ; assign rxdata_out[21] = \ ; assign rxdata_out[20] = \ ; assign rxdata_out[19] = \ ; assign rxdata_out[18] = \ ; assign rxdata_out[17] = \ ; assign rxdata_out[16] = \ ; assign rxdata_out[15] = \ ; assign rxdata_out[14] = \ ; assign rxdata_out[13] = \ ; assign rxdata_out[12] = \ ; assign rxdata_out[11] = \ ; assign rxdata_out[10] = \ ; assign rxdata_out[9] = \ ; assign rxdata_out[8] = \ ; assign rxdata_out[7] = \ ; assign rxdata_out[6] = \ ; assign rxdata_out[5] = \ ; assign rxdata_out[4] = \ ; assign rxdata_out[3] = \ ; assign rxdata_out[2] = \ ; assign rxdata_out[1] = \ ; assign rxdata_out[0] = \ ; assign rxdataextendrsvd_out[7] = \ ; assign rxdataextendrsvd_out[6] = \ ; assign rxdataextendrsvd_out[5] = \ ; assign rxdataextendrsvd_out[4] = \ ; assign rxdataextendrsvd_out[3] = \ ; assign rxdataextendrsvd_out[2] = \ ; assign rxdataextendrsvd_out[1] = \ ; assign rxdataextendrsvd_out[0] = \ ; assign rxdatavalid_out[1] = \ ; assign rxdatavalid_out[0] = \ ; assign rxdlysresetdone_out[0] = \ ; assign rxelecidle_out[0] = \ ; assign rxheader_out[5] = \ ; assign rxheader_out[4] = \ ; assign rxheader_out[3] = \ ; assign rxheader_out[2] = \ ; assign rxheader_out[1] = \ ; assign rxheader_out[0] = \ ; assign rxheadervalid_out[1] = \ ; assign rxheadervalid_out[0] = \ ; assign rxlfpstresetdet_out[0] = \ ; assign rxlfpsu2lpexitdet_out[0] = \ ; assign rxlfpsu3wakedet_out[0] = \ ; assign rxmonitorout_out[6] = \ ; assign rxmonitorout_out[5] = \ ; assign rxmonitorout_out[4] = \ ; assign rxmonitorout_out[3] = \ ; assign rxmonitorout_out[2] = \ ; assign rxmonitorout_out[1] = \ ; assign rxmonitorout_out[0] = \ ; assign rxosintdone_out[0] = \ ; assign rxosintstarted_out[0] = \ ; assign rxosintstrobedone_out[0] = \ ; assign rxosintstrobestarted_out[0] = \ ; assign rxoutclkfabric_out[0] = \ ; assign rxoutclkpcs_out[0] = \ ; assign rxphaligndone_out[0] = \ ; assign rxphalignerr_out[0] = \ ; assign rxpmaresetdone_out[0] = \ ; assign rxprbserr_out[0] = \ ; assign rxprbslocked_out[0] = \ ; assign rxprgdivresetdone_out[0] = \ ; assign rxqpisenn_out[0] = \ ; assign rxqpisenp_out[0] = \ ; assign rxratedone_out[0] = \ ; assign rxrecclk0_sel_out[1] = \ ; assign rxrecclk0_sel_out[0] = \ ; assign rxrecclk0sel_out[0] = \ ; assign rxrecclk1_sel_out[1] = \ ; assign rxrecclk1_sel_out[0] = \ ; assign rxrecclk1sel_out[0] = \ ; assign rxrecclkout_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign rxsliderdy_out[0] = \ ; assign rxslipdone_out[0] = \ ; assign rxslipoutclkrdy_out[0] = \ ; assign rxslippmardy_out[0] = \ ; assign rxstartofseq_out[1] = \ ; assign rxstartofseq_out[0] = \ ; assign rxstatus_out[2] = \ ; assign rxstatus_out[1] = \ ; assign rxstatus_out[0] = \ ; assign rxsyncdone_out[0] = \ ; assign rxsyncout_out[0] = \ ; assign rxvalid_out[0] = \ ; assign sdm0finalout_out[0] = \ ; assign sdm0testdata_out[0] = \ ; assign sdm1finalout_out[0] = \ ; assign sdm1testdata_out[0] = \ ; assign tcongpo_out[0] = \ ; assign tconrsvdout0_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txcomfinish_out[0] = \ ; assign txdccdone_out[0] = \ ; assign txdlysresetdone_out[0] = \ ; assign txoutclkfabric_out[0] = \ ; assign txoutclkpcs_out[0] = \ ; assign txphaligndone_out[0] = \ ; assign txphinitdone_out[0] = \ ; assign txpmaresetdone_out[0] = \ ; assign txprgdivresetdone_out[0] = \ ; assign txqpisenn_out[0] = \ ; assign txqpisenp_out[0] = \ ; assign txratedone_out[0] = \ ; assign txresetdone_out[0] = \ ; assign txsyncdone_out[0] = \ ; assign txsyncout_out[0] = \ ; assign ubdaddr_out[0] = \ ; assign ubden_out[0] = \ ; assign ubdi_out[0] = \ ; assign ubdwe_out[0] = \ ; assign ubmdmtdo_out[0] = \ ; assign ubrsvdout_out[0] = \ ; assign ubtxuart_out[0] = \ ; GND GND (.G(\ )); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 \gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rxbufstatus_out(\^rxbufstatus_out ), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(\^rxctrl0_out ), .rxctrl1_out(\^rxctrl1_out ), .rxctrl2_out(\^rxctrl2_out ), .rxctrl3_out(\^rxctrl3_out ), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in[1]), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(\^txbufstatus_out ), .txctrl0_in(txctrl0_in[1:0]), .txctrl1_in(txctrl1_in[1:0]), .txctrl2_in(txctrl2_in[1:0]), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync (reset_out, rxuserclk2, gtwiz_reset_rx_done_out); output reset_out; input rxuserclk2; input [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_done_out; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire rxuserclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(rxuserclk2), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 (gtwiz_reset_rx_done_out_int_reg0, reset_out, rxuserclk2, SR); output gtwiz_reset_rx_done_out_int_reg0; input reset_out; input rxuserclk2; input [0:0]SR; wire [0:0]SR; wire gtwiz_reset_rx_done_out_int_reg0; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire rxreset_int; wire rxuserclk2; LUT2 #( .INIT(4'h8)) gtwiz_reset_rx_done_out_int_reg_i_1 (.I0(rxreset_int), .I1(reset_out), .O(gtwiz_reset_rx_done_out_int_reg0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(rxuserclk2), .CE(1'b1), .D(1'b0), .PRE(SR), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(SR), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(SR), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(SR), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(SR), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(rxreset_int)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 (gtwiz_reset_tx_done_out_int_reg0, gtwiz_reset_tx_done_out, userclk, txreset); output gtwiz_reset_tx_done_out_int_reg0; input [0:0]gtwiz_reset_tx_done_out; input userclk; input txreset; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_reset_tx_done_out_int_reg0; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire txreset; wire txreset_int; wire userclk; LUT2 #( .INIT(4'h8)) gtwiz_reset_tx_done_out_int_reg_i_1 (.I0(txreset_int), .I1(gtwiz_reset_tx_done_out), .O(gtwiz_reset_tx_done_out_int_reg0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk), .CE(1'b1), .D(1'b0), .PRE(txreset), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk), .CE(1'b1), .D(reset_sync_reg1), .PRE(txreset), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk), .CE(1'b1), .D(reset_sync_reg2), .PRE(txreset), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk), .CE(1'b1), .D(reset_sync_reg3), .PRE(txreset), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk), .CE(1'b1), .D(reset_sync_reg4), .PRE(txreset), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(txreset_int)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 (reset_out, userclk2, enablealign); output reset_out; input userclk2; input enablealign; wire enablealign; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk2), .CE(1'b1), .D(1'b0), .PRE(enablealign), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(enablealign), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(enablealign), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(enablealign), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(enablealign), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_sync_block" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_sync_block (resetdone, data_in, userclk2); output resetdone; input data_in; input userclk2; wire data_in; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire resetdone; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk2), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk2), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk2), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk2), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk2), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk2), .CE(1'b1), .D(data_sync5), .Q(resetdone), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_transceiver" *) module gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_transceiver (cplllock, txn, txp, gtpowergood, rxoutclk, txoutclk, rxchariscomma, rxcharisk, Q, \rxdata_reg[7]_0 , rxdisperr, rxnotintable, rxbuferr, txbuferr, data_in, mmcm_reset, userclk2, enablealign, userclk, txreset, rxuserclk2, SR, mmcm_locked, pma_reset, independent_clock_bufg, rxn, rxp, gtrefclk, D, powerdown, txchardispval_reg_reg_0, txchardispmode_reg_reg_0, txcharisk_reg_reg_0); output cplllock; output txn; output txp; output gtpowergood; output rxoutclk; output txoutclk; output rxchariscomma; output rxcharisk; output [1:0]Q; output [7:0]\rxdata_reg[7]_0 ; output rxdisperr; output rxnotintable; output rxbuferr; output txbuferr; output data_in; output mmcm_reset; input userclk2; input enablealign; input userclk; input txreset; input rxuserclk2; input [0:0]SR; input mmcm_locked; input pma_reset; input independent_clock_bufg; input rxn; input rxp; input gtrefclk; input [7:0]D; input powerdown; input [0:0]txchardispval_reg_reg_0; input [0:0]txchardispmode_reg_reg_0; input [0:0]txcharisk_reg_reg_0; wire [7:0]D; wire [1:0]Q; wire [0:0]SR; wire cplllock; wire data_in; wire enablealign; wire encommaalign_int; wire gig_ethernet_pcs_pma_0_gt_i_n_118; wire gig_ethernet_pcs_pma_0_gt_i_n_58; wire gtpowergood; wire gtrefclk; wire gtwiz_reset_rx_done_out_int; wire gtwiz_reset_rx_done_out_int_reg; wire gtwiz_reset_rx_done_out_int_reg0; wire gtwiz_reset_rx_done_out_reg; wire gtwiz_reset_tx_done_out_int; wire gtwiz_reset_tx_done_out_int_reg; wire gtwiz_reset_tx_done_out_int_reg0; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire p_0_in; wire [7:0]p_1_in; wire [0:0]p_1_in__0; wire [0:0]p_1_in__1; wire [0:0]p_1_in__2; wire pma_reset; wire powerdown; wire rxbuferr; wire rxchariscomma; wire [1:0]rxchariscomma_double; wire rxchariscomma_i_1_n_0; wire [1:0]rxchariscomma_reg__0; wire rxcharisk; wire [1:0]rxcharisk_double; wire rxcharisk_i_1_n_0; wire [1:0]rxcharisk_reg__0; wire [1:0]rxclkcorcnt_double; wire [1:0]rxclkcorcnt_int; wire [1:0]rxclkcorcnt_reg; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire \rxdata[0]_i_1_n_0 ; wire \rxdata[1]_i_1_n_0 ; wire \rxdata[2]_i_1_n_0 ; wire \rxdata[3]_i_1_n_0 ; wire \rxdata[4]_i_1_n_0 ; wire \rxdata[5]_i_1_n_0 ; wire \rxdata[6]_i_1_n_0 ; wire \rxdata[7]_i_1_n_0 ; wire [15:0]rxdata_double; wire [15:0]rxdata_int; wire [15:0]rxdata_reg; wire [7:0]\rxdata_reg[7]_0 ; wire rxdisperr; wire [1:0]rxdisperr_double; wire rxdisperr_i_1_n_0; wire [1:0]rxdisperr_reg__0; wire rxn; wire rxnotintable; wire [1:0]rxnotintable_double; wire rxnotintable_i_1_n_0; wire [1:0]rxnotintable_reg__0; wire rxoutclk; wire rxp; wire rxpowerdown; wire rxpowerdown_double; wire rxpowerdown_reg__0; wire rxuserclk2; wire toggle; wire toggle_i_1_n_0; wire txbuferr; wire [1:1]txbufstatus_reg; wire [1:0]txchardispmode_double; wire [1:0]txchardispmode_int; wire [0:0]txchardispmode_reg_reg_0; wire [1:0]txchardispval_double; wire [1:0]txchardispval_int; wire [0:0]txchardispval_reg_reg_0; wire [1:0]txcharisk_double; wire [1:0]txcharisk_int; wire [0:0]txcharisk_reg_reg_0; wire [15:0]txdata_double; wire [15:0]txdata_int; wire txn; wire txoutclk; wire txp; wire txpowerdown; wire txpowerdown_double; wire txpowerdown_reg__0; wire txreset; wire userclk; wire userclk2; wire [16:0]NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED; wire [15:0]NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED; wire [15:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED; wire [15:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED; wire [7:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED; wire [7:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED; gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync SYNC_ASYNC_RESET_GT_RX (.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out_int), .reset_out(gtwiz_reset_rx_done_out_reg), .rxuserclk2(rxuserclk2)); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_0 SYNC_ASYNC_RESET_RX (.SR(SR), .gtwiz_reset_rx_done_out_int_reg0(gtwiz_reset_rx_done_out_int_reg0), .reset_out(gtwiz_reset_rx_done_out_reg), .rxuserclk2(rxuserclk2)); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_1 SYNC_ASYNC_RESET_TX (.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out_int), .gtwiz_reset_tx_done_out_int_reg0(gtwiz_reset_tx_done_out_int_reg0), .txreset(txreset), .userclk(userclk)); LUT2 #( .INIT(4'h8)) data_sync1_i_1 (.I0(gtwiz_reset_tx_done_out_int), .I1(gtwiz_reset_rx_done_out_int), .O(data_in)); (* CHECK_LICENSE_TYPE = "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}" *) (* X_CORE_INFO = "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2" *) (* downgradeipidentifiedwarnings = "yes" *) gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_gt gig_ethernet_pcs_pma_0_gt_i (.cplllock_out(cplllock), .cpllrefclksel_in({1'b0,1'b0,1'b1}), .dmonitorout_out(NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED[16:0]), .drpaddr_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpclk_in(independent_clock_bufg), .drpdi_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdo_out(NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED[15:0]), .drpen_in(1'b0), .drprdy_out(NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED[0]), .drpwe_in(1'b0), .eyescandataerror_out(NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED[0]), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .gthrxn_in(rxn), .gthrxp_in(rxp), .gthtxn_out(txn), .gthtxp_out(txp), .gtpowergood_out(gtpowergood), .gtrefclk0_in(gtrefclk), .gtrefclk1_in(1'b0), .gtwiz_reset_all_in(pma_reset), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_rx_cdr_stable_out(NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_done_out_int_reg), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out_int), .gtwiz_reset_rx_pll_and_datapath_in(1'b0), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_done_out_int_reg), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out_int), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(1'b0), .gtwiz_userclk_tx_active_in(mmcm_locked), .gtwiz_userdata_rx_out(rxdata_int), .gtwiz_userdata_tx_in(txdata_int), .loopback_in({1'b0,1'b0,1'b0}), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx8b10ben_in(1'b1), .rxbufreset_in(1'b0), .rxbufstatus_out({gig_ethernet_pcs_pma_0_gt_i_n_58,NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED[1:0]}), .rxbyteisaligned_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED[0]), .rxbyterealign_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED[0]), .rxcdrhold_in(1'b0), .rxclkcorcnt_out(rxclkcorcnt_int), .rxcommadet_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED[0]), .rxcommadeten_in(1'b1), .rxctrl0_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED[15:2],rxctrl0_out}), .rxctrl1_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED[15:2],rxctrl1_out}), .rxctrl2_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED[7:2],rxctrl2_out}), .rxctrl3_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED[7:2],rxctrl3_out}), .rxdfelpmreset_in(1'b0), .rxlpmen_in(1'b1), .rxmcommaalignen_in(encommaalign_int), .rxoutclk_out(rxoutclk), .rxpcommaalignen_in(1'b0), .rxpcsreset_in(1'b0), .rxpd_in({rxpowerdown,1'b0}), .rxpmareset_in(1'b0), .rxpmaresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED[0]), .rxpolarity_in(1'b0), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxrate_in({1'b0,1'b0,1'b0}), .rxresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED[0]), .rxusrclk2_in(1'b0), .rxusrclk_in(userclk), .tx8b10ben_in(1'b1), .txbufstatus_out({gig_ethernet_pcs_pma_0_gt_i_n_118,NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED[0]}), .txctrl0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txchardispval_int}), .txctrl1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txchardispmode_int}), .txctrl2_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txcharisk_int}), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txelecidle_in(txpowerdown), .txinhibit_in(1'b0), .txoutclk_out(txoutclk), .txpcsreset_in(1'b0), .txpd_in({1'b0,1'b0}), .txpmareset_in(1'b0), .txpmaresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED[0]), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprgdivresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED[0]), .txresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED[0]), .txusrclk2_in(1'b0), .txusrclk_in(1'b0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_done_out_int_reg_reg (.C(rxuserclk2), .CE(1'b1), .D(gtwiz_reset_rx_done_out_int_reg0), .Q(gtwiz_reset_rx_done_out_int_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_done_out_int_reg_reg (.C(userclk), .CE(1'b1), .D(gtwiz_reset_tx_done_out_int_reg0), .Q(gtwiz_reset_tx_done_out_int_reg), .R(1'b0)); LUT1 #( .INIT(2'h1)) mmcm_reset_INST_0 (.I0(cplllock), .O(mmcm_reset)); gig_ethernet_pcs_pma_0_gig_ethernet_pcs_pma_0_reset_sync_2 reclock_encommaalign (.enablealign(enablealign), .reset_out(encommaalign_int), .userclk2(userclk2)); FDRE rxbuferr_reg (.C(userclk2), .CE(1'b1), .D(p_0_in), .Q(rxbuferr), .R(1'b0)); FDRE \rxbufstatus_reg_reg[2] (.C(userclk), .CE(1'b1), .D(gig_ethernet_pcs_pma_0_gt_i_n_58), .Q(p_0_in), .R(1'b0)); FDRE \rxchariscomma_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[0]), .Q(rxchariscomma_double[0]), .R(SR)); FDRE \rxchariscomma_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[1]), .Q(rxchariscomma_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) rxchariscomma_i_1 (.I0(rxchariscomma_double[1]), .I1(toggle), .I2(rxchariscomma_double[0]), .O(rxchariscomma_i_1_n_0)); FDRE rxchariscomma_reg (.C(userclk2), .CE(1'b1), .D(rxchariscomma_i_1_n_0), .Q(rxchariscomma), .R(SR)); FDRE \rxchariscomma_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl2_out[0]), .Q(rxchariscomma_reg__0[0]), .R(1'b0)); FDRE \rxchariscomma_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl2_out[1]), .Q(rxchariscomma_reg__0[1]), .R(1'b0)); FDRE \rxcharisk_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[0]), .Q(rxcharisk_double[0]), .R(SR)); FDRE \rxcharisk_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[1]), .Q(rxcharisk_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) rxcharisk_i_1 (.I0(rxcharisk_double[1]), .I1(toggle), .I2(rxcharisk_double[0]), .O(rxcharisk_i_1_n_0)); FDRE rxcharisk_reg (.C(userclk2), .CE(1'b1), .D(rxcharisk_i_1_n_0), .Q(rxcharisk), .R(SR)); FDRE \rxcharisk_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl0_out[0]), .Q(rxcharisk_reg__0[0]), .R(1'b0)); FDRE \rxcharisk_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl0_out[1]), .Q(rxcharisk_reg__0[1]), .R(1'b0)); FDRE \rxclkcorcnt_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[0]), .Q(rxclkcorcnt_double[0]), .R(SR)); FDRE \rxclkcorcnt_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[1]), .Q(rxclkcorcnt_double[1]), .R(SR)); FDRE \rxclkcorcnt_reg[0] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[0]), .Q(Q[0]), .R(SR)); FDRE \rxclkcorcnt_reg[1] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[1]), .Q(Q[1]), .R(SR)); FDRE \rxclkcorcnt_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[0]), .Q(rxclkcorcnt_reg[0]), .R(1'b0)); FDRE \rxclkcorcnt_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[1]), .Q(rxclkcorcnt_reg[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) \rxdata[0]_i_1 (.I0(rxdata_double[8]), .I1(toggle), .I2(rxdata_double[0]), .O(\rxdata[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) \rxdata[1]_i_1 (.I0(rxdata_double[9]), .I1(toggle), .I2(rxdata_double[1]), .O(\rxdata[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \rxdata[2]_i_1 (.I0(rxdata_double[10]), .I1(toggle), .I2(rxdata_double[2]), .O(\rxdata[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \rxdata[3]_i_1 (.I0(rxdata_double[11]), .I1(toggle), .I2(rxdata_double[3]), .O(\rxdata[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) \rxdata[4]_i_1 (.I0(rxdata_double[12]), .I1(toggle), .I2(rxdata_double[4]), .O(\rxdata[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) \rxdata[5]_i_1 (.I0(rxdata_double[13]), .I1(toggle), .I2(rxdata_double[5]), .O(\rxdata[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) \rxdata[6]_i_1 (.I0(rxdata_double[14]), .I1(toggle), .I2(rxdata_double[6]), .O(\rxdata[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) \rxdata[7]_i_1 (.I0(rxdata_double[15]), .I1(toggle), .I2(rxdata_double[7]), .O(\rxdata[7]_i_1_n_0 )); FDRE \rxdata_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdata_reg[0]), .Q(rxdata_double[0]), .R(SR)); FDRE \rxdata_double_reg[10] (.C(userclk2), .CE(toggle), .D(rxdata_reg[10]), .Q(rxdata_double[10]), .R(SR)); FDRE \rxdata_double_reg[11] (.C(userclk2), .CE(toggle), .D(rxdata_reg[11]), .Q(rxdata_double[11]), .R(SR)); FDRE \rxdata_double_reg[12] (.C(userclk2), .CE(toggle), .D(rxdata_reg[12]), .Q(rxdata_double[12]), .R(SR)); FDRE \rxdata_double_reg[13] (.C(userclk2), .CE(toggle), .D(rxdata_reg[13]), .Q(rxdata_double[13]), .R(SR)); FDRE \rxdata_double_reg[14] (.C(userclk2), .CE(toggle), .D(rxdata_reg[14]), .Q(rxdata_double[14]), .R(SR)); FDRE \rxdata_double_reg[15] (.C(userclk2), .CE(toggle), .D(rxdata_reg[15]), .Q(rxdata_double[15]), .R(SR)); FDRE \rxdata_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdata_reg[1]), .Q(rxdata_double[1]), .R(SR)); FDRE \rxdata_double_reg[2] (.C(userclk2), .CE(toggle), .D(rxdata_reg[2]), .Q(rxdata_double[2]), .R(SR)); FDRE \rxdata_double_reg[3] (.C(userclk2), .CE(toggle), .D(rxdata_reg[3]), .Q(rxdata_double[3]), .R(SR)); FDRE \rxdata_double_reg[4] (.C(userclk2), .CE(toggle), .D(rxdata_reg[4]), .Q(rxdata_double[4]), .R(SR)); FDRE \rxdata_double_reg[5] (.C(userclk2), .CE(toggle), .D(rxdata_reg[5]), .Q(rxdata_double[5]), .R(SR)); FDRE \rxdata_double_reg[6] (.C(userclk2), .CE(toggle), .D(rxdata_reg[6]), .Q(rxdata_double[6]), .R(SR)); FDRE \rxdata_double_reg[7] (.C(userclk2), .CE(toggle), .D(rxdata_reg[7]), .Q(rxdata_double[7]), .R(SR)); FDRE \rxdata_double_reg[8] (.C(userclk2), .CE(toggle), .D(rxdata_reg[8]), .Q(rxdata_double[8]), .R(SR)); FDRE \rxdata_double_reg[9] (.C(userclk2), .CE(toggle), .D(rxdata_reg[9]), .Q(rxdata_double[9]), .R(SR)); FDRE \rxdata_reg[0] (.C(userclk2), .CE(1'b1), .D(\rxdata[0]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [0]), .R(SR)); FDRE \rxdata_reg[1] (.C(userclk2), .CE(1'b1), .D(\rxdata[1]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [1]), .R(SR)); FDRE \rxdata_reg[2] (.C(userclk2), .CE(1'b1), .D(\rxdata[2]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [2]), .R(SR)); FDRE \rxdata_reg[3] (.C(userclk2), .CE(1'b1), .D(\rxdata[3]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [3]), .R(SR)); FDRE \rxdata_reg[4] (.C(userclk2), .CE(1'b1), .D(\rxdata[4]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [4]), .R(SR)); FDRE \rxdata_reg[5] (.C(userclk2), .CE(1'b1), .D(\rxdata[5]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [5]), .R(SR)); FDRE \rxdata_reg[6] (.C(userclk2), .CE(1'b1), .D(\rxdata[6]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [6]), .R(SR)); FDRE \rxdata_reg[7] (.C(userclk2), .CE(1'b1), .D(\rxdata[7]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [7]), .R(SR)); FDRE \rxdata_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxdata_int[0]), .Q(rxdata_reg[0]), .R(1'b0)); FDRE \rxdata_reg_reg[10] (.C(userclk), .CE(1'b1), .D(rxdata_int[10]), .Q(rxdata_reg[10]), .R(1'b0)); FDRE \rxdata_reg_reg[11] (.C(userclk), .CE(1'b1), .D(rxdata_int[11]), .Q(rxdata_reg[11]), .R(1'b0)); FDRE \rxdata_reg_reg[12] (.C(userclk), .CE(1'b1), .D(rxdata_int[12]), .Q(rxdata_reg[12]), .R(1'b0)); FDRE \rxdata_reg_reg[13] (.C(userclk), .CE(1'b1), .D(rxdata_int[13]), .Q(rxdata_reg[13]), .R(1'b0)); FDRE \rxdata_reg_reg[14] (.C(userclk), .CE(1'b1), .D(rxdata_int[14]), .Q(rxdata_reg[14]), .R(1'b0)); FDRE \rxdata_reg_reg[15] (.C(userclk), .CE(1'b1), .D(rxdata_int[15]), .Q(rxdata_reg[15]), .R(1'b0)); FDRE \rxdata_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxdata_int[1]), .Q(rxdata_reg[1]), .R(1'b0)); FDRE \rxdata_reg_reg[2] (.C(userclk), .CE(1'b1), .D(rxdata_int[2]), .Q(rxdata_reg[2]), .R(1'b0)); FDRE \rxdata_reg_reg[3] (.C(userclk), .CE(1'b1), .D(rxdata_int[3]), .Q(rxdata_reg[3]), .R(1'b0)); FDRE \rxdata_reg_reg[4] (.C(userclk), .CE(1'b1), .D(rxdata_int[4]), .Q(rxdata_reg[4]), .R(1'b0)); FDRE \rxdata_reg_reg[5] (.C(userclk), .CE(1'b1), .D(rxdata_int[5]), .Q(rxdata_reg[5]), .R(1'b0)); FDRE \rxdata_reg_reg[6] (.C(userclk), .CE(1'b1), .D(rxdata_int[6]), .Q(rxdata_reg[6]), .R(1'b0)); FDRE \rxdata_reg_reg[7] (.C(userclk), .CE(1'b1), .D(rxdata_int[7]), .Q(rxdata_reg[7]), .R(1'b0)); FDRE \rxdata_reg_reg[8] (.C(userclk), .CE(1'b1), .D(rxdata_int[8]), .Q(rxdata_reg[8]), .R(1'b0)); FDRE \rxdata_reg_reg[9] (.C(userclk), .CE(1'b1), .D(rxdata_int[9]), .Q(rxdata_reg[9]), .R(1'b0)); FDRE \rxdisperr_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[0]), .Q(rxdisperr_double[0]), .R(SR)); FDRE \rxdisperr_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[1]), .Q(rxdisperr_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) rxdisperr_i_1 (.I0(rxdisperr_double[1]), .I1(toggle), .I2(rxdisperr_double[0]), .O(rxdisperr_i_1_n_0)); FDRE rxdisperr_reg (.C(userclk2), .CE(1'b1), .D(rxdisperr_i_1_n_0), .Q(rxdisperr), .R(SR)); FDRE \rxdisperr_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl1_out[0]), .Q(rxdisperr_reg__0[0]), .R(1'b0)); FDRE \rxdisperr_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl1_out[1]), .Q(rxdisperr_reg__0[1]), .R(1'b0)); FDRE \rxnotintable_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[0]), .Q(rxnotintable_double[0]), .R(SR)); FDRE \rxnotintable_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[1]), .Q(rxnotintable_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) rxnotintable_i_1 (.I0(rxnotintable_double[1]), .I1(toggle), .I2(rxnotintable_double[0]), .O(rxnotintable_i_1_n_0)); FDRE rxnotintable_reg (.C(userclk2), .CE(1'b1), .D(rxnotintable_i_1_n_0), .Q(rxnotintable), .R(SR)); FDRE \rxnotintable_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl3_out[0]), .Q(rxnotintable_reg__0[0]), .R(1'b0)); FDRE \rxnotintable_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl3_out[1]), .Q(rxnotintable_reg__0[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_double_reg (.C(userclk2), .CE(toggle), .D(rxpowerdown_reg__0), .Q(rxpowerdown_double), .R(SR)); FDRE #( .INIT(1'b0)) rxpowerdown_reg (.C(userclk), .CE(1'b1), .D(rxpowerdown_double), .Q(rxpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(rxpowerdown_reg__0), .R(SR)); LUT1 #( .INIT(2'h1)) toggle_i_1 (.I0(toggle), .O(toggle_i_1_n_0)); FDRE #( .INIT(1'b0)) toggle_reg (.C(userclk2), .CE(1'b1), .D(toggle_i_1_n_0), .Q(toggle), .R(1'b0)); FDRE txbuferr_reg (.C(userclk2), .CE(1'b1), .D(txbufstatus_reg), .Q(txbuferr), .R(1'b0)); FDRE \txbufstatus_reg_reg[1] (.C(userclk), .CE(1'b1), .D(gig_ethernet_pcs_pma_0_gt_i_n_118), .Q(txbufstatus_reg), .R(1'b0)); FDRE \txchardispmode_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1), .Q(txchardispmode_double[0]), .R(txreset)); FDRE \txchardispmode_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txchardispmode_reg_reg_0), .Q(txchardispmode_double[1]), .R(txreset)); FDRE \txchardispmode_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[0]), .Q(txchardispmode_int[0]), .R(1'b0)); FDRE \txchardispmode_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[1]), .Q(txchardispmode_int[1]), .R(1'b0)); FDRE txchardispmode_reg_reg (.C(userclk2), .CE(1'b1), .D(txchardispmode_reg_reg_0), .Q(p_1_in__1), .R(txreset)); FDRE \txchardispval_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__0), .Q(txchardispval_double[0]), .R(txreset)); FDRE \txchardispval_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txchardispval_reg_reg_0), .Q(txchardispval_double[1]), .R(txreset)); FDRE \txchardispval_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispval_double[0]), .Q(txchardispval_int[0]), .R(1'b0)); FDRE \txchardispval_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispval_double[1]), .Q(txchardispval_int[1]), .R(1'b0)); FDRE txchardispval_reg_reg (.C(userclk2), .CE(1'b1), .D(txchardispval_reg_reg_0), .Q(p_1_in__0), .R(txreset)); FDRE \txcharisk_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__2), .Q(txcharisk_double[0]), .R(txreset)); FDRE \txcharisk_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txcharisk_reg_reg_0), .Q(txcharisk_double[1]), .R(txreset)); FDRE \txcharisk_int_reg[0] (.C(userclk), .CE(1'b1), .D(txcharisk_double[0]), .Q(txcharisk_int[0]), .R(1'b0)); FDRE \txcharisk_int_reg[1] (.C(userclk), .CE(1'b1), .D(txcharisk_double[1]), .Q(txcharisk_int[1]), .R(1'b0)); FDRE txcharisk_reg_reg (.C(userclk2), .CE(1'b1), .D(txcharisk_reg_reg_0), .Q(p_1_in__2), .R(txreset)); FDRE \txdata_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[0]), .Q(txdata_double[0]), .R(txreset)); FDRE \txdata_double_reg[10] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[2]), .Q(txdata_double[10]), .R(txreset)); FDRE \txdata_double_reg[11] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[3]), .Q(txdata_double[11]), .R(txreset)); FDRE \txdata_double_reg[12] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[4]), .Q(txdata_double[12]), .R(txreset)); FDRE \txdata_double_reg[13] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[5]), .Q(txdata_double[13]), .R(txreset)); FDRE \txdata_double_reg[14] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[6]), .Q(txdata_double[14]), .R(txreset)); FDRE \txdata_double_reg[15] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[7]), .Q(txdata_double[15]), .R(txreset)); FDRE \txdata_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[1]), .Q(txdata_double[1]), .R(txreset)); FDRE \txdata_double_reg[2] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[2]), .Q(txdata_double[2]), .R(txreset)); FDRE \txdata_double_reg[3] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[3]), .Q(txdata_double[3]), .R(txreset)); FDRE \txdata_double_reg[4] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[4]), .Q(txdata_double[4]), .R(txreset)); FDRE \txdata_double_reg[5] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[5]), .Q(txdata_double[5]), .R(txreset)); FDRE \txdata_double_reg[6] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[6]), .Q(txdata_double[6]), .R(txreset)); FDRE \txdata_double_reg[7] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[7]), .Q(txdata_double[7]), .R(txreset)); FDRE \txdata_double_reg[8] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[0]), .Q(txdata_double[8]), .R(txreset)); FDRE \txdata_double_reg[9] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[1]), .Q(txdata_double[9]), .R(txreset)); FDRE \txdata_int_reg[0] (.C(userclk), .CE(1'b1), .D(txdata_double[0]), .Q(txdata_int[0]), .R(1'b0)); FDRE \txdata_int_reg[10] (.C(userclk), .CE(1'b1), .D(txdata_double[10]), .Q(txdata_int[10]), .R(1'b0)); FDRE \txdata_int_reg[11] (.C(userclk), .CE(1'b1), .D(txdata_double[11]), .Q(txdata_int[11]), .R(1'b0)); FDRE \txdata_int_reg[12] (.C(userclk), .CE(1'b1), .D(txdata_double[12]), .Q(txdata_int[12]), .R(1'b0)); FDRE \txdata_int_reg[13] (.C(userclk), .CE(1'b1), .D(txdata_double[13]), .Q(txdata_int[13]), .R(1'b0)); FDRE \txdata_int_reg[14] (.C(userclk), .CE(1'b1), .D(txdata_double[14]), .Q(txdata_int[14]), .R(1'b0)); FDRE \txdata_int_reg[15] (.C(userclk), .CE(1'b1), .D(txdata_double[15]), .Q(txdata_int[15]), .R(1'b0)); FDRE \txdata_int_reg[1] (.C(userclk), .CE(1'b1), .D(txdata_double[1]), .Q(txdata_int[1]), .R(1'b0)); FDRE \txdata_int_reg[2] (.C(userclk), .CE(1'b1), .D(txdata_double[2]), .Q(txdata_int[2]), .R(1'b0)); FDRE \txdata_int_reg[3] (.C(userclk), .CE(1'b1), .D(txdata_double[3]), .Q(txdata_int[3]), .R(1'b0)); FDRE \txdata_int_reg[4] (.C(userclk), .CE(1'b1), .D(txdata_double[4]), .Q(txdata_int[4]), .R(1'b0)); FDRE \txdata_int_reg[5] (.C(userclk), .CE(1'b1), .D(txdata_double[5]), .Q(txdata_int[5]), .R(1'b0)); FDRE \txdata_int_reg[6] (.C(userclk), .CE(1'b1), .D(txdata_double[6]), .Q(txdata_int[6]), .R(1'b0)); FDRE \txdata_int_reg[7] (.C(userclk), .CE(1'b1), .D(txdata_double[7]), .Q(txdata_int[7]), .R(1'b0)); FDRE \txdata_int_reg[8] (.C(userclk), .CE(1'b1), .D(txdata_double[8]), .Q(txdata_int[8]), .R(1'b0)); FDRE \txdata_int_reg[9] (.C(userclk), .CE(1'b1), .D(txdata_double[9]), .Q(txdata_int[9]), .R(1'b0)); FDRE \txdata_reg_reg[0] (.C(userclk2), .CE(1'b1), .D(D[0]), .Q(p_1_in[0]), .R(txreset)); FDRE \txdata_reg_reg[1] (.C(userclk2), .CE(1'b1), .D(D[1]), .Q(p_1_in[1]), .R(txreset)); FDRE \txdata_reg_reg[2] (.C(userclk2), .CE(1'b1), .D(D[2]), .Q(p_1_in[2]), .R(txreset)); FDRE \txdata_reg_reg[3] (.C(userclk2), .CE(1'b1), .D(D[3]), .Q(p_1_in[3]), .R(txreset)); FDRE \txdata_reg_reg[4] (.C(userclk2), .CE(1'b1), .D(D[4]), .Q(p_1_in[4]), .R(txreset)); FDRE \txdata_reg_reg[5] (.C(userclk2), .CE(1'b1), .D(D[5]), .Q(p_1_in[5]), .R(txreset)); FDRE \txdata_reg_reg[6] (.C(userclk2), .CE(1'b1), .D(D[6]), .Q(p_1_in[6]), .R(txreset)); FDRE \txdata_reg_reg[7] (.C(userclk2), .CE(1'b1), .D(D[7]), .Q(p_1_in[7]), .R(txreset)); FDRE #( .INIT(1'b0)) txpowerdown_double_reg (.C(userclk2), .CE(1'b1), .D(txpowerdown_reg__0), .Q(txpowerdown_double), .R(txreset)); FDRE #( .INIT(1'b0)) txpowerdown_reg (.C(userclk), .CE(1'b1), .D(txpowerdown_double), .Q(txpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) txpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(txpowerdown_reg__0), .R(txreset)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , rxresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]rxresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]rxresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 (gtwiz_reset_userclk_tx_active_sync, \FSM_sequential_sm_reset_tx_reg[2] , i_in_out_reg_0, gtwiz_userclk_tx_active_in, drpclk_in, Q, sm_reset_tx_timer_clr_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , sm_reset_tx_timer_clr_reg_0, plllock_tx_sync, \FSM_sequential_sm_reset_tx_reg[0] , \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 , sm_reset_tx_pll_timer_sat); output gtwiz_reset_userclk_tx_active_sync; output \FSM_sequential_sm_reset_tx_reg[2] ; output i_in_out_reg_0; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]drpclk_in; input [2:0]Q; input sm_reset_tx_timer_clr_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input sm_reset_tx_timer_clr_reg_0; input plllock_tx_sync; input \FSM_sequential_sm_reset_tx_reg[0] ; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; input sm_reset_tx_pll_timer_sat; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire \FSM_sequential_sm_reset_tx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_tx_active_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_timer_clr_i_2_n_0; wire sm_reset_tx_timer_clr_reg; wire sm_reset_tx_timer_clr_reg_0; LUT6 #( .INIT(64'h000F000088888888)) \FSM_sequential_sm_reset_tx[2]_i_5 (.I0(\FSM_sequential_sm_reset_tx_reg[0] ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I3(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .I4(sm_reset_tx_pll_timer_sat), .I5(Q[0]), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_userclk_tx_active_in), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_tx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT5 #( .INIT(32'hEBEB282B)) sm_reset_tx_timer_clr_i_1 (.I0(sm_reset_tx_timer_clr_i_2_n_0), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(sm_reset_tx_timer_clr_reg), .O(\FSM_sequential_sm_reset_tx_reg[2] )); LUT6 #( .INIT(64'hA0C0A0C0F0F000F0)) sm_reset_tx_timer_clr_i_2 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(sm_reset_tx_timer_clr_reg_0), .I3(Q[0]), .I4(plllock_tx_sync), .I5(Q[2]), .O(sm_reset_tx_timer_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 (plllock_rx_sync, i_in_out_reg_0, \FSM_sequential_sm_reset_rx_reg[1] , cplllock_out, drpclk_in, gtwiz_reset_rx_done_int_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , Q, gtwiz_reset_rx_done_int_reg_0); output plllock_rx_sync; output i_in_out_reg_0; output \FSM_sequential_sm_reset_rx_reg[1] ; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_rx_done_int_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [2:0]Q; input gtwiz_reset_rx_done_int_reg_0; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_done_int; wire gtwiz_reset_rx_done_int_reg; wire gtwiz_reset_rx_done_int_reg_0; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; LUT6 #( .INIT(64'hAAC0FFFFAAC00000)) gtwiz_reset_rx_done_int_i_1 (.I0(plllock_rx_sync), .I1(gtwiz_reset_rx_done_int_reg), .I2(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int), .I5(gtwiz_reset_rx_done_int_reg_0), .O(i_in_out_reg_0)); LUT6 #( .INIT(64'h4C40000040400000)) gtwiz_reset_rx_done_int_i_2 (.I0(plllock_rx_sync), .I1(Q[2]), .I2(Q[0]), .I3(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I4(Q[1]), .I5(gtwiz_reset_rx_done_int_reg), .O(gtwiz_reset_rx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_rx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'h88880000F5FF5555)) sm_reset_rx_timer_clr_i_3 (.I0(Q[1]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int_reg), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 (plllock_tx_sync, gtwiz_reset_tx_done_int_reg, i_in_out_reg_0, cplllock_out, drpclk_in, gtwiz_reset_tx_done_int_reg_0, Q, sm_reset_tx_timer_sat, gtwiz_reset_tx_done_int_reg_1, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , \FSM_sequential_sm_reset_tx_reg[0] ); output plllock_tx_sync; output gtwiz_reset_tx_done_int_reg; output i_in_out_reg_0; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_tx_done_int_reg_0; input [2:0]Q; input sm_reset_tx_timer_sat; input gtwiz_reset_tx_done_int_reg_1; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_tx_done_int; wire gtwiz_reset_tx_done_int_i_2_n_0; wire gtwiz_reset_tx_done_int_reg; wire gtwiz_reset_tx_done_int_reg_0; wire gtwiz_reset_tx_done_int_reg_1; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_timer_sat; LUT6 #( .INIT(64'h00CFA00000000000)) \FSM_sequential_sm_reset_tx[2]_i_4 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(plllock_tx_sync), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(\FSM_sequential_sm_reset_tx_reg[0] ), .O(i_in_out_reg_0)); LUT3 #( .INIT(8'hB8)) gtwiz_reset_tx_done_int_i_1 (.I0(gtwiz_reset_tx_done_int_i_2_n_0), .I1(gtwiz_reset_tx_done_int), .I2(gtwiz_reset_tx_done_int_reg_0), .O(gtwiz_reset_tx_done_int_reg)); LUT6 #( .INIT(64'h4444444444F44444)) gtwiz_reset_tx_done_int_i_2 (.I0(Q[0]), .I1(plllock_tx_sync), .I2(sm_reset_tx_timer_sat), .I3(gtwiz_reset_tx_done_int_reg_1), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I5(Q[1]), .O(gtwiz_reset_tx_done_int_i_2_n_0)); LUT6 #( .INIT(64'h3000404000004040)) gtwiz_reset_tx_done_int_i_3 (.I0(plllock_tx_sync), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_tx_reg[0] ), .I4(Q[0]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .O(gtwiz_reset_tx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_tx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 (\FSM_sequential_sm_reset_rx_reg[2] , \FSM_sequential_sm_reset_rx_reg[1] , sm_reset_rx_cdr_to_sat_reg, rxcdrlock_out, drpclk_in, sm_reset_rx_cdr_to_clr_reg, Q, plllock_rx_sync, sm_reset_rx_cdr_to_clr, \FSM_sequential_sm_reset_rx_reg[0] , sm_reset_rx_cdr_to_sat); output \FSM_sequential_sm_reset_rx_reg[2] ; output \FSM_sequential_sm_reset_rx_reg[1] ; output sm_reset_rx_cdr_to_sat_reg; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input sm_reset_rx_cdr_to_clr_reg; input [2:0]Q; input plllock_rx_sync; input sm_reset_rx_cdr_to_clr; input \FSM_sequential_sm_reset_rx_reg[0] ; input sm_reset_rx_cdr_to_sat; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_n_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; wire [0:0]rxcdrlock_out; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_2_n_0; wire sm_reset_rx_cdr_to_clr_reg; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_reg; LUT6 #( .INIT(64'h000A000AC0C000C0)) \FSM_sequential_sm_reset_rx[2]_i_4 (.I0(sm_reset_rx_cdr_to_sat_reg), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[1]), .I3(Q[0]), .I4(plllock_rx_sync), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxcdrlock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(i_in_out_reg_n_0), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT2 #( .INIT(4'hE)) rxprogdivreset_out_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .O(sm_reset_rx_cdr_to_sat_reg)); LUT6 #( .INIT(64'hFBFFFFFF0800AAAA)) sm_reset_rx_cdr_to_clr_i_1 (.I0(sm_reset_rx_cdr_to_clr_i_2_n_0), .I1(sm_reset_rx_cdr_to_clr_reg), .I2(Q[2]), .I3(plllock_rx_sync), .I4(Q[0]), .I5(sm_reset_rx_cdr_to_clr), .O(\FSM_sequential_sm_reset_rx_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h00EF)) sm_reset_rx_cdr_to_clr_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .I2(Q[2]), .I3(Q[1]), .O(sm_reset_rx_cdr_to_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , txresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input [0:0]txresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]txresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(txresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 (E, gtpowergood_out, drpclk_in, \FSM_sequential_sm_reset_all_reg[0] , Q, \FSM_sequential_sm_reset_all_reg[0]_0 ); output [0:0]E; input [0:0]gtpowergood_out; input [0:0]drpclk_in; input \FSM_sequential_sm_reset_all_reg[0] ; input [2:0]Q; input \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [0:0]E; wire \FSM_sequential_sm_reset_all_reg[0] ; wire \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire [0:0]gtpowergood_out; wire gtpowergood_sync; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; LUT6 #( .INIT(64'hAF0FAF00CFFFCFFF)) \FSM_sequential_sm_reset_all[2]_i_1 (.I0(gtpowergood_sync), .I1(\FSM_sequential_sm_reset_all_reg[0] ), .I2(Q[2]), .I3(Q[0]), .I4(\FSM_sequential_sm_reset_all_reg[0]_0 ), .I5(Q[1]), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtpowergood_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtpowergood_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 (gtwiz_reset_rx_datapath_dly, in0, drpclk_in); output gtwiz_reset_rx_datapath_dly; input in0; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire gtwiz_reset_rx_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 (D, i_in_out_reg_0, in0, drpclk_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , \FSM_sequential_sm_reset_rx_reg[0] , Q, gtwiz_reset_rx_datapath_dly, \FSM_sequential_sm_reset_rx_reg[0]_0 ); output [1:0]D; output i_in_out_reg_0; input in0; input [0:0]drpclk_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input \FSM_sequential_sm_reset_rx_reg[0] ; input [2:0]Q; input gtwiz_reset_rx_datapath_dly; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [1:0]D; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_datapath_dly; wire gtwiz_reset_rx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFF0088FF00FFFFF0)) \FSM_sequential_sm_reset_rx[0]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(gtwiz_reset_rx_pll_and_datapath_dly), .I3(Q[2]), .I4(Q[0]), .I5(Q[1]), .O(D[0])); LUT6 #( .INIT(64'h0000FFFF8F8F000F)) \FSM_sequential_sm_reset_rx[1]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[2]), .I3(gtwiz_reset_rx_pll_and_datapath_dly), .I4(Q[1]), .I5(Q[0]), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFF0000000E)) \FSM_sequential_sm_reset_rx[2]_i_5 (.I0(gtwiz_reset_rx_pll_and_datapath_dly), .I1(gtwiz_reset_rx_datapath_dly), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 (E, in0, drpclk_in, Q, \FSM_sequential_sm_reset_tx_reg[0] , gtwiz_reset_tx_pll_and_datapath_dly, \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 ); output [0:0]E; input in0; input [0:0]drpclk_in; input [0:0]Q; input \FSM_sequential_sm_reset_tx_reg[0] ; input gtwiz_reset_tx_pll_and_datapath_dly; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]E; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFFFFFFFFFFFF1110)) \FSM_sequential_sm_reset_tx[2]_i_1 (.I0(Q), .I1(\FSM_sequential_sm_reset_tx_reg[0] ), .I2(gtwiz_reset_tx_datapath_dly), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .I4(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I5(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 (gtwiz_reset_tx_pll_and_datapath_dly, D, in0, drpclk_in, Q); output gtwiz_reset_tx_pll_and_datapath_dly; output [1:0]D; input in0; input [0:0]drpclk_in; input [2:0]Q; wire [1:0]D; wire [2:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h1F1E)) \FSM_sequential_sm_reset_tx[0]_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h0FF1)) \FSM_sequential_sm_reset_tx[1]_i_1 (.I0(Q[2]), .I1(gtwiz_reset_tx_pll_and_datapath_dly), .I2(Q[1]), .I3(Q[0]), .O(D[1])); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 (\FSM_sequential_sm_reset_rx_reg[0] , \FSM_sequential_sm_reset_rx_reg[2] , E, rxpmaresetdone_out, drpclk_in, sm_reset_rx_timer_clr_reg, Q, sm_reset_rx_timer_clr_reg_0, gtwiz_reset_rx_any_sync, \gen_gtwizard_gthe3.rxuserrdy_int , \FSM_sequential_sm_reset_rx_reg[0]_0 , \FSM_sequential_sm_reset_rx_reg[0]_1 , \FSM_sequential_sm_reset_rx_reg[0]_2 , sm_reset_rx_pll_timer_sat, sm_reset_rx_timer_sat); output \FSM_sequential_sm_reset_rx_reg[0] ; output \FSM_sequential_sm_reset_rx_reg[2] ; output [0:0]E; input [0:0]rxpmaresetdone_out; input [0:0]drpclk_in; input sm_reset_rx_timer_clr_reg; input [2:0]Q; input sm_reset_rx_timer_clr_reg_0; input gtwiz_reset_rx_any_sync; input \gen_gtwizard_gthe3.rxuserrdy_int ; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; input \FSM_sequential_sm_reset_rx_reg[0]_1 ; input \FSM_sequential_sm_reset_rx_reg[0]_2 ; input sm_reset_rx_pll_timer_sat; input sm_reset_rx_timer_sat; wire [0:0]E; wire \FSM_sequential_sm_reset_rx[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire \FSM_sequential_sm_reset_rx_reg[0]_1 ; wire \FSM_sequential_sm_reset_rx_reg[0]_2 ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_userclk_rx_active_sync; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]rxpmaresetdone_out; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_timer_clr_i_2_n_0; wire sm_reset_rx_timer_clr_reg; wire sm_reset_rx_timer_clr_reg_0; wire sm_reset_rx_timer_sat; LUT3 #( .INIT(8'hFE)) \FSM_sequential_sm_reset_rx[2]_i_1 (.I0(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 ), .I1(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .I2(\FSM_sequential_sm_reset_rx_reg[0]_1 ), .O(E)); LUT6 #( .INIT(64'h2023202000000000)) \FSM_sequential_sm_reset_rx[2]_i_3 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_rx_reg[0]_2 ), .I4(sm_reset_rx_pll_timer_sat), .I5(Q[0]), .O(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxpmaresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_rx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFAAF00000800)) rxuserrdy_out_i_1 (.I0(Q[2]), .I1(sm_reset_rx_timer_clr_i_2_n_0), .I2(Q[1]), .I3(Q[0]), .I4(gtwiz_reset_rx_any_sync), .I5(\gen_gtwizard_gthe3.rxuserrdy_int ), .O(\FSM_sequential_sm_reset_rx_reg[2] )); LUT6 #( .INIT(64'hFCCCEFFE0CCCE00E)) sm_reset_rx_timer_clr_i_1 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(sm_reset_rx_timer_clr_reg), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(sm_reset_rx_timer_clr_reg_0), .O(\FSM_sequential_sm_reset_rx_reg[0] )); LUT3 #( .INIT(8'h40)) sm_reset_rx_timer_clr_i_2 (.I0(sm_reset_rx_timer_clr_reg_0), .I1(sm_reset_rx_timer_sat), .I2(gtwiz_reset_userclk_rx_active_sync), .O(sm_reset_rx_timer_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_gthe3_channel" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gthe3_channel (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txresetdone_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxmcommaalignen_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, txelecidle_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txresetdone_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxmcommaalignen_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxpmaresetdone_out; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [0:0]txresetdone_out; (* box_type = "PRIMITIVE" *) GTHE3_CHANNEL #( .ACJTAG_DEBUG_MODE(1'b0), .ACJTAG_MODE(1'b0), .ACJTAG_RESET(1'b0), .ADAPT_CFG0(16'hF800), .ADAPT_CFG1(16'h0000), .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'b1111111111), .ALIGN_COMMA_WORD(2), .ALIGN_MCOMMA_DET("TRUE"), .ALIGN_MCOMMA_VALUE(10'b1010000011), .ALIGN_PCOMMA_DET("TRUE"), .ALIGN_PCOMMA_VALUE(10'b0101111100), .A_RXOSCALRESET(1'b0), .A_RXPROGDIVRESET(1'b0), .A_TXPROGDIVRESET(1'b0), .CBCC_DATA_SOURCE_SEL("DECODED"), .CDR_SWAP_MODE_EN(1'b0), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1), .CHAN_BOND_SEQ_1_1(10'b0000000000), .CHAN_BOND_SEQ_1_2(10'b0000000000), .CHAN_BOND_SEQ_1_3(10'b0000000000), .CHAN_BOND_SEQ_1_4(10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_1(10'b0000000000), .CHAN_BOND_SEQ_2_2(10'b0000000000), .CHAN_BOND_SEQ_2_3(10'b0000000000), .CHAN_BOND_SEQ_2_4(10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1), .CLK_CORRECT_USE("TRUE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(15), .CLK_COR_MIN_LAT(12), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(0), .CLK_COR_SEQ_1_1(10'b0110111100), .CLK_COR_SEQ_1_2(10'b0001010000), .CLK_COR_SEQ_1_3(10'b0000000000), .CLK_COR_SEQ_1_4(10'b0000000000), .CLK_COR_SEQ_1_ENABLE(4'b1111), .CLK_COR_SEQ_2_1(10'b0110111100), .CLK_COR_SEQ_2_2(10'b0010110101), .CLK_COR_SEQ_2_3(10'b0000000000), .CLK_COR_SEQ_2_4(10'b0000000000), .CLK_COR_SEQ_2_ENABLE(4'b1111), .CLK_COR_SEQ_2_USE("TRUE"), .CLK_COR_SEQ_LEN(2), .CPLL_CFG0(16'h67F8), .CPLL_CFG1(16'hA4AC), .CPLL_CFG2(16'h0007), .CPLL_CFG3(6'h00), .CPLL_FBDIV(5), .CPLL_FBDIV_45(4), .CPLL_INIT_CFG0(16'h02B2), .CPLL_INIT_CFG1(8'h00), .CPLL_LOCK_CFG(16'h01E8), .CPLL_REFCLK_DIV(1), .DDI_CTRL(2'b00), .DDI_REALIGN_WAIT(15), .DEC_MCOMMA_DETECT("TRUE"), .DEC_PCOMMA_DETECT("TRUE"), .DEC_VALID_COMMA_ONLY("FALSE"), .DFE_D_X_REL_POS(1'b0), .DFE_VCM_COMP_EN(1'b0), .DMONITOR_CFG0(10'h000), .DMONITOR_CFG1(8'h00), .ES_CLK_PHASE_SEL(1'b0), .ES_CONTROL(6'b000000), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("FALSE"), .ES_HORZ_OFFSET(12'h000), .ES_PMA_CFG(10'b0000000000), .ES_PRESCALE(5'b00000), .ES_QUALIFIER0(16'h0000), .ES_QUALIFIER1(16'h0000), .ES_QUALIFIER2(16'h0000), .ES_QUALIFIER3(16'h0000), .ES_QUALIFIER4(16'h0000), .ES_QUAL_MASK0(16'h0000), .ES_QUAL_MASK1(16'h0000), .ES_QUAL_MASK2(16'h0000), .ES_QUAL_MASK3(16'h0000), .ES_QUAL_MASK4(16'h0000), .ES_SDATA_MASK0(16'h0000), .ES_SDATA_MASK1(16'h0000), .ES_SDATA_MASK2(16'h0000), .ES_SDATA_MASK3(16'h0000), .ES_SDATA_MASK4(16'h0000), .EVODD_PHI_CFG(11'b00000000000), .EYE_SCAN_SWAP_EN(1'b0), .FTS_DESKEW_SEQ_ENABLE(4'b1111), .FTS_LANE_DESKEW_CFG(4'b1111), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(5'b00000), .GM_BIAS_SELECT(1'b0), .LOCAL_MASTER(1'b1), .OOBDIVCTL(2'b00), .OOB_PWRUP(1'b0), .PCI3_AUTO_REALIGN("OVR_1K_BLK"), .PCI3_PIPE_RX_ELECIDLE(1'b0), .PCI3_RX_ASYNC_EBUF_BYPASS(2'b00), .PCI3_RX_ELECIDLE_EI2_ENABLE(1'b0), .PCI3_RX_ELECIDLE_H2L_COUNT(6'b000000), .PCI3_RX_ELECIDLE_H2L_DISABLE(3'b000), .PCI3_RX_ELECIDLE_HI_COUNT(6'b000000), .PCI3_RX_ELECIDLE_LP4_DISABLE(1'b0), .PCI3_RX_FIFO_DISABLE(1'b0), .PCIE_BUFG_DIV_CTRL(16'h1000), .PCIE_RXPCS_CFG_GEN3(16'h02A4), .PCIE_RXPMA_CFG(16'h000A), .PCIE_TXPCS_CFG_GEN3(16'h2CA4), .PCIE_TXPMA_CFG(16'h000A), .PCS_PCIE_EN("FALSE"), .PCS_RSVD0(16'b0000000000000000), .PCS_RSVD1(3'b000), .PD_TRANS_TIME_FROM_P2(12'h03C), .PD_TRANS_TIME_NONE_P2(8'h19), .PD_TRANS_TIME_TO_P2(8'h64), .PLL_SEL_MODE_GEN12(2'h0), .PLL_SEL_MODE_GEN3(2'h3), .PMA_RSV1(16'hF000), .PROCESS_PAR(3'b010), .RATE_SW_USE_DRP(1'b1), .RESET_POWERSAVE_DISABLE(1'b0), .RXBUFRESET_TIME(5'b00011), .RXBUF_ADDR_MODE("FULL"), .RXBUF_EIDLE_HI_CNT(4'b1000), .RXBUF_EIDLE_LO_CNT(4'b0000), .RXBUF_EN("TRUE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(0), .RXBUF_THRESH_OVRD("FALSE"), .RXBUF_THRESH_UNDFLW(0), .RXCDRFREQRESET_TIME(5'b00001), .RXCDRPHRESET_TIME(5'b00001), .RXCDR_CFG0(16'h0000), .RXCDR_CFG0_GEN3(16'h0000), .RXCDR_CFG1(16'h0000), .RXCDR_CFG1_GEN3(16'h0000), .RXCDR_CFG2(16'h0746), .RXCDR_CFG2_GEN3(16'h07E6), .RXCDR_CFG3(16'h0000), .RXCDR_CFG3_GEN3(16'h0000), .RXCDR_CFG4(16'h0000), .RXCDR_CFG4_GEN3(16'h0000), .RXCDR_CFG5(16'h0000), .RXCDR_CFG5_GEN3(16'h0000), .RXCDR_FR_RESET_ON_EIDLE(1'b0), .RXCDR_HOLD_DURING_EIDLE(1'b0), .RXCDR_LOCK_CFG0(16'h4480), .RXCDR_LOCK_CFG1(16'h5FFF), .RXCDR_LOCK_CFG2(16'h77C3), .RXCDR_PH_RESET_ON_EIDLE(1'b0), .RXCFOK_CFG0(16'h4000), .RXCFOK_CFG1(16'h0065), .RXCFOK_CFG2(16'h002E), .RXDFELPMRESET_TIME(7'b0001111), .RXDFELPM_KL_CFG0(16'h0000), .RXDFELPM_KL_CFG1(16'h0032), .RXDFELPM_KL_CFG2(16'h0000), .RXDFE_CFG0(16'h0A00), .RXDFE_CFG1(16'h0000), .RXDFE_GC_CFG0(16'h0000), .RXDFE_GC_CFG1(16'h7870), .RXDFE_GC_CFG2(16'h0000), .RXDFE_H2_CFG0(16'h0000), .RXDFE_H2_CFG1(16'h0000), .RXDFE_H3_CFG0(16'h4000), .RXDFE_H3_CFG1(16'h0000), .RXDFE_H4_CFG0(16'h2000), .RXDFE_H4_CFG1(16'h0003), .RXDFE_H5_CFG0(16'h2000), .RXDFE_H5_CFG1(16'h0003), .RXDFE_H6_CFG0(16'h2000), .RXDFE_H6_CFG1(16'h0000), .RXDFE_H7_CFG0(16'h2000), .RXDFE_H7_CFG1(16'h0000), .RXDFE_H8_CFG0(16'h2000), .RXDFE_H8_CFG1(16'h0000), .RXDFE_H9_CFG0(16'h2000), .RXDFE_H9_CFG1(16'h0000), .RXDFE_HA_CFG0(16'h2000), .RXDFE_HA_CFG1(16'h0000), .RXDFE_HB_CFG0(16'h2000), .RXDFE_HB_CFG1(16'h0000), .RXDFE_HC_CFG0(16'h0000), .RXDFE_HC_CFG1(16'h0000), .RXDFE_HD_CFG0(16'h0000), .RXDFE_HD_CFG1(16'h0000), .RXDFE_HE_CFG0(16'h0000), .RXDFE_HE_CFG1(16'h0000), .RXDFE_HF_CFG0(16'h0000), .RXDFE_HF_CFG1(16'h0000), .RXDFE_OS_CFG0(16'h8000), .RXDFE_OS_CFG1(16'h0000), .RXDFE_UT_CFG0(16'h8000), .RXDFE_UT_CFG1(16'h0003), .RXDFE_VP_CFG0(16'hAA00), .RXDFE_VP_CFG1(16'h0033), .RXDLY_CFG(16'h001F), .RXDLY_LCFG(16'h0030), .RXELECIDLE_CFG("Sigcfg_4"), .RXGBOX_FIFO_INIT_RD_ADDR(4), .RXGEARBOX_EN("FALSE"), .RXISCANRESET_TIME(5'b00001), .RXLPM_CFG(16'h0000), .RXLPM_GC_CFG(16'h1000), .RXLPM_KH_CFG0(16'h0000), .RXLPM_KH_CFG1(16'h0002), .RXLPM_OS_CFG0(16'h8000), .RXLPM_OS_CFG1(16'h0002), .RXOOB_CFG(9'b000000110), .RXOOB_CLK_CFG("PMA"), .RXOSCALRESET_TIME(5'b00011), .RXOUT_DIV(4), .RXPCSRESET_TIME(5'b00011), .RXPHBEACON_CFG(16'h0000), .RXPHDLY_CFG(16'h2020), .RXPHSAMP_CFG(16'h2100), .RXPHSLIP_CFG(16'h6622), .RXPH_MONITOR_SEL(5'b00000), .RXPI_CFG0(2'b01), .RXPI_CFG1(2'b01), .RXPI_CFG2(2'b01), .RXPI_CFG3(2'b01), .RXPI_CFG4(1'b1), .RXPI_CFG5(1'b1), .RXPI_CFG6(3'b011), .RXPI_LPM(1'b0), .RXPI_VREFSEL(1'b0), .RXPMACLK_SEL("DATA"), .RXPMARESET_TIME(5'b00011), .RXPRBS_ERR_LOOPBACK(1'b0), .RXPRBS_LINKACQ_CNT(15), .RXSLIDE_AUTO_WAIT(7), .RXSLIDE_MODE("OFF"), .RXSYNC_MULTILANE(1'b0), .RXSYNC_OVRD(1'b0), .RXSYNC_SKIP_DA(1'b0), .RX_AFE_CM_EN(1'b0), .RX_BIAS_CFG0(16'h0AB4), .RX_BUFFER_CFG(6'b000000), .RX_CAPFF_SARC_ENB(1'b0), .RX_CLK25_DIV(5), .RX_CLKMUX_EN(1'b1), .RX_CLK_SLIP_OVRD(5'b00000), .RX_CM_BUF_CFG(4'b1010), .RX_CM_BUF_PD(1'b0), .RX_CM_SEL(2'b11), .RX_CM_TRIM(4'b1010), .RX_CTLE3_LPF(8'b00000001), .RX_DATA_WIDTH(20), .RX_DDI_SEL(6'b000000), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DFELPM_CFG0(4'b0110), .RX_DFELPM_CFG1(1'b1), .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1), .RX_DFE_AGC_CFG0(2'b10), .RX_DFE_AGC_CFG1(3'b000), .RX_DFE_KL_LPM_KH_CFG0(2'b01), .RX_DFE_KL_LPM_KH_CFG1(3'b000), .RX_DFE_KL_LPM_KL_CFG0(2'b01), .RX_DFE_KL_LPM_KL_CFG1(3'b000), .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0), .RX_DISPERR_SEQ_MATCH("TRUE"), .RX_DIVRESET_TIME(5'b00001), .RX_EN_HI_LR(1'b0), .RX_EYESCAN_VS_CODE(7'b0000000), .RX_EYESCAN_VS_NEG_DIR(1'b0), .RX_EYESCAN_VS_RANGE(2'b00), .RX_EYESCAN_VS_UT_SIGN(1'b0), .RX_FABINT_USRCLK_FLOP(1'b0), .RX_INT_DATAWIDTH(0), .RX_PMA_POWER_SAVE(1'b0), .RX_PROGDIV_CFG(0.000000), .RX_SAMPLE_PERIOD(3'b111), .RX_SIG_VALID_DLY(11), .RX_SUM_DFETAPREP_EN(1'b0), .RX_SUM_IREF_TUNE(4'b1100), .RX_SUM_RES_CTRL(2'b11), .RX_SUM_VCMTUNE(4'b0000), .RX_SUM_VCM_OVWR(1'b0), .RX_SUM_VREF_TUNE(3'b000), .RX_TUNE_AFE_OS(2'b10), .RX_WIDEMODE_CDR(1'b0), .RX_XCLK_SEL("RXDES"), .SAS_MAX_COM(64), .SAS_MIN_COM(36), .SATA_BURST_SEQ_LEN(4'b1110), .SATA_BURST_VAL(3'b100), .SATA_CPLL_CFG("VCO_3000MHZ"), .SATA_EIDLE_VAL(3'b100), .SATA_MAX_BURST(8), .SATA_MAX_INIT(21), .SATA_MAX_WAKE(7), .SATA_MIN_BURST(4), .SATA_MIN_INIT(12), .SATA_MIN_WAKE(4), .SHOW_REALIGN_COMMA("TRUE"), .SIM_MODE("FAST"), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL(1'b0), .SIM_VERSION(2), .TAPDLY_SET_TX(2'h0), .TEMPERATUR_PAR(4'b0010), .TERM_RCAL_CFG(15'b100001000010000), .TERM_RCAL_OVRD(3'b000), .TRANS_TIME_RATE(8'h0E), .TST_RSV0(8'h00), .TST_RSV1(8'h00), .TXBUF_EN("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(16'h0009), .TXDLY_LCFG(16'h0050), .TXDRVBIAS_N(4'b1010), .TXDRVBIAS_P(4'b1010), .TXFIFO_ADDR_CFG("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR(4), .TXGEARBOX_EN("FALSE"), .TXOUT_DIV(4), .TXPCSRESET_TIME(5'b00011), .TXPHDLY_CFG0(16'h2020), .TXPHDLY_CFG1(16'h0075), .TXPH_CFG(16'h0980), .TXPH_MONITOR_SEL(5'b00000), .TXPI_CFG0(2'b01), .TXPI_CFG1(2'b01), .TXPI_CFG2(2'b01), .TXPI_CFG3(1'b1), .TXPI_CFG4(1'b1), .TXPI_CFG5(3'b011), .TXPI_GRAY_SEL(1'b0), .TXPI_INVSTROBE_SEL(1'b1), .TXPI_LPM(1'b0), .TXPI_PPMCLK_SEL("TXUSRCLK2"), .TXPI_PPM_CFG(8'b00000000), .TXPI_SYNFREQ_PPM(3'b001), .TXPI_VREFSEL(1'b0), .TXPMARESET_TIME(5'b00011), .TXSYNC_MULTILANE(1'b0), .TXSYNC_OVRD(1'b0), .TXSYNC_SKIP_DA(1'b0), .TX_CLK25_DIV(5), .TX_CLKMUX_EN(1'b1), .TX_DATA_WIDTH(20), .TX_DCD_CFG(6'b000010), .TX_DCD_EN(1'b0), .TX_DEEMPH0(6'b000000), .TX_DEEMPH1(6'b000000), .TX_DIVRESET_TIME(5'b00001), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'b100), .TX_EIDLE_DEASSERT_DELAY(3'b011), .TX_EML_PHI_TUNE(1'b0), .TX_FABINT_USRCLK_FLOP(1'b0), .TX_IDLE_DATA_ZERO(1'b0), .TX_INT_DATAWIDTH(0), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'b0), .TX_MARGIN_FULL_0(7'b1001111), .TX_MARGIN_FULL_1(7'b1001110), .TX_MARGIN_FULL_2(7'b1001100), .TX_MARGIN_FULL_3(7'b1001010), .TX_MARGIN_FULL_4(7'b1001000), .TX_MARGIN_LOW_0(7'b1000110), .TX_MARGIN_LOW_1(7'b1000101), .TX_MARGIN_LOW_2(7'b1000011), .TX_MARGIN_LOW_3(7'b1000010), .TX_MARGIN_LOW_4(7'b1000000), .TX_MODE_SEL(3'b000), .TX_PMADATA_OPT(1'b0), .TX_PMA_POWER_SAVE(1'b0), .TX_PROGCLK_SEL("CPLL"), .TX_PROGDIV_CFG(20.000000), .TX_QPI_STATUS_EN(1'b0), .TX_RXDETECT_CFG(14'h0032), .TX_RXDETECT_REF(3'b100), .TX_SAMPLE_PERIOD(3'b111), .TX_SARC_LPBK_ENB(1'b0), .TX_XCLK_SEL("TXOUT"), .USE_PCS_CLK_PHASE_SEL(1'b0), .WB_MODE(2'b00)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (.BUFGTCE({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 }), .BUFGTCEMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 }), .BUFGTDIV({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 }), .BUFGTRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 }), .BUFGTRSTMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 }), .CFGRESET(1'b0), .CLKRSVD0(1'b0), .CLKRSVD1(1'b0), .CPLLFBCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ), .CPLLLOCK(cplllock_out), .CPLLLOCKDETCLK(1'b0), .CPLLLOCKEN(1'b1), .CPLLPD(\gen_gtwizard_gthe3.cpllpd_ch_int ), .CPLLREFCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ), .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), .CPLLRESET(1'b0), .DMONFIFORESET(1'b0), .DMONITORCLK(1'b0), .DMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 }), .DRPADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPCLK(drpclk_in), .DRPDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPDO({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225 }), .DRPEN(1'b0), .DRPRDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3 ), .DRPWE(1'b0), .EVODDPHICALDONE(1'b0), .EVODDPHICALSTART(1'b0), .EVODDPHIDRDEN(1'b0), .EVODDPHIDWREN(1'b0), .EVODDPHIXRDEN(1'b0), .EVODDPHIXWREN(1'b0), .EYESCANDATAERROR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ), .EYESCANMODE(1'b0), .EYESCANRESET(1'b0), .EYESCANTRIGGER(1'b0), .GTGREFCLK(1'b0), .GTHRXN(gthrxn_in), .GTHRXP(gthrxp_in), .GTHTXN(gthtxn_out), .GTHTXP(gthtxp_out), .GTNORTHREFCLK0(1'b0), .GTNORTHREFCLK1(1'b0), .GTPOWERGOOD(gtpowergood_out), .GTREFCLK0(gtrefclk0_in), .GTREFCLK1(1'b0), .GTREFCLKMONITOR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ), .GTRESETSEL(1'b0), .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .GTRXRESET(\gen_gtwizard_gthe3.gtrxreset_int ), .GTSOUTHREFCLK0(1'b0), .GTSOUTHREFCLK1(1'b0), .GTTXRESET(\gen_gtwizard_gthe3.gttxreset_int ), .LOOPBACK({1'b0,1'b0,1'b0}), .LPBKRXTXSEREN(1'b0), .LPBKTXRXSEREN(1'b0), .PCIEEQRXEQADAPTDONE(1'b0), .PCIERATEGEN3(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ), .PCIERATEIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ), .PCIERATEQPLLPD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 }), .PCIERATEQPLLRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 }), .PCIERSTIDLE(1'b0), .PCIERSTTXSYNCSTART(1'b0), .PCIESYNCTXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ), .PCIEUSERGEN3RDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ), .PCIEUSERPHYSTATUSRST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ), .PCIEUSERRATEDONE(1'b0), .PCIEUSERRATESTART(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ), .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDOUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 }), .PHYSTATUS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ), .PINRSRVDAS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 }), .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .QPLL0CLK(1'b0), .QPLL0REFCLK(1'b0), .QPLL1CLK(1'b0), .QPLL1REFCLK(1'b0), .RESETEXCEPTION(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ), .RESETOVRD(1'b0), .RSTCLKENTX(1'b0), .RX8B10BEN(1'b1), .RXBUFRESET(1'b0), .RXBUFSTATUS({rxbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 }), .RXBYTEISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ), .RXBYTEREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ), .RXCDRFREQRESET(1'b0), .RXCDRHOLD(1'b0), .RXCDRLOCK(rxcdrlock_out), .RXCDROVRDEN(1'b0), .RXCDRPHDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ), .RXCDRRESET(1'b0), .RXCDRRESETRSV(1'b0), .RXCHANBONDSEQ(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ), .RXCHANISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ), .RXCHANREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ), .RXCHBONDEN(1'b0), .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), .RXCHBONDMASTER(1'b0), .RXCHBONDO({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 }), .RXCHBONDSLAVE(1'b0), .RXCLKCORCNT(rxclkcorcnt_out), .RXCOMINITDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ), .RXCOMMADET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ), .RXCOMMADETEN(1'b1), .RXCOMSASDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ), .RXCOMWAKEDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ), .RXCTRL0({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ,rxctrl0_out}), .RXCTRL1({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ,rxctrl1_out}), .RXCTRL2({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ,rxctrl2_out}), .RXCTRL3({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ,rxctrl3_out}), .RXDATA({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193 ,gtwiz_userdata_rx_out}), .RXDATAEXTENDRSVD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 }), .RXDATAVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282 }), .RXDFEAGCCTRL({1'b0,1'b1}), .RXDFEAGCHOLD(1'b0), .RXDFEAGCOVRDEN(1'b0), .RXDFELFHOLD(1'b0), .RXDFELFOVRDEN(1'b0), .RXDFELPMRESET(1'b0), .RXDFETAP10HOLD(1'b0), .RXDFETAP10OVRDEN(1'b0), .RXDFETAP11HOLD(1'b0), .RXDFETAP11OVRDEN(1'b0), .RXDFETAP12HOLD(1'b0), .RXDFETAP12OVRDEN(1'b0), .RXDFETAP13HOLD(1'b0), .RXDFETAP13OVRDEN(1'b0), .RXDFETAP14HOLD(1'b0), .RXDFETAP14OVRDEN(1'b0), .RXDFETAP15HOLD(1'b0), .RXDFETAP15OVRDEN(1'b0), .RXDFETAP2HOLD(1'b0), .RXDFETAP2OVRDEN(1'b0), .RXDFETAP3HOLD(1'b0), .RXDFETAP3OVRDEN(1'b0), .RXDFETAP4HOLD(1'b0), .RXDFETAP4OVRDEN(1'b0), .RXDFETAP5HOLD(1'b0), .RXDFETAP5OVRDEN(1'b0), .RXDFETAP6HOLD(1'b0), .RXDFETAP6OVRDEN(1'b0), .RXDFETAP7HOLD(1'b0), .RXDFETAP7OVRDEN(1'b0), .RXDFETAP8HOLD(1'b0), .RXDFETAP8OVRDEN(1'b0), .RXDFETAP9HOLD(1'b0), .RXDFETAP9OVRDEN(1'b0), .RXDFEUTHOLD(1'b0), .RXDFEUTOVRDEN(1'b0), .RXDFEVPHOLD(1'b0), .RXDFEVPOVRDEN(1'b0), .RXDFEVSEN(1'b0), .RXDFEXYDEN(1'b1), .RXDLYBYPASS(1'b1), .RXDLYEN(1'b0), .RXDLYOVRDEN(1'b0), .RXDLYSRESET(1'b0), .RXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ), .RXELECIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ), .RXELECIDLEMODE({1'b1,1'b1}), .RXGEARBOXSLIP(1'b0), .RXHEADER({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317 }), .RXHEADERVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284 }), .RXLATCLK(1'b0), .RXLPMEN(1'b1), .RXLPMGCHOLD(1'b0), .RXLPMGCOVRDEN(1'b0), .RXLPMHFHOLD(1'b0), .RXLPMHFOVRDEN(1'b0), .RXLPMLFHOLD(1'b0), .RXLPMLFKLOVRDEN(1'b0), .RXLPMOSHOLD(1'b0), .RXLPMOSOVRDEN(1'b0), .RXMCOMMAALIGNEN(rxmcommaalignen_in), .RXMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 }), .RXMONITORSEL({1'b0,1'b0}), .RXOOBRESET(1'b0), .RXOSCALRESET(1'b0), .RXOSHOLD(1'b0), .RXOSINTCFG({1'b1,1'b1,1'b0,1'b1}), .RXOSINTDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ), .RXOSINTEN(1'b1), .RXOSINTHOLD(1'b0), .RXOSINTOVRDEN(1'b0), .RXOSINTSTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ), .RXOSINTSTROBE(1'b0), .RXOSINTSTROBEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ), .RXOSINTSTROBESTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ), .RXOSINTTESTOVRDEN(1'b0), .RXOSOVRDEN(1'b0), .RXOUTCLK(rxoutclk_out), .RXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ), .RXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ), .RXOUTCLKSEL({1'b0,1'b1,1'b0}), .RXPCOMMAALIGNEN(rxmcommaalignen_in), .RXPCSRESET(1'b0), .RXPD({rxpd_in,rxpd_in}), .RXPHALIGN(1'b0), .RXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ), .RXPHALIGNEN(1'b0), .RXPHALIGNERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ), .RXPHDLYPD(1'b1), .RXPHDLYRESET(1'b0), .RXPHOVRDEN(1'b0), .RXPLLCLKSEL({1'b0,1'b0}), .RXPMARESET(1'b0), .RXPMARESETDONE(rxpmaresetdone_out), .RXPOLARITY(1'b0), .RXPRBSCNTRESET(1'b0), .RXPRBSERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ), .RXPRBSLOCKED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ), .RXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .RXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ), .RXPROGDIVRESET(\gen_gtwizard_gthe3.rxprogdivreset_int ), .RXQPIEN(1'b0), .RXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ), .RXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ), .RXRATE({1'b0,1'b0,1'b0}), .RXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ), .RXRATEMODE(1'b0), .RXRECCLKOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ), .RXRESETDONE(rxresetdone_out), .RXSLIDE(1'b0), .RXSLIDERDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ), .RXSLIPDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ), .RXSLIPOUTCLK(1'b0), .RXSLIPOUTCLKRDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ), .RXSLIPPMA(1'b0), .RXSLIPPMARDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ), .RXSTARTOFSEQ({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 }), .RXSTATUS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 }), .RXSYNCALLIN(1'b0), .RXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ), .RXSYNCIN(1'b0), .RXSYNCMODE(1'b0), .RXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ), .RXSYSCLKSEL({1'b0,1'b0}), .RXUSERRDY(\gen_gtwizard_gthe3.rxuserrdy_int ), .RXUSRCLK(rxusrclk_in), .RXUSRCLK2(rxusrclk_in), .RXVALID(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ), .SIGVALIDCLK(1'b0), .TSTIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BEN(1'b1), .TXBUFDIFFCTRL({1'b0,1'b0,1'b0}), .TXBUFSTATUS({txbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 }), .TXCOMFINISH(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ), .TXCOMINIT(1'b0), .TXCOMSAS(1'b0), .TXCOMWAKE(1'b0), .TXCTRL0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl0_in}), .TXCTRL1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl1_in}), .TXCTRL2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl2_in}), .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gtwiz_userdata_tx_in}), .TXDATAEXTENDRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXDEEMPH(1'b0), .TXDETECTRX(1'b0), .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}), .TXDIFFPD(1'b0), .TXDLYBYPASS(1'b1), .TXDLYEN(1'b0), .TXDLYHOLD(1'b0), .TXDLYOVRDEN(1'b0), .TXDLYSRESET(1'b0), .TXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ), .TXDLYUPDOWN(1'b0), .TXELECIDLE(txelecidle_in), .TXHEADER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXINHIBIT(1'b0), .TXLATCLK(1'b0), .TXMAINCURSOR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXMARGIN({1'b0,1'b0,1'b0}), .TXOUTCLK(txoutclk_out), .TXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ), .TXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ), .TXOUTCLKSEL({1'b1,1'b0,1'b1}), .TXPCSRESET(1'b0), .TXPD({txelecidle_in,txelecidle_in}), .TXPDELECIDLEMODE(1'b0), .TXPHALIGN(1'b0), .TXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ), .TXPHALIGNEN(1'b0), .TXPHDLYPD(1'b1), .TXPHDLYRESET(1'b0), .TXPHDLYTSTCLK(1'b0), .TXPHINIT(1'b0), .TXPHINITDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ), .TXPHOVRDEN(1'b0), .TXPIPPMEN(1'b0), .TXPIPPMOVRDEN(1'b0), .TXPIPPMPD(1'b0), .TXPIPPMSEL(1'b0), .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPISOPD(1'b0), .TXPLLCLKSEL({1'b0,1'b0}), .TXPMARESET(1'b0), .TXPMARESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62 ), .TXPOLARITY(1'b0), .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPOSTCURSORINV(1'b0), .TXPRBSFORCEERR(1'b0), .TXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPRECURSORINV(1'b0), .TXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ), .TXPROGDIVRESET(\gen_gtwizard_gthe3.txprogdivreset_int ), .TXQPIBIASEN(1'b0), .TXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ), .TXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ), .TXQPISTRONGPDOWN(1'b0), .TXQPIWEAKPUP(1'b0), .TXRATE({1'b0,1'b0,1'b0}), .TXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ), .TXRATEMODE(1'b0), .TXRESETDONE(txresetdone_out), .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXSWING(1'b0), .TXSYNCALLIN(1'b0), .TXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ), .TXSYNCIN(1'b0), .TXSYNCMODE(1'b0), .TXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ), .TXSYSCLKSEL({1'b0,1'b0}), .TXUSERRDY(\gen_gtwizard_gthe3.txuserrdy_int ), .TXUSRCLK(rxusrclk_in), .TXUSRCLK2(rxusrclk_in)); LUT1 #( .INIT(2'h1)) rst_in_meta_i_1__2 (.I0(cplllock_out), .O(rst_in0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_gtwiz_reset" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset (\gen_gtwizard_gthe3.txprogdivreset_int , gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, \gen_gtwizard_gthe3.gttxreset_int , \gen_gtwizard_gthe3.txuserrdy_int , \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , \gen_gtwizard_gthe3.cpllpd_ch_int , gtpowergood_out, gtwiz_userclk_tx_active_in, cplllock_out, rxpmaresetdone_out, rxcdrlock_out, drpclk_in, gtwiz_reset_all_in, gtwiz_reset_tx_datapath_in, rst_in0, rxusrclk_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , gtwiz_reset_rx_datapath_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ); output \gen_gtwizard_gthe3.txprogdivreset_int ; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output \gen_gtwizard_gthe3.gttxreset_int ; output \gen_gtwizard_gthe3.txuserrdy_int ; output \gen_gtwizard_gthe3.rxprogdivreset_int ; output \gen_gtwizard_gthe3.gtrxreset_int ; output \gen_gtwizard_gthe3.rxuserrdy_int ; output \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]gtpowergood_out; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]cplllock_out; input [0:0]rxpmaresetdone_out; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_datapath_in; input rst_in0; input [0:0]rxusrclk_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]gtwiz_reset_rx_datapath_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \FSM_sequential_sm_reset_all[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_all[2]_i_4_n_0 ; wire \FSM_sequential_sm_reset_rx[1]_i_2_n_0 ; wire \FSM_sequential_sm_reset_rx[2]_i_6_n_0 ; wire \FSM_sequential_sm_reset_tx[2]_i_3_n_0 ; wire bit_synchronizer_gtpowergood_inst_n_0; wire bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2; wire bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2; wire bit_synchronizer_plllock_rx_inst_n_1; wire bit_synchronizer_plllock_rx_inst_n_2; wire bit_synchronizer_plllock_tx_inst_n_1; wire bit_synchronizer_plllock_tx_inst_n_2; wire bit_synchronizer_rxcdrlock_inst_n_0; wire bit_synchronizer_rxcdrlock_inst_n_1; wire bit_synchronizer_rxcdrlock_inst_n_2; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gtpowergood_out; wire gttxreset_out_i_3_n_0; wire [0:0]gtwiz_reset_all_in; wire gtwiz_reset_all_sync; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_rx_datapath_dly; wire [0:0]gtwiz_reset_rx_datapath_in; wire gtwiz_reset_rx_datapath_int_i_1_n_0; wire gtwiz_reset_rx_datapath_int_reg_n_0; wire gtwiz_reset_rx_datapath_sync; wire gtwiz_reset_rx_done_int_reg_n_0; wire [0:0]gtwiz_reset_rx_done_out; wire gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_rx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_rx_pll_and_datapath_sync; wire gtwiz_reset_tx_any_sync; wire [0:0]gtwiz_reset_tx_datapath_in; wire gtwiz_reset_tx_datapath_sync; wire gtwiz_reset_tx_done_int_reg_n_0; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_reset_tx_pll_and_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_tx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_tx_pll_and_datapath_sync; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_tx_active_in; wire p_0_in; wire [9:0]p_0_in__0; wire [9:0]p_0_in__1; wire [2:0]p_1_in; wire plllock_rx_sync; wire plllock_tx_sync; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_3; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_3; wire rst_in0; wire [0:0]rxcdrlock_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxusrclk_in; wire sel; wire [2:0]sm_reset_all; wire [2:0]sm_reset_all__0; wire sm_reset_all_timer_clr_i_1_n_0; wire sm_reset_all_timer_clr_i_2_n_0; wire sm_reset_all_timer_clr_reg_n_0; wire [2:0]sm_reset_all_timer_ctr; wire sm_reset_all_timer_ctr0_n_0; wire \sm_reset_all_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[2]_i_1_n_0 ; wire sm_reset_all_timer_sat; wire sm_reset_all_timer_sat_i_1_n_0; wire [2:0]sm_reset_rx; wire [2:0]sm_reset_rx__0; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_3_n_0; wire \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 ; wire [25:0]sm_reset_rx_cdr_to_ctr_reg; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_i_1_n_0; wire sm_reset_rx_cdr_to_sat_i_2_n_0; wire sm_reset_rx_cdr_to_sat_i_3_n_0; wire sm_reset_rx_cdr_to_sat_i_4_n_0; wire sm_reset_rx_cdr_to_sat_i_5_n_0; wire sm_reset_rx_cdr_to_sat_i_6_n_0; wire sm_reset_rx_pll_timer_clr_i_1_n_0; wire sm_reset_rx_pll_timer_clr_reg_n_0; wire \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_rx_pll_timer_ctr_reg; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_pll_timer_sat_i_1_n_0; wire sm_reset_rx_pll_timer_sat_i_2_n_0; wire sm_reset_rx_pll_timer_sat_i_3_n_0; wire sm_reset_rx_timer_clr_reg_n_0; wire [2:0]sm_reset_rx_timer_ctr; wire sm_reset_rx_timer_ctr0_n_0; wire \sm_reset_rx_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[2]_i_1_n_0 ; wire sm_reset_rx_timer_sat; wire sm_reset_rx_timer_sat_i_1_n_0; wire [2:0]sm_reset_tx; wire [2:0]sm_reset_tx__0; wire sm_reset_tx_pll_timer_clr_i_1_n_0; wire sm_reset_tx_pll_timer_clr_reg_n_0; wire \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_tx_pll_timer_ctr_reg; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_pll_timer_sat_i_1_n_0; wire sm_reset_tx_pll_timer_sat_i_2_n_0; wire sm_reset_tx_pll_timer_sat_i_3_n_0; wire sm_reset_tx_timer_clr_reg_n_0; wire [2:0]sm_reset_tx_timer_ctr; wire sm_reset_tx_timer_sat; wire sm_reset_tx_timer_sat_i_1_n_0; wire txuserrdy_out_i_3_n_0; wire [7:1]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED ; LUT6 #( .INIT(64'h00FFF70000FFFFFF)) \FSM_sequential_sm_reset_all[0]_i_1 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(sm_reset_all_timer_clr_reg_n_0), .I3(sm_reset_all[2]), .I4(sm_reset_all[1]), .I5(sm_reset_all[0]), .O(sm_reset_all__0[0])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'h34)) \FSM_sequential_sm_reset_all[1]_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[1]), .I2(sm_reset_all[0]), .O(sm_reset_all__0[1])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'h4A)) \FSM_sequential_sm_reset_all[2]_i_2 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .O(sm_reset_all__0[2])); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_sm_reset_all[2]_i_3 (.I0(sm_reset_all_timer_sat), .I1(gtwiz_reset_rx_done_int_reg_n_0), .I2(sm_reset_all_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h40)) \FSM_sequential_sm_reset_all[2]_i_4 (.I0(sm_reset_all_timer_clr_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(gtwiz_reset_tx_done_int_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_4_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[0]), .Q(sm_reset_all[0]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[1]), .Q(sm_reset_all[1]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[2]), .Q(sm_reset_all[2]), .R(gtwiz_reset_all_sync)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_sm_reset_rx[1]_i_2 (.I0(sm_reset_rx_timer_sat), .I1(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 )); LUT6 #( .INIT(64'hDDFD8888DDDD8888)) \FSM_sequential_sm_reset_rx[2]_i_2 (.I0(sm_reset_rx[1]), .I1(sm_reset_rx[0]), .I2(sm_reset_rx_timer_sat), .I3(sm_reset_rx_timer_clr_reg_n_0), .I4(sm_reset_rx[2]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .O(sm_reset_rx__0[2])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h00004000)) \FSM_sequential_sm_reset_rx[2]_i_6 (.I0(sm_reset_rx[0]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(sm_reset_rx[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[2]_i_6_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[0]), .Q(sm_reset_rx[0]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[1]), .Q(sm_reset_rx[1]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[2]), .Q(sm_reset_rx[2]), .R(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( .INIT(8'h38)) \FSM_sequential_sm_reset_tx[2]_i_2 (.I0(sm_reset_tx[0]), .I1(sm_reset_tx[1]), .I2(sm_reset_tx[2]), .O(sm_reset_tx__0[2])); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_sm_reset_tx[2]_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .O(\FSM_sequential_sm_reset_tx[2]_i_3_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[0]), .Q(sm_reset_tx[0]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[1]), .Q(sm_reset_tx[1]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[2]), .Q(sm_reset_tx[2]), .R(gtwiz_reset_tx_any_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 bit_synchronizer_gtpowergood_inst (.E(bit_synchronizer_gtpowergood_inst_n_0), .\FSM_sequential_sm_reset_all_reg[0] (\FSM_sequential_sm_reset_all[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_all_reg[0]_0 (\FSM_sequential_sm_reset_all[2]_i_4_n_0 ), .Q(sm_reset_all), .drpclk_in(drpclk_in), .gtpowergood_out(gtpowergood_out)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .in0(gtwiz_reset_rx_datapath_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (.D(sm_reset_rx__0[1:0]), .\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[0]_0 (\FSM_sequential_sm_reset_rx[2]_i_6_n_0 ), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .in0(gtwiz_reset_rx_pll_and_datapath_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (.E(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .\FSM_sequential_sm_reset_tx_reg[0] (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_0 (bit_synchronizer_plllock_tx_inst_n_2), .\FSM_sequential_sm_reset_tx_reg[0]_1 (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .Q(sm_reset_tx[0]), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_datapath_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (.D(sm_reset_tx__0[1:0]), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_pll_and_datapath_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (.E(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .\FSM_sequential_sm_reset_rx_reg[0]_0 (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[0]_1 (bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0]_2 (sm_reset_rx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .rxpmaresetdone_out(rxpmaresetdone_out), .sm_reset_rx_pll_timer_sat(sm_reset_rx_pll_timer_sat), .sm_reset_rx_timer_clr_reg(bit_synchronizer_plllock_rx_inst_n_2), .sm_reset_rx_timer_clr_reg_0(sm_reset_rx_timer_clr_reg_n_0), .sm_reset_rx_timer_sat(sm_reset_rx_timer_sat)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (.\FSM_sequential_sm_reset_tx_reg[0] (txuserrdy_out_i_3_n_0), .\FSM_sequential_sm_reset_tx_reg[0]_0 (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_1 (sm_reset_tx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_tx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_pll_timer_sat(sm_reset_tx_pll_timer_sat), .sm_reset_tx_timer_clr_reg(sm_reset_tx_timer_clr_reg_n_0), .sm_reset_tx_timer_clr_reg_0(gttxreset_out_i_3_n_0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 bit_synchronizer_plllock_rx_inst (.\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_plllock_rx_inst_n_2), .Q(sm_reset_rx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_done_int_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_done_int_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_rx_inst_n_1), .plllock_rx_sync(plllock_rx_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 bit_synchronizer_plllock_tx_inst (.\FSM_sequential_sm_reset_tx_reg[0] (gttxreset_out_i_3_n_0), .Q(sm_reset_tx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_tx_done_int_reg(bit_synchronizer_plllock_tx_inst_n_1), .gtwiz_reset_tx_done_int_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .gtwiz_reset_tx_done_int_reg_1(sm_reset_tx_timer_clr_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_tx_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_timer_sat(sm_reset_tx_timer_sat)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 bit_synchronizer_rxcdrlock_inst (.\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .plllock_rx_sync(plllock_rx_sync), .rxcdrlock_out(rxcdrlock_out), .sm_reset_rx_cdr_to_clr(sm_reset_rx_cdr_to_clr), .sm_reset_rx_cdr_to_clr_reg(sm_reset_rx_cdr_to_clr_i_3_n_0), .sm_reset_rx_cdr_to_sat(sm_reset_rx_cdr_to_sat), .sm_reset_rx_cdr_to_sat_reg(bit_synchronizer_rxcdrlock_inst_n_2)); LUT2 #( .INIT(4'hE)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\gen_gtwizard_gthe3.cpllpd_ch_int )); FDRE #( .INIT(1'b1)) gtrxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.gtrxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT2 #( .INIT(4'h2)) gttxreset_out_i_3 (.I0(sm_reset_tx_timer_sat), .I1(sm_reset_tx_timer_clr_reg_n_0), .O(gttxreset_out_i_3_n_0)); FDRE #( .INIT(1'b1)) gttxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.gttxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'hF740)) gtwiz_reset_rx_datapath_int_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_datapath_int_reg_n_0), .O(gtwiz_reset_rx_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_rx_inst_n_1), .Q(gtwiz_reset_rx_done_int_reg_n_0), .R(gtwiz_reset_rx_any_sync)); LUT4 #( .INIT(16'hF704)) gtwiz_reset_rx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[2]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_tx_inst_n_1), .Q(gtwiz_reset_tx_done_int_reg_n_0), .R(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'hFB02)) gtwiz_reset_tx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) pllreset_rx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .R(1'b0)); FDRE #( .INIT(1'b1)) pllreset_tx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .R(1'b0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (.drpclk_in(drpclk_in), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_all_sync(gtwiz_reset_all_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 reset_synchronizer_gtwiz_reset_rx_any_inst (.\FSM_sequential_sm_reset_rx_reg[1] (reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[1]_0 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[1]_1 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .gtrxreset_out_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .plllock_rx_sync(plllock_rx_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0), .rst_in_out_reg_1(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .rxprogdivreset_out_reg(bit_synchronizer_rxcdrlock_inst_n_2)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 reset_synchronizer_gtwiz_reset_rx_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .in0(gtwiz_reset_rx_datapath_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_rx_pll_and_datapath_sync), .rst_in_meta_reg_0(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 reset_synchronizer_gtwiz_reset_tx_any_inst (.\FSM_sequential_sm_reset_tx_reg[0] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .\FSM_sequential_sm_reset_tx_reg[1] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .\FSM_sequential_sm_reset_tx_reg[1]_0 (reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gttxreset_out_reg(gttxreset_out_i_3_n_0), .gtwiz_reset_tx_any_sync(gtwiz_reset_tx_any_sync), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .plllock_tx_sync(plllock_tx_sync), .rst_in_out_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .txuserrdy_out_reg(txuserrdy_out_i_3_n_0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 reset_synchronizer_gtwiz_reset_tx_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .in0(gtwiz_reset_tx_datapath_sync)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_tx_pll_and_datapath_sync), .rst_in_meta_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_rx_done_inst (.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .rxusrclk_in(rxusrclk_in)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 reset_synchronizer_tx_done_inst (.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .rxusrclk_in(rxusrclk_in)); gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 reset_synchronizer_txprogdivreset_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .rst_in0(rst_in0)); FDRE #( .INIT(1'b1)) rxprogdivreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.rxprogdivreset_int ), .R(1'b0)); FDRE #( .INIT(1'b0)) rxuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(\gen_gtwizard_gthe3.rxuserrdy_int ), .R(1'b0)); LUT5 #( .INIT(32'hEFFA200A)) sm_reset_all_timer_clr_i_1 (.I0(sm_reset_all_timer_clr_i_2_n_0), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(sm_reset_all[0]), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_clr_i_1_n_0)); LUT6 #( .INIT(64'h0000B0003333BB33)) sm_reset_all_timer_clr_i_2 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all[2]), .I2(gtwiz_reset_tx_done_int_reg_n_0), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .I5(sm_reset_all[1]), .O(sm_reset_all_timer_clr_i_2_n_0)); FDSE #( .INIT(1'b1)) sm_reset_all_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_clr_i_1_n_0), .Q(sm_reset_all_timer_clr_reg_n_0), .S(gtwiz_reset_all_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_all_timer_ctr0 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .O(sm_reset_all_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_all_timer_ctr[0]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .O(\sm_reset_all_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT2 #( .INIT(4'h6)) \sm_reset_all_timer_ctr[1]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .O(\sm_reset_all_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h78)) \sm_reset_all_timer_ctr[2]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .I2(sm_reset_all_timer_ctr[2]), .O(\sm_reset_all_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[0]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[1]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[2]), .R(sm_reset_all_timer_clr_reg_n_0)); LUT5 #( .INIT(32'h0000FF80)) sm_reset_all_timer_sat_i_1 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_all_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_sat_i_1_n_0), .Q(sm_reset_all_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'h40)) sm_reset_rx_cdr_to_clr_i_3 (.I0(sm_reset_rx_timer_clr_reg_n_0), .I1(sm_reset_rx_timer_sat), .I2(sm_reset_rx[1]), .O(sm_reset_rx_cdr_to_clr_i_3_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_cdr_to_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx_cdr_to_clr), .S(gtwiz_reset_rx_any_sync)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \sm_reset_rx_cdr_to_ctr[0]_i_1 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .I1(sm_reset_rx_cdr_to_ctr_reg[1]), .I2(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ), .I3(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ), .I4(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ), .I5(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ), .O(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[18]), .I1(sm_reset_rx_cdr_to_ctr_reg[19]), .I2(sm_reset_rx_cdr_to_ctr_reg[17]), .I3(sm_reset_rx_cdr_to_ctr_reg[16]), .I4(sm_reset_rx_cdr_to_ctr_reg[14]), .I5(sm_reset_rx_cdr_to_ctr_reg[15]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[24]), .I1(sm_reset_rx_cdr_to_ctr_reg[25]), .I2(sm_reset_rx_cdr_to_ctr_reg[22]), .I3(sm_reset_rx_cdr_to_ctr_reg[23]), .I4(sm_reset_rx_cdr_to_ctr_reg[21]), .I5(sm_reset_rx_cdr_to_ctr_reg[20]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[12]), .I1(sm_reset_rx_cdr_to_ctr_reg[13]), .I2(sm_reset_rx_cdr_to_ctr_reg[10]), .I3(sm_reset_rx_cdr_to_ctr_reg[11]), .I4(sm_reset_rx_cdr_to_ctr_reg[9]), .I5(sm_reset_rx_cdr_to_ctr_reg[8]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \sm_reset_rx_cdr_to_ctr[0]_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[6]), .I1(sm_reset_rx_cdr_to_ctr_reg[7]), .I2(sm_reset_rx_cdr_to_ctr_reg[4]), .I3(sm_reset_rx_cdr_to_ctr_reg[5]), .I4(sm_reset_rx_cdr_to_ctr_reg[3]), .I5(sm_reset_rx_cdr_to_ctr_reg[2]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \sm_reset_rx_cdr_to_ctr[0]_i_7 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[0]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[0]_i_2 (.CI(1'b0), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}), .O({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 }), .S({sm_reset_rx_cdr_to_ctr_reg[7:1],\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[10] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[10]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[11] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[11]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[12] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[12]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[13] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[13]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[14] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[14]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[15] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[15]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[16] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[16]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[16]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[23:16])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[17] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[17]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[18] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[18]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[19] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[19]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[1]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[20] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[20]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[21] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[21]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[22] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[22]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[23] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[23]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[24] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[24]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[24]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED [7:1],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED [7:2],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 }), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,sm_reset_rx_cdr_to_ctr_reg[25:24]})); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[25] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[25]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[2]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[3]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[4]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[5]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[6]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[7]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[8]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[8]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[15:8])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[9]), .R(sm_reset_rx_cdr_to_clr)); LUT3 #( .INIT(8'h0E)) sm_reset_rx_cdr_to_sat_i_1 (.I0(sm_reset_rx_cdr_to_sat), .I1(sm_reset_rx_cdr_to_sat_i_2_n_0), .I2(sm_reset_rx_cdr_to_clr), .O(sm_reset_rx_cdr_to_sat_i_1_n_0)); LUT6 #( .INIT(64'h0000000000008000)) sm_reset_rx_cdr_to_sat_i_2 (.I0(sm_reset_rx_cdr_to_sat_i_3_n_0), .I1(sm_reset_rx_cdr_to_sat_i_4_n_0), .I2(sm_reset_rx_cdr_to_sat_i_5_n_0), .I3(sm_reset_rx_cdr_to_sat_i_6_n_0), .I4(sm_reset_rx_cdr_to_ctr_reg[0]), .I5(sm_reset_rx_cdr_to_ctr_reg[1]), .O(sm_reset_rx_cdr_to_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000100000000)) sm_reset_rx_cdr_to_sat_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[4]), .I1(sm_reset_rx_cdr_to_ctr_reg[5]), .I2(sm_reset_rx_cdr_to_ctr_reg[2]), .I3(sm_reset_rx_cdr_to_ctr_reg[3]), .I4(sm_reset_rx_cdr_to_ctr_reg[7]), .I5(sm_reset_rx_cdr_to_ctr_reg[6]), .O(sm_reset_rx_cdr_to_sat_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000010)) sm_reset_rx_cdr_to_sat_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[22]), .I1(sm_reset_rx_cdr_to_ctr_reg[23]), .I2(sm_reset_rx_cdr_to_ctr_reg[20]), .I3(sm_reset_rx_cdr_to_ctr_reg[21]), .I4(sm_reset_rx_cdr_to_ctr_reg[25]), .I5(sm_reset_rx_cdr_to_ctr_reg[24]), .O(sm_reset_rx_cdr_to_sat_i_4_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[17]), .I1(sm_reset_rx_cdr_to_ctr_reg[16]), .I2(sm_reset_rx_cdr_to_ctr_reg[15]), .I3(sm_reset_rx_cdr_to_ctr_reg[14]), .I4(sm_reset_rx_cdr_to_ctr_reg[19]), .I5(sm_reset_rx_cdr_to_ctr_reg[18]), .O(sm_reset_rx_cdr_to_sat_i_5_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[10]), .I1(sm_reset_rx_cdr_to_ctr_reg[11]), .I2(sm_reset_rx_cdr_to_ctr_reg[8]), .I3(sm_reset_rx_cdr_to_ctr_reg[9]), .I4(sm_reset_rx_cdr_to_ctr_reg[13]), .I5(sm_reset_rx_cdr_to_ctr_reg[12]), .O(sm_reset_rx_cdr_to_sat_i_6_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_cdr_to_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_cdr_to_sat_i_1_n_0), .Q(sm_reset_rx_cdr_to_sat), .R(1'b0)); LUT5 #( .INIT(32'hFFF3000B)) sm_reset_rx_pll_timer_clr_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx[0]), .I2(sm_reset_rx[1]), .I3(sm_reset_rx[2]), .I4(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_clr_i_1_n_0), .Q(sm_reset_rx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT1 #( .INIT(2'h1)) \sm_reset_rx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_rx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[2]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[3]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_rx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[1]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[2]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_rx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(p_0_in__1[5])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h9)) \sm_reset_rx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT3 #( .INIT(8'hD2)) \sm_reset_rx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[7]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_rx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[7]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[8]), .O(p_0_in__1[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_rx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .I4(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ), .O(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_rx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .I2(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .O(p_0_in__1[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[9]), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[0]), .Q(sm_reset_rx_pll_timer_ctr_reg[0]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[1]), .Q(sm_reset_rx_pll_timer_ctr_reg[1]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[2]), .Q(sm_reset_rx_pll_timer_ctr_reg[2]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[3]), .Q(sm_reset_rx_pll_timer_ctr_reg[3]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[4]), .Q(sm_reset_rx_pll_timer_ctr_reg[4]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[5]), .Q(sm_reset_rx_pll_timer_ctr_reg[5]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[6]), .Q(sm_reset_rx_pll_timer_ctr_reg[6]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[7]), .Q(sm_reset_rx_pll_timer_ctr_reg[7]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[8]), .Q(sm_reset_rx_pll_timer_ctr_reg[8]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[9]), .Q(sm_reset_rx_pll_timer_ctr_reg[9]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_rx_pll_timer_sat_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx_pll_timer_sat_i_2_n_0), .I2(sm_reset_rx_pll_timer_sat_i_3_n_0), .I3(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0040)) sm_reset_rx_pll_timer_sat_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .O(sm_reset_rx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_rx_pll_timer_sat_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(sm_reset_rx_pll_timer_ctr_reg[7]), .I2(sm_reset_rx_pll_timer_ctr_reg[5]), .I3(sm_reset_rx_pll_timer_ctr_reg[4]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .I5(sm_reset_rx_pll_timer_ctr_reg[8]), .O(sm_reset_rx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_sat_i_1_n_0), .Q(sm_reset_rx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_rx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .Q(sm_reset_rx_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_rx_timer_ctr0 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .O(sm_reset_rx_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_rx_timer_ctr[0]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .O(\sm_reset_rx_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_timer_ctr[1]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .O(\sm_reset_rx_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_timer_ctr[2]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .I2(sm_reset_rx_timer_ctr[2]), .O(\sm_reset_rx_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[0]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[1]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[2]), .R(sm_reset_rx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_rx_timer_sat_i_1 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(sm_reset_rx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_timer_sat_i_1_n_0), .Q(sm_reset_rx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'hEFEF1101)) sm_reset_tx_pll_timer_clr_i_1 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx[0]), .I3(sm_reset_tx_pll_timer_sat), .I4(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_tx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_clr_i_1_n_0), .Q(sm_reset_tx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT1 #( .INIT(2'h1)) \sm_reset_tx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_tx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[2]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_tx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[1]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[2]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_tx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h9)) \sm_reset_tx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'hD2)) \sm_reset_tx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[7]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_tx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[7]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[8]), .O(p_0_in__0[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_tx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .I4(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ), .O(sel)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_tx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .I2(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .O(p_0_in__0[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[9]), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[0]), .Q(sm_reset_tx_pll_timer_ctr_reg[0]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[1]), .Q(sm_reset_tx_pll_timer_ctr_reg[1]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[2]), .Q(sm_reset_tx_pll_timer_ctr_reg[2]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[3]), .Q(sm_reset_tx_pll_timer_ctr_reg[3]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[4]), .Q(sm_reset_tx_pll_timer_ctr_reg[4]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[5]), .Q(sm_reset_tx_pll_timer_ctr_reg[5]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[6]), .Q(sm_reset_tx_pll_timer_ctr_reg[6]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[7]), .Q(sm_reset_tx_pll_timer_ctr_reg[7]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[8]), .Q(sm_reset_tx_pll_timer_ctr_reg[8]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[9]), .Q(sm_reset_tx_pll_timer_ctr_reg[9]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_tx_pll_timer_sat_i_1 (.I0(sm_reset_tx_pll_timer_sat), .I1(sm_reset_tx_pll_timer_sat_i_2_n_0), .I2(sm_reset_tx_pll_timer_sat_i_3_n_0), .I3(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'h0040)) sm_reset_tx_pll_timer_sat_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .O(sm_reset_tx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_tx_pll_timer_sat_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(sm_reset_tx_pll_timer_ctr_reg[7]), .I2(sm_reset_tx_pll_timer_ctr_reg[5]), .I3(sm_reset_tx_pll_timer_ctr_reg[4]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .I5(sm_reset_tx_pll_timer_ctr_reg[8]), .O(sm_reset_tx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_sat_i_1_n_0), .Q(sm_reset_tx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_tx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_tx_timer_ctr0 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .O(p_0_in)); LUT1 #( .INIT(2'h1)) \sm_reset_tx_timer_ctr[0]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_timer_ctr[1]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .O(p_1_in[1])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_timer_ctr[2]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .I2(sm_reset_tx_timer_ctr[2]), .O(p_1_in[2])); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[0] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[0]), .Q(sm_reset_tx_timer_ctr[0]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[1] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[1]), .Q(sm_reset_tx_timer_ctr[1]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[2] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[2]), .Q(sm_reset_tx_timer_ctr[2]), .R(sm_reset_tx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_tx_timer_sat_i_1 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .I3(sm_reset_tx_timer_sat), .I4(sm_reset_tx_timer_clr_reg_n_0), .O(sm_reset_tx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_timer_sat_i_1_n_0), .Q(sm_reset_tx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'h0400)) txuserrdy_out_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx_timer_clr_reg_n_0), .I3(sm_reset_tx_timer_sat), .O(txuserrdy_out_i_3_n_0)); FDRE #( .INIT(1'b0)) txuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.txuserrdy_int ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer (gtwiz_reset_rx_done_out, rxusrclk_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_rx_done_out; input [0:0]rxusrclk_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_rx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1__0_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]rxusrclk_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1__0 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1__0_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_rx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 (gtwiz_reset_tx_done_out, rxusrclk_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_tx_done_out; input [0:0]rxusrclk_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_tx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]rxusrclk_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_tx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer (gtwiz_reset_all_sync, drpclk_in, gtwiz_reset_all_in); output gtwiz_reset_all_sync; input [0:0]drpclk_in; input [0:0]gtwiz_reset_all_in; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_all_in; wire gtwiz_reset_all_sync; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_all_in), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_all_in), .Q(gtwiz_reset_all_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 (gtwiz_reset_rx_any_sync, \FSM_sequential_sm_reset_rx_reg[1] , \FSM_sequential_sm_reset_rx_reg[1]_0 , \FSM_sequential_sm_reset_rx_reg[1]_1 , drpclk_in, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int , rxprogdivreset_out_reg, \gen_gtwizard_gthe3.rxprogdivreset_int , plllock_rx_sync, gtrxreset_out_reg, \gen_gtwizard_gthe3.gtrxreset_int , rst_in_out_reg_0, gtwiz_reset_rx_datapath_in, rst_in_out_reg_1); output gtwiz_reset_rx_any_sync; output \FSM_sequential_sm_reset_rx_reg[1] ; output \FSM_sequential_sm_reset_rx_reg[1]_0 ; output \FSM_sequential_sm_reset_rx_reg[1]_1 ; input [0:0]drpclk_in; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; input rxprogdivreset_out_reg; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input plllock_rx_sync; input gtrxreset_out_reg; input \gen_gtwizard_gthe3.gtrxreset_int ; input rst_in_out_reg_0; input [0:0]gtwiz_reset_rx_datapath_in; input rst_in_out_reg_1; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[1]_0 ; wire \FSM_sequential_sm_reset_rx_reg[1]_1 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire gtrxreset_out_i_2_n_0; wire gtrxreset_out_reg; wire gtwiz_reset_rx_any; wire gtwiz_reset_rx_any_sync; wire [0:0]gtwiz_reset_rx_datapath_in; wire plllock_rx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; wire rst_in_out_reg_1; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire rxprogdivreset_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gtrxreset_out_i_1 (.I0(Q[1]), .I1(gtrxreset_out_i_2_n_0), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtrxreset_out_reg), .I5(\gen_gtwizard_gthe3.gtrxreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'h1)) gtrxreset_out_i_2 (.I0(gtwiz_reset_rx_any_sync), .I1(Q[2]), .O(gtrxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_rx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_rx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\FSM_sequential_sm_reset_rx_reg[1] )); LUT3 #( .INIT(8'hFE)) rst_in_meta_i_1 (.I0(rst_in_out_reg_0), .I1(gtwiz_reset_rx_datapath_in), .I2(rst_in_out_reg_1), .O(gtwiz_reset_rx_any)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_any), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_rx_any), .Q(gtwiz_reset_rx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hFFFBFFFF00120012)) rxprogdivreset_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_rx_any_sync), .I4(rxprogdivreset_out_reg), .I5(\gen_gtwizard_gthe3.rxprogdivreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_0 )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 (in0, drpclk_in, gtwiz_reset_rx_datapath_in, rst_in_out_reg_0); output in0; input [0:0]drpclk_in; input [0:0]gtwiz_reset_rx_datapath_in; input rst_in_out_reg_0; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire in0; wire rst_in0_0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__0 (.I0(gtwiz_reset_rx_datapath_in), .I1(rst_in_out_reg_0), .O(rst_in0_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 (in0, drpclk_in, rst_in_meta_reg_0); output in0; input [0:0]drpclk_in; input rst_in_meta_reg_0; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_meta_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_meta_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_meta_reg_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 (gtwiz_reset_tx_any_sync, \FSM_sequential_sm_reset_tx_reg[1] , \FSM_sequential_sm_reset_tx_reg[1]_0 , \FSM_sequential_sm_reset_tx_reg[0] , drpclk_in, gtwiz_reset_tx_datapath_in, rst_in_out_reg_0, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int , plllock_tx_sync, gttxreset_out_reg, \gen_gtwizard_gthe3.gttxreset_int , txuserrdy_out_reg, gtwiz_reset_userclk_tx_active_sync, \gen_gtwizard_gthe3.txuserrdy_int ); output gtwiz_reset_tx_any_sync; output \FSM_sequential_sm_reset_tx_reg[1] ; output \FSM_sequential_sm_reset_tx_reg[1]_0 ; output \FSM_sequential_sm_reset_tx_reg[0] ; input [0:0]drpclk_in; input [0:0]gtwiz_reset_tx_datapath_in; input rst_in_out_reg_0; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; input plllock_tx_sync; input gttxreset_out_reg; input \gen_gtwizard_gthe3.gttxreset_int ; input txuserrdy_out_reg; input gtwiz_reset_userclk_tx_active_sync; input \gen_gtwizard_gthe3.txuserrdy_int ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[1] ; wire \FSM_sequential_sm_reset_tx_reg[1]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire gttxreset_out_i_2_n_0; wire gttxreset_out_reg; wire gtwiz_reset_tx_any; wire gtwiz_reset_tx_any_sync; wire [0:0]gtwiz_reset_tx_datapath_in; wire gtwiz_reset_userclk_tx_active_sync; wire plllock_tx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire txuserrdy_out_i_2_n_0; wire txuserrdy_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gttxreset_out_i_1 (.I0(Q[1]), .I1(gttxreset_out_i_2_n_0), .I2(plllock_tx_sync), .I3(Q[0]), .I4(gttxreset_out_reg), .I5(\gen_gtwizard_gthe3.gttxreset_int ), .O(\FSM_sequential_sm_reset_tx_reg[1]_0 )); LUT2 #( .INIT(4'h1)) gttxreset_out_i_2 (.I0(gtwiz_reset_tx_any_sync), .I1(Q[2]), .O(gttxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_tx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_tx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .O(\FSM_sequential_sm_reset_tx_reg[1] )); LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__1 (.I0(gtwiz_reset_tx_datapath_in), .I1(rst_in_out_reg_0), .O(gtwiz_reset_tx_any)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_tx_any), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_tx_any), .Q(gtwiz_reset_tx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hDD55DD5588008C00)) txuserrdy_out_i_1 (.I0(txuserrdy_out_i_2_n_0), .I1(txuserrdy_out_reg), .I2(Q[0]), .I3(gtwiz_reset_userclk_tx_active_sync), .I4(gtwiz_reset_tx_any_sync), .I5(\gen_gtwizard_gthe3.txuserrdy_int ), .O(\FSM_sequential_sm_reset_tx_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0110)) txuserrdy_out_i_2 (.I0(Q[2]), .I1(gtwiz_reset_tx_any_sync), .I2(Q[1]), .I3(Q[0]), .O(txuserrdy_out_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 (in0, drpclk_in, gtwiz_reset_tx_datapath_in); output in0; input [0:0]drpclk_in; input [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_tx_datapath_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_tx_datapath_in), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 (in0, drpclk_in, rst_in_meta_reg_0); output in0; input [0:0]drpclk_in; input rst_in_meta_reg_0; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_meta_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_meta_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_meta_reg_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module gig_ethernet_pcs_pma_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 (\gen_gtwizard_gthe3.txprogdivreset_int , drpclk_in, rst_in0); output \gen_gtwizard_gthe3.txprogdivreset_int ; input [0:0]drpclk_in; input rst_in0; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire rst_in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0), .Q(\gen_gtwizard_gthe3.txprogdivreset_int )); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0), .Q(rst_in_sync3)); endmodule `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) `pragma protect key_block WrLPAmevOeee/HiaIGgPKffTsGjPw79Mvhb1LvIE3IQs20r9+LQOoFGpfUylEN1UW2O2frWdS04S 72SDyqvJ5A== `pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block C57Uh05FvDEJaXQ4H8lC5UbDO/jg7m+45NOtD4cM+eEYb3jcEPXS/mMv8e0ZOAe/mg7S5VXmkWr7 VEk0dR5AU4kxRj4XjFKlvVLZkhNdXiS3LQk/EziN2GSKJjjDKBkNHEfhYIGF1ZkOpC43O4yuYrxk CIWTpVXywZi8wCaExe8= `pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block lnTbrZfs2R120YpSyobtyskobEgxZSAlXnUQXw1gJpszgY/hqhzTy3v0ru7GipkY6qPoEcZwNnVX iD7GpCBRhqKix8pqMugQ1kvNhkn1r2YRhmA6XHA0ry90LNrf+n9uqlf476IBJTLTd3uu4ZngV06I QvBbiq8tjaP25el1krCHHl5rfNirhuwiDDOMI2E116k0hSU8spCYQ0rZ4zCPJqOKT+fAtz1I+L2I 7khRnsRzR+YQ1RpBojQPxfqkEiv3A1XZQAUu2jSrW9PWm/3IpjLtJkZmcI7pciYLWv6MsTfFOhxV 6plNRVK33O7OxS/zjPhtulkG1IT36qOdQJ/Taw== `pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block NYPBrFjA8rEwnRj94/W5n/OoJJ3VW9KspqmB8LGhkba5zTpRXGx5cP5VSAONdwboNqGe1cRhXJpS mEHlKqR0glqNIxnLFETHEfkwnm/8dMDrYX6GKlEZVWbhg4uvlJIq7o63AhclqIqjyA+EUIWFI9av c/Cg2WZkvMEk5Voduuli2eqGDoNjtmDUO4UdgeH75LdFY+E+U4xGGx2EjuMxwi6MtgMAzDD+P/gb 2nE3Cf73IZGJnwsh0ov4Y7OeTZ3lhbpUZqjEbOmWRvr+qHsDr7W/qKnJlzCwft/TK1nwPSkQvDoO Sh4iuY6J4CC2wm95ser/gBAkQRbDLCyN6r+p6Q== `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block l8u9KWR7K0iPE4cKBtlWMJgIHngboNXFVNkkmZ6xHn0dciEOTcoZJ47OzbolWOOFGMusDRe3wPtf ExmCTLetP1a5jaZMnwKNMmVJqq0v1MCXmQo7CRSSvmjqubldjetWzfvokwLk6MZBAh7O+uM2lRVg 2JUh5JSpOyhotZWrrds= `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block sS8d+5TDoy1zTTZMk5jun5fAGkESRFp8QMV8vg1sxwTYGe/MJptNpwEltS6HAqGJ0yAsHgTGiwbT +PlF6ZE7GdA3glLDui13HfwGjVy0dNgtbTeWYb0FHGMjNDSJfT/IEaYDdKr1JpgrZJPIOQ7HrQF6 YMldqxFOawfLh/OhhNaa5tKLjc6+CsSrjpDc2xu/XL01G1T40M44u9ezedVs8kEEFbhhJoSZJr+R Ylnota7Y4vr97XPxV540BG16z5uWCTfxzmtqjY0jRsdmMdWnhPVEemtBUdyBgpquhyWigLjIdd+m 9FytOvuiYqx/QxlsxkfK+SGt5NTbSf8tnbpcTg== `pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block jNC3g1ETgClEMyVRhJ9X1s0X3KSfCdTvdZ0hojJSjoINg4/IQZvPSTnm6KvDNN/9PD4ErCjmDDOV 7sMbtgU6WCbq/U9qhyKK/PWjXyTgOd32u9xnMP6sNlms5y7haCan/c0J3oVpTutiV6FVgEClXJfB n6wb0JyxR6eXI1RBZNNu4xSis1Eylp63Pg2jds0dA3HV1PfmkSmZ2llTUpuUh9dt5hBDsgevFCqq lEiJByppRy8Qv3L8bbNSl4LQSQfiGho07tKxnCrEOqJG7yd5jckcWNgwK4ONAZrBPYPjgPr/6etW 42E/gtZfx84l0bOSgB+lTAvbVJ/HXcEJ+ULNJQ== `pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block pTLqFXpPpE2wsvVFAPd6keg/FFvC68hyF9vLqKPMM2rj+6kUgPBCKgz90mreQi2fbuua+uvx6l++ PnxknxaYB9TXxHfRJsyoZX/lDaUDvlgNy3lgZ10JP/sGNlu8DMEiANoLx2Ohda9e4aq9Dcpr3IWp CBAzAaUYSGBBZlIxhN0o1NGemu0bHisB4FMqqN144xTFb3G/ofll70V6WbXVqq4JSE85mg9m8Sny Mylfwhg7XM4vQBhWx1WmUxD19oquKtZeWYm8xJ/0FtlO/dZW/v/IrTsBHO+g31Tuc4Yeq02xEa1c lAadhPvCyPFXNR39xVwlTKf8TjWKchWjriUEHA== `pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Mz18GBawyyJpgag5k/ejGuWP7010DXxbJmmL/KB398ON6rHGp/E040EN7rcmiOjYamjthKi+JJ2H Tsnh2qF0B/TBwgXWQfN04JV3tPSOr334V4HruGr6OWUGQAHJKJsH0QNDci9vwkafL+ZLz1+0JhRU Gw+LKI/lB6iQ5sxRT75gHKPtr4swUQdSkdcS9UFHulKsKMJPsSMMQnlVkHPnlvM3c5gHCbWM1V/+ GXVuzNWNhwqGZz8iUOKWTw2IVwb2FoqM8OcImKR2VhTloz8FFMN3uYbLd6PqzMrb/IOKBNzLq6ZA HllfEYb6sxyvg7DpPdUkiMIe4F4KLLEgaFkhGw== `pragma protect data_method = "AES128-CBC" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 148800) `pragma protect data_block 1roWfichpEH93M9uZ6CH7ERwl1i1jpNBmZwDfIDj5x61v3gbDHlzWCR50NeCGZeKNg0O3B1BnnV2 sO4eUKDQHk/0hdhs0ObAT0evp4TJWmpPUFWk7oEdj3lqrVRyvfYgn60807cHMtaBs8P1vhx5dcTA hEbohQoHejsnisRIzTE1YmyQMhp4qzUSLOLWKNXevDz4QT6AJu1/pG6dcZfttjZZzb/+pRn91jVZ DbZwSu9fQK2q+jokbW1OO4AVVKAI31jHjTfAO/CvLxZ1Uo/cN6ljlND1j7TG13v13zgKrR0yZyA4 I4IhCEbF7ckIupk8/X9oY3PkriIFwbKQz3i4kdY9rwgMBMnExnn2VnAGOvG3tEl7VSoWsAw9rWQr HumilFyY4N32r6cLparw/q10pxGfZO3S4nvknJ6V/Qil2ytRnrufcktxmPZ4WVkER4o69VcI18CZ aERIE/+FDxGT2GBT6VPHKeo0b7Wwe1rlRxowMcWoAEnhqxqSEUAQC1wOTwtD9oJ0HXxXF4GUJY2+ MBXh/edz034ufXRiPCJvT70OABNNbkNPptcwM8oH29KcNQ0jEV/g4MG4NTyXFkPlSYm33p/AWWA9 5Z3EcacAKctYU8a+yHdRaWSF7Jg+JFaDK5OA0eUICV+2sJemALsR2CfzZxnyMt2wrP/eZgTy8HuI m8sud+kR0yYAll12lGZnNY7QaOf0m2bYVcjbsPsL2z+ANZydTxJdCd16AkRb8hNlGQqCQinQRlAm r1yCH1QzkCCjToNs4zksMmo7sb/A1GGJSFXXM5H8iuk6ClLKt7HQwTYteq4mvPhwXHJYu0PPbtKI R3kuuxlVqiN8N+fAR+KpKIDUjlahF9TT72em/8EKYZGJwRi7I8DRck3HkkZ1piJqsfCWEcW4mmph ocF8S0/mBGBIfZ3caJF+4+ycFbuBjFAc42NVUn9GEsr+D3mUwIXSTWZa7t6oCkP3+1eUvAeezMKm 84R6jpHBJsF5XU7rJIlNYk3FqJB0NOE/nFaAlLcUWIA3vOFZN4ZrfBOXIp3sT95nCpznPSDXSPhs z8h6LSDp5b8xLNs2/D3gNevWJcz50weAUGBQvgbVR5YNiB56pLVDP1m9FC0SviIlwy9tFbZro5Xa UnE39QXOC+IQIcl8H4vM35RM3R4k0VoJmSZaH5gkhYzWcfMi8EW17UDmdlUdSlStQgk5xLFdvFex 1M3MBfzGRKm8r73QifonhuB9dpb7bsoxogUtQlXUQ665HJZJCJQPn8iBljRrs5skuReoVTT8dfUR Larl8SFJDWsUJEkUWOWdqmLJGNjUYQS+j2RhbyTZJ61EDLlTDRyGUYQl4RRhif+0Hw56YpCwlfRE VG5ypxZRXlW5ASvv8+cy9+qXLbDCDvPMDte7ZlMBNoNpWfb98ecgv4QJlefT0WGUGVghvZf6t2Ps CVE2pDqISgF1BbK1efH8WNmqR+/DjmuE6gTX7WhWHVN1x48hiisU1J4Vz8Nw4sLKtLi+7z++l8kB ohbDFwvLX+zLmw1Vcksk26IxguvJum4Wl74K0e77WbirG8JJU/5jJyF2YCOKHZB2c9ORb15slUqK 7R06fafhKrAhcs7C6MrX0ZpW61eShWfJCgQyXesJ/317pia6XyETr46e9J9GQam93D6KuBiCXKAU 8kV6IjsuLtabjL9A/VHlei9ZR2kWTTl0IjKVg54GJyVKrTv/922glUogUa3PTZgcH74dp81B0/sl rZZjvs9Lk+GmOJc8mp3eubjUZmO7rASQ94CSO8IKZkUN/1vzPxYwc0s5vpY7emerSUhhFPeodwcA iqSZtypBZtGFTglrv19UJuq3NjApPbZw7g6PsPiOtzNOVM2RB3PoJf8LTXdZ+GQVkrxnuqzOl0iC nmpXk52bKf29mqmEpPXTZuP2J5CI+jsLeIx7ShW2QRBWyGdcsI399v1dmE0c772grHT+s7pzFrIM FgF6WBgCCBlQbMxRLZcbNgzNdivQ4WEp+mfdU1yZtbBdZXCA/dJc99AUi058mOml2s9WwTaB1XSU eQzpq0rovhKjHNxyt1uTysyHhLKVnFWyqwKNKrFMTxnjE1mWaZ129C05gQBuSjGTSuu15MVVeLD3 7DcEcRg1F9IjnsSGhBJ6/RgldiTVKHvJI2qEb6ePsD9C//Xg/k8XLSjDaJQ5FCdMA8zUHy59DEez HVSnmnBPKiEIIdsmCkSOAUSU/JqNJWSgmIZTznR+YvsKjLQfzhbiMUF78YQcZNKpF41NCelwj/2y ry5tlbEIH+gadtpv3jW0OHksZ5QFHdf7Zx1OuC5JX02Aw9g+OMr853mEZEFFjgfFz93Ujx4vPfn9 QNLuMNnwKYyndbJTfCbL64Ejhns3droYcRiDqFPhzX82ATzOuzOjN/un/qZS1sct62RUs79mFyUK lttoN/wq2S7tizTw4AE3MDiIVGp46XEM7ojF93oo4b8DsD0W8YSgGgB1swdciPXnw2ru24QC5IfA pf0umz6Gov8Eu/4/I4lQxv/Iev7x1wEktVabiL1Gl/1MCJd9GxOVcz4gQUsPjgdy/dftw6dpBFCD 25ExejjEltdc5QqHqbUL5qsDo9lIUV4AgNWoEHKS0bhcCxqtRtN5vrTVD+S6GZdc9uPNZBKJtuRp U4Auyx+EX9+u6ufOHw3NU2Xl2jg6fVPadDfoZa0y8xWZfuwtypetkW0zcmzK2pe29N7NAofoga0U CA9zpbHRzdzZ33rBJ9ZNKMYqHDkK8WT7WYaXzaGnyGTKYovaYqu/gdUDZ4keO5WOpQeye0HfH3My yBkYum1MEtX2p6A5RStqgkoW7x4JAiwyVmQs+FNtBgSU0/zt+kQyabbnpyQMLflTqFVrfrw0xXOS vjlBuZjpLuObYeVtZ75/UDIzJUtqxuacHiPrbhE/Vh3fcpbKaZUnlBFaMQG3vOtg308XFm7EUuli vdNf3wsNN7VbKJMBS249SWzgxKId11tz9SkNIKtAQ0Y0zju57JJSbuGjpKAmhgiEEl09Fs+jsJyt B8iBOXFtLDwV/Gb+bz3avhuO5RJn6xR2KE+xDKO0Hs3nuvqzAKIInjkl/bD6Nwpa0AlfsGsGlFKp miP7WkFkyvzahGP4wIZQrH1ndTOEPjalvtrR8DS4q1GXUUfzYy6kJg0WPDWS/oAiCpTntjB0Zcpj PGCk08QM6n9NedxCw6f17TSnQwbp/r9AfSm38CfXiHJoV8XCLXDKVv+B0TqvaBLvFaARjkRTRNOL gMQw/fPrUtu85SeOMV7UytiktLI5ousmwo6y5wp6SHYkMr/7WU9rNxfy533tBqNoVu8SlxXT15rC f6P9aPpUVgA2nmmT8/UqPH76cN6uvoh2ierSj3G591eaXkYS/bWduTe43AZFG8InZJvkWEezz6Ze Z4fWpZQ+GHAevUlAZNx6mXBkGOcXt9wF+RfrDbMH1Az+SASYskHmO+5NWWhSS4UYdKRwBEsbb+85 5oihlpcyZ8hqEOmv4+FTmqZvbXFM+5IvvmYC7P/3V2RkYn4XzCQOoCnpw93JS8e+jeTaa6ceiV51 GQCBsRjo4oquef/Pv+aE/nip900WxXHpVoe79blq3aB0g+PNNlvQxZqhWv2Lx/MG3oRau7wAKoRT ZZ8ZkA+c7PCgpPGGFxgePmcMMMUR/jnwlFopWOiqgx548UCpJqZpKZ0Y2GlWJvZ3JFnmsXnwpjl3 j1S1NmIZtEORqVmCPyPEuFbyYknUJVInbuLEhAkuoSjLUKV5iMVR0addHQooKP53BjbnJeqhHJMv WuWfBQtuA+qVagvMvIBENgEXd4THqdPSwbTncb0npOR9uNv4XNGHQEkLYxc0RlX+NgLAzVQikQNL D9fDh2ACERe8cPz2tV0nb3oDW0/fFEvqzZ5BoHPBf/CVZRmGIl00KsGORBvOsI+ThM8X3J7Hi7oh rAq/9jM3zwLv8Zz+0vo4l4cVs+7aYquoVkGE7mTlKk70yE5uMwhBnf1JHJZ+6W8aSYH2ri2feqgf Ma1LvCb7zJFVOBAK+ZEnxVq14jbb1+qrU6LsnulgUgjyQdXSF6XEiUt3Bzq2OBXkxhAhY3laZTUN l/zl2ZJbCwva4hBfpm42uk/61vURivF8jkLAokoKZYIvWchWBlHSjphjnv7x+R714c1kd6HGXcdh gc3QvTkrIjdkYzx8vNVvXR2Nxn7NLP0OD94giFIfDOg2TNslBhKDfLM0aPktwitYTkbPHQkacK5G bl2DN43D17tfz+8X/6C/SOubz6hnWcruO0c9J7/ib8VYmAw0n0u/BqeSBdvV7oksJrALMyMnNABc nI7EnXLt7xSeVtMkqP2ooLqdJ+0yHOfBr22XxbsosMif9JX2b+iXjSp0BoMiOZoHakd8TCDwvQ20 ZzETYpBEXiV50gs3qqdKcMnu3eAn6nbsExPfxb8tpfG+Uox5ngkgVUISuChmRI4WUgAYhQ5HGGsB CtErLairFeq3CcyLszyKTk2se/1uI/SqbJEsvGFkYi6Z/yuMZD72MTLqNXpn2gKj2cl+QNRLC2SI 8CELC60v/bgyEC516OHu87B523CI2ghYeMPNnRs6BjuiM3DWy60o/+LKRdnYJl5+irB+dHsd2xf3 EdqwKUt1dgF/KAX3oFLw3RJvhIAv4u9IdXR4kZBG8Qe++wlpAZNFv1b4NBT8bDWoTl/wOR09u6Z9 mECEhCh0efTN9jiIgWXVxzfNtnCLKJn1AgAo7LJ74p1v2TJGujvrl/dtjaYHd3tHyBs5Gl28W+ST OlaAY4XiK4zb6Z3qgKhYAcedj5yaG4ThTtmM6L7Ftl8M8Zli53P0ICbEJIf1B6L2jV7xHA0ou6Ec pHLqmhODIKvIgtsDpidsIG/340uTUxA/JnMSBBtl3lHfrGxWkKrkYnlcnztNevw3I2sTG9qDuBI8 djlZ1lmyG/3Q83RoHwhxNqU8NJngfKQ4H6fF0Z/UYuShByFdTLZD0NpB56y4/CEYd89zKtIYaQ8U XTksXchdkJWe1Kx2mg/ukOAHNYXoSFwfFwxMgLMDcajhMfk2UZZGfovU896IL962cTTPO+ljwXCn obIO7KKbJe5V1yX3dt+yAkbdmiFZN6zdsBUyDu3+C7K+pQcyHYhrvtI7GUoffHdsrViVgIt68ZAh Jgt4KeAOWwZIyhlFDVpVtxruYGfea8C3eeYuTnW2nYESn4GwzIGcHSKCgdKJct76S5BVR5hScTwx uoGs3FflvS1+jac7R8+8kvOlZYm0dAlH5zclv/NmBSg5D9CdZUbuUXEquYQ3tN4J7uofRtzXd8mi KM6wcMGez68BmAimsH1avu9XA5DeD1CkU/cDvQ1Q+ulaF8PJTLwrmR3xA8IF7mXxZhb1b3dTY9Mf Z2C/32IzNn/lftnKznxUqlQZUm+bz9qdO0S/UHZa+Dob/jWCV9atlUNSPnYRWxr3KOUQfebLOZiJ H6S6NXYnmF8Ym2/lbzNIUcVzf2u/Rmi7kyD1eMzEmdiZq0haJ2r3nUSzelC/XvOi1oOGj7DN+U5Y O2YuO8qlBGa0rkoEm+PnnB2F5LHG0s3KMg3GHY1C46gkOKvVw8FbSRy1FnqJEJInNm/40lS2KCes ks36r83Np9gRTRfNTOD7PFnLuUXqptiehEgxiujQpNvWEPklnTuIFTfDC+veHXVLJCwO23rbiTYj qEHif0+AOMhm4jHgWzA+Ci4/iqLh2s8QudaK7zI/UJXMUwWYuuCIOrGbpED0NFON2hRcLy7bZqjs sQ3+u5c6Pf/NZoeZjlwSCRwvPOVp0Pwo6FaM2DEqGy0S0FrX4RM+tFXdyzSrotF3Hw3fDVa25yk1 eFheh6L8fACiPyA893S1liT+yGGCzZScuOnP4zUq9MKVn05XpPEEC3nr0pEQOCxtccAWPLohQfV+ YmugYP0/+4dMeNbHvwCJ8mI8MwXUo3lilNz1nsHBNxakhr6aKtiTHj4uljUTk57ui3IH4xIfL6Bg 96lFPxPRUsglWMFm80NTeE5swyWa+HBLT1DpTZs4uvoC4o69gxY6thJolsGl++6iRXOSStSgig8Q c1G6VyZchChNJMjUmxif/BTI2x9jc3+yYhSBOGqa8fPmHLADx71AHjXiuQ1zaw+nG8rftH36DUvq BJL9KlD9uWUpkAJwmjzsw8kFVUXb/1DO1Jrey0r1cOkE+zks0X4C2CjguX11dFc5wH54R5LaHk5X yXILgpzeEXg40/sPRWE1rWWpWq7bVNZAziuwuoL1D72E1YToUhKG4/d17TpgaNhiUL5qFKdJq82X Ba/sx8ExEYlg6bYI9hBma4SWgxxtJ6auR9Q+2g5XgVsQED3VJwhwL/49rcH9d+083GR7nHNWyjR4 u3603zOya8J7FZNMgJq5yU0njSCdCikOsooL4pwOYGlUKqOIlWqhp2oOhpAOQVFow9Vq5bdGzrRA wQYsFp6JdlJAY55etmZJ2SDFzeqtK8DAo83Ar3UOz3OzD2a/ZjRhcVUJwlepHuS/uxG1zaSGowE6 9IUL0f8urN31xGOEIfc6xQ4r74RrcvTf1d3dnG1BadodItNpNrHtDj8HwkOgKGCvg5v2ETqYA7BT rh7a1s7VhO4gwuAE69yxSfscJphs8ZxWux0CuUbHneGPRSoWAukhipZEolpZX1ePqHtvCjH1yHrJ Mt66WJfa30LobJW8gvSmPVCtetucNLDJCLBpGrFX/nsXhErv7aGjzI12TrH4BjrKO8XHzMFoayux CVoa5XCZP3awrqVVXZ2JIcr59+SZ4Be/mGrSGe7gTHQGmeLR3Q9BzXjxVmtZcmUSOuoJqeKxKBBD viD7g/GntAjjxazBnDC1XvK6VPyJb3ZSn8HggG3ZA/jWNc/VFn9ZgBQu9UxI8Al3lZawE11bpwvb 2BRpLbVdTca76eKK5hvJbgLPmfkV84/NKcNf4TAtWzZqSrR0fYP8htJd4GTdq2Y8NfyMZa8+qhOm 6TefavcUnD0ZAAGHIHJDDMeOS/nxBj1ow/i47+nsKlJgyZm3wsCas4zvZHJYlPY4PTqZKC0ELZpH +itIQneXWgbmXIXPg1ZeXhdjlA6iPKDTagADi1A5zSnCvoo0DqjoUbwetkDjeLbU55hmds9qJSFA RzwYBJfEFynJvXJK06EdAQ/1bmbP8VBxUpKZvDkRxdDvUa7inIPGgPFjss1aFYmEyvgmUXgop46j W8KCYo760NdW9budiA2vCTO5r8F4N+6vGKfYnRshjBdfDYlfvVDYu41DQ9n7BRLKuyVVStaoe3ux N0k+bp8B8/l7Sq06WuBYL6idb3BWeJ5TzSAgSgxB232njN1yCzFnpJmE7mG6GSDrRB/XFLgiS37x ZZgSwoyr5HAYgxo0dOb6jyjOlck+IQAYBO/IO20WgAkI2yk1KdUbOsjMh/mfkUQIbTLf5BvxvDuI nn4fJ+7Kt7xDXfj7wA4qa+JQK6aLbjEqpesneFiKneTMT4TYyFXlBWt0sVncS+6mMrLfboo6OFsz 2Pu8v8gQTVRuvt5mY0Gds3aIYqvsEHzNwjeZCH14PunE4LA/I0I302Gduf1VQTMkK7oWVTnWUrA5 WHSdAtXA7aEVsBaDr6J50vzCTPhZtV0VRL5ycuPqB3n8t3XOHPj8kRcijU2Yz7cOQ/t+oQr9wXpA m+SzKx8lIFt/xWz1jUDgFhzGL+XAlPTC+vM3kAJMY0jn2onscgjvEZ8F3kEJV9xbHthak4M620P7 M/C3J2XzGlhyeVeXZW7nfTJzDiymD6hF9f/1kYSbq0ZhhxkFdr7OH0Q16woHmU/Ik6y03SKhfB0U jiShdb2tkSmGYDudCbZR8fSfPziqDelJbZHYeLJMFOazuAHCv1XShsVaG1FOE1MTyxpzEjdHKycl bOx1omrSZjpRF7eAFASao3hSeBh7tjaMyyVHwKUWJKe30tCb4EhAF9rHxSBY/dasc6ajWCFQ8X9r ju6DIGyKkAuU1rP3xWckZwokXYsLLK5H45Ft5i5GtNvMP+J5XmWs4hnYmaZCH91yxtcA0G12+zNb EM5KLGrZnz8NnkIllIEsJDISCo/M7AjT44c5IyZqoeBgKgFW/vEQhUn6Y2SgiQrfQ/U4Kg6DmBX4 yICDO/lsFZ5xoooTuIcM88Zu5XJyOdz4F8pW7FOD7XzTVjvlAAHKW5kLPzWOYrw0+cenpCd0+3/8 UfznvriWZS9K6LOvqDdFk+3b3sQ1K/PX2/cufJiQ9KlRnWJkv16n+44kb7y/607pSzVJQWskMsa5 qpdhzq8xe2+wJVGcbFliSXyuSX7c5gPTAINiskeG4wG5xxek7NyMt4tz1ZyXp18n+c7p+YbVbGhU YncVgwFg5mF5cM6kyUMR1p1yXb2KcJvtI3bN3EOWL5LYSQm9C/baXkKZCW+L4BbIHgCzSFK3r6Uz bKlgsylPCVcAvRrNjXOjaCvM7LLXlKN7HZ8v8f0tzFDG1tn5h/m6mFZXM96NVSC33Vvol591aqa6 TuNhfCTn76wnBQ62uRaKf9IX/9RdOLkZRZOG1plTN/V3ZL/hdZZsXYLEzYvmWMzQFdDuyq7HE6l9 +oGQFB1RCxhfyX9RAQBn/HPwf9UDzzVNQOg/PSQgRlB96E2H7Rf4rmsc1DPfXODdYcjWyAtxzyHH 9fkHnFaUtjpjLNf5USX8F7rezhijB0L9xDuUokRs6XJAy1AhXfKgoij8jMAm3wy00Dj0QymrmblA GI/Iud5jACpeIypnQyyxnPkGotybq2STTQInEuj54VSyOoN5IuU3pSncPfikaBUwSj5HEjWkbOG7 xgUjQxYgLwG4Lg5Bgbf2mp0prqmDgXEqYw8ZCeLQTcqJXDISGSF4tQtBVGcAMlqAcyKLJONPaca0 zrmHkGBwLdLZCAIo9dlx0ikQR8uueF5wyDStThCLlmUiyFH5lTLuUd51MLgKwWSKxIAFPHqPxrDH X31cwx9UtzQMRhdFJ0Q3gBL20ZjPSZUQ/crFqQ8E7l6mUSBgQWGkPjFFYipQ0nFLRlQEA3l0uIKP Mcj2rSCt2Ludl06U6nwjtALDAki33OTSe8NGsSxKH0/s6dYR6tke7E0mHUotq98ZumBw/7shE8DH 2fI1C+tJwLbTRK3i+TotV9qyzjafilNppXMKx+r4um33nMfAAoNjSefsUNRgOc55V8oujj1MpHvf OTTO7f5j1g+LgeaAhcbHM5axcqBHrcdmpAr1Tje+6pPUd5k08Yln5LW2lhEQi9QZ7GJir4vxWcMw Sj7OtOVxrlUxtGxPHE/JNdQwvAwThalGhLEv5qUBpW7srYUnP/1UjvXTulxrIETyflzjqVJVXldq MEmg7o9ZoVyjoou9DznDLshntaGExW0FiJA+nKUKoQ7ypW0LVdLmxJn811Sd1DVnyUS9OfGHacXl voC50pgaIkLVcnI3xuijKufQQLHGqviNiLAv3n/piPB5S6gyI0XQjhaFrlgiTOM4s/XGf10YC4LE htSzbehPOM5rm/TNm9Fz65Jp3MuFob0rbpXsu0eOD3drjO2DRQmUcrXlTnYNtYRqfMJ6knvaDqo4 gICxtmEcFPai3CnG8e9Xbt/QqE8Na6IrEeovUjTKEcALiBVWBwH97/NlST7NMbClIa3xn1NuObGT 4glgA/yZZaK4ymilQVcQP1sPPqLeH8RXrVxQR/bLzzqMtnOpUkdrEF31/adOOz9nbk0M8JKN56RW mv4YVZFKmHkfFvUNMPSwX6iJ5m4HXP8wiAph7VlZGCEWUmWG0hGsh3vxSy/rX3V28/DHpMq47mYt ulx6qFWBh02+/Q9oIHjXN0v8KyJI50kkcAPUPRGcRdqBkyUG6KWNalbr6rsN2kCvX7GYVmQvKqHl mlpXpnm8TK7OcYvuVopaBXZSDdQosCZchHRNWwbTyn5U1lOIn96tCR2at9vhfGeH5ZvQwubS/7UY 1d6g4GLqPDul9EF6GK6fcPLYFlnTBTUeOcvXkWUUCbKQYT5wM2nKLzK/1e2w6qHPjc00OxllmuAs ksOWNYACJT9iAcf4yK9Ksa/BreUuzAZnxsxSFGjgevoueXm/XR4Mmmgi6LN4M5KPplq8qJ4FuFE+ new3nRhT9GI3dSyaTqC1gFwFNKRqlwDz96u95PwZ/Az2wjEc5m8doFTpS1kdVyilUQH8/x1yQo4P 3qCkWHlrUZiR9QZKgfkZTbVYQQvPXNHid/AqhSJOkOILoq5HvdgOuHjK9s1/IXL0Hpi91ncWPUhc wRkKcuThv71YHdkIFnkoHmbHMPPf0cO/qaRNa3W/7XwAjgNSPDNDLgrUgsXqcvXgFXAdxiMlw7eT AKCuE/7TJwh63FO9yR+W0OoXwJFYLUkuiIgurMPR0+bW4sdAgvPzB0aI3SWiYGAN1kfqEcRL/nt7 GtvTG2WkR15VRfSM17n36g+dmmEUXrgxIKRElyxJscefzca+FImENIikUmoZ9o4RlBArIfCFY4l3 vzjU3wXWmQCxvuYRamFYp8RZqsm6ZBtao26RH4XxGkCk/RlL5f/is1yXtbiDOcPM/b7fgJASsZnP Wzah5fltB0mKREtrANOCHpcoJ/4Una0LEQ4mMjP7GGfWdOCt8YViSBmxvHQUmJUq5mVKmyPsr2K0 fn4nHqz5kIrgqOP78gzLVpm2pIBBzxvT/FKZ3TrrHapbYdrunfzn6b8JN81owhPyWwwyQViisE5a i4aa8QeMbO8X1I6ZcYOpIKtrBz/QhjV4bD5Oq4giwo4uaDgi1Jv3FcGdp8Brwutu2oMgs6qpxm8D AJp1o2GtN2h72oM1MZxNqAgqrWIqtBI9/M4YQ4Sa0p1bUlkdgbJf50A0RRztAZ0PMTM6Xk05wxPp LnlYo53g8naPhc8zm9iDxikat/HhpXkIkhwIovM4Sz11KDmRVN601OiLsLuWDWXcQrl7h7Jd3Ugq 4OOXtrGYjv5B15OsuYqoX6Wtq4XJCrH9CkssCCN6QL2OA6azhUN4UVggdsdIY26Twkhwp+h/yN8b Y7GVma/EaxUJXIvXJ97yS/gbkNIc/LxS/agxJGJHKAJeZdCvArHVd/3zF9awFun56tZmG6r5BNeU yJG0wPhHlmGJnW+NJvRwym784O+S4/Ik7RVkx/xEvWoUB2qh1UazYsYy687dTIU4IB7asXZ2yMkE rsd/rrxzjl6PuMKO6hjK+Rhqt3DOh0kbSu9PH0O2SxmNlFXmomv6RsOnJRswZy9lK+0+R8IRuflo WREpvrqyhdAjCuHDPscLcEZIhnZic1gbc1CZfWlfl5BL9IbxesyL/CsPKennwm0fEo3zlAOuKLTp 1J6mZI70X9K3pmBoR6H2wCxj3l9Um64A7fYd089HbcdbT4uQoYN5vNK/ol/1m8dJNjXXYZFqsaQf yi3AjKqXZUi3gl70Vsa8en37o4/YRhd83MrjVNg5JGx/fp+LHHWHuI/L2Q72z0cB7MaxDQk3CQ4x oLD9q9rDx+t8G8Y+XfVlTbJIZ+k7eT/Oxg2mrG1yfb9mEY4MdzHVXBVghFakBJYkVNMMC/3XtRJi LEOS4c1HVKXIU9VMTUgAfnlN3d3NiQKajHLUtgdBUkQuN4bjnp2uP7lwvCtBj/x2oLjnCanSepjW l9YEzbXTT92C0pZI4FXnJZ9JksuBYUq0/Rr7yt4ZgQ8rs049FhEJTTMkwTFicAQEJG+DbE8c4T86 jUTBKlQsIiueFKoP4Yxe94u0yumTxghh0WHyp2RprvWReeGSSbKUFjk/2//GaZaCQq+bT2BMy/1A W5V8ao1CzDQFNsstM6NxaoMtw8NvqoTeBxirj+aFeQkBytf8vS52zSA+buBZkEu4AgCgXGzjQ4OU PEYJCOblWQ8QMfJeu8/XeFhMv+0jiUj15X3BD37+094A3Uw8LCBPzEa3ufiMBTAc+JY1tV8eFhy5 S6VqHivrX3bdj/btz8Q5OFJNd1jQCj7nhLc0ZqTwivbUgSvakQOImpGwE5yiGAeAP8x2qYZvticK 8M9UgFeK4n5RfpWxTFq2PYDQHN0s57bY1NYTSIUPof1koLi680LAj9HI4zMYZwNDhLp0qyYE1i+4 xOu6V18w45N6eb6+lM7N4xG0srVb+T9YFNtzw89O02+cnK7vBLglxqUGoyhuC67YKNi0Ak52t/FL LmyuXNZEUQHDpXfo/BRMeeTEZsGz7tzEwVRFmELsKKUvz7/yAq8Nxq9twZwYdx/iSoi5h30w70Iq BJ3UC3ke4p4DfxnU8JTXdxBdQ7cN0j5q6igHEU0yxeKSsOlYWVlXIPoXMK7EZe+hiV7qJVgD50bD ftDeT7Rgz+hTSDHoH+FcliRfjjZ5DJhLKdy1Ox3UNuOWh3zZC9WX0iKwTdxwBGtxYnUg/CHbcvvr OzZdaeiURmu1JN7e/4URVcEWJvi19YVG+SLUPsu1OIpedJrWF6TI5Q7nqIr9oGPtCNTPiUtC1Hwv 5mFQ05A1nmP5sieh6whKGE4Dlkeh0pX/rLc1qjHlZ0pqDNC/JDZPoXT7YgPYVHOv/O9wAKbpUF7w DUTXfMhfZS49pOJMSBu4Yb0NPUu0dPLPxnbnLvCr2YGs+P1Kmj5GWxrs1AkjcYOcw+yI6n76boMZ I842HL6v/gEFXRFN0J7gO/zH/1ZmjtkKVw113PBa+dlk++6suGYvEAOtgSC4JNpZSuPoGupnFHJO hQLyF+4aKSmc9ODw7HJyZVHdPVZ3xIYUTtx7k79fruO4PYKrKnf6vTwcMk21bRt48dZyRx1YTEUL 2XylkjoLYJqAbxEtNx8vrLln2P9I5Mq+Sd7obmQv2tg22LjbzP8WBB6SfG1MiRApoKbf8G/y3QnG o5rZw8vWBz5ERV0Imn6GyQ+GK4Ms2d8rUw8OU1+y1pq+Uf4MuqF0yXqzf/ZA1mpkR5ltkVfpumJv F6aFTf5Oh0A72I265Q9NOKXpciwg7caEpVNp5RGrlY9wDdc1IL5QZmU+miTiHUR5J0hmlnaqUeRH pUUyqB4Xhn3pAqJTZE5QwvtwX8o7BgZq8MIFbphyMoaVRnz4iXDp7dMSNxzxrRZKtiiCExw/HU1e AGZHUNNXUDc9pO03D9/MBRRFc4f9NdUodBTCKcnDPIuA761qUJsMbM0hgOYJyP43080hqCbhKFMT YySjTjuBEVB9JNYfTPLhM3wkRwjSy3nfKVtex57E5Xvrx/M8qlVIV+v5Pug1vtK4GEb1pf1NBKNS 4YWTEzFC7pGlxhUE2c4xdy5NyncBjUCkf2FtbVVcVKIbn8YzQCmC31mwx6705uwZjnJJgIyTUpcd kRKeU9MWYGYI9BcLpiQ+k7qOVfYXMVH2fOMjwbtHeFq+Qak93Ks+vbWI4aQesWhJhSa/FRUlmB/l WSWItbYO2RlncW//jejZ9PwL5nsfrWpx+IWY5WeYFEvZqk8jS/FhTY4V+/sxqQQ6c7j0EOxOHAX7 vlgv+LfyPTlIV5Ofn493pIPd/IrIX1MH/NTYiG97qw9Ilfo6I9k+rbyDuDvP4DY6dXSB3OIihzww gSWteokgU5kOtBHQmUSqrHBNyDrR9jv3/JXqH2hdoV3M3IezK2/W6lF4IgyDZkFGFON4g6YFD3cW NeSxTQawb9PWNxBfTUl7HsXhj093LqUqxvDWJT/Jp+4clnSfUO1KeEbcM1XfY+r7zFQnpK0Lcr+M wcvLnoAkpHSN8+MGAV0ZenNmNiBFWIsftTSY/ISASuv8+YWzvP8rM98KGBnUfBVkRQhtS7RUmdoQ d0PMas/gggdgwh37S0zaVx/PModqdNFzzR2LVo8H4vGdLaZvQlXFajYLXD+rJCd6QKhWAY4FeMTX 2Dnt2p9VxBP4KkaQ5h3psHCmU5DkRukzJ/f+7rSbyMQuqDyvmMDauQSg9Z/yhyflHBlyTrm2bS/5 0B9xJMbDmVozzpYP1+uoHoXvcob1K1gQ2S8Kwa08HnGghMi5ze75uJssJ3RTMqc/eFPL51d444jk ShjrtfMy211sfKJMIjzPlsh0AQc77s2UKirR91id4h8ZQwa10kXJZyHegeuUimS18DUEg6giETPS JNEVBqDLux2iCbfvtOKmoD5jISUTbOc8FupvJU0padX0t/Cq03w/ViIVVluLj8CYWc3kQ8Pdde1B yOJ+pr1305MsKeB/qhayBJpwxrCE6mt5ag5eCCnOwS4SgezCe74RT3kWQDFV1Bhrk6ZEmf0ypiXJ uyb3674+S4++Eviombqy2Sp1esVVXH6cYJX9Aq5DwGFU579PESwpB/LfYe/oTmYwnSZaGXMaSZ8e DfEmFJqcyniKHysQUuCod/tQ4K13WtlUnZQ5Xk2XCDK3mP+AgxAHkZjKaXUbJB77T5NGmkJlCmzX GIA/+vQu95DSKJwPQQHtjr7AWfWUOBLTtFOIo3WOZN2EFeCsDtrngWL+B209zFmBOiabmAso42/v HRW6rjcPFszSB+sGA7OnJoDmXh1oXzZbIlGMgs/m0sy2F2AKBY0BDUElnuv0nULkhWKPKkVbagWL TqobkBTwJkUmKuoZCK35HjoGRquPkDf20lah9U2gftXwg5FUhrv/MOz5mayWH/Ihyc/pfDWgpVXl TA5fKVuC8Amyi7mNXnrPHdu0f2JXF4/URSgV4u/lCPAjODZgF71bRnuLBUSPuIu4mpPUuv7GoTsY SvhONGPtHs+cPDWam+FK+fjI9Kf9dWMOf35d/avD9u4t2/b6BTVEDcA+8ry7NE2B2oqFiVaeASIj d1iHbOFH8jNRGJK0OF3aHyzEo0RHOjohFuPKqgj5eMplUDYSjEmXvwFDJmBysHtXg5nOVDWEIH3n ihoZZ9TFCIVfC67aST5/HvxXDXnT60rHjpBk+xuys8Ilso7slw6RzW+XyJ8HTez3F5KpP/oszme9 UcPEAk/U9zgB2Mxr6QyYWfaDrlSSyoCSvA2Upci3HjJYRR2/ePTAj817My57jiGvPwlaQKkc9Ujp bNrgAl9KSVGM9pfmw9vmytrvKCGd2ZFYxV3mY2pSbziDBTho4//EJ3WAKi1GPAq1UKk/nhOt0/X3 pRJh1jBgsRWkaojDOMOSO5FPbRgCEC9QnHd2x68RhaCZ5NDu9lWArie5Uz68d5p05X9Ze+eGuzIS eOYc5pnZfnbjs9tZ5b2U3UKzgN/KBU/juEvXStO57MN1eEWeuFcO6kY9MhanAPIGR4Moigo+SpZx d9z21g3BkpJI8eHlZmSj3eRR6q7LXIQeXe2VX5iTcWJS/kaS3mga6Q7/5XDByJMwzruivXLVDvpY S6zvNxfVbntXE4QhF1nm4WrYPTXZ6KZsbfRyJSKicNh5dAp10CXcikW3Ak3Svy+RJRePl4ievW1O 6zRrPB3C5lDqsGTGi70yzOQNy3cENhsPCNahE77awj3S4MjYpz3Mzy6Fv0bXwJ8URNziX9mWaYRE RmYAc80PN+WPMSbnJRQNKeUkU6RG0FS6GOGUSD7ZcD6Up7bJB/v7i6Ezf1AVG8ZnZdww5F0cwkYy QdIiF0k/cQbb41ZdEtXRLpRQ+Pm8/RFXlSi2FjrJ3EMLyUYDetZpKT6uP1yom3iW+snZ2ElV1XLv KfNsEezF677oGxYMAmRmI+OABcWFmRztxJS/lH5g9PVOXFW201VQ3xEIw+RGo0vPQGmj1Q/RwrSz wl6YgW3IWVjQQBkjUJasNBU0K6/I848KikvqmYx36QS99KOC0hYdER7DLeS2ORSdAaXZ2wLq4DAk fMlEIFno9ulmVbABOeb0MT5PaYjbh/qwOBlomC4RtV04JILRXStpf79dSKKXYRZnylw9ahJDzMwF EE2qFiBljnrNe+dSIK9HGdYZf2Od6a2nRuTQh9VQ4UHxfbMi/Y68lTGkQq0eJrf54PfevlYJ9pVI Bco91NdXx7PHDPZtrQiK97Kvz/v7REuimFi7rlWhpuUWWbZTx21Z+Q1+wOXLvj4yX8S6jsCr9eHD Wq0T4wA5ow39U5nSIQX/FAIgbpjhE1kAWy9dwcS/ES0PuMHYP5cdLZpEQdbPmUFFAXszx03/rHYE He3CAtf1Vg9K72lb53Bzhx33CFHHghDUhsQ7lih0P2Kf98KQmbM4hZpSYQGKlKy3w9rGjsGzIr4l FyrCYK+yRR13m4PVOB6F8VUIb072gbl8NUWLA/m4OBhedmm9DQnJfpOD39KnIYeI8/49S1o3vTx+ qNimOCJ4n35mT0Q6N4Kef3bM2qe6t5snqnTyEmRrElNc7X3jNVHhb7mhwnEgXatl6aVFKIC0Q8uk MSphEBOm6s19qq/B1gZAg5IJdNts/7Zkr8n05kYR2eCsH8oxSoxotuk5DdFup/rESMskpoLII+YD lj+k3AC1nIxgVXEHSaHtEWjTyqWI06V4vnRcF1HVxNRrtt/SbeaMAw+hf8no/oa1i2GAudDVoiOn 5DxMJwlSGWJYkSUykgUWkcPyG++XiBURzfx8Wer1PjhQY1lzENrf7AC21uGfcYMWg29H7u2bwAWZ kPBDVvQIKkCRYRwZJagTBwQ7AFH+HyKMVzXvoUdrRZpe87IBt3amT1V3Oev/Hs53I5E7BiQPSn8j hFgS2Kk1TurWQhcJU/tJDrNO2fPc4zgogMvD98gROBX0AZrAEPEIYdIeUz89Ni4uG0YvQXC3fBnF mjxMLu8nfzKUUfTJ8ZDvLXkCCCEKgcuQVxjbVzPs7sF1gX6k4s4b9XfpcsidFT7r/cMGkY8k04cW pcxRI/iC34gT2tPr4kq8DznvitBlPoX3FoWh68bDoMU/qKcghPFnz+P6Zy+j1Ds6fbIMwmQjGrUw j+i2J7rypRLEvHbRxcwZnbh9QpkrfZrtye34N5oMH5KyEQ/ER9mPq9VhKvLCNNUAeF/6OKUjstU9 pUIZNvQTfIB/eQ77gqxf2xGegXeM0Si1azdmmUPW15b3meS4ItWQSh7jRVowMdcM3W7c9u2D+cDz 2o4TY7OR83Kmogat636MX9MhbMxGBhdtDs4fBtQfTDFuZBu+oX8KqRypFFxjsZhjs/TzzTH4mzvA o8MzdivhC35LtjEPp8kwp6rvsAbL+SyMAIcfPRBV2kD2zE20UHQsx/+Jncu6gcA4LNSVXXL5sd5L FAJOevV2XdylixGve8MpeB3M+jX3kyyTuUrtc8X67xDBaW8uAsxWTYWvPr/Mw+NOBZXRj8BcYhPD PK1zvqrTIjOHKv7pFHclhx/OrVj9uU+KzqRboSq1YoD3KQ5va6yBywi7YiPHOBTPlupf13oPPOtl aNJfKT7oXqNmMttZLiZZ5vhTp/XumNUqoOVIezk0IjSCgxQXBf40BaMIwK3JrRADq7YQJHVwJGhq CuQwhEfvMNBb7HrvNLnRjAOvSgIgZ09QOfgp/1dfd5ktoP5WQbLVdyec52T+vdITy/kKCQHhv+wD wWFicS3gUcGfC9oqM8u6KgppiBvHzwHT2oiXo04/OQ2U2uv9bD/1H0c2Vd12VvQJAnfgBAqK0uGj wDhkn/q/q7jkpXGiw3BnSuPWY9DzMxZEzA97MvRzv9W8zbcc7FR/t3fbvgybae/gpXrQK1jtqBU2 oMomvqeTXb+ECFYvg76fj7B5FITsoCB0Eqdz2I0OF+4xiXnuJjPOZyamX9Bsl9bcMaMBgKXnLfmU wK6ffNlHSLlopWvu8f5FjJ5JmylZBxyqFoinXaNSGqT1n5Muvb6I/5CL2+/N4XeVXplAXSUZy9dy 8Uw5fgofm5S1HKYkFXxMQJAa9uVJHSTTC7rcanRLqwA8OMf7rIxfHjiCFHNjDS8A0mYlsNNxyEgD hrUt+6akmz1hkRKpMBUIFITHUQi4QSTbd9PoX8qXwCDsJ4r8fbAAAvApx59MKY32vMuw2FxirD3d eg7Vn1L0nO/nErQncD2/+8R824qe0UHC5/T+Paduj2YEWQVSH7YwX8UCZSvJla1Po2EC63JQZheX WMlLBLAt2hb8xxwS5UYkgcNOAWUuS8Xtaq0KgmRkMB13nDGf+Bb+w+92CwrZYAzRM7fN0x2Fq92g M3QAOOZaLnhmMrJSZMPkNzng1Q+A5r/Lvdh3Afgc1QjKFzKM7MCSz2fuh1d48hS8h6hkrXsSh47E CHm6dXrJM+t1ivLg/q/725shGu2x+Mz4uBb+Tx+DoOWddWsvZF7o5t76y/H3Ne/gFSxARAsbT3so l9IQKZ8wh0y7KtCqkmwYQbaD5JSlbOwf2py7XPzwb9aqsHdOMrDvuQtZjRr3O69sMGZLqiqej4IO zZ7o1tWlX6G6uQllE81geQ45Ix7dCXIoFbCcVBgBag9pTCUMnBWAaA3RmIHKKblX2zraOJrwVhLR UA4wc+dJm+piYUknwf7DaWLroF7YIfiZtCeDauuoU7HfgroYFdg0aoNN63vNB8Uq78E+/pFnD0I2 yIzZAjTnTonUnALzL6N6t6TVWyTYAIxiWs9pLQoxzcqvnuFe++zqFdRLn3cAKmL7pt3+qL1hvKZh 6NTPQINlKutpqV39lSpmgpBZnfcUdoxYITu1tae5WbfaaM1ifCWji0o9/y9GcmDByKGgDwW2S9tF YhVI1X9k8jnNNZAG6Ul8E7iPAI6d5ae+Qq8YIHEGmvufn8cMinytZM1IXVPlwyTi8Rr7adstl7a0 YuUzkCmdGTjouzjAsKMISu6vr0ZpTq8z/awUP/XQ+z1XIs/4YrRLyXM5H4gDIRD61GTX1mpdkM/G ZocG5NBEki6aNdlqNYk88phuBIB5chzkR2nqE2VFUHRWLrMeGKbVkifYwgrFwQttJC/Kva697Ip+ FFQc0kONSctE6r6ZSt0cUjIXIMzvuCWqI92SOc14KyurtNcSZnyLKt4WVBWiNSRIUyCAEXdyr2jU kq5ciqjz33vMifjkz1Ji/xHLZkZkJuDtQWzX/Q8P9xYlSSFWMoImI+zq1LyR4eeiX/KwPnc1lTe1 fFKgaO34xi6Vmlcj4c9SIGhMyih1yYJqPq2C9vuyFFgwVsGHIR5xbWNotLxx+hhCyYRtFpxfBB28 cBPpa6EsgTtnnb5QDYBPkQdlLzQuSKgxW4YA5jfukEwNM2IAL+OuOjP04dKAXsRRYK7hSTGGzGLH 0XTzbjHhjlVgmXBPKXtGCq5YVox5nlJq6OxtPHr79UYxBaBRsNaZ0u2TUsZPftwBhrIu/citjZpd iNedh3CGvUOsIWhrpyHJ+nL28+/9rio4LHxjgvTnMkeCI9bcuFzXqQHusZH0PS6e2Vxo4tHy9dg1 PE0m/IWBFkt+szDRXkQWspbvWpgP9tUA4mgjATOUx3UjESp/tKkAmmx18evujkBDm+q9YYK3Q5D5 kjh3rk8Q93J0KxpId9umHcJryxvTTXdBILB5ekw1X5kfZg1moVB+NVbOXfN2+g+icnIIoK2sD9qg J/AhWKu4cNef/+Bht1zfNbKmEntWnA0BVbe8iscAERy7pWc3fi3Rf+Ix0i013b1gHT2IUIe51fjS hK3XMWh/36eNgpVJusMAfZXj/lJdwRLm+cJbOPx90P2KSZCfKUO5HFz7f3CvZAZcZpU5A9/9AJxu Ap9AFqun2gozONm31DRuVz1y0X/Uh6aSI8LfuSzHTwemCtC6wqYdgvz2CoazuA0ipIk/1JYY5w9f Kfp2iNZNlIzE3NCScGFT19+UcK0rV0MQov9wS6f8dI1kurU30sP47MoVuyKnXjxPEQOTt4nIWno2 kthN4zDq63pD2TZ4MQJgAjZ0LXgflySElVUN3OIFvNovmQAub5NL409ndXRup3GCDzNYl70beW93 Io0n7y+i0+gE7Fmcgps8eoXipgOC7/SdkoS6uBCoPBct++TVqJsLiQN3sgF9jxOPFnBxa3FBfLfI PI6MaakaQxV1IE9ullEF+ei762bKaYovmpL1vhCJD05E5A51cdZ0x9rsWGCpwsvcFnYKunC/vlkM /r0Appi6dyjP9n35j0GEd84UPpi9SKc+/YSebmSrR/5OjyzOgKEQXi8WRVSZKG7XMR/mTPXmclHK 5xoPBxDz4847WUYh7ZrIWuXoI2fJNTw/MJSvx9T6vnoiy9EBDALU1W5OAtjYBSnOEh2mQrnl6QT2 01iKm4Fx9TRQDyvhgbqhDB9j6vbws9XJUI/lomFQwo2Az8GN750jjgjz23gPJGVdd0d9fNBKHfnU xYx1IggPeLIrLUVNztXBnmXm/y/FanmJ1PttfYZT7/u+zyp3NiV1lKMPQvSg469jYvJusRri2CDv XU5dIjWIShhyhQdeHX2UK1QyYym0FKPYjf8ypxdAaDVfZuZ9dlv+VjRMmD+P5YYh0RFrJoyGnyPF IWmFZ1sTxvBI0USjmgl5EpQVdh8C5Qces4p95HuWvjbOrnoTrGPunK5ZYUc+dGbOfA7aY9Mi3u4N 9OYmncVhJ8ari7PTWhuZ3JNvGTgn6pkVNKV8DJ2jttrg8SsYU5RKJEUeFj7XbhCO8Vub6UfckesE /CB2fcDzAMQlnj98HuKVwCfRHomx0jDD3XjA4PdLFJnLSDaEmCH9a2JWiSsJCYtbesEUm2Rr0Oli OkfXmSPBx3+N58g11U7Owqh1+HiURnwhSL8ApRBf9lWY0B/x/nnj25pxpIKr1gGsf8+2QtYQ9KXe 0D+nimDlreUf+bDI717hGeQRO+l2usErKmaoQbc1f+By9jReF9Ky+yoB5j0GQ0lxnyieqEfyOQ0b peboRusaQKvLOIzf1mdGdkwiFWAWnqLXo7hmv2++zFE+oC/LgVQI2WNKTPR3aVjrALI9h92uVKWx jC1vLbUr4VcwHXMdZpk5vTYCcyEW+zd1BbiP8o8y0pryk9QCa+umFBfZ+wF2K7VlPscxMlaBY32x w13y+T1V7hEZRNI/Cl8atf2gHNo11VwXp37FCxYOFGRbK3Tnul2bKWddck9PBIj9r9btWlm7GKlJ VOJcxm1uhRHH8gAX/hpGbNHo/2zGcl9zJIQVtufpBlyFL5LYrKc5hrfs01RHofeFK5bTxPr9vSjK yu1WMOdoeLshn8zEg0pNSS6eMsZMf2L/WSTaK0cffXTfdoSYWuiEpas1ft5KbXad+QQrl0EZzevq T0hWY3q7eoLFhKATQwDUfwhXWp+H+0nlyqkqKLP9kjeLI0wIdCq/lYBQD54T7R8dZZ+QZNk0pFMe OXAnmMxV4HlQWLm+RaIiQC28McmTP0MTayGPrAwjyQwnst1RodjV71sEpaQcV2VuSO4wTjfoZu51 4bF08dvvilZMaUQ2FXQ5lxDeqXABiMtkNemmayDxCkP7Km2kDGilVCZJfbYCdOLYmU+RRB5S36Z8 3nMrjso/BiM0/kVv2DS4E6Gjfiv8+ablRaPeoEmu2eGj3/IdWgb4ZTbqqM8Ds6zcaeWPhrjV6DAV HRvFR1x6UG8mvD2BvbZkI4no/pYrYpyulTthdmbvGJzsTKmgsjEv2EIAH1Jb69moaZgsezXIji6N OBRDo4jnJAbaHa37c02rlGQeqG4SAt9guYYsAl6sr+0UCUUHSWMPqWvmfwAAx4QipijwORVhAvGU xNN4pR0UCqXUI0SnPIbOs1xf51XT2q1Ji77E1WAaMOrGU2uRi9M4TES0Y651OKc4M5Tz6mxJxlWN 9J4BZOKG6VD15+q+3Smd0HmuTl5Lh0ieAF1VonK7OPnNql1u86PrL31Mb/aWfXum14BHqhKdEV1c WM6D8rP5cddYEP81MEB9A+OxUCNPZTrSST5Z70Bv7AC9GmxwzcHHI1XbneHDV2VZ5aLGsxArWlTj j4bNSyRduLYZBq51eZIRWt5jxHqh2Hn70BGCzGqaOFV3fb9z/ptl1o4CNKRdWvrGmvOYyA7Ubmk7 FeRuJAugjoXluaFow3f+mMPYcrG2Z8U3rtcDkKf8KYsc7NjKlt1az0hWHeu+RyRLLJ3KtYegzcrz JOzTX9VltGc1PVkdJyI3oj2ynBodZx5jdVAp8QwdFyMVigh2Mq1qRUlz7aqVWYF/k6/elZ4prsYX tYdzGXmdp2uwgYy578/Ljpw8P2pWFkKiJsZg1ww2ELgZL50hkVM8m+pkX9gzqsxVCSLshrX26G/A BuznBem03ADBnETiuNezYb5N3TzcJs/bIfgEqSHCJrD/C8G1LpX44F2QOkjjYKFKY5U8ILUL5k16 tmIwceYgYX/7VpwMTpgoQgTBJGsUATjSSEC3IzjvClOBWB5gkp+NYuetK+Ie4MFsEE+xxTWLpWN5 gDdMI2eJ9eHdPkPQ7BGTdbZk+NVjYzMKQ6fl0kWMAzytUlcjxSe+56KEbNrUMl/+BfYSvyfQ9R2M jmdefVR34JwSJux6aaRrGF00gpEbYV+zcF+N3XwutvA4m3StV17Qh+tZZucV1eiGfdP4gjhhzFuL igRLEg3K8VjiRNORTUJQEsaVCNDGcBReECIJ/BfwcSliOd8eT0DQy30cuHnPbGziGMBnFBhgIXz2 U8tpnggpWMRRQ6WLtDKJo7jdQjJjwU+Opdo+B3skPFMr38M7tRLjjhsONoD26gl/5YJCgcmyvce+ e2FFK/W6XHp9g6yNxi/NaikW9uwkvfTLE5xUUJAz2+4pbYYS2Y/ZZYuRvk4PMI8mLGEYsk6o3c3n hNN21XfuJZkMky+14MhP5N5tDj4ihBx3fedQ79N3P5dxkGO+AejZEn9pGiqEOnEs/Xj8h5+8iSnx iIcwWufR7+Eyfb5R2EEA4701//W8ZM15dcLP6WNPlA9UCYvUJR0ga32JBG03xaTK9taM3KUmRLjD LPZmZs/pUV7/X8iP0wZDs8xPGemx1RnoSzYjSwsfhxYLFobmzmSz8XHorXCYuJdfNGTBCnOxYlxJ xbdpRn/7KsiEdeIXZ8zRxVKLexRe9QI5qi6E7wB5zL/qg8fKLLIw0xU3KSEEqZ0MxKt/KZjdo9xI d2W+l5p5am/mIs+5R0fcAGxE+4QllIeuLZdt+Bt7HpQhyCSbwpdZ9N49fg86magtBwlPpNKFsIMB zG7xMA87v7eQ9dkWuNuCTx82zmfdVA63GGmHWEamkUYYHKZ8e+W/KRELd0CwpYHJgh9zjn4PN+KO 6SprdF2LyxZht1R1AlXgRqrtY1BjVNyLYBk46fM4szHOftP1dUjBwI1j8AZ2yHJ/F8O+Phu3UdjY jsLCb33vVH2Me7lqc012IL9DlaBXP9ekGeuy89fsFoNBnWih8GtmJL9RpUzsQz0DlhOPnUJN8KCT sWaKTMWwNcRKDPOEERZNgqEz62W0Ikyx+7AEL2UK4O2tO9RQd7FInRFTUXjhf8CJhE4thNs18d9C R+fbktEw+Pip8vOqzz/IPJbIJ64gUvcxcnPkjqTGB5K7QyCYryHrj30AScBo1N+ipaERnVIpcuLF 1vJRv/2DJDHWBJqlr56I2Z62R83zcgmmIFFtDa+5/75YjHmlUd0qjcn1oOzSJc+c3zvT5Vqat5Ex Qpa7NV2yR1FTQM4sSHDcqxlNO4h098Q9RGbl7t90AiHHX8V9HDoWCEc7s+9fQ/GiRZcNBFi6BWZX 9sF1DlcoF/5zUmha0ERm0p2eITlKdhjKCePcMy8GQ2E7JxOL79XRtvyvYp6EaF4idEiFYsyIiMZr 63ojBxu33epxPhc5UrTzcvL2ay9erIXjMPvjtzJYxQ1EJ/MKdPS/K6c+vIt+iacMLrjmNSrSrmVv JnCR0iIBfBlmOuR0xsEjK4B+1vZA2+eNXNrSdSOBfy5fc+nSAUigdeJjk5WFpNZAjYgHyFdjwDZe i6/7Q7Paw3t0OP1PwDmD0HWpkEeZf8JN4EgkXrLXp8nTPr5fdg98Jmi1KqT4tmLaQX0+KuvKZYIf Woys8/CK7ES95aSwXSxUSEoKRaS3EdJwKt2qTpop0sR6BwfAXnU0uW0RHN6FmgX4vcj7YF3xJycj dQ8n5hoUGeM/dRRqj4dRb8K9Cac32JN68pKXvcw0BGS2Y/xi/i6J6nVsx4Ta0SG4pPOHT4EHhiJr 4Z6XQxdp1r6EnP4aoRPf5+Y7+XDSioHdI3X5HntnaeVWjlbFFplkDTkWG8Iguyx/6zDKG4CnxaSd el4g3tt9+oZJXO/jHrmlFZK14z57tGRnSAqa7hNFoJnyoV3Z1+xVap7EotI2s2/I7cVv35ImTnoB z3/5WZWlN2TWlQwR4DIvdsaVVEDEadlYK9HKMa0EDeHWFNoj6JNWsprvwMMbuuDrIJGFDdzDQ3g6 JcRQTMRNoQULstQamK8fNHzgXiQFChvDzov9GfYj3atR3j9M3KCW1mKQE+/ruEh/lx9iKloksXhO jTeJ7bfplCLz/vZYJb/RriYRurHm2KNkmqp+X2/MlRk5hdloPHTIf+OuuxxeJfdYK0IrBFvedDYQ 7F5pXdGAIfwQ0C+Sl/ld9i+vXu3IZlPhexR+vlda4kNZbPZ5bsLz6ef8Af66zTNKn3zwrHFJZJ51 GalKZferbNsQpaToO7mWh/i6K/mLij0/sP3p0oE8NIAHl78a1oOv4IDBNfVMYMc0K6UH/ktb4eHp g9bgvFiqG50tYJoE7F7W+WQdXxiCN4jhh5dzi+C53pc6oMR1qIQpx58Nb1aOHqHTbpC+WzZj05Lb 4crY2q56kqdnQ3kZEMAFX4vIbEIElWantCTdk5WbeaTs1W5g2dxLDbGUQe8D6lhyNOtBeGesofW3 qgXc9UufWRM+MH+SI7tLyCCTD1c+wv65c+Hisj7RcTSZpaOPjKRv12eQPj7vH/RyASdpWKk1lyTp WJREPxjI2ERWcv1JFp3QXwl7JU21IAgYTuupC/M9Br9mhzVL/XfscaP1Xl99wo11GBU6Iu209tM+ 3rZiiNx4V4OpPRDDPuk31BclR1s3sP5JDNbreFm+fQ2e4MUHI2SWyesUSXX3xsAqa7bmWaExfXkR ApCL+nws9ABx+REAr2wZp4x9g7OgV8b1Y/Z2myaaF0Z52rGiWMpiLr5QXiydGJUMFjHeNKAS+WhM D852GLP5/0I1VJb/0S4dZJWWVO5SOQHnCNi866hI7aEqL1SttIHI5ccQ+O10CxviCdP+N8OvuYXM keXzGxKTFvnzZ/XOriy2KsQrkXuoPuJyqY3T+IBANuuFKTwcQVzCkD6zQsfBAI/cEJIr778UyUDQ HktFuOihF3WvBjNghC7PsRV5vvb1FtsXC9KWn7BZzKB5cmlfeOhWcXPwI46oKWkzmArLJu0GBG+B 8G7ym2QRVlQXw2Kl4Phy6oBxn1+6ae8sgrwSljQiExzHJntgmbtgYbTd93YHMqUJkbv4asFE3ZIZ dg47m1eu/vLlY2u65fX9oDQZWFWRWRMzdXU9oxv3CiKYCb+JCDyrWQ1wlOOYi+60XUWReXiOJLWw x3eyL+zfRAfytZBHqNv6APn4iWGp9rsjmCevqR+WHAo7HJ060sYd75Y4O+tAyfpbfdg1aJp2KJOm sIszD5nzEKX2GLLexEx+8sBWzniBOFYSMY7eXB/dEG8i6NvXwDRW+sAKqvuUvlMRHNOyXDj90Yg6 6j9Hk8VSbGNmk35LvniZHqCJL6B8+Bo5NWgc5P3tMwaqdfDOW7uD3rFGNm1BHAemQut7FaOLEFH9 YbxpYlMTivQJ4tb5Y9yJjWFGveVZfyxO/+DQ9KmWf/8t3s4TYgdqoWVFRUqvC0maHVBgXmUrdJKg e64FSXy0FPR5AVnm0EuQ+3bJ3xcicbOpjGj10wJrx62SUCpmpCL+QBqsxnPvMJ6DOdAMqFLcrhL/ qtyoV25dPqWfo0zMZyoE7BwC0mlHJAtMpVTvTPVz774hEznzF7GZbzH4DxmTj4k6ByOJuPXjZmS3 NnXWtlV5wO594IjmFxCAJMiyLLWwpkuYnt/se6aQL4GHPVEwSkkKsE274X/2ZdJuerd7GD4thYlb pwe3ZX4c3Agih2sEGGO8F6HpfSfnjKYLx1Jbc2Pep/UZAWLxZoyRDE9CijAuqAAKuVB+Vf0Txme6 QonBm3nuKDhWfmhoTAj/HpJKydyHjbYTzMo0uC73t4JHtMh3ZrO0dIg2zJIzMtltY7CbrF+DKkEs Xd7tuaHiJhm9ezTgZpZvXIG+ayZuh+NPit8tGZV6rvevv+W9G0uhjBmBmxNdfkvdujzJOD8V5Gft oWGGIyiaQ6ygKC2Mr1hxNXWJcKUIWFbzL4me6f8sMcodvXbLP8KqkB8CoR2WZH7VaBr2p0duCMNw 69wy1KyQEMQipqe2rcVhc34OsqExASPeqSbGA3GIx2yeA06yu7qWA7luShrDkCWf6b4zeU2RisLy XNBpxGi3mDNgQJ6W7MsDbBJxESazYDJpdgb2qU5MNXy7l87wxKAzTSStq6029AO0ak/W8eMDQUMv G3gwKoFilX+E0+HnMGvqlrJ7/+PX/gj/FFWQef7n1JSACoQruSCq9sM0WcOSMJhE3vqmW1QR3nsX uEh4sZXNr02m7RSk4FtWRTcltBnZTrspwAsd3TDRkn4Qq5OIbsUt4SfBzohL2oXxjB08qPrWG6yx 23df44fXMz27NKZxdEjF09RD9n/rylStOWgA/6kbRb6LFnn2T+tPhXKsh8bLdzrHo4nLmNSaXcYl QNd4kP+GBGALWejqe9PC+HoLBGMyqjBaD6FLsfTaHA4bTWZXzbkFWe2erTZrqkIIEIHdezv+iYSD oUifD0yRMKTqbmwx8LL8nerB/2GYWvua20ElfoZjKxEnL2feTKbZZGOi/2sKAbD3MtXvi4Zm81YI PI0pX55iPJRqRTizcLO9fg/7tlHBQHzvJnQfsyLVdOO0hLfzccnG1fMe7/bKCPx36m/HBgvCfhIR v7V5RpIjF/RGsCH5BsP9u2Oi1vFJomCaoDiAfFk4gUSTO2E1K3xTW3iSs6gIMsCHoVnmz11Z1js0 ed0xQUynJGQfY3SfcVamZCrvkY4mwaIhA7ZXt6Rx2XrKESPg3yvVKU86tq5NH1hq+PSJeFTq3a8f qi2N7mDh+JfIKdQjCyGiQu9lBbCYwSdOyVmvyY0k/zlfA47TApqbd8IRI39Vf8CMmYiwryxxeK3v LDPsAcsOvsJUGBdVlRTPTiCWi2Y9DdkJBtZ46sm8sq0fct64xRCzNkr42ADq4PlMIDwy7iQH+2X7 Yp7OptICAExCPxT2NQ+AMNJcja5+W349ReBhu2oDznsfx3dV00twJiHPxZghSnCaV1UYa6vpUOM1 exkHB7IHlig30MQtHRiFvNSL9biQRJWr+asGmRq9wPs4XYs5F1SOo5bUfDpXjbChegm6cyexJf86 Kp11NdzgVPa4+GKjPyf3j/0jdhelusIE2fyjjfwNz76zI7P/Su4Jq7nWwvYechw2VsDokDvlZOy+ c1Ofl4Wt/K32siSX+hVNp0IRx5f8vjDigAtiKMciEQOeyDH5VWujCtz2cuwzRLFtirKdI9xky9bG r8E+oMA5Z2x5NELqsOwvREL83g0tg5pzdFm57NmwA+ybovm2InP7V3j8VJAg/desRtIEZd/ksd8w eZ1CzodoG514M4108xjKzVpstLMU/owVKWMLjuptBYZD7ELlQtTM9AwnNIn41ze3U3YvOYCDLvge F2ASlqJ3QzLmxcG3Jc4wjjP4nJRnSAnkamLvqY3lRkbP6sQfdF+VH9FmQJLLE0xtCvrPZKHDgkgv iRx6ytJv/M1sZ+bAualct8Mx+JZcG5qKL2whYNfzg47bHlhXunVRMRTPWj+ylHbvfvPEh65L8pmI M9qOvQIbRnkbWu7bHvjewwK3gufrwhIVUz2vs7jDmYK7A5djKG0ax/cBInwRdxCmYiVj2MxkS+11 H1fOhbeTIk/H+S0dU+D4hgPdwzQzNokAVRQhH6Gy5CO14nSRt3HxQX9c0i80AiYRIa+eHE/zpgaT jJT4yyBsuXGCq6JQ1v2Cr5124p95KWwckSHvptP9nSlUHVfOHRrZWlAAsLDG7TuJPonpibvCCvWt 7Wob/sa4ZyvsvpDOnzMGErFM23wxDChkwdTNE/xA1ukwJUcJIpS43beLk2q9ajcrROWik0EfLp9y QU06QZ+FM8vMmR5g/zwkVQr/L+V2ykqikconc7IK762cDXadyQzKLokcvV1OY+GD9Mst+jPEhIAx RzMnWP2rQbt1ZOEiXtImKvRoRy/+1/gT+ruZuN0/pz/zwbTy1GngVYeVCdDWhqHeAv/wOm3w54CP twbfTl9ze2IonuFBRIg5Antj1zjdg7P5IPvk36eLsQMms9WBFaMaDNeVg5RtPjPHvzdjjPyzhDXE GYjVND0LfJ6mSKHO3Ip9H+o4Yj5woxXcDdC3WMU0bjo7xc9rAWlb44WKLjo33g+PcTTb6jy4oJB+ rAWb84HtjBWKYSw8Hgz/+FIhg5kHpYXhb24jELfth4plQV8j7q2rarnuVX3evs1hhQtRvEJYjC9W P+lrwc6dTyebvD9fiJTSsvP7R5HamkA0eqlWHaGiLRBEjYZ7/DY/q6QkE/RDixxxRo8qBtcYAiPl Jyv6JDO5sFdVb1Ar/pkRelpHdYy+gD2jnwpIp9sMr62jf1Jp4uuXZG/NTg07GvKgg7t/vogTphEE u71sAisYAJYL5APJr7ooVAw4rPwq+xInET4zOdmx3lTfxXiAN1t1SnyiZ798T/S/PoKA6vsqgWvS oTcpbXf40Z6jiAX/jCnvDKHsgC6f/efGMCqG7SaOqcoCm8m9M5v+Y6TRxmDAgO23Uyqo5CsDVMUU Jr3hQlf6mYLG2iLtASqp6oJ9++sPZaWjhrgvZIv2Id6Y0BRmOjLbCGDJGrA9duMluGIG7K7mkHK1 MU2KeM4btwzOpiC4qY8ZmdG0MRqLKaIBQ1TvCzXN3MvCGO7ZWPv0X99R+GojsUlnlQtxdtF9vZ28 dRKYYZzShQVd6Ej7EUyz0zhsN5CIL8CVewzWMde2qWfDgFK0NSb9q7H/seqrIVtteDmaiUbx5Lid xtmDIBlUcBb0fpOTvQp3wAGaP8KfZE9Vo43aQiwI2+2PiDtRCqoe0iS2HbEWPqSNyXTfT8m4iSbB nFz+QtmRXiFvlX3aUT7BofJinOE0jGVcMwN5YdHByBI9fwkyRMmDvmziNcYqXqe/nptxm0Ckh+h4 DFDD6St6xj4upBlve8aZga4wgOo75Je0doZJQCqbt0ArHEcByaNFNYELH+KleqbK0tXBcm8DDcYN kVafkk68nAJfZCX2I/g/GKQV0IYjHNxxyoB9qldIuyVuxLP0HeUSMy60W/25TiI9v3nw9I6YKYU0 sEnuiPrCQMlXP8nXkn23JV22hI0YCq0y1P24VF7nS/3W8QNpRcxgvQZP8v9uwWekN0Yb7Htb6Umy dS3OZBwhmKQ0ULRw21X74RtKQSJ3DORFOqeirlUuiFCaCVLSJC7FXsvxOChMJbLH5Wh+MPBEuztL t7WtuoZiB3P1gBj1kcSuYwIYMlSNMLJvnRpmV2fRFG9jtXdBKx2k2C+6xxATpj8cwk+yztWZDRjD sL/HJtYZoMLhyiTASYN0SFmp0G6wxeXjl61q/qP1V/25igTGULu7NHEuS+PBQTvSZS0VyZn8DG7A Q2MN5kArzbdgte+jr5TtchGkW16Wiiw+LppUqeFefP5AZ5/VgSKgbusjPEgraJufqy3R+kLa3t1v iE3sPubiPVh4Tv8hFHo07xD8XkS79ZrDbLck+/PDMzPD4T3BZFRTckFpQNjgt+DkanGV9LlXU2hj NUvfSKngVmkrg9khlbTzIFQtO4Dxxpzv5xd4D31COBAQ4fVXwHmGeyuwNKYucvAwhPaq3AgfD653 jf4Ji8Yj6izpVBuVConCOIiOkfFNMTHtgWCQWZVlMT/wAb0Qno/wwqTGuzy1A0za1TjQc+Zmaf0e rq7kM/tYnH5oOQltbG2iGCqtdRGLcBv7OAnDp3WUvg7vc+Z5dzTXP369caSW/AOUvpZodhE8yl7D zgxhbvv4Jh0wJLmKWwCXl0t8A9mikRk7GQhcAHdgsC3cK0WCGtfLTqjbNH6dJMcv+lanxNJBeYGo 3Fl7iohxZBKoJkziWJgQF2qXIfM4aekTj98l74+1cO+MW3CJUBDmXnvgRs0Fe20kOdqA3kDGG43R A600j10V/wyUIERVhU8vO2y+sduUjEdpRWAreRMj3fzSYfkeueWZk2e+mQ2fxiq35VXdL7ZVwOWb +I+Zl0GWbD3Hg4n4xvAjmc0XHmQgnLJs81PDM8p/zHzJZNebbv2ffowsnTGKFFfzAi+bDOTVfQlM f/1rOZ2tbjuMjsE91XA8bqiNkPC4gLvtvssIY5MuD+HOxTw+K4n+eOOX2PP4UMQndv0VCZ2yiBMT 8/hvIRFScGSupOQhzvQi5qroVQU1frEE2Igabw1oWZe3R9GmliUPChEqW8UYW4xOQf3NNPog42cB +vjFJpDe8fDdEm3t5vq166lRCVBAG6KqPvkgZoUVgBtEVxC+BjYTwZTE0S4UV7xevpFK8Ewtqzwr wfhcEM0LJBAonuexdksiGI+lOpjn6mfQS4kq7CoxUzCIJ9f8enYVTQf8Jvagnc1G+c5llrehUbwf r2E38ZyhPFvlWwSw/X2FXtyL94/ixpsQKmeiXEID8rBUrKto6zB70uXWb94a0eMv4bukrKCOLidd QII7u4morr0KeS1P2tasb/s/3MGzWT1and6yTluR6U7Ua1JqtIZQsByhOQom13s+KGPBqEYrp1MW kJc5mjlukiLaIl0pPAh64mVHsHqndHEYVeUkqh1dzab5R9iWlnZMkMltE5guNXmCeDalsM6LPYhc ZyBpZV18iQCCDjY2LwhuwuCnrdwwYEdChcuoeYBUNbH/YqCgoI/fUaezYpxiSFBwzumZW/6w/JwV DyM9KyVbhIQrE322IqyqfWrWeuveCLbUCJP4QISjGhn+KLfeBNTRVXoCmQ/6jZnHlVoRvnSssQNG GqnJJyQzvSU3WlAEnrtTTMBjjqcfRIytE16amE+D1sTeXquZh8ID6hXOv7at9bUsbFUVtTLgJP8c ocHD6niZ6ikkVEay2IDRrF2nT7wrRq5w5kq9wPkpDENVpuewhy8vfr4IGbY9V0v7V94EUatOjUqW V8HjkGH9lzMkL0yGLDTQXYJ04PLegIOSqyakoxlEvasLh4CABzacTR0nUDR30zTYRNFsvy4PMgnX 3GJppbeucix9PJbf0MlckEUFtirLYTJ1+1n0O9gBPrE+BhXpREhhhlX0Gw2Bh7TIJ8TWVus04nLV JvFzoCwzrPc6o+fFCRma3o+ETsZv2aN1liClUqgzFlaYYl7j6jYc4TTJlgBX+cg7D9b9XLUmHorM sBsUD2/tWmMXvT+BICSPfXFtodFhHJUZ5DT1+89T5hGvFwhcf01Gg7+o3k9nxcm0xhOIUrb0Q9dj R85z6scWB06yobkRRiLKidCcYqfIvATw1IGrC/ndIu5GOcJFVUV5oFgADUPGUzS75b+uaFKiQIdW bIhYlCbZ5LPMDizsRiXDy6cNuZOaDIgaQym1ukFImFXPuqxyu1NQ5kSLUuwBLUwTbi9zqwjiJITB mc1WtbAGL9QJlGtxPY3xHbRIsrluth2DUpBdgcIV3jSdKeGq8OGPPJKFsh5FQ3PQDV/oPswsBp0U m81Qz9lsSy1/8SzHXAIkWPhTY3y/Sa1itLWIAU0mOgpWybpXwiiuqPXgDaUey6OSRzfYOKE8F+7f hANLs96nRaSB91+aEfVAspM/a1j9rn14via04td2WHXEsIsHRSC2j9QrNsOd0xROnTcZndIJk+kv 3q9eqCmtxvW7cUlbzyv+XWx32jpMMVkPcmGCPdgVrQRrdtTBvYrjCs0O/rzVGtxu0r9CWTfpFRTB wcEDI94v9o6SPz+ylY860SigwaY8ymgqvcJZOA0i7xNZfp2XcAyFPQHLtnbQ9IptFKISo8VT73/9 WG8n9ar9lIobUIxtzSQPkPZFGAOuAyuzr6+tg8GEJUk0y+vwNAQ5WkM9U2tBvXi6pKyePWN0ZVQn R6+j3+QZTb8wfNEuPURcAuZOC8hpSG2q00Hb9cq0pffMsNnAS0fCoVfH0BpESM2m13w4FsLiqobX biiwRWQ+n9s4tD7VhZCDyUOCkbOaCp7Rx4Lczzp96rczHTg2IW/Tmt+JpeSFdaBXs701ifDwghM0 t+miWYLs8s7c8PYraaFI4quBVOViuWYlX8fB7X+LHhwyHCeNziXYRUNM36fgI4Ql/Z89jvJeGOsB WnZgg/L3O8wM28CQmwGsFZSaxIuaKVbz/We/ewRI0Qgzo/KLyN13/HcNUfOrBJyffn0PMTcePypK 9AIHKNnYPhH4ZSgi9RChz5tdzI5l2T5lRoI7DB2ZU/xcgQApMn1OGuSZJtiP/vLXKf/kL810amDN VoorXW/0ZTmQj4q/BDhWMvgj62pyGkO0AbhM+fdHNGX2TdFDpZaJ4ctYgWuRfsqg/Wlulr3Dig+y vhkx/dzlPex+XrZYDI8zQ+lhGrb2ALVYmJfFm31hbL6gkT9ue8LOGRqGA6MR6P5qflfONJOiOUq/ aCcM+UeojuTvIKnxfATW8l9yIJ/9NOOOf6IMTbkoK8gr5UGSQsdaBNsxIt78vLaqnWFr5DLVbg4l R5lHSlz8VzOx/us3R2/+COCXnjP0/OhsWdykMvry5W9C53GX6nihkLx/9bB+SLxrlMIAQAL4whXN Cr0xTDqpqiE33YdGGHXjf9WYd3jFObBdjzxbv4UyaeIcku3b/IDC8WyJPoZuSuQXr51vSxSQcllg M9G3/GPG47P6/flY9/JhBd2DLjumI/6bv6dnhxNPNW6EO8cPAdjvc0g63MQWEwZQ5ssA1gAM+1+N 2u7ggxd3trkatK1o/fu7VVu1LajiIkiMX7QPoA27l4gwtCxwgEY4bBv0ma+wQ4KiYROPO6F4gXV4 Np9i+sfWum8TzP4Oc/T6fhsq1R5jkA030Q6PLrm7+We+6YCECGXE/S4Tykwsr3LcJuoaPM5RYA4o EIVNfpJn1CtLMYxJaXN0ZL93sdORqSjiEun38ffMxzJfZBtMUB10DO52oZtlo9Xy7BgG8Dz4/NLs GyrOpn54ejkv57BQ5ryWG/fgUr3+WB/Ad1tXa+cHgaI++fQuhUG71WTNiBeGxBqxTIgZurFKdeB5 YRlh5lz+OqjbWRg+YK2+DDuwHxLMY7dW3bj1ZJfTC4WQH8D45RybJ2fU5aOdnJ8fqS93TC2X6uXk XjQl5AOKDs/PDXk4JO4iZQlRMqyMpDLIbavKVfd1KCbrpxUiM7nbk4g1X4Z+tEpZKpJGmF6IWiSk zUGOn91sJ9lDcUQ73FPhJ4EePLf4K2GfMpqSQhlMQaXpKgnuWndgDRuP+MKQbwdbr6EC4gUPMjp0 5vtUfYlAn7dOqwi6EkhhMZXuZIPhXvE0I5nNpZfpgVh8VHR3ZIJRRGakzeL1Jlb5ohlc/VQLfRSv 8tu7FGnacLPkZse0pEt7s2oatn5m/ZKNZr5bzyo+dXPpuTnMMaYXWp2pM2Tobmj1OZJjX9b9ts81 5dEaRM8U7WaRYomLZhxrur/Mo/VS2cvBvUkSGAi7sf9JNa9jDTplykOEfKYNfkWp9it6ohdyfx4y eWJS+DTogsL6UMdcs3BXk29LCQS9hzj4E+l+y98Spn4IvPQuErP3kjVP0c9D+v9uyx17+O6FB3OX OvJLM/XgY2OyP5qQS67WxNM8dFTqsHH2MlmJdy9jAdycnRdMUim9rGrzN1OVI/kxb+9VGnSruwHV Ontvr6jai8j1Sp8widsgZZFcbY3vvIswr/HdzG8Kyi3nyKzlmMgKiT8R3IImhl1tSa9YcF38XZq8 GbT0mAmqZtaVDOCyI4OVt5Mw3Eaot18/hxMhHZcwGy+kMjTg3Nh7P65w+7+LXaAeXdCckddGOet2 la9ZpSkNuOU8UyZRuWaOKtjEd2HFRGKTM+mjjV2kUtL93GLNIUsMdGBGCyd9h/ljuQ7gDo13/bo2 Ybl4BNLlYHjXeI3PZfx9shXmlcj+8kl1SJiP6w4rvUQiBpCgn6/XVtjn9opVMUo9GUf2ww0XUk1k hmMnm+44TbLjDrhKaQfwDqAktzpZ9OMjmx0aZMEY1zMVJjPf3C5I09srqo81Wy5mgLXJt7s1RGDQ RUnNcsUfVLr0H8FaBvna3HpE3MR2PzU4xJI31o0CPk7IuX6kujs8k8daHQX3Hg34TtG48sy7uYjq OX5vx2Ec5rfjvfghDwBtue+IGyT6sP+zSG7q7+OG+uMYyMdHOTSvmcGK8u/IAwkdFPT0u9BWHxen AKqBTkt26AdzN9yileSzuuo55dQs6iNP+5zAPDFV8LiMBFEXq7aFauVocacIZyxy6TPRzhax5CLz 4G0r7VSUAJOqNRw4xp1n6fDBu6EIzVbl/b2CzRz9SSGdvAcUg24m4IlVrkdZwJul2VHuEquXaMQ7 IaLjJOQOUzuTcsa3ZuFJL2LrdAdeR1BL52q45aUM7lJSy8rK7+lXUfcySlTp97uN1TS5XFBjRscp S4lQ6bjLb51h4E5eYZtbNyioo7KR1yVA3gnW5xUyE3ilCrRIPXeStRnFaAZrn1k4Qtsq1uuGLB/L BmN/JgwyJzA7bgcyLogECEHeo/POkmHJwZoOMYj5LOUAZl7X7wm5E+3M2dt/QRt1fMExPRqzf9AI fD/lH1bxleBFkPaubOtVtdVA8zXDthvWc2SFFPQCmmuOZmjWu3/QW8ZAzJqqukOQ6dFAtGdXMQgJ gBlmyMaCVrqaAtXta0/z8m10iy9o8q8GecKE3hdnECqGjL0l+DwEyAPHBnymqQak8WARD0Qn5d3H wTZWDUKqA/ou5oWwPzUeZCtYh50ry4uFvpbdb6v8MyY8X2+Ls32I8/itmA6SMA9Eg3U4Bm9GOnY9 MyPS+YATtK5Ir8RltyXbS7pwgLhq0gpEGebKIP3Rvc88PZOnqsji8KgdXaRGhMuabj0ljVnTJeDm ho1gac6eeXtgNTxpuCzWuWEiHyfWi6k2gMIYRHQtyP9At9DtC9KLjcPp6Fo6Y5pR3pu3641NL+LC 7dugKuC1JWIKuC2pTcnBvX7fLPb9/YxRB8JjYd7R5v4eyF2MQEv/7s79c4QcE/KOUevZ4WSnKf9l 1zPnmUmSqunsZBfw4goLIYfzqKd/WeBfP05cj6VOJu2D79kzjomFZ5RXxC00znu+AIEBm/lm0v8B dB0Lm9k1gA5M0Hfei6383RfB1bbWIFo76bmonI7w8PDfNFnnNbrRdWD6pwEZu07i+mg9/S4zVF9V JEbNGIeaMJwzxzsVuYmoBOGqR8KY1yYiIOKlLAZqh2CJWO5oDaIDB7rYYV/Xo47kwazGQIXxfAV9 nrBb8QjOpEqCMEQ6unmgI6AP/fbHwJp9jMMARq5qhNeYXkw2ctiAFqZ5kjAnVRSyE7GZOyAQHg6k ND01vTuMnoODNABy532sGsJO7p9VhIpf0w4yZL1o4dif0TcX612RpSwMCD/epS1Eb3kPuPMK7HRK SWTjsh3G191g0OMrWwUi07f1n8ZXs2LX56/FitWlFH/MUJoJx3StAnzqYyW+lD34hJZbU6aBme+g gFgLz7zgE+ybybpxv1G0r2G7i/lSJtdecOtpVuu93b3bjpKs6kfgR4yZbAtTRZX4Et0X8Wktlj3J Umnyh2A5iicuMan3ScgLKTBHq01PyDC65ikT7I/tsnL2dYdp5vmiBXbhBdWw/zG53eAgW7OUNp/E 2nZdE/X17bDJ4Q1eV9pegdz/soW5eMKwTjpjda7JVQM4Tjl79DCllrSd96e9gMN+IsgEWL1xS9Nr SNIrwTsC36+AaJmsbdKJDoY2WmfuiLFydfs9caO0ayfpXd4xweqHPe71bc3MGiBf9YNiL16E+OdQ 0kHQ5bKSQRo43DdNlu9X5aOPN5LzGM4f8YbMg3F042kcb2cX7Kk31LArPaDKRY4fdoQfok3+l5Qn 4UmEeIMoCKzE0/BNPzthwTya/WPu5lgy/6fcwrhgcQExCI/zHGIpb/O60jdzeF3YpyEbBGwc9VDo 0c3538burzfgzX2FLN77Ds+3LgMUz0iSbhvZ8qpnwEMbpvYHS1PWxNUnRPUWmwjGxL5X6kDhRnIJ BkQki1ACp4MPfPyLcdXRQgoEJ/NR/cSeGiUoKL3FveaZzCP7MxOorhQfHxisbh7BrdC0glOOKFXU ThHJDsMKWKoyRL1R2W9+LjrkkUczFE8GXgbCm95cwPwXcxnQqoGJ+JBL+BG9QWexi6Ga1iZMS+m9 87Pb/sTOXiZAbWE+s7jS10tt3hJUZqgc/419mgTxrJxv9Usc874ui2RY0R0CgD640ORHJtbRQ2nT wuYIQuYEiwbzCDRm7dSytGNqyS0n2GJGCTrB2O13aL/AFMjMZxC0vRvLvhFwy+n13+nFU2/MerxP zFeiI4ndRU1Y9EfkbzJkLmdtOnwErGOUmO2TieGMPJzvSOvnuoeHtovwnDE36EOZT3omC7ffVYrQ MZnn89XjA8TYE+MzMgnTRzqN/MOIn/m6GYxyeGJYRqALKxwVtKSAcMMcY57dBKkX7tUGGKluVbCi E77ZwzgHTJnRNHhy+U2JSLATmylVXVsLSawth6kg7pKVZkJgaZOSx4EoW1ypsr5Zaklwkv2d+Y/d cuPdMMiCOEmQYUuRqNhhFhS/B4NSLk+lryULidO4uQqu95bXAXt9FJXIo4FewwEhXs8jVocOWSbg cHA7pwRingiIM3el/dQShE4Y5Tnp8kZ8zhHpk+CfIXdcmsnGAUPPjPzKHEAa2XFiePQ6Zj1zIkdM Dmk/vzwAkBjDcLEyOJ9Hxk4HYWDwPrDDHOi2e+0lri0HDAIPAmTzwUoXQSau9o1e6ZHS8VPDswYn Ct54BhWVHwUPXwUaAIdaBqTHraXl+kVQbxEtwymD6ragocmX2iAcuHG8tcVMzuJeMYz3ommvSM1s Duvfuv5h58Y+ltdEPrX+y0Ak6SjAIgA0mn9A3dNSrDc4lax2Z3E30rBYbEeyiwZ4xPOmLlOOvvsY XiPD/oBZJT+WdGKW/qWBBypjbBtJvSusuKwxjFA6TDD7FeCh3xul05ETFGOpbd20nKt+ZiZvQxUN nQX9qB6ljEQe1b00un/FCCzczYRmmfaZybi/p0lukuELK69qqCf/mWe9e3jKDBAa4JjXy/sVuANK zUCBrRdE9arkYEIq1/quKSCT3wqAgZk9Hm/kkNgeMX+O06X0EkKJbKvklE8JdbsIYshjMxW5sdWc Sr4yiUZxOn4kqEeZszsPu8aoC2ruHinzfucGDe+k7zUlmkOcHKMkQrS83q41j976iHARbO3e+F3P 0xwHplEy5/YZcLyXfg6qhq0pzwoCBkp6ipz6WPxF3wlpHFjRg3X6X0NecuFvB8jJC9zruh8CCGEP Qs4z16xdA7Hg3H+O+YRX7obhjecJ9bRchcvJLyHwU/tgzOoBk4qTJkvWgo8sTECagOxhSyzBxlTh lRE4AMbeLw61WWoeurxoDLWUhBoov4k+ah/3f/+3MsYlm6uhVpVK2Wm59kNqYNUzI1ankQV4YBZq s6L6k7jndzre1Ko2vomwuuZ/T/RFDMDvh5IUHVdIqGhEg42UpqDTK2os9Y2ub3A9UEQo+k/Hn+7v aJvlKNTsETgLVXWYxFyCTJfyPoKHvJ8cxbelxVk8y8NjBSERG/9nBA/ZP+KI351/6Nr9rKx0nEJ3 LHZWitEq6bCcCzelSzGS/ExNjop4fdJKUuyttclhTZeyDOhd6k3HfBPplyXn7OsJx3db0NWUZKit RW6kDYIKoAUxZUiMJRwQOrGGnF3AY25MtopEQysIIWmFmVTJT4bJO/9DrSF4KHCmaBexWD0qQsT4 1/N4BkHEbRiWtWGRswZOQj8M2TNS2sDVxKZeCHoV35E8Jzo4gm+z9BER+SsR2Ua9pU7yLOXGZy7i eokAEQhqHreADtuNPRpthxdwn673WiA7b6miLqe1/kI+WPYu7zPC/AtqkiMxzgGnTyWu0a21zkFv To8UGxs9jTv2TgH+dN30dBjJ4AVViTBiIj7epDXciiPXcYvO3l0aDwufiPhanThOsYQcZaDr39zq y11/xj7vEkZd5J9jHd18+vNCFkt3UyCj4G1BY1OAFOCjxjFnYMS96ucUczqggiY37NN4CTdbcts2 kOYe40VKeq/0qznMbqayCrjDdme9Yloy5kyq0nSvmAJygLoOgMkhjtPicPqU4JjC418+xnSQE+7D +7F82gbEeU5tQjXEFapsAz15d6J1968qO9DEwXU7vbc0RHcnXZkOcbo9rW4dbV3pDv/PhIEkHtXE KsgxpxztYdfckbkcxLA8H/eSYYkdipKzFSq7RgjSywaKuPY/pX54g7xNyiK9dd/mGUg/nVoL3SZ/ efiF6Z3lcke8PN99u93t8tD6sj8cdxmF2nx4AId9kDK4OiXpO/fls5kXp42yy0JpC0VjCb/TWqco 95c6tJ85sHL06bXhKXfmhEj32OgLgBT6FqV0WKHeWifmE0PfF/ecD3cXGaFQxa+woqYrFUAU3Sii pNAQln+TjtF4NL27EE6I4yIaXLksi6Icq8pxVPYie1AvAaF1fry0n18XVNYmVd4TVIy7Ztau7m9f ZTrW9uS5AEjGK6ZpkKDxcCMNm4SWUHcvxkVUrptjWBblo5nOLvapR3jFjp2//UdgBRIuKzLIonoo +mEGDhA6FB/Ztl4fDRoq7wytLA+nBottxe/Z8RIlfdljuaCCr6wy5VefvhSI8Hq3lBhnhSdfqnEI zrCEsn1vdHoWr991LGqB7GNVigmGeLHSROlqFxhcuL+pn7fxr3CgZbF/aykCpBOpizZ754Pn2+BF hMVR7c3pNj240V2TJY52ys41qzYgOX/WRYcotYq9OoMt1nFnkEwJ5Cxrd6SzopTM8/A6QXak9Hcr ZnEp+f869jt8AQtdSFzUVD1v/wfFpIwG2ocED7EInxv6fp8SriKVp+DVodZLHneifczCT0XKL3tv bJczDrBiRkB/dj84M9L3nNCgnGIdC/0OiGwvHS/7n+onsr8hgGiQ49q/0y4WdXfmZrTx3xj67RSR gEE9EedaOWF5c8YKMp94PmnQcaphMCps4LsB5PRV2EEIkWZb57e6og31LYQmU+Eav3AwbapHlqOP +n0ARBX9fn5KrhEUyHCC+fHMLVLVnytqBRRflKK1ADw3OAPPbgycIgyFd9G3YfRJuuk0T4G36L1M Bs9tPvlOu2ZTvPJgWny1xkWSF6ju68SqE+8X6HI3ncE0bNEJjd2Hguqma9WVLuJbzjveciRaIasG 3IqJK95AHyu7OukPaIAY/r7CENeCjv+G0gwnhQTekfZNmHcYfxr1bh3W0XfVNp9ZaGI0yMpUJvFA kkPBTEMGuP3Xu69lKfWHjadqcnEpsiR/WZXS+vdH81yloCXmQrtti+IsVpkNE8j8Cg9YzUXXDSO1 6CREYm8UzAFyCmPMCheyvV/w6tn/V1uxZsTXa6Nkc8314Yixv42VR/UFrOpvzfrhPBBWFtQv65HS bBM6faot/jkoLkvZzqzgRMfnMkIeGEU14Oyh8VbfRipf5MTcWFRRE8Ce/qWqRrvcNX80AlgoOa5c 0lE7BD3O2wwL9f2Y+U12oCRvC95EoTJcWMfHt8BUS2OTCwBZ02UIUI79KfaIZj+0C0vE+2Kw+rcS zD5jakutg0pSx5XKJTiEVLC2dY764NdR1bdLLpfkeW9yxCPlsA3K/j0kZVLzNU2/qh8OoG42vpZS pr4Hs7FmZH/rmITU7vGKhPSkplg0094wtF/F2aK7G+zirTQNOebTco3p5Yfx4ZofHRVugBf8um1r V5nKV8YC8JLLitUh3WhFyWHoIwUSLGWGnuxg4j631ZnegXSHHOZyEdJCKUgxH6OvUdrLsJYvCQWJ GCbFBBxV4AIimDE93dgsyy/JYFZsF+PZG/rHkD8nU34swJVuq/AeupXoLNQEngfmPl3HjBT9+UEh RlkFiOShtz69SYfIeFMdlEf6Xj95mdawTKYaEhUzqCVYjDhvajQi4xHCQgV6TqpfDNnQ0Dn0Int6 qUd+ynRrdkisMkm7fgrfsZ78L/M+HpLpMmpGXrxxeHn5u91A8hIbSRyIJdLBn25XFfDHVSOv2sWd 867nNOnW/ls5Ggfi8RcyjtLoWwS/mGyVRJutP8yaz+D3aooIFWCiiYrNJLvHmpMZlptQesz1Udlh 1pnT1rzMmCIhU3mvPSBgxDMKSi8Y6QsG39yPxIaqV4BP1uGmk8BeTDKvdoK+G61WDcBo2hoOLdhH AUwl4jTRmNbwl9pTSx+FyuPczMpT82LHTS+q5vPjobFVx/+ISp8K/cfuRkzyVW52nfAWje7SV63X NmL0pZJFV0FDqQhfbMdFmDP7o4COP2QwaDqsrEFO9mqWvPvQZiB/HZf367opeM9WntgagIyZIKQF TcGJZxVEnzUaiLjvsEEoY66I2TedBsBlBM2Eblf6oFTxbytlnoLw4gj6la3jFQZ28fEtCFeMiDPU G1bSpyVqZQMnupFTtKG/0SgV6mR8Rk/GUhCF/zF/bJS9Dw519y4DB9QarrIq55WnQEOnqjtkRJo2 N9dvAuoLe2JKslew5RSLNGNb18lwqwqWFAPCpJlK5UfhBDBuMXwQwGmUi71rIVVYYNJjM7tWVY4Q 2Q4CL99FeDzMHh7Sy7VvVx55dzQJpkDGljSr+c7uIqC5Q0f5ZEtXGl2Bg+DQigtOZGE0vPxIDZT6 ml/4g19m2lA2JrXbscK5uaYx4sNcrvInKrCfuEZ1dWyeHcXn0sfGWpm6BMp2L6OC9nCL1XcZzjGI kchWmn7Dn3tQfqaQgoH4oiGElONS2ALGZqT0wopXuSUbKhHOiuvNMPsuBpf3dDZrovhe7a1+lo7m 0SERM2Lz1/7XX7volYgl7I62vExyfINUNMM8vtUCzWxZxFsuyKfDAm/1/R+EhH+fGpNRtTIlmZHP 6F6Y7M9aUD3+FM5OjPhB/o+7P6c1oLunScEU+7KrK0lat/ehF0cx16MLXBonslbO1kXNErDx/51g hFmiT8hCB9FxhRJvDfT6fpbBOIddTxfqRSOpW/3C92r6yWNDbAG0psl28frSoGAILmyaOVSnuJa+ 6ZbSOZfblAEhqy55yhfB84sCDCn/nBb5/eTjRUbrR4zdabYsNrQt7CCgOjykMDT6wFYmRvnc6ogr qLXnXmr8OtfE0f9PL6PqMam0aXPsXL9e4yOI/bYLr1SXC7Qt9+QjDDhPd+c+d0VT9ATStInhJ8Yd MTXU9GmV96L/Adujuff86tSbz0sN2783tbzpEzodo68+C7GfSWHCCXvKjlcbs7O6pGA+KGg8wray 3VlHpF3ikjO/g0+rstAtB8hffjBUibh+/QVmGiXH2/vxREGf4VvekdfBTS6PvC9AklRSUSLQMVlV 0ZhgqXulZiPV0YSvbGYiUFMAAM2NyqdWlkw2ljVFBqYQVsnm4owv/uMXR4DsohSXrpk3TU9l12JS dVRYOpOvBB7Mp0tU36dpdnt8tajNbuOHHWpqy9Oz4IC7Ds3o+Jg9nZkP9f7alMIkPHWxKYT0jrG4 eHuPJY3KpFidD3ChCqaOlEtVjOeB9K1hFGWzXL1NTeOyC4weqEZox0qaBv1l7C/gfwqROcLzOpdx +k/jvkFndDvEEmYcomEcDRhjQm+NNl9SYOLDd3PVsesWyISoaEgBTQWqFgYXsqLrsFR8pnlWGy06 EVPo32rwcQ/0M+IpW0l1TI5I6B/Mw0mASiIApC9UqfTZXmTTxyRNuSMGyWWjBsfrMVPeUqC9vP3O iQLDpEtPS4sVQswZF3AekmZc0l93H7BoDEuoyc9I8LxaLP8tnxNrjpqBJ1mt4/pSRWQMVgtj6afL vB+ghYpHdMAh0B58kmj5FqQEPsFz7JO6oIWumSDLNH8IS1GZfU2CjT4LEe13iKLzTg6g2MGeEZmz 8KnPpniL5EJ5deooyZg93rfc/0EExvpV42mbnOk9utWaChPUOWWYSGokDXczL8Jyk07zcx5Zzzjp slS7/07AkpOeJPYsUQDj288vxo7MOS4bLE+9ogM3USB8pzLgmHPJJp522zQ2JjSFO+XvG3CKA8HB YnNjM42xszb1cnuvZqaeSRtzZdwuDfrqjIy5AKpipuiyvsv8DgnpEV/FmPRV8+gN4QihE8gVm3vK XOo+vbYLxH47z/V/tKelloyNGV/2QrNC1pJ92u9qCFUXq0adX2NTxTOMypJoNB6GYvMMW1UG9I18 diAYyKQ86+xR5DLRqcFY0RBv2fquIJSrzWTqmVL+fYeIlG9skTDTD9WtGfEdN4RMlzdMK59RNJ/s ImwccxtMcVsOGG6L7YiSCwTLYv340tKoBJnG09eSNIQUPE4KHpBUB92Wi6Fs8IrN7rgTlj7Op9lj DpEre4n5ZI8BaRJ1Trh5TgiQjUKp5OKIg0+Q7wlWczd2r2Fs5SaFtrXzv+KLNdmJKI5Ia3jSrMem SyM+NVjuHlyLec748i/Jlh8dKcGKm7fvMuHhbA58p2UR6J1j8uQRmFGphBUGuQdlWhzZVhJsjqFn 7BKXe531uQJQU8F50dcGj5JLJkhCLcsTQg8dXBBZZIf5m69+r+9juuUNb/4Xg8qRvw8/VnfhgIP7 cVR0ooN3VB1sbmFbIVGsinlrRqeHaId3ZAp11vjMfE+IrnH90Xm+MXldo7FAGIxo6uZ/6gaKa5Mm LfbZtU3Ih0Gkki2qqm018I62+nLznLl18PD1hDx7PD9TG8PQL5OO7QU6MwVEOXoArN/fvLpAxFLg 1sw68TgxtTHuXD5pc7wPocc3PI4kuOVcCucd8k1bEuGjKhH+Asnow9m2jgdTZZ4f4kJRI+d8LRzQ 3FHbR1hScJYFxc+0gcvNcmmmiIbdSJWmuKplTg6b3j1GFxVktvddPjJ56II5+YcsJ8IOrjOpaIUn hMv1elVFXY9EZs0lWLcG6haWfkqegPmd5vCvGVVUdHIrRaHMjEGq36nmqVhh26i/Q695MzPIeBJb xnlZbV1+6wyE2QTmzKnhYWlY/eVGS2hPWoUKn1KT/vdSa7zIU1/q7EEjc4oc7RMqUfKU1Trgahzl aEmBUoPNJ4Iezps1Yu7pRJ2ugIsf8cMiOA5fN7uzTSZ/joaTW34DhQJKc8JLtG7YpEV4pEkjJ40Z MNE3cYFbHPOg090GrrutK4ofwL0p5FDLwPkG1cf48tJ1UvP7fItyyvRuY3epJV8SwPnb+Tz9a/BL OFHSoZy24tmYKw8I0frr7ufFa+9aPgaVqA9GJfiS/+688nU8Ou9RPqhcDuBgQz50kJtTnqHNSyhJ cZKwfh61xMGPwh9dgHWUcNMjiTahEGugMYXTJuBlBhp7j7JzlakC8D/zkFM+XgQ+NQzpAIfWRv0S /JkZ+FfQSEvVoiiVXlCXo0vN+cS7ek+03noOF+2DftSqTSX0lln0g3Wh9Icg9Jx+7s4Z7HmoHodx HtOtkxbKuLonrPA4mMHF1JBdfeyIchEA7MCWRdE5VkPdlbfNSRza7rBQ6P5gacnNwfS1SAALn//l tsbO1A2114uS+XQ83cHojRCL3T4yJ45rILDJHG4cyy/D/jn8WW9pSaKzVd0z3vF4yzid/pHOTT07 ap3SDcSSEaz1JF3T3Fng4bl7bWDQDU5EwSchg7piblHxKhxapJSWXBlq+eFvKfnuUNmBp9UN4euN 6vtCatp3xjJAvkT+k679DVP4v8r0iBtXC4xm9GbTiV/nWJxmJo/ginChEuyjdvgWIXtpv5wCv5yL m7VK3De1UDJav1c3ofNcqVdxPgvVfDD4SAnfaxeqNkwsqvhp3RClx6bP+bQ8+piXhAgA+v5BVW7B yjorcwjq/GQ9E9wyfqEb13go93ueSce38ZGq8vLTijNN2dj7KUuxQ4Za/8RR3Gu5qJC+3wPXUizP sjyE2IEiN4vYc21/rk16N38/0OECBERjvuV6YwR8P497mAmrQfpWECMEOvKx9+SZU8TgZfWQv5Cc dsDvQZZEMLNvDVazZ6VPqzzHqKW8HPyli/W/m/iiaEMqW6A/oAhaKmD+s0f/+CxZe9OZAkGrppy1 83vslkK5I6m+Z+sF/IJiQ162SWrWMdtEqLqitidp+NBUWZ0/3/TS/jrrTQp73zdb6C60ABelLaJ5 aZnx0N1e11uWY7fwIc7kk6hebU/xc/ZVS0TE6lop6teYC5juBkDfcpp6L1xB0hAu8tW2e+wCY8Xs NGXNSbXsFBeZMrJ1NXwIsQQTyTsaR45NcrQuafJPIBWFJad6EzS6BxMTxws0iLo9flReGAsh0BeB dCLXMWohe/f6bYUW8kfSr1nHnhUovUcJT+01JilZz2xaPNRJmSc9UL7oZb3WG8DLn1cKZWmrFPGh 6zEEL+DHgTbsnZ0PHqUMsD2u0IR1pFCKyDQwbrNWyEx9QolC8EYx2JvtmjkVz57tC5aucWsQ33+/ XZ2s0ZjmIKHrO18znflMyKzqiooGopssW16xQJYevzMGCtMshDUzYcTnhDQV9uoB3o8mECa4WTTL dC/XvQxrosgbdkI21l0JYigxy1nq+Kr064g+tlD5IRxVM+ocepiFXwIk/eXGH70kRqJssdahSEyO bzbBw3NBURZcoUSn4p8FGROA/VERx41zbRFxKuM+9enD3Qbi+PJvAhZs192krAgOnIT82IboTgi/ wxkHNo7jO2XqSHXwX+CxMWY3cZtEaB7Rjvfj4objfTljeggSoAma9Hb8KAcQHno6d61Y+23q/Qvi rAFfLYYHLeeg4quhOkQZV4FSXBgY0brm0rAOHudyhji5Y9gx3bkYA8inu6sdqpxAEYsS3/zj0MMX C34cttc41cOzJi6G7EHWh4i3bRfL0DPRZnVgKqwmQGlYsdX6JqAA6CEC3JcKGCgbK8+Oym+YFHMK 7VlMaILEbg2HJPdin0IsRkbMBNsTA/IQkAFEd/ec/7RdyUcgGE5MbIXJ/nAk4H3RixWlpYINGXKx 6fEi50PkenIuIqW1BTEXemXylgEtsC+hvfXYiBe73eTxx/1Ueh4mtDqmqlwIcm9BEEtq29Wrzsej +uFshiNUa0eEfpDqtMAzdiSgg2j5hYh2vyBa5ogigoay26kP/C+0ojq3AFdKKiCWv6YFaF3x42td hCcMJkLYYXMmuJ5OkjoL0YGuVLju+TSCEEhSW8p/GYdZG49S5XE1czJ3kWlibkxIKJhq63KW+FeW 1hmRDzugWIH/Otved1kPHhOyw37tKWr/JXgr4Q1HLtWfK247rhQjBbIXY8VnwjX0KFZe2vg+uNjG 8uPLQEc60jsrjvUEGgxSf03vQuhZgNeNR6sVnFmVfiiwsvSP3cuYtWcTxzE+dsql497Uz9XMevar SczEamVDzZCQjY+sQN42Pp5bFUApocUvy5ZbSeM9F3y4qhN+aGRI/twfx1Qd7Tq6gnska7KwcKNB k9W3pPEsVNQPjkpOPr6K0lup0VZtTrpfvwqOj+y1ajlxADuOgfwrR+7fqJyXdTfaCyVLWotJcXiM 8TghKDbn6AkA2swnHBGPPh8lkbKfxdENiz+Yb7PctzCgH7pQ48J0V4zS9sydYfJaKu4DeGa5pnvc /WTQHbnk3fxt7gs7aAxL8ihBDjYq4hWSvsPXimmjdj25sEuM9iv2b2mEbgHVBGQD4jRXd/WavJNG ++nIAKo5dDOvTdJEzuUK0BfsaPQtQvo27I3XZ47Qa2qaM4lC5YDNbZcyDFKygfA9gTitXTmGNWBW Ummvt/9o0d2I4tzGr6uzGQprRu/fspYMrTsUrKT2deF7+Nh5fEr+PMImtSOFcuKY1hoU2CUmnwc3 T1VBmUghJi7gne70gJvcqT500uBWhD4CJ/fpYfAjh5sGuexSgIBFDAxGNX/w+odN0ZjzLWMVjTCZ r52KzUP9bI/mfeka5NWY2E4VA7rMnJlsM/9xfguWQomgzzOX68MsCNPHhKNDypT8RuR7UvNMbdlE QnrB6nCD4DqfLikcDBK+KMy7uNQ6kl6IqLS+if5J3Q9HAtKQG9fKE84FNf2IVViuuYauPgAHJ68+ 1mlUqnx1fHPPdqSyJEUb19VzS28FRAqZvyAfS2QarFVLMIzGKK3ltt4SFcNL0NtUO0xgCFvFWJG2 E9KT4qFDXMWJc+ArxFGeInn6Gf8YfW8nWRKZX2Fn2WOjmN0P0hWF9ppsjjiMyrm0BsqntqiAbo3b R9RfkCSR3wPKSoAFJxBqUiiVO+ucOIeuu25DwgztauVhobv3YJ+rW2zm+vzPsPO0XDG9uvdEm9FY lpx7VxTBeWQOaBAsrg1Ax6JlvsmgxS5gnWBUI01LIMBJQ7HRWu9YtG9+S4tPZ5BusH5q0iRKyV51 hL5gB7oDX9ZwsVEuU1B9b9AyIj6DJJpfoeylxPD5b+OGhG/r4xa+8mgpivNTYS6IytqPnYiqEG8N 1TKRM5ZyKCfznp1NUNEZSRMf19uf8p1omGE4KRQ/rl82n2HvC4l9Hbejeq10iSIL1qvJ8QTMve2R gm8+FYHiezRb+/YuxRz1FlRNCwndImU9ijM4yy2GScSdoJe8GVJdUoGJzhn57GhjBu1hoAjxNhcL djcad0J57gxIRo+5hKm/jVTAuUoRZMAreyZCQPtQXj4JyBk0yPVb0Q9z2d20VBHdAwGUHcmeQ5gX dJuZe608iY30ysF0waoq6pZ57NI2WvgcpZozJhFY/uW5+IWDDNH+UFFLHNSGYwthuownJIUUPMEb qtCZaTNjtBULM0qZerqJQVsKm8P2CIug2vFuZQL8CTxpPllqo5AwFSxPqx59oJJEsD/gDkSHPPLw Mm1ht9Ylf2w85yH70Y3UKXNIYKeh+vGk8rRgb5XDxXOI8RfX8wYcd+GuAsTRVLZQJFW6jAAaBDv5 dJYnFkqrzSTLWOYLwL6P3qNnF+egpbovWfwzn0kiD9bmSCK9n7pK2zqhdleqQT/2t6WfKssV8MmQ uWOMTkh+wm9/hVgGn2SxUQSpWcxvZkKG21u+gjn6EaYxnQcgnqxg5B9jPixhdd1hCSeaooI16DrY +E8wK8ym7IB0YXfiNejH26xzo0MtVpsaCjj1gtWmOaQDtEiaXzhLonTzkU8ciMgu8rvrsm6Oxehl Z3wUUoJFy3mR2A5UrhEFLRf2q6C3y6iNsVN52SVBjQKx/Z6qdJTw09GRMtmS6/Frm7cUTP/brHhb D4Bh9mGDs+RA/3Zp4K9vMtX9clK3a088wn4h9P0KXEDygxKyBT1qt34+5gw4DCbd7yBIZqHtpBbg qc3HSn2aNW5jJoKHypb39KudwohxvRqtJ12CA6Kwcn4ajXRY+YuuXM8/dpkanzw/dVuDABzFLYuz MfSFjpGQxs66Y/xfiI1kcdOlLs39hfnVydXTE98EH+GXfnWe4lfbf3m0wCYz3kIMs6+XdYgklsW9 2e0KH4xB5aTM26nNAHUcEI07Qlr/CbvnCC+D43jpwraOKrphjFgqUqh1AQiJTnULwfcXv5oQXnEV /oR3VGqyBi/TVHD7/lPrkc6FYT03KCoiacqseKeKRlDuTmJc+F9s8uW/tuazAMzVa7derBZ3eefi eDQsP3fAKyryJXqPvj4QIoI+hBF2wS+FxIo7i/ckDXUAysPctkfxipKI0/maUAmgsAeN2psk57fj 1IKlhlqp4+OKCrV0zH+PqMfF12z7zb1Exil6QGDBC8b6LP/ie/tZ/7xR4esObCSqcByHV7ImkyNj AE0ELUCrHJO0gqpO4zNh8p0un4+8TfvchKE0WRrk5Q/4NqOti+XI2V50moQ0gLx+cPPMFzI291eB WpoBc8smMPt4B7YCtFAeb23QAy6sGtRy8zBECBen68Vw8KGNa49152iw591P68bSldQP+rrUZtyd HQQ9aiLFdM4KzvcGVdiHfjFsqSJU8gwa4O5ALmEGa26zRnabWwtrhNH60pSfBK5szouRZxdNDmFV bPTX8g+aP3aBJ3FcJSri5mSX/PjJ1H4nbsP/1rrrX4xkiKc8VgKruyfYKA0+bbWtdEbG//35jkTi cDdMCtJbt0CiR28YnOcpVLtyoHndHbZR18ZZgJJRG7ggPfKKlXWwfb59rOZkZd48+JeQA6b9tpnE f2k9JVUWA7v910fBgh/RBPx91V9AR5Z3FwoTiD/p3tJfjUpVkKNybHAkO3DK9aRf9+JIANunm4ob uB65uVn3MQ05Rx49zKztMP/uQV1vIfUaQAALvBEkn4BGRrl2NT+D+6kx8fjTO9iks6uo87I5O07m lvdMR+/+k5ROq6kvYxST0bNXfHRMsL3QyXmSoDaGfsod5Y6xxJi+dXEyxm7kw4z2Zjf2cPA96BUH JbpoWi1XCYDRr1fOFXKTq/KDC7hhVEtcrGmN99PkDkz/lztCxfq9CTYJDaEZrFtj0kiTgqcCpoUV zU2ckPjIMH0j8ZyS3+JeVSqDJtYMYf6Bep3w1Pymvg+wUJ+e8EwoJ4ozr5wQ3gEATydp3lNsdwRP LnFB/uz61KOsxcKDx/BSMT39n1bOpALqOosbwL89+C382306H0TvKnAOrYXcOnUJM0ccEdf364xx Jo583Y+Xa0cY1ILwhbg5ZzoqI9ZCnXu5EgXIAWBEJ2KOtpSRp5nCbkeK7Lw4QMyaxjI21OL5N6HA tsa8uxzMEPVXkgCIX7wcRaMxxKJpWOWGQ0t7RecXTPCTsttRxGGvq+0gckJOYcQf6TyJhijAnLjE ysKX7uM8KINwz0Wd59vJH7rnYyhBRVAvlVP47z3takH+UwoTtUUy7DPGhmjLIk5iz84k0fB0p7Gp H7jO061Gm0PNeRpcYVyzZl/pG2xjcLfjEwU1/BeFWS8u+ag8Ewd7Wr2OvqyH73EIHrWO1I3WEdi5 r4nPC6esOcKbAAkiVrGBtFawFFcjz6pSsSDlQWajnE/wnvkGCPbvzxp6M2D7qOg2qjgXpAwnUVMc XG0L83Yks5/YqCDfJbFnaSbIb7egig2/1ft9bP1bnhMvJ18st5SKed8EiM3ZFcS6jBfB+fX5c2Am ZMT2URVO+wXUa4owX2sfLvouSpRvTkGzOJEC7n6F2kBEbyalYxDnAfk6G6TfpxgoHpf86nIVfg7H BtUbbnPwoQmjlR8649D9YWCBjIeHXuABHTUby0+RYRMj7NU/tiVDrvrwsknT/4F/w1MJCh/i/KR3 Ab131oe1zumhejr5iMeakH9GF/jPEZjzF37a4eL+R3r6QXL6bDrxInTp5SesPmSlvcS4tM3m/UxQ MiJHHb2uI4yzvIc5UgSYKtM/NRWATimhcJyuD6Me/9ts+G8U2ARD0/F9GgHPS/gO7LTRIBCcSEa/ +8bOePiXMslDBXIDMqC7hmtc50amIvQjyVmzAMIcD+vCjmLk9GiwZBHUDXY//WLFPFRDTYUcqH8S OVca34DpwB7z+StbOZgKKPhAnqDrYJW++ge1iaDqUugqX9EwC6/XAtBz1XC1LZEQPwYEDH5fisTn cndwIvIigpiHWSI23UZz23d9JUe82reysghyIDfJn7NQjWe7qVq5k+MEpUnbwFAy6L1QdtOqa/5Y xcFGGx6+o11qHl/p32Mtzd4O04w7XCrELWYewwvgGFT/zaay8G663vbdM28SuO1B7HOFS3mnBTGD gWWZP4bIPTYTPZKqmAiPUbsUmGXSau9cIUZgG1Mobo0q6a92dqb8NucIHbTLmdkuYDykxX5OSKrI +D4cUyI73SUA8G95FMOP76+5AnUphPCSaqWEAz3D2heS4HHiMPsNDz/ykqM4DgjCmOkDi1DFWhb6 uIkTo0Ls+b9r3p9EP0c1BO5soHQgS9pP/EnDXoQy9vhDCR4cpyztCCZsB3TZRhcck2OhNV+2TAS+ Ny1QlcwowFhGQuHsv8tH823jFMzD5AVcGIVv7XhQYC2YAtj+rgsEIdyT0VEEMY+IIB3wi6EuUHUo hyXKRbhT3mVAtbGHyH1bQVtw22XOD5dzNr5vY/xHGwPJLiiSMPE91G473UYaUYjvXd9B7tPIPXN2 Qh6LHR3PuUWY2h1d0WwTcSCzI7vdjW+rlFCZra0GeqWCgo9xGCpJeOF8xJAQTtoY90p2dkGuCGyB cP8BpnREYKUYZ/z1qUr17EJoYwDFddo6/+w6u8RE3AvZlUorOiJp6P8JH8aj2S6zRLVfmv8AhXgs hfT+NcI8PzQ3x5hJ8Ptca/kEaIHFZ3yNnXmg/7o5OOCqHOM8ulvmAkztj/kow+IHgA9gFUfrF02m k+WBb5v0uN5bAkkW34fYW2D+nsbNd5RXIQa0punC7hlKqPIxUqSjWKCL7n5vYH7AXQLvQ0p2K/zS sGaXXzxVkb7zPyYWKxKZoMGVxdXfQjqoGewb+bD8griN/OZFVr5C8cuMLZ9tTAXWsPP2KeWQ7oS1 eD7Fv2iQiNL7I3mqR5wHuLP9WKkUhQcy4bQZoaxEutrLcKeBQbrTFeNuzDb6nJGq7hnjGpN/DaFS Y2Ba3yIrUySzDE/BZsDdyy1FMbVf1uxnVKSkIez/x/mMu9C+wgIM4+cZimbdw09YbtwtsOcJi4Am t42+jYVxb8YbffvUUo12ruMtxEerknP6JDbmyne8z94ogV6BhPTVLJ4wUviCRhY6CAvmqCSKzKpC hQlh6UI2NMKlVdVRQvuerZ+gK99bYXvh755IOJm7md/MrICnzirD/WJu3Jzs8/CvnXlBXLjNOiKa 6fSJXK/Z38BaFTmz81AepeuUd++HF9e+XbtHN4eM2iUZWpedfR9zM7a1ErjXPOK2Zm88wg6EnfO6 T1sDR1klvb/L6VtAeb/F/S4QX07d1+mrZBBV52qX1c/atPevNSmOL2rhqWHnTRozvjA4r31FupEA 9zsVg18J17rv6IgtclcjLb9+AYekqpbaCptVU19I6ln0UIKAgOxDo0jJq3DpzJdV7h+akmnmq9My L7tolVL+fILQtF4tLCZ0+A4wq0YHCzk0nMFsUAaUna53F/eak2vwI5GvVl/SSBYuOJdZsX4j/JFc b1CRyqZZZvnUlyfmVbPsUyWvzWBAMlVTAciop9KDDS75VQhl+2vkQwqPIcfuozIqoyeIbjsJa8BN ATheirZ5bprKlTiiviBWcNeocIX/T0GuQzU6gV5BAuoVe4/YX/9imbZUNNOiu0YgUTpHTmFs1vxJ ygXnYRL8+3jR34q36IaI7XIF1gxK9yd1bGSuW8/3FN2D4bxJHFCBJDWdh2S8hLuipLAFKUkvrrzF oOSaUQe+QxsQrVyIqJ9b/dVg9T1Bb++jSAQcDqQzWoHL5Yb7STN3DP346liATeUV6AXjLPnXAWmJ r4x/i0/xkZ6Y5zkVMyrJtxYEAuIZ+Rky2ufEL0oawOVYm4xVUTf/Hz168sGODcyWogAf8a6H6WCD YXZYWwzgi9Q1K8UOZ71uRmpJw/tyst2bRDzZbmS7NJrvrHxaxm+KlkkQa3QD+wswVoNbG4icO45e B2eTX0eT1SREokxXoiXUhBmePsyBM3R8N1VIPdEn4uDNK25QV0WYFwYMEJ1eUy2QrTb9AsYf0mjj yfjmt1TQ44gxPk/NZC8HPFIeWh1h6RS4biSd7wY64su7Vf8mtP6mr0hPpnHYhELLODM3MI98ITd7 sWE0phIla+1m/XwCzhGZuZlU4indTkXBbHDup9m8OMWTLKSF0SHNlyvjfXPvgSyLpjnAOsK2RPUO clJAGUHCGTHbGPige+DDUSKOglk5Ff0xJpHjaOh02RrfPbW9XTb0xWL+tCTMJiPJuDjo7mj8XEDX t1UYDWSfhphyPiZIw9wLRB0PKKC1+HN5wL1EEms2xqM5MsSL/61GlWTpUzj4YlOYBOidtLBf6qEv P6m3j13MUH472YWHAZb6+/b6XlABmu17OyYxVzfMbtwjM4bG6VT8YOn41D0Lh0voWXZUxYGlN/Bd 05XVpZHvQrPOehF9RMElH2st0to/XSrGuuTlfwxfEOz6hEMnEm4mcKQEt+PkqOU0EKm2G8F4Fyi+ IbnbnMNkH4e7H/xp/mnZ4u/3OHCZbOlyLNQm9tHi/dyWgmMR8dPNwI1ISHOsp7Jq+225++qQ6Vrj fsJ4u72c/dY2isuo+qQLa8AWHKLla/sKCvozIZ7KYZUhcbx83BY0JywAiAIBXMNgVil+AZWoK237 /6bJj2vE2HvUW7nOhGCI8eEit5JZ3pXP1QDMr0tO+qsZoDDnzZykegjGTyi4QEddq98zfTw3dNWv 9grr4hL0KiO63+cW5kWt0dzNL050iTu514CBD3RC9583pBFO3TovdxvWHdvdGRkd7aX10bHst38k zTHi9Vy3yO78yrDjbw4J5jpRZnQOocnsy9KNQeboBQdUAGGkKad7wMO1i0LKNsobVnUpqpO+8XI7 uySQn0YAXHbjicxpUpT4UtBfrv8naGqfTqKkSGIuje0/WzujAXL1BVAau5wn7xepvN+O32wsc9R/ /+PKIEShiqisKp9ygsJl2HqVflAlnv4gLRjMA40Oqmr1HVu1SWNIpEwzpdaTcH72VJ0M43RPrwnH TrMPJHklxbkWd+guN/pXqKAVA1lWr4LTOPZDD8VfMTbzdUEEnsIONQDRJ5YURq7iukavWMaxdP2Z eZFBek8trWEFQ6IrVV+5uW1aFg1J3RdMEbs4lhxRNrNJYP2wtWrmfrmnqFDagVF1f+mLBkNJrHSp aqBT9wjW4I6Kzfc7pf9gx6/fpCh29Eh8t88tlbSBvHZktCPD0ayQ9fFgL1ckZ4xJMyn0aj0RbcJ1 GhtB+gEdQQzH5WiRllcqI3ZZzj/vLDjCiNsGOl58PPghphc4LCv96f6aqsWhsTSwJH+Pk0TNmvR3 3X6aHMNWYEBNiaTvjWunNjV+PTWcAjPFdBX9InNgngJSV80N1bsVKUPMDQhGcn3J9SO07EdxW3xo JG4dAfdSY299FeOAbqxL8xF913AdlH4FKSQVMdp1H/I/w83mZgwU2MJjZizPjY+zJ/G+mSgLgP8I GLzY0OEAHxRH5H6riNw6KxIN5v+XcRozHXYWEhxImprr3kyGOMpHmiFT1WrFy7g1jnUBHqIm0ZJM 50xrm17mygn1b+kaid0XPc5MrDH9yJMhSeCotx3RiXq40znq4COwzKM6HYus6/NN46LlYwFno/RC FvZSaZTRqyUn3eAU11z9ZOuUwfPTBA0IiDds3D0LaelcqlH+Mm2TronYcmgSwIyBsG5sBJOgwKmI 5WW/LJQD6I1PGnbD+d1Fby8lXeErqcdJ2kWLLayXX6DkehAtfOmwFsSEA99VekHgxeWrrz6WwBxZ 4oSz9xMXx50BhwPOd3SfJseDzjWK1lpCI/0kinhpMsUfpI0xB2tfkJhO7Zy8Q2UktP4pKpmi2/kc uPeqn4c4qeYJSMWZU6utbfZmhJKFxsC+8fkhOSOs5xW2Nrt32a5XvQpvKfX5JdVCDYzaYIVAkW4E kRzo5W6YRhvCi5lmh/7UHQPPEAPS+VJujNt2xKq5WuERFPr+tQVB7eIhC+hLhYpqH9W3sRzT06Cq Kvm0jW6Xxz3nF/jreuLtUdNowMBMXZqZ056lVKea3yQurtbZHdo/73D+AwMBowKRDOQklKXTPe/6 4FC5J/QocsvKjUgVGIFAr4Cius3DGTzl04Dvf8XNnOHAHDtbcIj0AIGMMPLRwkrg/AHKkGfI/A98 07cO9VvUkCggOBRUxxnL4+vqRzDetKeZnksefZmUTDAE6vvrr8zhr3lNJEav092jBs7deckoLqrT dcaE75UHtBIOo1ZeRdRNuawtgOuGZXoCoiEPWXHL5jqxZbj9ff6b28IZ2m2wvWulII4+o1RfTVZw lQaF/rATuzhAK+lkqKF1E14Xgj5dGkHoPcSx5MRGunfnNBnMJhUEfVNPLyhti0Uj5j2vc5ELAdt0 uuBJVqsWrBAFyvBLGemxli6WbQZiHVFX5U5Okxnx2zFVQGcGXfjJuFiJJnpnAhYnb2ZROwmJxOye l48XMLCYTlO2LCOT9IBparM9YjSz7DHyoBSyjFQVJ3NJQ8EnSCrdkWlGQf/ZPGAwKe1u0E0MPFi3 kb4XtWWGvhL1gxRqVFDBGPkx/Mc+OuG7KZvV0xUtvQdtl3jGFlGv/vA0XWOevVIVgY3tzW5/QXQD xU6iab7TB4WHGQeETFrFN0IA+TqBdfbYbI8yvun6aMAG0tCp4zu+Y9lf+azUiQluuFZYHetv21Uh qPw9FKXFQ5/kQ/UefnWMq9aBuyCJW/f7a4sjUiEqFb1s15kpvVOazetl8maEtZyryU3Nktjbra4S VyvOrEC9kr1PxIB95T1Keac33F7b2xDGmyUpUrIfqbp8aplwAZTtWf9qkfovzUN/oSwWQ6JwxwYC bKtz2qOgA62PlZqFif0E4uBAH2oUAtf0t/D7H0+dwwbfgZld0xsWtIGzrg8FIn9gZvvUi06yh0oW M3ord0KZsTPtVN7kii9z6eNJQK6TceQKzdz8bg4v0+ushdzLsSAhYeE7ahEeEoeWaZSjZwbY6yrq Dca55KHqjWmGEQVZBEwkffzVEubvFflCBG1QreNn4G/u4YFMrBX+3CH2nqLbPxVV1DSldxb5k92b 6Q86REUvXc77Dg3Ah0sf1XyMA97FVoQruD7Kfb2ccnxRwi7eT17T6EaTq6tyKgG2hS7EMuSWIPmr G6B85MiLdQ1g9x7jASTmOqvv3nNiFT0Y1WQkI/3fMkRm8anh83QKXpwTTxqeuOYcJf0KfdsdkHBR o5iZGNK7kEPxWmxo+K8CiTavDJ9NRqxRCDWqNERpf3uRqrbkrKMVITtUH/4iS5w4XOZjxyTHZ0cE cqTPQ1Zzusa2KUj7E+fGSdgR6mQ1cAumvCImOOvOU6Xl9u+hmPf7mYh/jwq6KNy6N8f+r8jc88aR +PFQFyNaakAJpe7V/PDRGl9Sqg5HoNJDW3ZZ2Lv1KN45xj/uvtS7ylLpwhjnJd58b2EJ0ebvz3hO fC3kpOsQ4grGLQVhP4UeBmzd0Sgbr4w4SfvViwzpLiGUclM2eWNuPK2LZp8SsobJigwzqFxU3hZ6 zylva5Hiy4l9YQ4fhlk8L7MGYCqGb5SGJ0aLsBcYXCBIJAYALOhAC0rakh0YbV32R7MwXTTwF5sC FMRjEoP7fxwA8LrpXzMcFMvvT/AhsjgKLMBsc4qEZpk7C20vZVXmWvLOAD/sP/8f9HBWnrXJWCug xJP1gQbUsOAN66pbi5dE/dy9MOOYMLzasdFZkZUJnWCfMlJw5AcCe2xpwQwwSMfHfjz/L5mX4elR SdDhdwZ3OyAczIS5n3YqWBNbIn9Rk2XTUVmSeb0yLjHxcdcKj511Q2eCKCRdw/X1to5kjHCuj3C/ Ow3JZUKe7muFVQzkQC2cLRtJzz8fjBZrpWe8fRxGjmLJrlnON80Hbe0W8tcqYm9b5XYRro5aGQHk /kvdGpKPzEF+EcuJMPWAT86zuVoS7vaaGorrWhDZLU/Q+7NWe6Op1lwGsRRYrRqhlbuD+PHrX+7u kn8p08xwW8CDkD5yini6TROvnK9JtGLOcAcdAgBOisHlOzS2s8slCRq+ovSSlfdUcQTzmTlK4GSA fBJfAQK9ABZ3fWP8OSiRCtkNOv1hl0S0fzKxXwlVozXdwG/FqYoqReoD8Z5D27/q+/5wmI5n46vh P4i2BbVSAiYAHFtzXqyNE42mEV/XEgTl9Fu7JW6unDBxgGQ82YmwebQoEMfsiUNpxTozewUHUKuB OhONMoMKwGS8+C8Qy9BptF+XfL0EpNbvG5o3lgWd0u/HQG0JF9Kg2OEDIJ87GNkxrBsbK/cidxhq iNXalmCoWfW86x7Yt1h0i3v4CYNq9YHALhbt2fJ/S3+aab23574uFWAarM/wmTz+072Ky86oh/qn RwpIj0TKKy7qC5McKqxB01rtFaEALabeZd4tdkhV68j7JDAwZ/oSCD/IN06vkE98rGy4oEc2ocn7 cjeBFsvHvPuvhGFApBxUPE3dWJ1Jz4PBSffHuCRvR+AyXRrCj99SdlheOQFQKFjQxF9IeIQnRoMd md6Udc+VPvgv6GFLAgXhqOvrzrHdEd/BYYeGC2so6mfw2LofeXnLH7gQ/9rPVL1+SopE6UG4hSHX sy3loWZ08dqkVovrux6rFSQjsIu2MdtFnBk2hRjtins2J9uHbERusYsvWZ6C3A0SmPITwJVwkXS6 BZsTM8f7oyrBfYyz8F8yZFJFFSPiOUbc9AK4UfyXyGnaRt0N72RzTP1i1eNKvHakLNe469xHIEJS OfeheFYWQcXmtIauEl5r7/75rJg134o7zFyKUsMKPg+ys+qM5KGEhrbW2g1Mglb/YUquOIcoLZtP +C3S+z7msYMJpCvta4s+hyyc2toI8Dtf/1MITXf7CeYnHRADF3e1a4BF0xWPyAAtbF1eQPLrInDK Un3jqMPVxov5+ilXUGNPFpOoGmKBGG2nkHfz73geOJ64fV7hqj2fVawA7d5RhxKT3r3PJLTPhnOO nlTfwyBnQoTWAhyyXjB8N2KDfk27bsp7eY2EQx3SfqIExVVGP6hElWN8OtbsNrtltqsRleYvGIQg zlrbW0wvaw8VPm53+bl5ZFkfZ9rNIiWiOjcdS0P1dN6LZ5Yc/U9BFmfIM7xlV+WUcM3xyGCOlMRJ ADfC4o76aibdkbl67qVz3kQuTLRKwYX5VcM+/0L3VtpirntDiakdEntGCpFNcbmPhfK/fNkJfABF cC2Fg7n1l1afJ0zGxnwsBgE6gTTmEirPyS0rfHvgbO5BOcjEHBJhK5rwMN67HKzLHhN+I3kuNuem SdhuZ0/HvXqMA6cIrZu4ey3GLumykV0nXeED1f128YCBBWzrHflb8GzQirluGTk0ppLDO/di9rXX jVCxZQgRD/4axsecbZpz1TYXxWRJf8qpfealM1I6Va7dJt3CZBF34kfUE8P2/5wmzHzh9bIrDmiF xh8GH9AgrEKIU0ueTuzQ89vtRUhVVK+XwJ3UcMtM2yiXgaOtt+9ttds7EwpYvhOHoZdg86/CVuLa S2nc9rjE0IWBGjhTxlmKwHWP30VjMkLfhmZT1ZjVvT93XKAOS3aD0lv99xWopBl/uqFBHgP7sm+6 Z2pYPLAoRqOA818KpGPIH28mB3S2chaarfHX0zGnyw6j9QK1t0RSGa1IkF/IIsTF+zV/w/QpYSn9 nMR8NuZ76SIHFtkoOrNOzda9zDqpf+MNxTNBU6Hfya6WfvUZz7UG7oPkGtTGa5LIyRYoqhJafJ7d 3LKr0qBF9+20qvJs4PxK6y6qdMJPBsowx7pW8s6dUlBGG5VZtpi0zCa5z92DtsnzusNG+rC9MUSA wg1aKis/ar8K9YVdQyCdRrUi97cagtak+rKJcMRYl5b3TKo/qr7rI4x0SIgy3mCi7P4AqHPYaqzr 0vpGCXsiQR5tKe+WcHDfywhpXF8Y/WKKmcdP4jAOZHonhsnCmyh+y2QU5u9docyjCzesrNfwqlMm awH8/soHFnt7h3/SU+nKa63OA60HODAQk4CeDOyjuveyF3QL4P4UifqTsHqyu1UMnG2Uul5T41Y7 aEbM3iXH2TU6DxXNAIfrYkZQe20F3CdMdZwosNxv9ze62e4h2yzQC7A4p7Vo3jJ6rS3zX4qm9rtK eHL0UDNRlOuE4UKy59a9KRrDGQlTeZ3/JxPV2xgEh+nuoFRBFyzDBG0/HLLdwb5zwIU+czaapncZ V43eo4slmAhinmgaqIPKHlnJk0RxICsqbwhSe7+hMxdH9urq2/mOjWyNl6tp4D+To/S2W/6bemIW qwwq1K+Gc7DTGdAoLqSoGpFwjeYyvB8ZH1QGL/3MCXSu63QQ9Ms5INauPOsxIFRfyDw7auaewPwY q3ElAqQHBfeXc23KGdBKfwy5sITmn0BX0xBG8JryklhS2nqQxgmyfCEzEigv/knrDnBdwMf0dnJf 5mpfnna3L6aitnFHuHcPH/QorAxi7Ae929MHGXFweauIHa/XZ9kgwTTDbb9gv12QDQE8aCnA8dBM dja+IRpH79swvOFNn5FDlWJc1mm3IEHetxIafmH2cjDjhHGS3lTXvrp1RkJmPzT0xG8FcNA0SgOf R0OqUeXYMw5qyPsKWimD7o3+NP1yE+zILVIDfYHGktlQgfX3qn+EJ9S4CWuAyZUAxvts+yAyCaif EDxT5m3EFMMR0S73u4vj8Sn+dNaQX0WufVEdXGh9ldX6MlsbxU+BjQvCH8DNRnv7vJ5QNJD9DNlW p6gxFQwO4eJ+V3q+XnPZcVW0PktPy6/8PHNBq5LrujChC1hSSBpGDBWXnFUOKOm3EzBF6jmziup/ e7FO92vXszqrMemfWYmc26ahnuMIuq6Qu6Q/drG0PSlCoRVHzZEzEagyIJ40gdCING8eeUP+FeGS wPBdaByuGHJ9tDWFyvNQyUZeujec6jIOdSckoE0BRJc4Ib0u20Q+DqJoLHYDMAc8LBoAGx7T15j6 UnQAcF61heCcQaIGZWISkEhDLrC73SdZgOXEJ6aXtlcFgKQ25AzLMh+PykJp+ljiYcI1K3AZuO5F 4YFZPMf8K7VlQlMQHFGR5Wc2rU+OCI2R9IWm+kWKOvNQ0RkHpuKHXV4fGlK3tfOsesdcud3g8PET 3ptAwhhBxycqKUqC7tN+3XzsfewtcxaSyvCZXhen1Zh8qayMdAX6oflqIL0RiZGbrHh2QLBVv6HL LOxnAEN9/ZQKnJkwbPq1wwC3uI8y74VnSQSRxf/enCn9sJ5neofbQdLVC5ru1etwcZ9AgcH5jC9T PbWsdSzCglFK0D6UsE5BkP8z3EUE/T6ruFoMG+xbivUhqvwiBAcc2OSHwTDvxvQiTsLFsZjJ7I1d rd3b0xoyA+P2Uzv7WTkk9fenfH0R91s2zJgyIyoL0Ed1DNWXfhSO6JPLnq0U0Yx3wwPSvuruuqQm vl2CB1kcQN3K4NNSCoBR6hcqtAXeLkGRcAYZuospjWOa2sXeWEV+EZ9ROpXTqVtN57Wr7cvlxxgG e6xzVewHNlVwyVBKPC56YbvzJgMl24y9ZqzACybWR0AZhM7Ys/+sBfX5nxgVeBZ+LsD1gDEelGye /seu2xtT2VjD8Cojb67djwe9v15IIjgcrLthDD20wWsaY9Vis0R4DPOaWKEJoWqq11Ci/4U7GUvq MMtPlXnmCYUzt60BHdRbPoRuGkxea+0tHBSie+eM2bEIjnS9bl7j5f7BL2rgNczHcffAWT7jFcah pbcVtX3+Tg2QSe12RDYNoxsQaHFjzt64hvsDQPwgumddeuL0USmABu281NcFlzHriUInGkC+ZNzl XjEnA+m3pm8UnttuxDSxFvFe9L8PHXQcPe2wpZixoOqrysmfpa/cwIMBtLFENDxcfXHAxUD+8RqL FdIOZMm3imdxxxhoqzBcK722x+r82hmZdQp5xR6ANFgT6wJg1P710eCJWqIw1ulA/T9gRIFKMBqv n021jyA4xipFiC4kaEGCRouYJVS+ZtOjKqpg9+afifqZsxkRcXIqhBQlW3A0NGwd+RcYYIFxMPcM R1jNKQhAz3XQTeyNBECeZFgKhWD3o+jSBDqzc1bGlixWric9QUwloC+aac8WxxWcbuetux4Rfzze b40d1d0KQ379vf2Ms5YuYrry89nQi5GYZEVsFFZgphzVtkOPcDc8AmX0pfO6Q+glqZDRJMqtAOII LMuitE45UPAAbiW/4xOq9ZBKwkq2NIbcVTpRlaUppJUQ4m491FNMY50H8tPGShLmD4EL+LWbFeua 4G/y0hTiIV8DT1xhWOulvIP6KxtuvL0IWa95eRzmfdsPOaRxwO4rydj4VO075+W+FC5vzeESzTct OjqeSaHURznLHAieygunY1RSh5ju/0elkMDH04Kzp28ORtLaWt6B/yreZ8FlsFkeA3uL8pC2+ffC 7gx1ZQyWF6LbFS3A7SNUl5z5isb4BIOcRHUQODwZKvLPIzvMnUwAgxoGtPRM39g1C720sn7/NpDR JaPiD+tvANNp/m4r5UpzWeaTegZUJOw3gIV6DeTYvnYz6AOzZlUAt7GtdF4u3cc5MEnbCHBplFac gO9fp4+g0DuDs9hz/AS3YB5KmuGkdPbV4qMjMd2AUkae/EOHqrYQCauSObELd56wDJlUrQdDYJYw 9c27jh3MNgiJrL7vTNygI7RssnkJAuuKCih5yyMjSMAnR0DoFAABKr8cIF0zZt8B/XST9O3+sieB ttWXiTVWGqCXuPRG7nTlSqVhFdA0eqOr1BRUE0ZpBuEz90iw/9o2qqGIFksST1a+3xHqvqOfKyhc XPF71e0gpj3H8Aw2nXtXzU4G9/pzLSIFfp1LTOABjPPBtE4c8fUw1fW8359TNTU+A6NhxR4o5zcM rbj9xSqB7RLLp0es2YBGszE+ocll+5HiOhmY66VVqYMlKW0aeZJZOaWHwWbI7dK19li8WuMYDTJn NmDhDqfDQtGUS3a+8XqFd3GbgT5qYFYVYFfA76dgpSsDAA9hAv7Bn7wTRoIH6nYk2PXo+sQg8BbJ T3v7c2sBIflwl6L28qrX0lJmLy/biQ4/UHCqLTx98+GqGg8b20b+zBVkIw5TWpxR4eSgtczNLmBs KBFs110PIal8NzvoZ31xhLXHRKnDaD9OLI65vVZ4Qly5+URp9I3Fx9jO/CvZcXM9YDv7pX1On2CL f8lRL/tBo5LnLdcRcmoVbbl5Q1LBXrpeCMq3hDAXdIe71acsMryo+hUZzTP3TCZzM80AoEv0Vv4X mjREO2/n9FBjAo+vTPFLp9pTlEZHpxZmK+Tu2NUmSywOKZTvUPIsnwVeQjHxKGM/AmkVy7LaYaOj MZXPaFUqelkWt/SzKgra4idPf803kGNZ0H+OsFkqrVVS1+W7pm0k9qf0VDvwjdgQmYFpJoksPfgZ yCJNBx/dBcE8tod1/cEENbovRqE+weJzJpw6NieETiTKHhCpJCS2Ffj00EbBZbM79PGsRwafgR50 Mti6RwzjixyDKhmoY9rbfNaxgWmr8qME0uDBeuBBxOtD5pBaN6hoS0Vou3uHooha+LZI99tIrTJy F3CWgFZXJ/2QXe7nOK+potNYiJxmL0yO8WRBJv8R6rDWh76fRt0N9S92D/mNaM2wOj1Ks46GgDAI LkgpX0P6XsZcoY0ynztUdQMeQA0i36xwetloN/zdC9Be0deOS0kAd/1Uc5HBOjKPh5/f39LNPCjn 8cIomsQmcG0fmEmCYEdX8L9jNQ/HiTqrnqZ7cTrZz5JSqcsP0oxBPd1LME/3nw8SR4EVx5tSFgWQ aep4V9WDM8oYRJdDnc75pr0wi594A3l+r87pwfRojN9T3MXUop0g7l1nzQsnF8ofxGewUMDX0had 1dTO1oOH3ucz9KGn8o59BM9R2kK0jjJCFyzyYP/SxUUFJldx1FxcxDyEQFJMrNUlMtfJFyJPe/uo gdFOQR2mvivKOcdCxDNIDAK5WXS14bB9kkz9PF4IDMYT4PSSliqgDhdmVH9ssPDVZyEtABM5yEgR EbAvwjyKk0WRnRfiMf7rsPmCpuBYGxUc20SNS72wEZRL9Ic4GU074MoL6AS9lqI9AI3wyvRVJzGS 1lqsW1xYWHGLA9NEaeF0hUfOGvv7N2TYMPfEBhkwfrH1VAvcmqVMnTT0Nz87uKthrOSkWKKpBs2w 3aS+mPdeIArc8kSb4M/UvNwC6VYdolVcEWtX1H6KsWfwYF3CBbzT4zKsb5cXVA0ZyQkUhT4HENmp v9//a9NewvkFqgg/4+YS8pvtcq4al0eqIUV0D52avrxe0qhbcWAZols91eN5od2a8llmlO8J/l5Y YQsclr3ohBCXiWkB8QSNcEDEQ5JSXYoTNzZr3Io6pudVpKyD41w96CyB43IYJuGTkTMVT3+qFsF9 I2mowPTOF5vFXuT2a/VK2TZPnmduBDUn5Fw2BWw6hqU8HH1p10ZGjeoDjUF/hLQjojWmcSJ4hF/3 QNCd9qr8ycOErhrI2W+C3IJzUROmcs2CLf+Q6BvRvCNy4/moZKkRyJCUPjwHj6GDgmHMTJKOKwTa dx9q/gXPm2/X10c/6ms0Pm8ipRbQhQSM1uSoD2pZW2vrTBiUNnXoyEV5T54jEXRbpRh4JNUil/cz zTz/IaJ1JigyhuOJgb97/TcIu+YJVO16NRF34sOO5oqUrDu8WHwwrLbihEc7fPHffzrDDPi8w6h+ 1S0s1MaZlPsyAg0juwF2W0393k5SQWSu08ABT09PeBcyrRUW/HSXKOCuODM6SVw/wYrqSCsPbATJ Jf48qMAx8mdyqk5qrjNszaSE/tMugKl3auJDL/aWjn1RbiHgYbYw+ojT6R+YZygH5mZkPfsV5+Tk zYHWB0e+hqx/H8/zQwo04eqkqaLDN1P0FUhkEN8kTAG2BE6ZSL+XaSQboDBNHWGAR6Ui1uJNqlmI iF/wSU9EX1n9WPZCVHBM8u1lE7oJ8PzYGT03/+GBw+Cj5MScKzTJ93Ekr+f6tNcHWMXZHJr3E5Pk rY35PYleu46LCtMcvlq9swKsJVzHQZ0Z7uXJi94wk1sY/M54zzzGf2RFawslz85Trd4pSugSFlyc VfArFroaCv3xvuS0VSOTlOOsTx+fPCaVQ/UUB6IP3udT+I4feMkOgdNNKbd18qjmFlBOLles+kmu wSkiUepb6WfyVN1p7dNh7njM0EgBDyol1Nb4pBTIzbRuenKJgmj2VtsHRBs1qG6kj+thE0BAAtQe msaPc7z12Ju9k5szJeI5doVddQH2I5swZ5YK/lVPOijB1EPFldXED4gINwX3WIXru9O+fcua8l8T 36UIsP8D1IT5Cp+IyCe98FHRd1Xi3OzJGa6GPaMTYwXWO5DV61lXcdIqDtSfyqLjUONEYmvtbLZt F+mnpmNiKM2hlqhmhNdhLhrlgLaV2klOoh/ikMwH9tH825HPt0QUB1FNHyeyf+rZxWLjMO5zsGL1 7x9tCu0gNVT+ujgL/t6bTW/HrE7pDP6zxGgMUJz1YT+oZoJ1+90uPRP2Z1+nnXpZCudzSnWPku9U 9So+vxcuaKEDhrFjuWOt44Xb9gVQUC0PoJqzcrDiUz8X2lBm1oTqLvC6Itrgm8+eUYYlsZ8YuneR heOXtsY4aoh4bGl3+Tx4g7WuqsFIwaarKP3gakQdNQKLBy+PkxmDd1M17nUY8eejwjTPZOUfllVh G0G56abYUsX682KB3FyPcCJLRnp6sRF1uxYEkqHPrScGFq9MVrL5Nd7VmZH2aLX8ZLJBpefKv2Tp kKAhAGkB1lyg6qSQNCAR8gUOpoqq4ErRcQnQy0axGs+TVVB8k4K7u+83V9uTnzJzYw+N8SniTSx9 1DArbOyAhC7IS04Y70nhkTRgUU2Ojilm4aZmBWaY7vAwKJeCiIHijsE0OE97WKGtudCkMD9TCyi6 GEm+ECGcLC4ekN7GoGIhQETK6J2/ezgV0hqHmJkn3quBXplHjH7jlmFISebZqpa5Yv0O0Hc3ooEL 5SMT+wQOZGb/AzC/rD+hlIpjU8bZhtebnlyoHowpWyM8Fbp8xgjLIgBvuncDuxChzl6R8fkBAhvD +pz4ewVHCMpxzrO6ooGUrLnRhEVlARVg5GtzNC6xoTGK3OSbzMMazOsuLBtOB6vBcvwaFoGTQZgU cifBnZOG3xZFX9jcD1zw7vgXZ05nHa2zpYDlI0Lw+L2PaJ5Z9E0hOFB7lv4p+G0W24Syovfy68Yr IKzB2sBhJ8xCOD4iK0oQqq+tixMFF1JnyCAeObXETNR0+nJCJ4/emYwjqEidwgG+9U3PwbEpiKjN X7kvTPxYoJ3/2BBlMsAqZQvuqZbea5DE0k5rOQG5F6mrALG49yu0NIeyCdP0SOXcJ63mfyUzOaU9 G0n4SBXoJjAdb0v80SJGd39cNfCnZ/UDRRTQQ5KPgLqEMCAp6w1N2IAxf0qPTljWf9cnpvvqweB7 vvPjd5b+tdMNv04ZaUY6MWuDuoDmPqyMeiE4Qko6oH06vC12G7+KW6JCPSNXU+LRL3SHcq5sEx0f UzKnMJP7wMclORf0DgoGTixUX5i4Jqmd8uriOJllSMSBVSQ+ISln2gxNVC6gQdvK2redzOUtLf8w 23ryA6kc3HGka0ocaWfbjzAMBFYwec+BrZXtt/8dpnRL9mqWoJ+1uuR0QqJLPJqlfsB4iMS47UTz 5IIkUyW88f5a7WQE3UzvaShKG2jjFi+OmMqZ/MjK5qHdYPHSfWDkYDCQDEBLT51gBa3ZQyDh8jY8 2QO47f4hjfPJ7KU9EMdUTPrOt5c9TBtVf06n/63qUMqaBgf2/sk37ZoYQtMj3anbwtcqEAeCh80J jB50IuAAtmrTpvrjHhK0CBhIyu9+EnT4ORZ9x2nVFpIpCUu0BuQKRVpguqaV9Z+ra07zO+w/orJU GIjtWWder1XVPGeBdRslmThoddUbyRGPubCae2ssrJQqTgcDdudK4B5zS4owNa3NaVFS7OTzCiJz Z6r6d1oEi/KSkKQfdSAY8K432ugz//wDTfhoYz/tcXjmRnODvCp2iZWn8Ul5QXj9cgtGDuxcuZxT gpbrrRmX6BXqiNpDH/0P9jRXOkxlMQxTr4wYfUjYHIiDnwH+noUkmuXwCgYBwvug1Va0AgHG2/GA /HXGGprdESFtyuYLb+6mtX8e2vsXgEZnrCfbXF5yWmfbnmgVrNnnqBBpjlB/+3MUfXeAv2gZ1tk9 5QVJliYwDcKY/48G0Z6tT1mXBp5KYY3x2j+NFuxB4SxcQD9a2FD8GIyiUP3qGuVFWdea8NoZkSM1 G2T9dKvKfJaznbG8GGXC3n6efzk8BF9V31mrxs1QbfROEz6tS9dIPuN3Xpir+IjmZzl1K72h2PmR SuXaxwbr17VUafbyakgFocQydkEPV0Y0YpV82rPj8oX1aaO2WEhGWaJtlMEAT9ozjRT5giSdkd0O +y11kKG0t1QH3QlUsiTkMFtYIDqmZVTBaJtrdim+IFZPkMlfYa/ID9SU+FurzbK/wVRrBaMpyM6Q 71vzouKfk6fnUZhCfmYrEM3FsvTkkC84oOoBCwPg2CB++pcUjTDn5/hSQwL86yGUwttXOPwixHud wiaBBOCqNbqZxruW8/7k1B06sVogWh44huijJxh4Y/OsXsYThYc9vynnS8PIM+Dj/5SYK+rvwSkY w36cJFh4Qqa1t/FHJI7VzmW16LV2Bi8JAwReyE17MFcoxWBwNVFKn8SHP6FXwPGF9psFMfmTHhrU LRDe5gk19B4+E6ETgl8Zpl7sMoP3OzuTpRCsp54Ji0hVzvhR0OdDPAZxLonGyoaRcG5NBYxntvKz yXsGlljA6SfUK8ZvzZVs5oeb/znHPCXEte4d6jAhJ40H9bMEG1q7pHaXqAkiz4og4npyJqXfaieX LgOtU+FaPdlYIPvMQ4XaOiRF4lDblDdU4/5Fl5R98xb+3QGhGDWMaRsePdQM1wJlHiLfEEYsNo6C 2UMmdrR+i5wOGb/i0s62Llz5o+h5MzmXIgtsGEjcqJRl1Jgmyh1b9D7sTMcRp9js/dSibM/knKPw bT1XII1ciOp3XGavWBx/xTUiROtIYJxXnxN2bSYJArt7Ivl0q8EmHVES/e06VsvPqMw1WwL3clin K9jdyHyHXLVe6+Rj4treT4Zmw5xxsp7oLJEjY907gt+DJqHoqz9TyU6104xsBymlUJgNXkKHbW8S 7faPKqQLIwmV8Qpwf3k4baGcx+LJVJPFV/bMel9544zcgyaXJuK6R+g0Ri4Cfoo6YneZCDgCfUJv NnjywdhTS0G26Xlo8AOVCIAvFE6HYSDrlbWVaRXP0yl+HwW9eXNoxvvQQWGetTI1KJH2fOoiK9/L +vVQRHLEAk8MgaZ3tw+Thzx0hOVuXrvECbh/DSi6nGH0gnlkcRKSlOIzj427G3Lw0ZrIVg+m7+ey 5AJx5FGaQpeokgaSKQvCdznohfeiKXtBSDLCJ2GEI3ydH+B4Cyk3IXpO2aRxnlrxGG/f1C16gJFF 0QdZCuwjHY3gyzSsnmpN0pMuhZ2lLfKjxUlYwHeasvIxcNkH3+AWe/vvRD2Nf5yZgx1dfAruNdpi xrNu2NEQt36UFXfAIOEc8vs79vqoQHtTcbAwDc3GerDKaTiNnH/RoTjBGp3iiQFpgMlHIOVeLX6n FOByD7eMj/lp5G1pXxg4iUFOQyEL83QstUhLvVqhwrjXhGlyxrGALpGa22suuBQ0gTbq+EC20IOS o0NI1vwxBeHBobeQrPBAJruAYoMPZrTsf4U9EXFcD5xuTn7PUvITI1gGepYqaW8RxwB+UvRfOb3l 0qoz3yillXZjSWv2Pr3A6Kgb8pXci33h/LYG17wiIo3oH1nw8BigxypT+aEld136bgIZ0GXzwIyL IDoRGbH/tSn9SSWpsYE2Tyb/dcJYs2Cf5UHQNgkESPMDKUtVq3lGYr+2ZWo4VB5NOlDoQASYi+X7 cJJoD4LmoA2V8AiC4504k8S4I4vwzu/uZJ3cOd0NVGIjjNGJb02AMKdWM8hFFkWD0gpbXcPJw6je lUE/3t9h4qheWZy001wxkKf4RQ33Of5YRgXXkhLeh0Ypkmi1UlXK/jdfIl3+Rb5722VD7Mw+Kq22 o8Ux7+79P7JQd2ArSmOX2i4nJ621GVjHkUPWV6wIfshk5xwTL8LKnDTj+f4CRzU6xtIb4aC0m8L3 58f6e1t7cTCTidZ9wdLaRHngRhul37Xm7QIt/gAQzaehy44q3DZmbpcItW5BVNo1dIoUqvslhuTl SgkahErPDE+KVnXbpByDIUK+2ESGgsG0YBSvtLks05gNxJtLRsKcW9AWipGRex9TxGAc9fpHmsFu C63FG+g++er+V0k5YGbZxgAfG8bsTV0mcvh3ktW7oFGv1iDaCz9zwrQ68wx9wCKb1ZlsvfaZRMRS BIPo5JGVBzCM48tkl1M5fOPZvHcYV9mgDDCZ5p+VT1Wo9v0FRi+B/F6WhFd9BfcqaNZIoDUmMdHf SrAiI1owt47OeN2AZFwbO8JWdyIsCSf2fQSqKx7SDdZSvzy1rgFQDEyBATm+cbvUoxXprW/yoME/ 95ytG+y611HHgoE/CacXlUe3CQJFQyK1fwEg5CHc99xPmEsn1ay4QtNKLa4hNMMA0PHoqtNc0wo7 Q36UxQt7do8TK0EYxkTh/gb+PcfbdJy2mdnxItzWcyD3TKsOFjBrAiz7VfgNYP/bW1JmpQCo/vOB OrYNx5S5rFGlzFED9XuhPx7/FHiKPDedoRK94HV3AQi1qqRlbxEZqO7f1OvFhlnqv91ybmBnO0nJ hJvE2lN0fAxj5xldzF187UXtIlt9CJMHQL7AbIShgoF8JjTWNsKlEOR/sXsT9D/EvSmIXcbxcHkO 3Hh5+wkfm9dELLeP2yxF3S0Jfhmro3HV7HW5tB84qxlsziOqszGQxKmLc7di+enUWFsRah1knbga DZ0/B01/ZofgCcxw/NeSV5H8P5hV3+ynPzSUStvIqKggvyucrApOWW2JWRxqioYTcXihhaCWiAwg v6h6WWhMwx0usFkpKcgszesbzftFExaMerUnvkxre2Fm6z8zn24QB9UYdtXWdovEFkPb36ljkX7E eKzo0M2Nms830WeGzjEPLto/PoM5fl9dOTDdJiFVoW+OnaxAZbR4tdPDnvFOO8nzpnaY4pnuwoGe H+XHnnG5M0Ioh49MNMLZcoxYJ92n7/80ZmJXba0c46taGAwgTbsNhlvPCuDYv3Gqo9ndxDEjkP6k SPvl+Pi1DEFHybkd1N+R+VfiFLdQQdFI7LNchEDic9NAjMeYoLOGz/f9oYhKO1mj7jahNODU9/4q 7xAR1GJdr1ydTuGcRsFAn8p8EZXTxOMgdL30PpCILqkwJeKKcUM63wqyt9SilUS26/Q1jxedoZ/e vdC0oFIKb7emWkLmp62LFzhtyTueKpjwb21UX8icwnfpzWZf2Xu6HwW3kwG+PCOXH6p4eZM/kxfS fWr6PZ/dSciADWXbBDojVBhoyvTJawkzoY5MhBY0AV1o28cUhGFSHtF58vklz7/Lrg1OB8fjoWtd LWrSVIA+GAhbaUqiL2YvXnDUHwpLviSL4l7cUpWqAjqIqkloinNwermbdZM70wbpnIliU+XFc/PL NLzVRknpDOnGNszTS3lMJqVKS4oEjPMy/Yd/t40togw3nC1jh22Ly7JulgpGl2pDgvBMcym3vsYi Z7euMgH+tzU0J7hhdtQsx+zhWVcHFjb7eGD7ws+p5JngrI4Q9+nRNrPiEIDibrrHyGoMDVBb9p6T jcqg+wxIMJbzk8datiYU0+AvcUpvpq85CCqCEKFMKhFf1KiqqHOX54G4sRDqrVoCF8n7+R4eAudz 8tcgsbGITXu9zVD9z24DninXxoxQ0eGLCeSPqWbu1Tvon25ZsSHqu5kXMA1tPc9ZN46WG/VsLNwn JNu+ec1jeQJpycyY9VwnFntFC9FvizfnKBk+ezCNZ1C1Rp3XINygTOeKQy4W/EiMaZ9G0K2L6W6r dukS/I0I1TOtae3KV/bRaa7/EIErgu0hVmXaJGNtb+0qQvUb25uOZz0NXp/yDBMLXBR7DuDeFn/9 /iuIKd5x1Ff2tUIm3TiiV1vT0qdD38QVpKA68iaZAhfI/ds1yiDzfkKs7b5RdR0X1AxpB2ctj4QJ hG4jDH68n7um/1bQZjWCSF6MQVju2XAcKgGTjjwnAYRzF4/3N63jBXme3vDKMuxKs33UQDL59/6J eNps/WetsiDlkeLieyPnh2bSC0m/XZBXNzgF7JOul/PxoOUCMCpJMUEAyh2rQZFSNj322Y5zzZ08 L/+IU9W+3JIdO9ztF6vLy66H3Xd0V8NQKkd8C3t7f7pe0NoQ/mVmDzrGxYKeiZPNes8jnwVUqpN3 2IxmZR74q/gl0n5VADKg0DBTy1TZNyHoxHgShzdP2yYFQnGL2rC5MQ6ZCY2F61gNQnkvMggcmI/P 8eAdUD87iLvbpfK5Eo61vTxusSfajPEyV8gXgDjRg3hDncU3w4PB3Rbg57IWuKC9lKrt+1n0a75a SRwF50AkPNjsRdGTFmBHYa/CrekSEWY9FOsG35GkRDxDHBlK8Yjmay1+kr/T8q59R1IytDrp9dPz EzEKZNiMds46HLb+Sx3W1UN5xQba2WJs9jrMxmxiFvNfyQskXWesiSFWDTDE91xtT2JMQBdS+AP9 O0b7dDGuFf34srgcFRgtvyG1OrFW6N2mqIX7FHxQ7JxsKgN/d97c7VVjLU0DeylPi995SNqJ2jkB hll2G10gGQF19N6aUUu3hVGMyt5QCrY8xlC0UuJ2AjnRnlphAUfXzP6QD3nndPX0bg12qiqRxBlZ faswo0Y4TJ3XSUH2W2eZe/CY+1CjMdzZ+3xy5RGiZcj5izzR7j7+GRA8l9YZIdrjT1OQ8EO+0sxx enbHErNw8zfs5owzlr5UqZPvk03RUkKrMCBjAUvInA75CmGaIcLTrOrQnzdCn8F2RCK3L+AQ3zKF VlcI0j11/1b2ynKS5a4ZK9UIC+E5Oh5omqMPVr0XKPu3rjd+O6ljzOR+d8ip7HR6+i7vDXPa9ywF E4YV39xQ19PBe859ElS5E47zMOqBRJk94JhXm5mEJQJuYZwVgQ4M5msqOeWYF+4JwLn6PopdCzay aGtrUg3vxaw40fCSsTMZUG3wnhJfmreDOsORie1Vy3SCezK8OqofXlWuN1L7+K7jlYpbxE7/V9c8 UrO8jKi7WHOPm3iWew2Xnms741QrpkS+efXVoqmIvfw2f48Vv+OQNbmEExiANXc8E1fDOHhUDc9O 9964NhXkwc1KF2cXTnVxLaPLJwkI5tEObj6PeUQQhJpWgLP6WllopQKu3Fq7zW+iZxOHcO/1LI5i vS2LOkipD88o11lDjozb/JPBVKguhTeqMcV4RZJwusX1J3Qbt4qMZcSgYYFWZA0YLwqoDX5+xoUP mAF3+O6zWRWLMA4riZV5p+g3cg8SUAvfITRbM+vQ0TIxaJ+KSSyFFQ8g0QlOr/KIVFKg1bnu21Qd UWMIqrNv1tsZURfKO2E9rtCuuNyTwQrhRqvNN9n+7WUnzmyOCmXBvU/QZzu64o3FDeKh0zM8W5LR KqvVkog9bQtje2/PUZu3rfGIe4JtES5I19lWsSOX/hK9zx97OpmaXdRSQFtatISfvBr+kz9sFQvW HX3TiC1JzWAkteXkdGf/pSwGCHadHJUNrX5kyKxAocwx90tQboLS8QEbbQ/EJjpJEOlwgYrSMW+O lHVRPbUqJXpqn5tS4z0Ld/nRQFy2SVKDB2+3jal67qkVPxQ0C153JJ4eoZ5BEIjQpnDlOW+kbT7B 8fMWQX/9LcleS3P6b0tKW3r8hcFCjJTj1zJOj/yNhnwe9+gFfYnT8HSoD1W6Z2xteOxASpMl+Sv4 vnWytgSFiHyd2uxwupPzRhvT5VMn4ur2iqUepKg+UHkPpT91Ff7PKniF6dFaOWE8WWMFhVNN7Bzo 5Rx+BdG9EHxsg4Akfw5xhzHMReC2Tsh2zouu8+yPQFIe93AKjOMDbL15EJlReW9ZK4e/4EW5r9UI 8uGdaMRG8+dUhTG2kuft+e8VmW7OBf+ndtKujXxlvE1cxWQeGPTjzlGbVbrsa1FuodhaVDgvza8e tfOnhfyWz04RNwl2Be1AYqR01begUgZJa01RgMkRIPWFQA/wZCWUj3VrCS/f1zy7SykL5UfIFA8q aCfmRiHkHcSzlwTrq7/lYn0CMHuYlsWm5Cw+DzB91oCTMxLHwiKYYB28le7RWbuHmCySEwz+qOsL 4PmfQv8FBk/dUtj3Ddt3g2ebh44fMDQxC67oOEvMvSMpenkplW5kbW7/l0Zy8W8C6VvyzjirvSHa ZEyS05Zes4b7V2zNWlVXO+Zx65fVsPTfm+0MNcuX9S0a+zP38rfUvF6GEixjWf0AT87wZNqFSKCX lCtSfTzCS9Xke3sVHbQ36Ux8XudJabzb3WUVxMsM5HWl+kAtgiI3GLL4g6nrSJvawvykb58ts2pj s11DRsWofo8q9a9+x23I4n6XzemIbuAINNmqmqDQtIyo6QkGlkcpopgeypjd2uZ/g//Nse640EIz vkkUke1bHyv+a14VYvMCP/Y37mPjpPEfGARkE5+SoBHvSzgl/SYCrI7OoXsJSYGpRw6YEY0PBnKq DmfKjizje0ncS6FYxCLBKgHy+j7aI7jX+DibWcq7GCrNAWtbgyLMh8UglVOBGGRuJ1+OIjch2ErC zFWt3KuZxqBORkLpGiZJ92VwxaYqt/su4VI7wmoOcXPumiLkNsibHjS3oOsN0uGQ0INokAmzsr0a wcM0sIEznBBq+f7wBdYvs6jMYnAg1VzYj6UsRkjhqggEdCmFzhbqUf1wvKtLz/st+7WtwycGb7z1 3LBbUoKj1YuL0/4BYDGbjz2WjNpt0Pee0DSTB7vwqvcG+pTr8xo3slyOxt00r1bCGcalvGH7vTow x0RkFhqZQS+6eXmz3enRf31DrgL07ABw9svivDMj89aV8cSeyG4KYgUhilN8Yv8A1TRgQPOn4qrx iVbLsw7ou0CGDINa+VvbLG3tpWyiSryDl7zkBxkEr89I3opNffb7ru2MQnkNYpqedjjJ/qndJzYR TgCp7HA/b1HRhKbsjLHe7t174AXkUq9hHDb/sjSXt/Q9O/JVLdpcdxKLQDbmzzKcZ4f0LKzQlP1J yw9PgoJNf5AO+2ow2uyB2HOqViCWl+UAcWwyaYrSlKIjsCqR+EuxgCkTQnzElTnkTlxFPu8kB5p0 e0988Zf1z1+DmEjGxTqamxwCDXASNDbDYRVFFgIrirUbbFKL8y5cbNh+S6iPtsSEQgWX+z306TTW zsnOswQALWiCRgY1qqNuOO1KndkUOxelIVvK9xmdv8JDh093kx+8irVRjwiHsVvLRxGIy+29lFsU Hbg2wsKG8A86VfXzs77HAkILjka3KI3Q4nTmuNzoUvFxXHYbdLz36/wQzsYAQB58Cdr4YwWZBp3U 0glVLLy/wq0aLS8jRkC0jYUlHHH1FyBnlxsyd4/NpwKyHtmEQH8IjH+jhWooVIoQLairQoMkrUyz poZp6eXvZHrYiUrj4gw+vWwpqj5NvOgBBwHSMguC4NYza7YJg4DzMJvGSIBDrXWA9dXqKO4bEl7r OGIhil2PhjSbIKY/8ZGmIxD8ClPv2mqHYXHeIpwSDCYv3TDj+vHTEQFuKhaPuyYVd9hc5VBTjQDl HpUbCS5FAmFpI/dCfIZt7iuL9hFMsGgPgX9fMI7W7SH217IpfJM1eCkGO6cx9RF4r48o2FKHN8IO xi7XED3Q94vNSfpwGUII0Ggw7rgsXpXC8/GH2ihyibW8oNgOLcqxtpKSjJwsmg+hADnNU00R0hgl GDhdPURbtCjKlyiL4+TYXDCc5cefoWcb+gncGFHy7FbdN+OcxvPvARzkdJtFAk/6wAkOoJlR1ZCn fvDtpDnWUf6v/o9BxFnaUxey53yxsybPi43aAwt2pDEHL+oLR3xIvfPRvqgr12K6RmFTks5DMl2e PhU6sacRJbpL68dbA/37NwUF30VVyZ57eG990L3CsHC8QVU+xnBnmXFJhNNXjI/hBsIl0ZX584Ck j5+e1FgLIOFJzKmGf6cvZbnROCQkQg0+U4CZOJVjiuUxt2Xhboi40H09BQbm5ilJMqVFSATqKhOD XLFcGz+V+hhd9IfDSZ9kWKGufGiPY7+XqB8xVEA7yE2cysv2/Pd96zd4WHAuITdS6R7zd1GVU5Ry Um/+Xw6uU8lNR0Y2oxJDzZtckYYlanqqQowrISM139KZAEIfxoe6bzu6aqakL2aINK0UAb0WaeA1 iN+ZwAlyyrUi7zlog+p0wpEe8cUpW7XbYJFlTCddvmS4my64UjRfrJZiLko8aJzsZamvc26WCS+V RR8DLy6Vf/9aEgQL7Yoj1oA7m1pZYO14e8DviGTQB00qLAMETgII64I2bnfIZekKcFxgMI36VpN0 igu6zt6pLZ4OAHfAbDCEpQ66eEzFqVTv02/51D81qvilx5OnvyaqFLX2WFcE+ilG3Oj/8XIwHvqh h1ckWbiXPd+hCG24b0RuAhVWWqnOYaeZmTvkED1Iw9s4pw7rmwJ0/0srfse0ivvfsf+MRk3JQV2E 3OnjQMB8w85mwm/dxUSkEoCc5b8aWQwiOuQ0PjOd3ysybKDJEoEmV3tpsfUhL5TDoH8cpNquzjCi JWdCSPrLvG80jp63dKjppb1NcoxxjZFd5CUqfPL4WOzmghL02dKiJclrbcXdN5S4QfD/WvNxGDRh 4wB5tFCJkN6gDrK51P4PEyQV+hQb7cU9/F8TZxyfdxf2oTiXI3+R828s3n5z8MbPLAEggC2vai+M 20B1AoWQOL4kRhx/Z67N15z6zeuJk46/wwG1mVrEdt1C6JvUcUd8wKUlSINfnSprOF4s/4C/i0lH tpIf4eyw0UBJL+LjcGqHQ42X7+oIuKmnzQj9eMOrCAgyKs2KlNzoCIrO+G3Dm64ON/c8b5Fr/RJB u4bOBoUALor2ttBsaSEfxEjdTiQ+nPZvJ5JXNBiNtV0H+HA+SSw9DAItB8TAwAJaUUMiVWQzj+YX J3ciONi3EMnyI6tJi29wlr74NIzTDXNAmgpWBdsP5w1qznGLgJ5OhgKJwFwtfQh6psJ3w8fqSP0z l0bd4gz9BgXQLgmImjADqJUyAf8h8Aa5uds7KZaq8LoIRVHjoFeyRnX2Vu700jl+1MUyZKLs3sFC l1LYTpFcDthXqQWmZKayyoxm38EYJsQV1Yv4EO5T3GasoBd+7HjF0L3bVYapPOxv3a3oLaXu2Dv1 6FCDCtjZ0BsuOCWhB6SiTNI8nMhb6CZHqkjvNXDHhguIJj96sqL6vKMG/Qcwk1ykY8puzwQO4XSN 4TWigCWaRCFHvFz7afM8NDZLjo8PacuIeOrvJb7njNQ/TONvLHaMP39SMjpKtIHfsZo9j+Agv2Vf AeBVRwyFlv6Uf7USupUSM0aqOQq2R5Fq6ewgAC7NYiHRG3mXxaMJJ5sdBIyHReVY6QrSRjgqfpqP 9edVu8EVxHTJ3V3H4qx07s7VTkeixqVy/OiJai+IsJNeCvTu5UrUUgGvEemy0dFkXXHOHoz9dfNU MFZewq7fm10uLoJ6j2yv3tvTTMTrpJpHflyNiiV1EHjgOn2zEnUC88YGj2ffcE01N+lG+ghfm9kn QasYdRl7O6ys4/OXJDt5jcrD/1XX+U/sY6wdGDsQdiIWvfUrBZwbaOscB/R3rtBK56LO4qfy1nRb xAiWiYo10a+wjWNCEYivEaHPqhyW3+AqeMOz0lY5PxMAmV4AtbMdV2JDgJbU+hK+DVlpW/rj96qv CUACWxqjUZba3Ybg6Fa7DKPdyDaUSm9s/wSSc48+71gqhgb0u7YPtUHDLlEq708zpuWPTF47k49t MRLFnsgHZ1WEMkwIR7hEjo+zDYERTAFNd+UWGNQ9GqtMOZU1Ysw3Yj4YlfLZ3qgDRIXGsTlexr0q kdBbP5eHgbyC5kRAP6CjoJDUNM+s+tfffTLVrXN5VqeVrVHG5/rzzECNvP8aHuf2Zw1yq9RQHvpG 5FlhR9/vc8OxbcE5xP27jt99JPdGGSX0V0cE3GkjXW/ool/R3Tw1fj5M6S+bbSTtMZ4VXYwFkGLy dPn+iApmmSmEOcxnRW35QppgG/Z4dv0bUxYeZohvaGEe+XdVx/3FcdygvzbS/DL27bpRgiUUhSid EkfWbZGWzpxHLs8QfxB1752MATIQfYyWzy5NWfrKmebNh0om1CdqUTW/xzeX1I0sr2SfsFddEIbT rwO0R9fF/8BkWrNiXgxV9AJkZAdfFgr5It8CRKygFVETC2wibxr8hzO5s7S2lRSinurgpZxpl5Vo z+iJsJ3J/wzZKFzXGCBMvFO41Bj1qz5STiqHX6Z764zUPcQXvqMKFQ10iuP7sY/jYpfcKdF1oMfO +efiTtZ8Pm9tXvVxCOHjft/6EjXoraQ16sf04z3ASlqsQao2IRHAH0+DI0wGdDK8efCMjReQGfUq hfAbm+0nFJhbq0DnQ6LkqQ9JUeJXi0lv9eQvigKp0fod2H21u/pl/9QRdjLFucigNnH61/KXk1mV uOR20yRqFSNk9/2t6t6vAorDxZjsiuDtmPrhKOjx+L/L1b3RQxanZKWgME0fA8yLE/RLYTcQObJ3 2K/gFUwrU25e3DDqMnkqnYwmyHtohrh6hCe7++nziJmjrdIuIdgbkSI1DTPEvKW7cUl3lZuq6m1g GrDtFSoNz9GwmA2Qf6Y3Y1EZdJDgkPTTWEOAOayjluVfYIZMLU2ShivVvBsA/W8KVB7S/b3PM8cb lhYs75+tsri9vDeCpztt8RZHxUxX3/Y8GvvciV1NFToyrrLCEn2hqBFEniow08a8kH7YpRFHyc9z YBcZBraTWba5JnUNfWW35mYMm7uXI+w/+BUjDJwrdQP7CCmhyvfpWxf2HbAl+eE6CMPjjDjmrbwV 1+fz+4Fxr8SSMwtZEjnx8GvK3rVm0aJ9uKm35mg4EmhsMELkfpazE3O9heCcrlX+loceo5B8Zoym h/S5G/kJjqfuCgKTkKDkLeTZ6gHWthR89IrPLwhMEvCG5sCUhNbzUs07DYKvp6iTB6qKOG94nJrf HEbEyxxo+9O0gFNU0B94KmgSvc2kqW75bHL9laM3q2iytLzZ+953D23XPRMA9RPCy8SUO5W39xD/ XEAaXx8yrZGLN5NfYLxtfIO3dGJDLy5netmxdbEfdQAUGCyfEBVqauvWhHHE+vWkiQbocCguJ925 1wQ+upiCxnZb/VbvMwvcYE1INTWdxkZQNSovPFOv0mKSMBkbgZSFBKC3eEU3sUWS0hc3IVOSmLSO PVbVJpqo41kSM1zAO7jb0+4GM6RdnMBG21cudmqhFSV/6CRx47vzKJ2yuPVJMhDivCntw5KnDSFi KFjs/9ySD58uh68xreDzMyisdDjZuXl/RMWO8jOA9kRv84paonVUeOiMc8onMWppeMTXAH7kT6ci cMdPFivRhkP14QMw3F30eyaptO9T/+xEuweYVrl4oPUWm/P4i9Rkq6UB50Xz1UsACNTeB1US1ysN JAi561TSynMd/kUUnqz2O+9+WyImvjXqGaoiHp1H3Sx2qDZGiM9n7/jQ2xi+cpA6rs1d7Po7qwGo FhDAWAGBdhC5IMh675i0UMMurcqM6NBvCABjf68ikJMmHW8UaHgTrpTt6M53jBlf655cbaNcdZP6 tEr4nlEPdxP4HMjJl65cDEpSH3UCslingqNr8hWMO2rZMXa5bLxgeCuOTCz9s5UIAQjLWUrb1cUv MIkJKDr3DBOjf70bIYFGbkXFaT6fucQzshEDTffT+DUIAe2pnN3zG9HU7NnH3GXFE1hoZ14QBXi+ N7peQPV8TvRp8QZ9mUUcrg2LwoR36HjdFqKuPO67CgHg6X0/cEPb21QV3jeZUBo86RGIqIuMTe35 ydBUWtVx/AlSmrwYwy4wr9Emw68I+NBguR31fFIVaCxWcQeEVX9p9e7WFPn5AoNv9M0Obc1dmKEd Rjj4LFQG5lIeztLFIAAvgxUANcOV7oKl/YS02pjGRRK/z2b126K2BdbcrDoiytA68wQSsKecluEL Vjdq2SADeOYQvwizgXXHJnqaIzZgPS8dsGgQ5Xpdr5Etmw7r2g7PdmMbtc2R25e0gAuQNto680Gf ALET86xrIF6PsmZ09BwyoSE8btfh+IS9jbnUG7rSjsqhRhvpQFKSjiJZJs7s2GqzXmt9EBuATNo8 xEZmGLQUJEdUGpl6k79i100mKRW7SCRhBBvrHfWncG51kvfOafFzZGw6R9rdTw3yFt96IpodJYyP qMLYT6snAzwNO3/eSqYTGhZOQ61EDC3hnD8lvZ2A6GmBXHpbRq37BUKwXwXi573Nwxq5dJYZpzVa Mv4Yp1Z6+MbhvTYnALCL64WFQ/VJB/M6ob5On/sJre+K7cHyBdb5nW9U/AwfkXKNOdWZB0VSALTF EucSW/2qzKHJ+GftSz3FvuOQIxUltNBB8QnCKzXqpCWvbvSVWghjE4uSwAvjehMEsXFgH+/zGSHx W+tVT3Llb7xO7xfTmtsO2X196c39qlYf0UI3k0UN8yhJ59OqH1boSi5aW8aG3BLfa5YJZBxGz+Em y7cJYUJVG1bVg6VsB6cMeX1LlflwG2AUdBs5LPJhr7ud1be7JYWGVsrkJp3Go9qTcUBC82cAdK5r JJL6ngNhVH+gMMPwQYIl6BCH1ex9LwljSvERL/+3xXC6rml6gGBLpjoEiPxzOu0J4mJDIu5qxBKs j3yBIVkBperAsf4nK3QMOQcJbK+wlEXORm/G4IFzApfCHRQNTrbkk/E3jI6o2+LtEmiOrGWK3Fsm vrAZxn83EiDFgqCyTFLbuCD3GjNrLUAJT+zRm08y/BTqGWGh0ScyHjnKORb0BbT81w8twuJBss0h pom7RQRSJcsRHQvYMXW26O3yBkOfy/L6pQ1yaDg4KMjuB9v147fB6woHqFzSMvmZtFbR8Dvot+qu hxHEXEZYH8j2As0+bwKMM6vap1Xnq95CAHJzwWOI8Uif7sYgkUQow1sXmcibB7Q4pDmXMxCXNSVB +szV+siydLVtFylQQwaBZJAQHhKFK4uZLlzJfli0/IihpGic0ks0m/8yYWmvHwmo4KKRi9f2Bao9 gDWoD0GCm6rEdWiyZy+RQw+LqQwed992CvKa7QKVRZ1rpf0/Y2D64zKGlw1NXWZ/sTVaKrxMCEzi sHU6TzKn4MBX9gLnGLsWoZTHpGp7vLDRr9VbRwEuLKeNBWflSyxc+yeref6ZTaW2bVOgDG1TRKCv RjAW0IV1ri7WPIOgaHfGSsVP+ZjaNFR/MHdWm1Xi4/l1Rv4dLn57YuG/T0RvDRiCzugmyH5Vh9Rc 7o9H1lL8fljv+DsXFtWrne0xk/xXqarmwLEBTBUp7elTyAwzS8xQL6YIr4716D7MZw5yCepCoVpH lWMv7l88zx1G6X7C+i36UleV28vEtA4VEVN6glebsji3TxfO1ZDfuHuXQAFw3m0JzM91IuLbkHoI ceXNpz4H7upYJ+wuY+Q7dYfF/+QQTykA0pAoyP8+ku5KqVx5buI6i/VQPz4ACeQUlVBL1G7XVAFM zOSptzgJLkjdqFVy4r6JNF76qnTCdFT1kfLPbPDwa9VKG8hLTcmjMqIw1GZZdh5RWipnmWnyeOUJ pXzbz4/76yBHbLfdSBsYO/+p+IpY/yP8OTdeYUzn78Gt1YdbyQ6ZKncEnzOANlI+nPxJJxPULbM4 8jIbtO1Hqq1FsAzZ26kIecmHiplDskX2sCCIpZvFby5+JOGCZHRr4e6eY7/7yvArfS9PZIK3JjgG c2LVQ4wZtfVtJ6EgiTb2Oo3vEEjD9Jm7QySTXjs7fumaD1fSqjwtSDmGuem4ZM0h72Aq/NWJc/CD AGYzhhg1ortPaxU/uOl2bUc9Q/ZYiokYJtbI0CcGRNn1uFzrCv0uUMS+ZFy0lfzBTl3gF0JaHy4m 3yNkhCe0QL/BzUU6BElb/v7fWkaW05hpKd/Es28IdXqlDi+RxStSZdcQ37rfMZGPADXIio/Crxwq ssdzv/ob6/fnpd3z0kc2Q6kPmJvjTocCTiidNaa/PfrLnrZIH+6Gv8PpSz2MF/N0YuDJ9v5Ohb4o Tc5ZEGSSKDtXyWXlxYNgLm3dsdPppgF3ppqoeWw+w5lgGyp/RPBf1qVeYejGo0IbEJJhwHsv4iOE ukoEyYXRzV22hEHSHuamio/Gi4j9OLJ+eiqrT4pQLugyyNPIA1hVgpiHdwFfXl9Nx73dC3VrFKaB LDoN4wzr3yQQjswmOruzw5u1V8ZkfWV7pK38rUPASvtJr92yRVu0vFp5EJx9jD5Zby9AhX4p3d4j MOyJdR6DLLWEU0ycvarUGNNNHayx2NSWeTo88RObN+BRpOQ+dCpwptVbYsbPTbsUUTtdPXww8Ld3 /hSkgh0Mp0uk9Zwfu6gO36Ym6BUw01nFMmjs1nAS4RamIRJU/Gguly9o0RMTZ3SUWvmsVD/PejTQ hbwnADJbjKMT2G2YnO0o3RKo/RNSD+r1xiJcrsguItj7iQAf6h50nZg6e57bMqnRA4exFwqe4C5P msm0+KoGLg0GSoIMmZCCWeDccInS9YvKoJPgPJ7x9CLZiCobpydpfrblUd1VpXHKKqBlWCteTot4 1ZN3nEdmO7vqRDII3UthuF4BTISfvCvah9kPfnbYqJdTKMz1j8zJIwUUWYaFLubcuKpzlzrLqBdv BayE/qHUVIv2goajwjor19DYUKCv8yMD5NkM07HUe/Z/iPOy79yhpGRl2vL+fXXDjf+zKyThY5LO 4HxaITPsEZRNBggME9lL6WC3h7C47FnoJVHL+uSST3k1t8+4GdUWGOHkqeDpNwBZLhFZ9wL+gC1A NFRH2zQmZA8o/nkgvgDCxFuW2tbJkka6l/WM0w+BteZyvXt9yI8vczoW4NcfMjukdlkqXYbfinJ1 Ixl5oeN3ft+mQtVZ0a404qwbdBuRYxPeIFxX4SKVlGwU2xSfiN6qQcO1u4/cJ/7aq9+CXL0hdOPX ivB+Qfg++OzKngQVwuF9dnKGWMSrGPIyjrHGiB4wk8rwYPSsBPqtc83nchL1Og1jHF45X5kKMXWv 188PLj5Q+9WuOTgbYhiDw4RL7FXdojVVmG/gMYbxD3nTHUMAwb2LstX+fWtaD/XBF4o8bFeVeBA8 szaiqZwswp7I/jiXPZQ3Ui2Yb+t3NsX1/W2O9E9l7XYoSJWNnop5S4JMkuICOYW/shP3/RBiGXh0 hDqK+HFomD+8HQa6AqsKyOW1q83V3Gdl11yzn8O7W3X/g2GewX880Cn22rTx3Uj434Jajp1LSGVW S1I7ywzMuRl+PYxZ1VHH6c9/MwRa+VkW/AHd1n4mGrXsIBV5USVF/8S+KVc1wnI/inGq+RcxUOst gAREc7jCXU9k3iNrQ/fxq7PqKT76oPPpF1NByH4x7N3WsKlPaC3LBLH8eEC87UBgGgzAWQ8EIyte lAJ7mI8av4h1wNTIYk1TYb1+8iJiuwKb9sFG23lPL6Rr6rHvRu9OIyRPsqQPgxHCMSLUgfnQTGui dnXZYSZ6kHHJmlDMmZSBrh/RtmPbnsTYyIwjW01EgV90jVMa+2s7IzpJ9ubI3/NJ+KhmKVCLNNB8 VAr96k7QU1f4ijk2Vl8EAPH6/QC3CDg0eplKlRTfOlHvLhHPaPO2VMbDDQWanp/NUp43aiUgfQ1c GeWOaGiRLXzpAN41Mj0G5RfBjYseS4ojf0EYsiSlLoWURBYFQTjLYNHeNlOi/Ow3Oe7RwZTTbL73 19JzHcFhJ/EsPhMASIqApDPz32bFEznW1vLqjTKUxqwFygI8z4lFrA7uV/wrkyACyXI+bHu5XBl9 z6l1hniV9xqxwFnmy07YDXwK8KnI/cXCLNnKTf6BCaBIqVURFiynLLlDAhjPR8sP55c+UAAfjd2P j21zq65GFA4SgJHlziQN+nFkoYBBZK5Dtd9SIiQvN7yYoCBPtjq6gFN0zAIwnYm+Dz+3FUamSZhB gK1qa8+jYx09K2yPKJlwe7CNIvcJK86G1QFG/9iC85sAi4DL7jB7gKcSlO0jsvkmj3OQs/52V/tm MMoMmEshMZ7aJ53gpx8kndqxRy6sHWBr/ajoSp5OCNjafSE9GvAUCZazv7bnW5OOg9xHoxWIidSN dVtUFpWfJjiuazq8xFegeR0kEMppZ1ygmFU+W9zFt2+xnu2ECmYCSNNAtk7cEldZFWA3MAmzTnJY SVGHeaCZZilAluu16FCjLX0FMdlnMht/jG+XaH+lTahtvvzwC3+mWQFtd80L6U53N2qw3mN3IToC pbbz34jetQysyIrHrTdkzaGG1kzKjVr4rlZdInyxThZvYpWSj7mIu3iUy+FYMSTmh3eCQY7Q0Maw YNMVlNq/+MvVP7x7FIggqxNFISKr9r0t+ZHzNz5pQDIdVYUNUWrhGnWXpAKSJZcMJATDDTr7jt80 0RCcsjQKZeyegZCXGDKSJtBWwPYzB7UQS4ZiXJU9zUNS3m+b3urym8xWzOvsiTswd9emsWLoPnnh VKl69zeCkq4hMt4OIjuVkY/GaHPWveboWftbob7WpKP0KjHUX2+LL9YD5CHL4l0FY6hw+lZ6ON+z AR+AwvBAXvgemWH9X4E5U3mPWHOddjQgoRwJd1EtNsgvXXxyTaoPFrSbM5bzyOKyUcOwOaBXvnqc xCF7CZOFA2XUEL/pQnRpmm+SbSo59ne/3GERvP+WRKxZ6Nv58eaD/r+tFeTBrNsdePgpNfhJop8J j5yvXAElrJbIBLTFdMEXRoaHNBMtb8gJufNd8rAihnMS7aJRmWD+rNdINhCF7jBdxljvpWvo0aWa Zz5KnSX7uKa1b0EsHN/oeWCuI1PSCosUhYK9UpkWsOpF7vKoqVlg5zSf2HzxxZL8OFVdn4cDXCUg C4NfY8grcVEQwcN6xKzYMyifXoJ00s+Xn1Z8tLXDI9EDj9PzCR8qtfqIgYS8jGq4s29Wt4q6C34L ZU71NWcOs82X6JNnMuCcmJuRcLD5jtr9SbqZor+a2Buqz3xg74QWVYFGFW0q0cntTCEKZBwptf3k J+FaT1dGQWxXq8iGRYRI7Y8gltRKk+7CshimMmLj0TftR5tUXxs32VbztyhU2RFyRUHMgIB1lBI/ a5R21KOqfGpxsDNDn0WSOmR/wLuDTU/DGVbPTeBWfNxrE2tWJyJzRoRfb/PPxorNBmFP9HJI0c0a K6diHJyWcwuN68GPPgsA4w9OIW4HeX2ltDeI2irkR6xgXdNsJYhOG52d90/jY5nllzXIECFjWrYY 6sXfv8lg0ffnxCrxVZcLf0/kqh/7EK1HlMQhq2z3jNT3jB61M2D/aHXQsbk2mT2GSL3K70obLJxR +gJDZhkQGnBqZPMg0mV12qSXg6BFto94X5H022rud0jbbG/si17j9e9DaygQSDElmXc7s1qs5BAA dNVd56nTR92hFhrigMQFIgPd+cM2pMg66wIWsyUcCMicXeR1nZpDxOQP2rVNjicm9vWm3gVLpgsf mNt9Ycb5HOi02nEPcinlcz5i2EEND+k8/C56vKjTZk41HCD+Wg6UIs9sydFE2H49nIZzTTWi1IKk Zq7DCUIDKW9mvw2tUuJx7i7yqLXZNrZMdnQWqilZ/YvDRgnb0kp3vroWub+a7MJt51Ew7cl00Ssf KgI0G6s66pKWUPPAT5MCvAZE6MuT56DsAmjZPDc+BwhNtbUziGraWCoBQnVLHPB8JLSmfsztBpoX calOUjgWyaHVxp292UnogyOpFAE7Cp0n8VZKcOxCRORwUt7Uu3geCPNVLWTFqk5SnRB7Vil9M2Ua /99fX7KkHWWuLgZtvzdjKMGyH+ruUirN2aAAZiz2O4lKDSYQ4Yk8DRtkq7VoeNlN3kzzLkP7i4y5 oL92GhJR6O0XQg1n2Bf9BJCkXcP+7ETadUk3+cICLwu5D9S/X/wAe0jPy4sH2dPI92x32cVPA+GR diuRg8Orp2c20StjktYv0fnttqafSnCUkbhAYNXSD7FckDWBjTcnEbP+AXoSuW14hktBdWqeFsY2 Y3B5999pF/o5QAFd8y7Sdf8ZQzn2gCirnox+IEktMxMX79Gb+qrPXSg2T+GZHVi8wLPCxhBxexQh swBZmGJZcgckyPTaB+ntuF2PckIBGZpEHMtjS8JLWIFbSdYx38K3r2B9KZ5A1cZInBskMRqqytXP Nh+ErVLP6eM2VJ88p6YZ1c1FyWSNeEOn5Hh25LLKishPNWJPP0BCG9BDgBWtGHpeyiSEyCQlknIQ rdnT+SkYsAbjur1SoEeszVFwWeqisREvm5GsOCHSEq9mkFZBgYCDJOQdeHdo2Zuf+/2kGyPqXWT6 sZiLscu7TWK2lIkLA3pd2koxpCU3zlL41pQ6QC7Dj68T/ZJ2z0O02MRONNb43ssZz0KUfDX4WRnh iDigHyopHMOPjXdSlk8RUGtxZ0vay18KWkDfSbujxzK9/c/zXrc0p+OqJox2ulvlFhkFWjF4YSMR M1DSKCVwGdKiPw8Nr1X9+xy/wIS+rP/N9NCnRy9rzenYTp9sgpS2sPykNQhRv9wqN2vmgB4cuHCy Qsta0bGuXagPBV6zhY1X8xBmWnzqsShqajf5LzKtkCJmLCRqz6T6aGECycrRPJiEYYgpqnp9j0ja O5gA1SABYJoEX2XoO/5QM5VO3SFizap5Px7fVu6kfkOwXBbClAFcY7RedlhirI3x6hKOMA0dlxsv omlrP80BYBGTuD9+EbvxTomD4/05npkixTEUnvlVI2C8Ba3fM4RP/jaxNIiXFwzFItHAfB/MSYGr c9XoAAZHN7jOd2VUI/elDoNTRdhMGcsmuHNjyKpT7J3jXwZGdT9jY4Lv47jNuY2FRdjN9jVbqiZk K0itXVJQqu64zs5t9PU5l/6Su0QuN1gUNVIRJOUbahS8q7pZXYsS56IqtIBerU20M4h3PTCM9ZvL lNX8z6/91ovWrZK6o07F4iy4R5buk52AtE16BpnMAnl4sYGmGdWcp6xO0Vz2Z+zVDiIteVID/ZQG aRuil7/KBbzoGQJ10bDzylitdDqPs6rUubsjTvpEDiZ7XyoeqnJkDIyOWhSNNV8Yo5LbUA1nZ/j7 1A8aATBysOfEncOAGKnVU/8o/eSnhCOoHYE2k6d5+nK8vsUSjVdGIDKMihgvt9VTyQWWL62YmH1A 1nczwp0ix2Xik+1MtYnSgVmjhMSG0IKJ8lBXCc+JlzkRfC5JUQ7J1AawF2Bf2GGDyBDr5+L1XG02 sh22TCufwu1793Cx9ahOH1u3BGemR9GZNe3WUdcXW0UqGfEQ++MmHnkTwrHsvcrCLxTtsjBPI3kf WDoK9YPWCyD6/arePgbJNElIU9E7ryIl0X3OHarfUAmQ0s8hv4GOJC0r9iRel3gJBd2oSzvPwdDP 6IBLnKbMTmjFsR5rOb/D9euIBuOCmEoX7GumPf9rBp20kustEPnhmFA2B1QGAEMi+FqMG7eA9SxI ixDTgz5A6D5YIA/yX2SSt4K9m6YDEMwYeMZ065w958l50a8DBNmeaXC1JkJ/cCWHRfTRR+ehkGBl RzB5VmY6DtfjNyVMPQTbF12pP0a0BcNFgb31T4eN+BPFNtQJvkYIlgozyEdE72KM3mvdyp7XJYkb oYfxxhaJJx0OGpwrnICJVu4JZT0xMVCWE7ncUKgntKH198iD+a0mJHoRqkgnPmgyZXkKFKnT/mxI tx18HYL8+3aqVkTYpirA4sbCnfjz/uHZBZK1HoHXcOWWnLAz4/gSjIb76O/pqD1ew/ifDo5LoQZX KENKrrGSIW2kUoO9bumM21Qk7J+EhW6URiN1Rgq+4mZpjCuFWfSVJXxVzQT8gJWYOzFXqHVte1mW RWXR/tZp55v7oMnNizFqdR0unp1cy6wjsNqtmBLOHDaFHoXcE90hRh6Qii4VGFjSPN/viilRtdBB h7rPo4LqwSrsd1D0acCwxFuziJuvfVyj2LzLqjbQ69IrC+hJSglr9bu4rCdaZn+d2r70pYX1mnru 0MONo7F1u1OZiMdzrul3cOLqpG/lEeaOcAO0asIJQK9XFqWVL2mvOjzbwqG7IY11vQX0jBWnq9RL zldX05QjSOsebkOSyUh8IdzkO35c4RsquenCqaGJV9xzK7d7MqH7hk+ae2YNF7YKzrFpzjQX7I6/ ZDn4xo09Md+bHXJCUZQxpz1Vhvvloyk3OFzfySS+AoFGP9tyq9QiewuSaa8t1WDCoCIsXzKtexeA xSGmtvR44Drg/KV/9vS4TsZ9B5Pxmu8sHo4zY1Y8qUGIWtMI0TK0O8c3Zht7B+gsHJIO1Kkq2y8u au6syx/HjZxe8dTG30SMxYgzYdbm1y4J2q2p9qdHYagKFoiZVdQUxoiwFHz1CYIoe4T9X6FFuBSK MtEf8lPZl3DFmrBSbsviA53POWrUeG17RsqTN/49iUREEXSf1tGEPTwNzccr9t6IvJpVrFjMr7hO AZ8s99GqJ0534QmZfZuwmczzpEjz3FPKbHwaQX7NUtYQy/TtUC+lUp90LJqgiiRErVsUnfaFkTek BlInQxOFDkqxC8/mIDmNvL2lfI3upg07ZtiJ70hTo1hZpLJFdUmtAnK36N/WncJIEvwoWFJUiTt9 fFobhW7grBKRiET+sz7mEdyG484lDUYRb/DdDDAHeswmtl3qS6ATyTKmytmUdT3OU6SIOJn+ieSJ +aUKACZZxawSH6FVbbonXAviVc7C0kxmn9ShX0E3KajmQZGCFvSwtyX5BcfzsnqQg/lsBXu2HQMF /8wZ0MGFF8mFLV9mmHdTQ52VZYlfP83BasvQ6/sfNNCir+YCGSg4BypNGJDmQoucM7L+LntvwKaj MCrC2XpoznXM+MooY9j7m4c3X2BNU3bWMM1K3yUzg9I0vBaJ+MwKucga2dDjjO7BA8Uc/YuW/PIa VFrZj95Eizzf1MNUPMuT7harOl+l8hCVEJHyUkCnzIMaem2jFaiYsRSHyXCbRTBMIS3fuNZ5YW3V sBRgTo97+e9yullSbCxjVRDzggOsSz7HE0KaWuAvWI6UDazPkIncOvgMDQBHQ5Zq75Jt/c/rv5Uv JQGt+E1zY8cD+y6uXqvAHD2ZVX5YQUTHP6lw0Hr2hBRrdZ/GSDc3qiAFRDFSC8JjDXAU5mMl2hQc MtmOsRzNALG76oYPhF+nnBGhprOuN7lqpq5OHhfXqAnbdpatj+eIDianio6kdYuHx04ReVtlipIT B20DxpwwgbCw/STVcq4up/1XCZPArHTm1CgTAEXLUgiJq+3yD4vrj9zTmW3zQSA7P2TbvwWPtpAr 3ZakykobV2j23KWuVHIUFrClbGL8qTftI8wDSMwacgh3P0CR5EMdllig7TtUDXSj4AyyBULUZx4N YMRQCF5jI6242coiVYWxhLGzJ2noCF/UKNMPD1NQ3LYVrk9FvEToG/+q9idBLcg87f8F2p+2UQXm YvDsNn1h3wHGsdDqYPAQw0iF/g9hgyzBxMdiTBByCLVu5R99XCTHvpd4a/DINYVPIDJs8+ACKq7D uYgNVWnKKDL1mczlx3ZUh2ZJPIaTZJ0I/QTJeJvsXhdNmI8NATjoNeQIE0syTg2Zk8vi1cRsXjpn V5LFqcSljeqPcrPUaRTK6aULr39zdb40vB9jGYEAVBRbJbXzkmxU2Zl2uWDKjxhxhIFlc1/1XdYC oFWokba1M+7qwioa8tFVCj9mi+oQYzh43V2aqhQsaIhqGHLdcHYdt6Exsb7BiavUAgTdMfORz6W8 JFH1QvAPnjg2Vcn3NvL1OYMhIFLklzIxK9KIxH5fw6UbV7RR7Qhs9xj41FkgFw/UUJ+duUEF9T1k HD4+6nPt8AtX6mu4Nrn9X39DwTmw27cNPbl2GpRZ5UEpeXaV+PNOCi2y/3el29fQ3YSeURXlOk6y pB7HqXt73fq9UyEFc6EAaOiMxPCLU7I4XS9LgSOKtE1FmQ2h7UqgUfoHNysi2ie4+dttOO4iBARa nDL+eqRHkx18Itaxu5s3xbYX9SZw9UzES59SBOpW32FiTPqCHeCJ0fN5iY9b+wbqQPP6UGfLM+g2 pEbI+HvYcbhGiALrvGWLEGK62Oau83uEKi5+7fYyR+j27QZz0KtBa5l2NCn2JHIyW8eMORclmah5 zVn2guijxrZsRO1Lfb6Sg2KE1lRg4iBVdL7jgBCenkm5GCSBPHE48QWPl2bD9TtHVKxkypwxDnt+ 6TK4WK+0t6rLQ9Kz1pKYDY1CTbSGwv/fpQrT84HLIrQb/MqZSLb/IONpWkNLd/MkDWfCHoetNaqK BIBfsSHHFZsM8fg9S2tObt+EX82YMwv2qzqMfqDuIRD/kT1H9lLclbSZaYRRJw3bV0FOO4O1985l DWvX375O13M7QoxupdhCQdMNoExuAZ8IgG5t7Rvn1w0QNFHLIIGprsBf2U8vbr09dcqA2URDlgxJ cKbadyjr/tu6prKO/ahvyZDLe2AuwOsYbzNTTgJTVgJLNDxTsQCgZLZlJtWPwBsrVAAR6y0MWo6m ObUuP+OGTVNLmgROqtmHK0b5GErZNNkhT5+L22it+ZhvbinGwv9UH84mPtL3C/nQd/U/AITnKKAl eJ9ZZBeVq9MTSYj/SVMT6nUi/sKMufwlE6hD0FvNGFlGlBSbnyfAlnSBM4sXv2VMLXrYlVKM4S8V x+o5OvUri5B+0bO6g/IuRf35Y++ddRRyOkJOTDa0D2O0uo8s7XV3kUS9vZ4wbsM229z6GUVQYTgl M+wmPKTtC7g5RtmCkjBZdBL97XePLtG/vuTNIjFpxjHJmXFjwBIbtSjU4w2f/NYaGbYcfhb0CQj2 Bma5W6vrMiv2ebh1gaSOc+jtY0jkEqVkZ3/WTiPG0E3Hv2ZuLkBzPebFQCzuOcqwOSKfVKAcbLA2 /GBB7p1Xg0oRUTA18SLWiL7JdH3W4E16f4ltt3OYstpqTMUW9oMf1kRfB9pyQ/A3JcerS3hOqjz5 XrPKMsCDEpfKScptCdNfu0rpxly52M3Yr6rjk5blSEUAyeHwooCZiHJI3UTsSaymKm0/63q3AZYo ty6uT1zWual7s0GqWS9X92AQKLr8qN22PbQHyEmtbw9q2oWzEztyFlmthGA8SgDdjwNQKMPihkTS wg2utrON4Pt029Si9oC/Y/jlhqbYgRG318BywwnBJ0ceI+Y8jbeoD5emwc9p/f+6IqKRu1zJNcbL IDhspZ6adMpd29O4AEG5csxnEiFkodlQ9rRd7iLIBlvFzgnU+1btxY8sx9UyfpgOk6YW0QpG6WjP KHfE+LEcBMfj3DptzOxcGdFz08JbER65NnwyeNqqAPu3W0XAL/5SMzy+ZUACcvahSfUj4QJFTDpv Y55msM2k49fnbvgEPin2iWVNUl5ySc4EVcSIzsgE65PHjfzXkJxmG6Yke6XDAUqY2g+xrt8f6JbB CvRzxqRcLxJFAt1U+aDAjs18gtUXe9J2G0j/WkLDRcfBESm7DlwbKo8YmjiljuIFkTEHpL1zzCIF yVPDTZ/CuzbE7ElZKPgEqXUqs8Ojl/jw8nQnRRKxa1E/Wo8reeqKFwv8aaP2n9Uv+O/mmzbA5LAu +uz6oDr3VnTUAPKwTr0SavnM3h1989EZp00bNLp8JTPSY1DtMdpbxCjL4ZGmLre0TNBaTERMtqB8 G5v8q6lWOQm3AkGoetwti0Z1UTPMCM4mvSJwj1Q3UH7j/nSDgGb0+wrn1KwjQpo95QpHpgMLySGz eTlU+gEXQv9WyCOrfusjV2gZpjI4AVmA2NcDNGbwHnb4pLwbzlRK2YKUf/gqploSYXRR3Oto/vTC OO8GicsHHU8miWZ/gpUxSefo/KVoFJXOqE34J2kORejhmL77zKJFdW7cjlV6LRXHgqZyZevfKWd9 zhAEqU/+KHIwEh4DMGsldkC4JBglsldSzmVaDgQjIEJG8JmKsTbds9pNgjjCFKHfrC0wA5zsMslo CeGf5Gzkbv8wXnqEYY+q6Ms+Z6S/wcdnky7YANofVGFsLZPLfRBjOIZ4/8rZZuM8ZdCWiatWjjNj aV2qvBqtoma3bkcKOj7yLopDpC2q4flr5DnDbXHjAc7xCbGMHA7YGSn/Ju8QZih+gVvVGNkpje73 uWNaUc7Aa/R1Tus1gFpVB2Qx/rYLgoLjsoccDUngEs3tKe+78uLzA7ORemtGz8nG8/vO87N7A29Y biX5KdND+n4S50sGWGlaMC7tnfbV34VtgEju+MYChuNLnqoFhX3zF42dZPbu17JewoROtPGRBY2b RZ0eL6MwBGAmhkKishrL/hO4ZocLKGuMZFaySizcdsqFSx0AfA5tYIPuUTsvU9Ks5/ko2DS4kvwZ aQzGVL/XvezBJsT7LizNyNnx0zZdLP8INYd1O+/fi6i9A6RTaZhd4G4WEhuipeOt+eJawNvbnGVV 71NQbnY7tZEL6co6vgv1hHdG0t3jnc+wnKEYZZJ4cp89+nDZfBBNeTR1iTWg9+MK8XaNPW1WO/hC s7PSYwbLf6Yzdn0hGCEYD21OcVmJ0KG5W1ThgIoHbPVBRREQsczhysfxSq8MDaIBbT9EPJ0CU6GT Wo6I93RE4apR/nZEJWaLG93VwSdpcf5Iv0c2TzZCGo1vq8mppJtSp6uL5RZOfG2j/lRH6rYj7F+H 2K4nsgk2W+Lw6r08vRpooYLY74aLGNhaf9CE/2AFDJ/ba8BTDmI9LfUlxCESIJiQRmDjKMUp8J/N LPdlnM7PTlazYxyL3VsRBMKf7jafgGK9xzxdUjygXmCnnf7zl5p7Cw7JDToOQGWc6H+3nX6mBO61 rrQjpl3TEMrDlTfA6R6qbNQW00YUxTDdFvL/egPkf2kWi9bxyGJKajTkSnA2QRw9JH7ndta1KdZW zK1q5c0lhB0EBvFeG0s5NymNWYpc1NoxQffToTTgTwCLQnsapcn8vPPu6o1iRzn0vligQTc/pmq8 14J6C1N+2B2Qw426GiJtYokmk5sUPoyjK3c6XQX/hvLZygx/c6bK6RDxi+1ND7aV47LbQ4qb2hof ioAg5z3noSxZTFcwsh65AyxZaYBktC/o3RTrteg6GLgyus/cNmbvY1q6hqnlocdGjj9MsgNWgKTG wir+Cyr6nfEikbi931eNumADJdeqWD9y3p9sZRbZyyarB4t2cg4ba6V2FSxuelIZhkXsMVp1IdKn UyLB6Z+DUVt10Bcpl1uILD5ZphBEL07p84bq7GBm9OQ6QpvIgr2/L6c8vjLSHGiyWN/lJRAy+4Iv 2IFmuU+FxB7YrItlSOE5B2wcxGypyyoJXyBRrRwfOeH4cB0KaZ/egVRdtIqMb5B5OcdPshKrVbUO XmAqM3qYfc9VJeqLDCsVziCiZkZ8CM6R0BIKBWd/StM9oHuAcUuxLPewqlZUTScxS/0Uv30e+/VL vXLDfklJfwsBdZeRqNddTFlqZ7y9o+6dVFptTCyZjN33lyM8d2euooilKANvTKP7fCKXlOJ/Uwk1 bYv6DRlfsp2KG42TJFNbIh4uUA+GY1FsKe2cv4Yh3luPOKdipMpm7pB8QKtngzPUpnrF7ahei9dS dJTgSozy4sto5u31zmaVef3YTDAMp27smg9uxzc3PV0oQcTOzsCBsN9dkk9e/v/3HY2z6IMNLQQr Fi940ScDxUbV+TEUCWZDE1qtqWhMl9SePCsJV5RJ1JNlbn8b3Y6+6OaIIc/dxLc1+nCxrVtFzAG3 mKkYMpaE8UQuDCE+uPetPp14g6cx5DOvtNc1MgTeaUb8Ly0yIWSyCb/UBo+xG694VHF+H7WveVjs Bj2Vv17LnTvh22vjAmYZ+NBZrE7gFnXIo0YBmIQCZ38OM8NHD9mBNBsUK/IRebovM4maDB39OgHm 5g9ZYvd6ernBWzwrpwZhCY/qM8gc7LWHB2a7vB2nEKdaKLWDosrv96xhwLfpdrEib/3FoEYpemDY N9o4EhnW++6oTNgFrYRR2PFqkcsec02Fa8nFrDSNv3enFixWPmaX1zuKMqs1+J9fv9nThk6myVeO McYWC+QzueXPL5Jn4goiNhLzGkOS/JxN74Kxl7sXR7vczkUdY1QaUJ1/EFyM+dliMvcs8EDsFTYt LE8ggz2mNZJuIgsfFbcbzF9DivV1UvJZKHUbyMSrijeW2DYzGU7A16QV1+1Pl3S0lN1eBQuMnUCA p7gfDywWJHAvLx0u9dh7qBe/oVE0wbz/x7lfcl4EYBT2vf6VqDNPmGYYQ54OV5qh4o/EFMl7PT1X SHoswxRzkR65uf3jEPjYqb+tzJaspBgD2A6c5PUi9dNYO0gQDPEQuIE3VJXSOab6pDXCJQvpGpVC 3hYdbJKYC2vGXOz40HZxNqFTCGkJ+fhP5pFvAjEdOpXnOa2BW9eEVIv8KnGP2Pf7QjiRAM8rXKpf 8QWWsSa0XryHAuRhv9ztwrk6/2ESf+xllXGU4WhQI1FIfvO7infYaFfi0aJlowOU3nm4AHXdlVZP yL3vsZCCO4Wti5fYeD2R03EeAhXjY7WtTqQ86wUBGPa5Ri2O1k4+xcf7z64tOAm8mmCo1ud9Rei6 o+TkewJT2kAu36TyENvpeVvclNdJUHdgWQXOf3o8YpqMapIUXBVezXUW560Ee2GpTNiY+PgBeQm1 w9wEVVZ8kiTmJpAadf6EeaDDLzYrQP9NzIKCBceO5meIxgFMyDH49WYIERkm/fjTCQ9iOZs3bZgL bM31Y9q9adU1zzsaQFWF0LWXdUqmnV3SHVSoD9X1inOyuEuHWCH76E5QhYF7L8Ao8HKzQeVkk1Rc SI2ZkziQDeVcS1EaRdAO5cMJCdfaGhacjcygXcEXE54kIdsvESmNH3d1SuPuEJ8NoFGpGso4uvk3 jWLqoilz+m7/bVbqAdQ1QcUhA0CeGtzfBqTvRpg1apl5pHmCs7WWVt5WA1PTDRXR1AKzDuvW2Hh+ PEN3LNdjvYnV9DDsXRN55desbIaWW4GuW9xkLBqoyREPzsDHltbU9+IZ+LZZesjyVt2XoskImYRP o1TGdUGhFaLKsklUo0F0UOllDKLQEqBu6iHAPzVVoKNs+LXroCK7oPUWWSc6lzx2MTXMDqqwrldZ WarfefcHWnyODvOTxoKQgNJ8fo5qhL4n2FM43t7cGLDZk4muCQO04Jt+WI72FQq1WsUQBoPEQEVP 6nVCPExzZxfo9rUsbhxkcFVOQk+PZGVtAYXxLIN7iDSQkfpXvsTpOlPaTiEkpuJTD4Qq4BntuBDE rJN/DmVCed96yymMTQlguUqswZwfCE0PLQzxvwvMIWjs2Kobrnkb72+pRGEjTMoWeiXGi+ZQpyez k9cqrfGqw88C/5Ok/wbUlApq+KowfQU8BI6euZhuuZuY51LuSL5TBzRJbyIFsEnnOpnb9bB1EwzU 7VeTEGQbgaHVw82agekl3uGxhmKQ56juFUQ68n9XpaxHrbqEEKTdRthwgD023D3/gTvt8A15272B uAWTgu0azas2fVxkRbVOkJuovEldpiaZvazvuDZVtIUJJDQp8jH9zJyKDiznsn+gmzH0lW4baJkj zaC1rPViO1ekD5Ue/FMKXX8gq02/JcQtqpSEWdNVnIMrcb4mUdlf3YRMnVUsc6sDYNC6AJ/5gRD6 1j124nFlZHeXdTxX3KctU6jIThWcGlpK+wiG8M39Y386AFSrLEjo4LBHnMwK5tC07RSIZkTLBxhN FDsoFCgdCMRC0TZw8JXH5PF5IlURznlc5tadUvSgWJbo9scPN6RhzH1Ee9nLveF3E6Y+1YLXx2kx pCWcHP9U6B8t715gCfmK2TNbHEN0uZ2I+xkTgWXBIuU8z2AKF1beJHPocUCQKhk47yE+TEOQbE1/ qgxumhDAiUofWvyu3LycJQ15QoChd7T9j9/sM85T0298J0Jd4J/dMkQlpsAXOn0oHGUnLFilYobA Rs5sBCJ0Fb0FNM9PV946RvjZEK1gxcx6x3Oa5AJ3qbGi+6XN+q/04QF+WE+7LZh2PIk+LwPn1R6L Hyk0i3kiftfyBYjjiiCu4t/lm7Z8B0BpOYhQvX17/gifxAjj1A1FqenUtrxo/m83AOpJTSH2pzzP 8KNPrlilD08b0cZg1KuxFNOGIFg5s43xwdSgPlXN0EqPGWPGg9FsgTMU7va1qXlx2lN3YYIUd6/M lxTyPel7tsLl7smbx+cG/gNWd3dK8AF9NHHQ9LhY1zguWE3lkpu186f1U/6W5mJb7O4cvjikDZCA ZA8ys2Fm7FGwFBBgSi0MPQYozNXNoBApnp/6P4fnX/OuDJWgnmO83qMAkhTvV54g1/rkDI1Bg4CW iBI+e0hofbwyY+d+x8r6BaJKDIOer40Fht2RlGOtRy4p8aVYcJUWGThh2qF05SzbhcyHbVmTAY2Y mSWwT7Ze6YIU4UswJRq4rv/l7+rAEUp4uAHBdWoP/6rzPlh2zjcw+xoHsxUJAHPWJmSeYeZgaM/y F/58N0Cu6vvXp95IJRkId0cQqHmpGE188HMR2p2Aozd0jviaQUfd3bm5liS6kkuOVyTmKrvpp8QE x9IsGKqHd2cyylqm7tUslkMxu2dVN0ToV20n5XqrbRXjUdj6NkWzhoqXUX05UzJgrXuySvRqV9vJ oXIxVLpZjnHfxL3mdj6px7Q4fG0eCLpAGeK5xcEV1CDAKkSM3OhkPKHHuWRJOJzZv/j+qYjCJK3h WG+32edmSTikMpEi9Yd5NELWJvF6tUcNIalxR7X4UwLBbp2hEQ0TvtzG3A8hTSPgXJx5+WYWocpl yB3TwizhewMQ5T+OyLB9zvQs1ZJJNyjf58jeG118jzkY72ON5KKwVe7uhZy8lC4FPeUkltEmLly4 ekjpQi2RLide0k75wnqRjrkSjJU/P7sfbZQqQt2RWKZtKIJdJL5jZU/e/Id9KEhU8ptVy5S3dKK4 +h1oHfBRgXcpXHLaKTmllV83NENRtF5AzNF/P7hVxOAKRzLkN35yFWs+6L7qGhn4xdBnmfu7PSrx +Fm12ltGmb6VS/lES09jRuzA1l8XGC26HoPQpQdjFQejnCyrGdrg9I41YO2+y5Owi4YEQGccNQIP kIxSrvQdA0kAjAFC5vIpEsfIlbFK+CsmMDppPymZFS2/A0eDLCLVqEVyh41wwPnBD7ewXDtZYygQ 2La1zVsUf0jeNhlyy/qo5ooZSwSHQO/W8SbUCKIP3kta7dKN/weWu4Bz1ItEyEzq+NXJSxx6qsOk 1aAhnhQ5D03eWfW78kX7T6n8xJC3k0V2yqU7jkcW4N9JnV+tuP/KEawwDpnuKpsiXC2GM6DqzvMJ Ky2yjU6vYavjEIT68gUV+/EdyK0Rwaaxahu0IsxJYlsgyJdEIpo1WXtSb107tO8idXxajdbI460s fcorwMUuN1dF/wbo3YiT94mbIcAPnbi5YhcUz5XFXHWZiuyqRqhC7MB+Gn6Z3IAOjpZMd3cE6feg hsgN7uUdZo3LltJVp6z+DB6it+ZX1Lo2sd6XE2+QgEE5viSKlwPfzkp57XqLXDbthXccnIM7M64F VsTrpkOXDh0Z0KEz8M/LuQHk4NSrb7IJl9wu28FlV93Mwct+2rAaEvzSb60yjxs4fincItzPysAd Tcm8xngCirNEZs4pt1FmX6CHyTpD8h1XukQS0lsf8GUWH5eg+CYvG4Cz9sZHRVPYKBNTIZIY9jmw 7dv6udCSIQlMEMg/a8+ZnI6H6EA6bqxqESHoXzMJcXQEM5wVd/VJ1u8XkF3TjSHBdRDkItjkQhBW LYYahe4uIaKt4M7scvFvo5r+KRWCuzq8btAkex7lh9SQfX93NCgRuM95YBWgI060sv90w3bR/UQw Op7kSViwMW6YnqEHbigzgPRNvIT7FT14vszJt7yPJYuCxYcEURMNgvXV6o6VWCDqLIcq8aeWbvuf Du4xNv32K5rDZeNqxlyhtKIS/0U1fS/I+nuZTHgknub9xnF7AJvYBVL3A5o+qSnfQ8onhYxaBEfQ XCSheZM32HVMTB+47dxlPGo8YLXHH4weMBynQzBq2qbKEDLh+pcMOynMk+sv9COcVGjWJlSIlIIv zvzJijvsOI76IBJxo+ah8wngA0zK15GnGnzEPLLQZgOu4NOYvK1JTbCy1cjUCW2LJuYPaOzYmNoi 7RbSRLsgXUFBqRHmAIID2vpQh5M5V/NMu+cgTrlZVA+JKw9Yn4tlTw+ISqI3MWHky1017drJ2T0p dKx1nQLlXX5i6fgmWM1yURB9vFJEZT+NKrdMGXvM6T0hFtG5Pv3n7fjT9kesQ23GxdeYs/+8HOjw 8phe2ZOX6XN5+/oW8BOzOY/xpiqzJtDXQ5OFtdoONQeuZjxRvA58+0lWFMP/FpmGaoo++hYXfXkm ir7JbbA5/Y/5OfXBnjpP8e3NS/ulCarNI/vC9//UnW1itjdtvdQNTYVygjHIO9yNxzDuTP8HIiNd QP38CK8GA4FMX9UOkw8VQoZUg33Dt4Yls27e0DFwS/wjcSYtc5GrJ9HZnsafSkLJISDveNYaNi6k eUWg2TPnTqb+lRUPDq4Z+Lx1By82OzLTQyScElwEvK89iKHUUoTghD2teyrPVGI/wMtZCTeNoJi8 Vdz022W+G5Lz/eppga6azpsJAz1p5TQTatVosRh5UuiLTYoSob5V1J2H6o4gXong1CdN/QAnuDQ2 BnGVEFv0oX2WV/dLJCtiQCKHgZ8cBU6k/9cpGg7X4W25zQiGwKvGcMoYcWVEitL3Z1jMgBfjue0Y GrJV1XpgUwiclTRXVJJ5U5FLnvb6cq7oF4gBb0cX8RLScuT9FbfD66E/+4BtMG8NbE8djRKEbH5Q 6x7fVI5HAhi0wcwbvKsTiSNbbW1N8Ung10OZ0SRMV9joQTLrKVWw5Jr3ivH16gMXbZhZd8LPj1Py RTR180wyVP1gUblY7W1Hy4UkJYRejqOUgMtLtAqNLMGA+8K3NAxLMuArXBzcdpNysR56kn18nX4Y +anKtR4Y6Agp67uMNjnSmqRhiSwgssU1mWmnzz1cvjHVohxihOms36P/eidrHIK8WQO1ukwDi6zU E+BKPWZ54OCBunyhTL5DC08mWfq7l0Wlz0PBo2CZ3L1ttQwk4sbECqYkExFO/0zlbNVyM5fdwkXW eVJycgi6Gxqyd01fT6iQwhUA32YiEPI0pxggyCwqPM5kK0r8sNKDtwyuS5GqLvDjjsWBsKMsL9tv oHzbF+q6XkWkF1QSS8bGVF/XUWLDktH++pTaP3xEa4hEFGchoAeC1erdVBzajr6SzNi47heDpraG KtInl0b0xq4bmMDQXC313Kk03chMZdHapVvGJy9ugBicVp+Nxng3RqG/ID1afxpjMrfuCHSp0jQ1 K7ZlFJ0d+kju15xm7+EhoTDccvjMMCR6HbU3sPRrL8qMU/cgScmIZcslMTqT8ZIdECLsfVjB7DoM 6YnaPdWfWbL7lE7Bh75bw/muS2iLG5CosPIvF5SGa293IBgQJpKPh0FRu4OUwc2nD0/2o+psEnki 6fbxaE+DM59ao2VuSfdqgYQWYiuGmTq9o/PueHkE3XHtJbtLqMKLtPriSUdTB9lENt8UubjyvC/p 42dlFH6kHFvSk75GJsARbpPGyeK7KI1p6E0F54ZAd1v2LS1gxvbN3wqdaUaE+DYYuMgPIV/R3fEX G/tdRA035pDaqZVRg6oKkZvXDvPalZSOttXvshXZ7duWe0dlsGbhYh43CpjYr6Irm4/CZjyFrhwv OqwDxbJwjaANfcYh8+Z/NU9Q1nVUFem73xLKJ3VcAZ9ELQDlPjybsdwgNqVVTsm0Zb3s99q8LQVY ywJ/BirBHsQNVMjJtMlHhczu/Pw4k2x3Y2SqWHkqf9HhvISsSDvMctZKcq4wdiwKzhslIuwtLE7C BXATACgF2OrzKJiakTZgXUY4ompCQWjJCjmWqm4QVE5Q00fxEMzlAo2JYGlgnuNyhD1z69OnKwae kN/2vKqFnZtkeATZigHebfZAu0s/iBUjIcJg1HsEnQpLzday27fx/VfAhwd9wHHwkRmtnNsZD5yd 5wnLQOf08LQy0ewUlNwKZnu0kLj/qYX4ShEaYDn2Pzku0i+W4nh2rph35/owfAsAelDOxy2lYV0b KYqkCAxN8OUKlACsOG4TUlsU8G8t287g9upHiexR5UxmSabwYJEP4NhncXEs6uVWqlSTuvcCmx7z 6bZoYtNS/1259gbR0YYHM6oo1bLp69AYK2H1csiUs3QhnZDsV3NFTPlLPGDc4yRQVcI22R8RcXD2 b34efcNdl/3GSXA32ZfbJMXWZtvBpYWeJm+Dw6id4JF9yfrXAyVwEA9WgAjfHp5Gdj7hSdWHvQbw pEIxYU0u+WhQghcNFdwF80V/iJK6+9WQ5Vxecv0ljSNfM+KUEVjCmKL8tLE+/Fawimzz10PM9+h/ VkPQwGvDi0n1fCAtIhvS/b6fuToAfWU90MUgRa9eiOLDgO6y6IpQfV4dEAw3t+SE0jJ1JTx+Jjzw P3y3tw/sYaLOGCHmzwREBv6lPpcE5UFk63kV4EAMYbfip90y/5H7OOw3Q2U5bIgUDljkj4XzxTV4 e54lE2guVRt/uaB8iu2GNLC+7kxC7xb2QHiuqWsUxfT+6lBjlJ5O1SVTSSOdMQSM/JCkAovRReje mSjkBLJKAQiUiXQB3uGCZ9qsVws/w7Uy+FgTGPjCfH8gEJvRvwOq7k49Pc9ts3BxhVwnFqgTEXhm 9XEKBfIQAhTec+wVElPYrAnTFUucQgDE2qw9jhALRQJjYhDYz71LdqyD74WrFiP16JgF/9AP+ctW W2HsOfVZrUHpwQdXEfgKxvq7DFGdVCHIWpP6q1nS/ZK6PKw/HJ/h1NPOasv65Ww0tvG2BLAMbqWU Ny9CoihZuCoD6rMLAOJ2tSPP1qejC6zwWbpTxYUMTDXswY88OavKYzMW+RxwZ6i9tc8Rx3s+FrC3 FYryCsjdXhRo47lY/FECr1KZj9f9711tsNgRXxIRzzA+CgSoaaUCIhHnG/MoZ7DbfY90Qp5CsU1r TT3XFoXvlQxY6Z8uB4i8SqmNyfmXBdh8W8slAqnsIRBtSNWdF7KN2YoXnRumdA1hnPIxazyT4esX oDeARRuTo3q3xus5STVPyOpWoT45nWmxbOF6TAnkRcVVkkwvzee4hwGtOa+qNg/X1WjE9NfSKCbo ZoHaB78jtmDNI4Iw3GddpIQje0f8xcMdr/QK4QpH8k3DI3O/8VRt896/6YePaMmmn9CsZejg9XzV ST3hYxYNDGHFnIp3h2fyT7Ur5r9KRUmjRphmeGD79k/C8AU6xjotu6hJKZIsoKDlFDzrwEu/mS3K P654kR2xt4W4+2u/DsB7dTqjEyGY1L0HNVDYIujWGRcbJKG3Eg/iBdXXhH5P7GK7ayHW6AMkFv0g UMECWkdHlqRkPC3+ArWJXb9AfTCKSWZn7qdFgLPx8LRYH5owPK0BBluruDhYpJyJzgxXaN2LnNiq TOuwMfixZ5ufn9dQ0/+79aG7WZlq6WFdtFCnmy3jT55/O1fQh2ii66vBOnyXf1fZI44XBxJg7ioP oFVYDyBo3qb/KUF/34HbrypC6mIESMQosn5F3KlfVc6Gv0exGIP8I2ITvD5SF+Flll+DF77InFoc Dub0Ixxk0wiLOxkUrckI0qJv56m503QqOtEHHlAXzBl+mdPk7YThRr4wYx0HrpqEKbU1ohtyzVKH R67LpR9zV9lHq8C3BFPi82W/C8GHXB7CZ3ngygZltFdhVUckUpPuxb0zfkT3ZKtnrE/6udPHvMlq 6LotBB7jsuTA54/IV74nRfm/OsFBhp/eMljwQN7fP030IFbi2c70mGIiSgQSOU3KYQYhGiNM0axO O3FIJYktR3DpYsHSmXXfAEroCq6cZ+VYa08nmdjwPp3JcgB8pm+2cV/5dcGVgTi9lIwR9Ap6ns8t 08dPAB4DKAV4bOfnrj9/58I8zVPhyIA3Qosp1M6OW4NhoiovKHvHFLFYW8lndcDMgB1FYKLej/+q lWsIENyHVG54ery/jGxVyX4x36AHQj4SGKU+0FwFUMZglL3F+rZDDmy2+D91pPVUkP38SVRgRAch lgrMXhCTsOyvoPn92ICRaOpaM0INalxafJkWTjUY8OFAjkPyuwjj28uYJqMrKh2WNk9+7JMJkJJZ SeTgs29NekmgAsZC/2x0kktY4YnDfMBK2Gg7jNQDFg1AxOmGX4/e7DQ2y39Kf0DZzdB0/WA9u2G9 tO+qwWZuKveuj6bGfoMN3i5dGR92M1PLfVvjgdpRCAihhJmgiQFUv/WLfgOxRso+HqQae5MnGLj8 YxQ6YCMWWUAXhE2W1jY/qzVix3hVNFt/IVKc9HZObYiLV7limdQrE7CVt2Bz3s+hrnaaZuvwISDb 0H4RDbqd/gvZQ1xJN819+sgqmVgTTzrATSFUjydoEngC+1TY3LXNPahkLXzOdCXI5Dg6ngQCuVuk 4EwT+jA7b4RiRxIwe9laizvy1x22A9I7iLmf8AyB0DC4pAIstBT8S11GHFcWoW+6cMr/7FCVkblA kJQtkxh1egytUxCLw+iuwi5blTda000MswKRmT915VGnWxBz4ea0jjO9bqevCYaqNghRBF75y/3f zxLZn5DX8HB/EDZjKO68e0EH4YXWJghjRcbyNblEnqi5nJNKVie9aafIiyKjbwSrHRpcjuWdpjpp lvCycl29UO2rL+LfYzA5/9oWsEDoZBeO4XuEQOrPTzCm66EQFS/ztWsIeCnz7r1DWBPu8/FEZl/P ekJPhmkyC1sbUybuOI/FXSSxTeiqMlY0HxyOXxzcog9Yeo1jWiwn8YSfobfTo1w4+S1APeLRiAe9 ne+PyLOgBO+DJxACagK+SDP2aUd9sYvGycMOQv3UQltrt6VKxPHLpnVow8y/bjNmvEViQnPl8FgI RPWVDZtT6O4LyTk1M1LX/Zm+9XOCSAKhJydl7bN0y7YoJhAVNZo2DwwN+yrdbAxSRsa8JybngmuB 4m6uDPQgmKsJ5yfzD0n8cYYwqCUnLUTRSIDTA/Bo530B4JKckfXG93VN1uWgjPcfHDyUP8krJqF6 sB3or2TyYRfeUEPIc4ADzQVkkIX8fEN0vXHw3+kT80nnUg7SlXFAEwFhH+naK38ItXMY8/OujqrI j58oW0AisaY0wGS08zNWfCKdxu3WQG3QOsJYTfG5jmPQrXFLBtiUvdEsWXdXRwpb0NPh19DAvlRB ZaGWB0XYXfE9GCR2CoitTncfbZaIS5D5D3Aj9i6Y5IdAf5Y/BAoMPf1XS3liuN9aan5OfdQA6MAo SLKknEOVdWaW/33waG4xdxlFgU9L84BOwIiFlLkFTyjyN1Pf3tHIDlA6wH82ngI0OUx4PcAvR+CY u8NKaafZgO86yJw9VN+SXPOAHR9P7Uy/qmzhuRaZLU2+qI3WBxsvjLj0ma8vZ46BeP2WmrgGO8K6 8Pho8Z2pknXGVik9Ezxuvqg1L0/1v3++KcGwJxgbHpbYCzVZpcqejBjsHSYP6RIAM4i3/XpRk8+6 BHsMbi8qdU0O5V0Cbees7GjtQRd4VgqqRZD/wk05sBXXvKUCYssVeSx02TBCMBnclaPdbhxzBOSm peHx2ARLPOK0eRmfKkjyVwtzAfs1/zFUImHdoqlCdNEXp57ujW7+HhIyAeAMWWdiXgsfIonPGPg4 MqVCC9VH0VfsjcT9i9QZxHFmjCyTPLGHlJEIgzXY5znMvi9X9gOIaaHrf+9nGwyY4OUNjBexqjaf 3iwqcnuS8IJmyFgAvbRSNnXuqB2DEYQRCEylkz+7/STQuk2f5GzLiVDvcHTAck3bkYJJstcwCYh/ wQLlv6f5CdF/K+qy8hEdgZxw1KpZqWXCyn72HvLeVd6w8UjrKdDAIE3echjKGFZpPEmDvbKb0F55 LEjTZtvyzAvBmBUo5Iy65USxCYlVJS3hSK6Qc55kpzdsL2OhA3vHH+YgVqmFB8CLRuTet4hUyQ89 WoIhUZhxbJGfehh78OtcVoyOLvPeG1Pe3QSDTomlgDGvPBwcmrrunloLsphnhnR7OcEnvGu0lSZy VEb/L2Pli591oOzJTSQMEW/vjP0KfEcYAF5EaeVA24nqkTMtwwSx5A9/l3PpeYSW2IsIo48MnfKS iRBy/o5i2s9BsrOF6M38X8NSrmLOlvJqJ9e7uMajXIL1wYzwVOMqI1l9fq86jZkr4oP1gPE1CB2I MTOfTPxfq92sAl1SgCiBLc3o2Om5aGotMTD3o3/kwRQc0TRq2GpAT3YspWO4Kms/yMDDJEdHi8e0 2sIlIebzFT04O55bnqTwo0OYnCi+PcAiORLtCFIlit/cxCyxxmLpMsOZKVG4hhglbA+88NQvnNyj NY1IfygdYHV4Yha2x/ADaq0bwu9clZj46+f1pVXlF9jBPpntqS1gmjIIm5YCb8qK1p7w/nzn8sbP 50jDtGdy0HZxOmLJevvDGuBQz4/ukSVyWLvSq31h8HAYUZqXDFEP1enHviaZL7PCmxtk+Q2l5p5b TU5z4yyVnBoQ5ZOrWD9vnNvtBPsgqNj/jHJ6IG9FwtzdnHUCE3a0yi4kC1wkli0gOpH12//JTRlL 2LgznxX/c73WDpA/Mij+zWgGKwWbPNOWSwmWCUDUIgJaBE53X8fCje4owbvhatpXKXCJpY/aakco YQLOBPI1jFHSWmN/5hntMHtMFqbyiInP5hmFIq8dD/xs4JDTkGmc7RTCQL4b789p9U2wtRck/hpr fLu7uEH/BqYG8ikivNbJ+8VSR4CCy0fx2G5k9m1fX85kEOwwFBdbvaw1hCMA1hnIaWt6E0TTQDn9 yYnHsTVODfZWA5zsVx+M/cVTGnodtMvtA1hghqtolZniY16nzOFURqTwT8J8OOix79oHeqJMrbSc LEXMQybHLo8+1YcHm/QjRDpj9IfQWPNu38KxTD8erMncV7kaPwEHvqIy27/VTtP0Tz8BJhsrb+2I P7mM1F+he9c0T1tzpy/9RKxqmFVpQCn6vaMDTW/TdBWSxaEOYk0rK7VLp3Z0K3d/a37iRVDSqkw5 WMqmCSxpBOUsjcGHW4NUWXdm251eL5ZFdYf3JaIbstufLm8Ne4LpWECGFH3dIvoL2kCRBHhr/9sj HcmeWohZi2xL0kMuwzigTY9kx4UZgbdtNhFiUGJJrvzQ93iCo9OrBC0yA70aJgse/3mCsopp4eif qlFARR6d1NjokWnArqPbxVVK7CcxndglnVGLNgmFTJ24poj+quFYlJl8MTLLS9wEAuO2mzzjhVtI Ewa51Fs96nPwszijxFExeQQGGl6+fj/2QC7dutrbAJhcNZvafM49xSRkuWGchxyQG8KbMqF9Shij m4/2qOghOn7lpM/hbZAXCLEITxs9UGR53QwTLn/To+3487y+iiooT0o9sWZh9vpqgpux2uv8Zry9 u+TBkH4VsJggtC9Q8F1EwJ06wD75Kl/OyGBB8RhWpWnklXZFZYi+/RVYlDsY7TfZGiHBeUCEtC6W h3Nmop775mXSAIitcv2pvb7NA30zzXvGaMG+dH3sw8g+SzXkztm9i4+7HA4WI0QKiiLycWQudk03 2kazYmRShGmkH9c8TJucn8sivFBN6Ny6pSoLfCgCUyfFhm7VFUTJfkOQXcYGVD7wSm6nYNBlesPL qd2fggBMrKR0tP/K9FjUZ6ZvtTMffgVbbMgOqHgGSGLf02OxK7Y10XKKK4i+v7M0/7BV+ntEZq/9 /QKRWzrYhy6B4CHmw0r++npCPFgl0zWn5TFH9hVcWs2uFwTIoEL8q1BbCc2k+rDlk2gftW0UqWUS ccar8eEUCfe+QdVRiymFndj9wR9nsVvncdY1skbsbdCZsQ4St9GkhK2LZxcqSzGbM7xKsOeR548L pjhQ3fmujsco+B4ri4S299cx9A2xwVv1SFha4MiOuR33C/v4B1Yvqz29VmNRt0L63IyaGemokk3l +lniDHOIOE5TJsu8dgmVRE/mt46wxEH13h4uVoBSzeNTj2F85AIi60F+ZGeAN1NUDIQ56sSO5g4w st9g8znZtM55hdTZhqG3mO1I6x8Jnw+AFvroEcLElREDiZ76SuHUoIAqkSYj8FXsYj3uVBR7Js/U sHxFK0OsFz7d/BAaCce4y2hvZI71+gIeUzpZAkbEm7ydr5SNl3nDWIdza122LYr84Ts6GdqZi4b3 rbkUOtE64G2cPJ5V8UmEPD38vzgoGEl0J0A/Ks+V7/ac3eHNc+cbs0bv3pYUeWSfoqN2Wd+SE7rg X26CPLRux3f4vD70sKMGDBGGzpZ8qciKwoXhnULQNBrDYEEuMerAIhcOu4kii1OARTJS4m04J0Fv Ec3A4E19yg8aZjFBZT8UkpxB00p6uczvDamtutM2vx4Hso/nfuQQFiTSTj+HvuNRKjbzCZ5KzeCo PNKrIxk77LlTnjaugthUd69i2Z31S9LjpwZEBu98Tp1ZPwVS9OoovMJu+vQmyqgQSl3NKVCNJpKG A2KNsfldyI0tUhJbY8cMmSmUjJ1ta7Ll8Xri6DVqoqTp+nhhWTktjq7z9mPRQ87xHa717a0n4Mlx a/Ia00BK7CLxQ/gZowQY6jzJl1Qb4JnAtjQnpCEXfOVkHgXAvUniwc/I/wZ4wUTTaEwDpfVulg5x HW6YFwWsjTX+1GP4+B359HsPKVF/eQAtcM8Ss37r8tnSwrYz/7vX01f1+jrjriL9mbzEyp/dNudl bqVUe1f2B8OWS/t9+nUCYOBj5ruTfNmfCNzpZlXPBJKPEXr+MH0zmjf2Ucv3hTFkVF0K9CVJte8Q +U7RwO1l3TeBhoMaAUkqmw4XnOy8oKd2VmH2BKDAhDf1P9HpRCRnKF7/6Tk40qTC6TQ2gPgp4th8 jHF6DoXKncaCfGI5GdsPsHPrE+iwJvnNb9Lwv0F0T8P45V2a+amX04obAFraUX88TvF2srhUd1h+ 0G3EsAr7/b1+pr0P2yD7DpsWZYgLYbAnEN3qUh0rvvTDKWfTebj3VRJ1jExAmYRt89zEPFf5YdlT TCdZcuikl3IB8/gAu6mv/P1XWDEr+LXEbiTcwOE5+ZLymycHjNaD38fgIzDYAS209RJbR6P9BWcB EhZ+u4zxlqWZfsZtYa0nl87Pt5w2zYk5PrFpqhVOX8moJfi6MV89LrOAEv5tZ1rYHPa7f9cugfqR lRsUhCAASh6N08Zsk93rYLSO4I9RuXvPsRKkFMF/TWlHtwAXSTJPsIDcBfmfMadBfp65b64eUYOe FufK0eQ+8UGwiL4p0gYx8AkMTHBxqTtUGzSrWXZ3HlKOgJZ+1Ksyf6zaskMJ1pBC7rveN4KKj2jl Gp/2m5MeqLtIUlTiFPiVQdja7G810lfpOMOJx1l8dx2zrVTw5uKz71brLkwnkELPNT7+1itz8/C9 V6u15RSttuDInSE62uYzX2OU99gtuF7roEnf6tiIRbU6ps3ypRKAcB6sFaLx9AEJ9x3haSL7eCDN /XZYkuxRj1h7hjqpH4H5nxnKK//y7h/abtXId4duJ5uW3RiWaSWNdkjWZXBbQ4Q9+vL+S7ZzC2z4 5u7EYZ9GPuvTtq/e39hs+YUZ7y7LMd200ELF8TdF1/bNgc4ESxilqNbJ+4ik7B2e4ctg77h2BkrS ZZ1iTmgAfPH8BZmJhGyjtHdSvWz6UyFC0nkUlfg9MxeYrB3NY37LJOa/z5Z3WQ1cNQvE7pSuXFNC yCntSK6Rq6t0GFq7U1mTV9rHU9xYBwH7YVOpUj+oOje+ocJ7cnr1Zpc9DnRLu/gTfGsfuWZAhI20 14U1RO5Eb0AJ1T6aL80k2y3BrdNS3z0maQ5Fliex/H55AHFQpajnsukCYnqmb5V16bIgSpmTDAKv 5sEVfQHEG2NBlL/Q+AozsMi9wONagPNTcAdOsp7ZSvuoMvAVHtPKoJJqwODL/iI1FQSpSwE2IJZF gUC0ISYSXPFf4RTO/59vlHqju/XUdPunB5qbLedKN3yLZLBL5Id2cN0UT16PZF0aQWvM01/uj7Jf WxLZFH7jYtsb2QcrtPxa9DgsCu3Qh8QN3CR6M1a8ERkWmaVCt9LURHDHNTsA/3W7+PTRU0izviTw 6LMl9YpNgj0BSz09arR7HP/fmKVLw6EoZHq26ZIE2Ydg8zfvpjf8xnYOMPHMsPUBsYOySVu1LWhJ NKouBO3C1Hx03OZzO11GUPMzDlwnXNlRgcmYC6M30bDBfoYxFjA9LqPvySIeoy/MqNhnXhLI1ZCz tQmQYwYAoLkHI8jygU8w5aca8Jc6XIWxuAyMLaX5/m/oluDZRClyVs96TUIbqJciQKvXpQ80WpSb L43/dpyw0vMsvOvoYWj1sqFdtkNou9EWS5IDXvPHibHyM4ef9NwhgJOSTC6zb6ehow5nrLTnPWAH f4nsQ6Z9EqdQRRwtUOPzMdmgyS3Ve4VViScX1u/738ByBCSlw5+5IVpO37kUxeuFYd8u+pJo7Y8B fi1tsh0oxnQYhEW/5T0mYrMf3qwGtDLxR1pazq9eHa66R75amLHx20O/cJDpwqW4lwKACLH0B2vL vsdb4A27zDUcYjwxTyMxrnTJScGzTP6+FbF4QycJRb1U2WgwbybC6f5nw0jv3J6yCLUWtBMZ4vYB qgqhAjUWMNHnK6ba4y4S6K1w0Qa/E8GBMI8yDqKbL2yUF+xXcIRz7Cnb+TmM3f0u4o443026/g7i ljdq/DisWV6go/33gJumHqUJGWChibpJlEToaWCm22n7CpHXpfl80Q1mKsSrLBp8w5LXQpjRwo5i IZkjb/t/JDvNXIEF9rNLM/sFQUEM2I9ufIoAucozaufeZduSWxFC6BOOGo/zxticXARXl7bU6Ae1 HGGEp/9x5xSNrAuP+RLfBuNET/M5oij00HB+2JCTbchx7LLGq84RNNCRsc4OMIlwO/y2/WkgK5pI 3Znr++sJYsvTPGCIpJTgpxGlo4MIpeIyzsUWwdLRGuvnk54iDnPC1oU++C97qBnFu/E/i5fZqqTB XdljlZf5EgVdZcnFad575eqfRGfgzJ4WlnL/pTz0U7+VzMc0xM/evauhBgDNosDCoksTObt0AjBG l8IT0c0vIpEpru2xoaDzpPexQLniQYKLXX8OdY3s6IIiCAkRdHUytIUzA2ABHHbqKIpMZgI0mqE5 zhd+vvnY07+Ge/iQZR63WfXpJHzv6hqSqE4J/xfPGkX3dyXes1X3Macf8L03ir4OvsIPnrRuLM9H FftAjICfGMOtMiyD/ogBfihi/0dFlrE1Vrx+h33rqnMmx1BXXwWLukKw1WfB+CgqfufXYkRUJmXY 4bGnRC9H9OU73GSX6ILb55MBMZCThRumEb/jKGQ2iB3DBmT5f36eylaYNX1AWMeztW1zFdS+UoJ+ ytRV6WUbZaY5TOlwgsCGEkJp7KtkxBmQh+YxpGreCSNbyTyj9OwtiaPfxMHQRmRyzaFORANy80nD 81Vh3B8GMNEiby7aefQgVIoJUC1N9dEa0bfA3duimLyfIWKOJEPgLSOh45/TIVvdWL9DeduugHmV n0tCm3Dfj73mCYQjKyeg39AyRvo2d8k8vnwrN35wSlpGDABSyw849aV605mm8ybnTmkoizbRKphs HJ+5J0/L0gd500YG25lZ8ZJFHmMTN2rUi5R0RetXlksCgIormsGaVZQsIfHh9lB+WrvmjCohCYOH wRgsp549UEOdU9tC9QI9Y+MsyFllzmdS11GsM4vYoOLnGeVJhSVjUKS9Lt5LcQ+wy6lYo4qg88aR W7G/5UGuuIwPArnuWv8blLzK1hCmAZOrJy5RfC7h+3Hux/2WwSwz5krMtgrpKcgL3DNZqDj7jaJw 7pVsGNYKjKB3EGqZ3T7FDT7KABO96W41564Zuj3gc6PDAkVm/XdkjXtRsXK3g+Nu0DmxwH8qs31H heMlIPzQdWhXBr3kKdryBkUKRXTXDgoRi2cQQWlgXGIs5BTw6TVffyMLwtfHfCMS4C054ul8cY4U FMhrNTPHiLhSMl8vRU8+/t30AdH/zV0UKDkiFGI6AgkUIQjZHZBJpUgi7N3Rx8vfS8mXKOlJCSF2 GR4fXKn7Ibw/Lu+ke/g5iZKF6+DehuR1queGmXlL9XjawXrbSkTVKPkLkNrO7tghqnArCQOccbl4 +wxjYfABBGXSsKlxHhEcyBs8LYPkJc22hk8aI+27Dt0LA+3Fw5d6g2UKayzeOHClNGzcum8TzcSM adYMarmhyXo/JA7NSxaC6hMXv825ReYFJOdOrIPNNk7UgdQLK3KddDoyFcV9+MSqxy3yOmWa5nYh h8t3ZCOni/tE3kPUZbfVPhTc6wAlxQ9VA+PzI9YMctVwNbqRGld0qFwoo+xTTP8v7Q2BqgnsX4i3 xoWhOoBF4dzSOiiuBBwm5jAEwViuP/+VbeFMicRKOxE/731N/jqXIKERBxETmHsvfDq0a1hzxc+I VFK0HkLjkgRC6zO7dh8zYUXpMEBhtP/utqsYCGixhlXg0EvaJHe3jU5JMwcjfV9QLiqDWvl14FuB Iw0npmQJmurMCCUPvta6XbuFpjMSZHdh0Z4kLdS+DuGS/HJsIW9dtegT1vlH+KyWW9G3a4cd6VDc dAlj5xEICBTk3hLU7JufmEto68xze4S5kS8qJsn+mkVv5cJSEFseFwoFOmGPmCot7KGs+DpxJ1hv Isrq1RvO5ybTIFUImjJEFpv8wDmLpBrZOS4kTtM7Km/ZKxDpyJZ80jisW5sOxDZq4XjVt/OcdsK7 lBsW4XjQ9zjx4txMeJMooou833CxcDZ/ZOOL+uJb2f+xZcyT5wRgE6xAl4Ag9llgImpW3C43dyea b6Dz/JRJ+cKNtsWpdVYW12s3IACvfV2nGWhraIRg+K7AprsEwEHF03JSyprXE043BuwphMZvdOPi TaNt1C3wrNOPV/I3lpWXvSx7JKssTZqB0+hx13E6bFbMZjvU0DyI93nTXnRBqeKINpHTKdPQ9sjm YUPG/4alwGIH1ryY6ySkmBhz6H5ZOxFSPqWG9x7UINotXtG/gkq1TYttqFaALh5N09fF3nT6NK7G hRlqtzWGGgscU3lsfiKjsMHuHNBSfGwQkZr68rQbKKmFbBnQLerclgzbfPT0HX/yNk9W9urNgtMj TVo3S8xP6PLUqYJ5AxkVF1NOmL3xboK/FoET/+Az7AJQO2LJoBXShejYAc+/+XhpKwUgTPyMpZ1r i4GS8zknO1mnD2/a+7/S8cSJCTYlGzC0uQH8TNnr/deT9/Hp1jSen4D9t5TbpMRXpg0+quzyfVmp VU5ZsOlwUCWBjuWfc9Oscu67FqDJHodYyrCBKjCPiGZhLsQgbJewqe7MW3c0QHtTPRACQIXdg3bR 3n6Hl2cJ2cmEUAGHHkwbWVoZC2gGVr7ym3xYr3PqXyRP3V8V01wWfH0pShVyMDCC221ZIBc9DX7K 7F7ULzIPm3ZhV12iuVBHY7KvHzUQUgz88c6UmSqFRo7zxpsz2ndry1s7pamuAXYDUIYPHvhbh9B7 iWjfXZXRXqprqbpkZAIZ3sKHwTONah3aTHTjckAngjet/GaiDHY8HxChEC2o9aISMkNt+tj0vpbL QC4VkVhD+H+L6fa0QvrCQoKKye7Tyl9gGrQ7e0//EtkyQn+4xxz442fBB8ofDqlUYRqFs5Q1c868 hSFhGMUKJ76fz1AKtzbZe+CLGeUrbgDh8PyNsUmR/UVUyMLAPYn3Hhfbm6nYuylxrQL5aSbuaugz CBq8J2aoi+CiSwmt/vVg5G1HWcdMGttp+V8rrb0kHUYHa+ZnYMtDFUvVjEjXa+HctvGbH71hKWjL X/yw+XhrApU1590rTcQY++E2lGa9R9QG0Er4Jhb+wounY6brF26XrIklCS9kd/EWCupPoLzjTwQU UT1Lzyu4kQJRiWfQMRYi7fbfVh6lewrlcp1ePyJkAKGq4Yp+Saec5EIXsnIaJNbl/mix4uOVId7b ZqLJMTZnhbmvKSTG+Tk5oV6aeei1PoZTDf3PwFHlDO/8pFCKUugJDFJRVgAHs2kZK/MC0F+uZ1DS JEa7zy89S0Nkm032kHSKW7XyPABVRn/V4fmgbNBCW+1klFmhBxG9UsTYvTfBMdxnpFIrqeTStJNB SyD7djg5gJUdheQf4mL0bJcL7Dj3903aFeP/um4d38DEDOrqwGOLhRe6VipVhU0LrkkP4cO1P4jd xSJFEg5Hhq3VIe2OaYpESRSeSU8cRivXuS+UbF6TIHJHG5WaAS17eTzHZH/zmWE5our4Fdu1UejN agrCNl3QFwX7C3K//ch623sdypd3TsYEvx0ZJaMm0Y9VlLrR9idT37zwuj7cUD/HUvy4ue98FlCd n0Qh6RsuNJGkV1xq9ThN7/PCradIXe02nPZuKqDSWtU35vtjXgGBv3RjLOHbrocmAoo+crWHHzbj wbopyIsMNiXYriv+qgccXjgrz9CV6fZzlV8zKRkfKx7ngTLxVF2QRWqaVQXnSuZxb2AGPl3YQ8Qj KkWwTAKNJWhxNhLkkxwQWBsN5SsKeazV6TC4OsAaEyABGUHKMAwDcVjswkhUnTdQg1m44Z/xMA9a DEUBV/yWd7mhHkp8FlS0LqGKboC1AoMrelolcFrM9Jqcw5YpF+EXDBVdm7Iw9njlp1GWTLM96Rrv DzgDPIyvW0I9OFV5s9WMyGbl2/BOvR9Z0CGuNLpm23XpOP0Ab1NxfYgR4V16dxxSL1jrsJZV7oCw 3ud1jD+YsJnU0q9x7hvY3xsIlTuwJkfp1QS14RsSvoDbWv/a78n4l2j6L9BQHKYl6zbZXsiXbbpb VECzlyJCVmi6rssnsqfahc1DIFZvhvmWWgWVuBD8ifHYRJil/6vwUe9aqvwz+phGWfVrjbuqWH6n ti9AOIdhE+DgMzmXYSM26qKeWccwBboVPgujlKlxafgZvNbWO2fBTgyWFGCiTzyPk+ZHLcUxrhlx SXUA+l26OspuBE+fGjjYF4KVsH74N6VXUkrJsELPBQD9xT//EaBO+IuOdyr2e+DaMyfKLzRKPYkm UDjdceWeOmP0L3cIy4lyyatW9coH4fVkaGM2hl3QVFDMB1FyH/4yPpHAcyByS2g6m4SHiVfJZCnJ Npp/khEbJ2njPZ1J12h8T0dZBj1O40Js97IGfayQHgkSh70xov3BFC+DI3788xvgPScDMNGwWsKe kY9RMiWjBlTRtrYBI9R1yeh/9hqXxEb+jkljxQQpK4m09HARk49QIqhNuAq0KKhoZZ8KFykf9hyo ejeNbi3VseSn/d1Q3gpabIPi6U2u4Ryo3H2pu8IahpKR0Y9zJd2V6F+WIo7K1gZXVa11nZTw2UtP j1E3bKn61YFL13UjHDjDpR1N3lw6/fojd6XxVKX+E6/sLHafK8PD6n/IsV9Tq6ex8Mw+BrJCJZgq DY4eY3aj1kpb/AQ8uzJwOcqSxVg9vFxQUQlcT9bZjvQRJhGxEmMkzeVO/8dw9qyJ73YrBRT0gXHN 2ndTx1kn7MhedLyRb3tTEIR18Y2bBHflOhqL7FGrW5qcv7WGlqp8jrUfUTSfQryBCxQkTFqrwnEa juNbOYWId0bTm2/4cWiBRHqws+Vzkj4l03onPIu0U3Mg0Fht/kqqhnFh9zRijlXZToy18+m0M16l lpEp3yAg4jVhnH6raYIHqj6CWWsVIkfa51M2vXQ++i63L1FwcdS61XhZ5iPJll4T+0imGBICoKhQ IWJ4MMwFJPwkyZjbUo5hyLmXpV0vv6Yo5SkuB8JRjZttbkEgulrOo4R3e/Njp8X9f3jQub7SZhKW ugnRKHtD1f2eu6bYGEGOEWFoGjwhvOtJG47sWgjhsoB0Zjoxg6OCPDhUU187mFQDclPgfI+eoMvY rUYsnnCGTy9dNZ4TiNqr+AM8LrjV4LNC0+xjarR2z58XBTKH/FfLda+Zcbl+aFOAsp9R3WfTkYEu BZQy83gZsLv+qMgohalHmcDSK0xIrpXCuo2AsW7qfQgpTvHareSASwB6AB8VMfJAG9pQzkY3cAWr jX32Hnjd2wwrslYF/dSadCM09tWyxxc7fpGipTIq3qlvGqQCX+0yU9oZ+9LknBMb3HagLc4ezbKl Wj05sNskb9Sgb5zMdUGh1xRfHlbFwp7acpFY8A4epY/gFNCmxF59UEWJXjK2Fxph07rvYRoGyEYL QeJepr4cx4U4nsBVpFqe9x6+4Lu8IzTcPVGWUINd8jXNYke9EnhLzrsh1uZABxmD16VDIyjFCHWq 0BPfVxHI/txSM+agHDKiy+ViHIwCeVH2+SIlN64MSdQR+8J07wwDVu5faR6TH1xDD4UO2dmcI+GI H7/x14ZdswrtkYyhUke1epjVryTPvvOjs9UOTIVdxNSORnuZNIBTOUjYzbBMgmF+hbp4ZnXnlue3 ARtvyZv1ZKc+PApTAILni+7DbuMD71fCHpwaX+f1AGxVcDTrQsbN4+e+GH+WoWqSgU92DbnXmdAM wfh33RnFmK9KI7yvwo13TBw6f5GwAwULe3XIohdVaygrzrVM47mVyG+DdZc4jfY039Mt4GUxh8fK gvCgkKDsholWa5dUYxhIQec77jZNmyNljG5K6N2u+4wWV9Aem50SvFDiBD4UhhpYqr8LpxVDe9ni k7kwYkYi/747f/6pjwLYfeIgSbO0FxhoCOHwHJt4Y1nh0GiMM4HfkeX5323X9rEzPFSneIY9f1tz dnErCqXSFpC2cYVdQg5DzTf07tnREi2tJj+vhaIjQqguTJdc1gyFQxrrTvgmFNVIWzFGt08E7ICE 462Y9btNSMAi6+OKDTz9Aoa9/kURhSPANPI2g53PgHWVkWscXADsv6Q9V/Yx5xQbnJ6S97OGt7ep P83/iwQRNaB0do/ptEOC2z28KxJl+rXC2MbiQxD0SSS0w9dr5nS9q+OxP74xHdev3DPgSlLvcG1q F177lTExlaLhCdlzBRKSZET9Gw4/i5WgMufhG2ZPjoxBDxi529CkZQjq3vVfW33x9lWJRNq47aGR Cv/sVO0CIa/gnBqTKdOqgkYMcrCNDIq/0R1BknuaNw0Zdmyn9SNAAcaCI1mxrrG6AeYPgmn//BEb n8VxpWN9Z7NniPGbVe4FhABTpQi6Q2ExMzost1JzPqO47mVhYWu5f/+M1b1igNSkUAD4Oc0z3S4a yA1rXyQR29eV3rSq+UBQmca7BWiCGeDR5UQhBI+IjjqZkTBHMK39Yoi6O9VdbnIL81VG9jLMDdOq IfyRju/noBZKAA4wsg7GfDvPsYhL2tMaCKeYoGnK1BIWLLHXXvbOPlNLcOR0pKSfeeUHec+XvmFg tPGwY1bcvN02s0h76LYMjHC0kWksOfnFaaATI+70dXcCHtizsOgXy3UcIeRSpWd3X4kzYEy7uQ0p t0bxKIb98l3SDskuklwMOJ2mVpty5Qy78Hz9SmTBL98KKmZ+iq236+EhhPesTD6FiuEmv7gYMtsH OkKnHHUDiwXvcrzalrNgnhxuIhUUVOEzYdsFCL523QpC9RRWnPUBRsQ5ilFM3X4ZUKCxhW070out rBb6yGXzryX8zVKgUAMefkxba2jfAY6INsAlIZNzBUZB7tBZaSd+bOEI5sc41kqTvlO1MY7CnG+4 sYq5xDkbLt1eYhMu28tqNRYrlaPftzprIS//LnO93e2DTFmSp6+ZJcCbCz7KVVasme6fKEiqVznf 8bjP3gJ/Zwd3VYfLHxcgyOYoyJM3e8a0UYx6K5PIdRMktiSdcF1te4USMvG5wfModX1vBHfm4eR1 6vj0LF/rqH/59ozxJMyRf/Zh6OP5Qc3y/zRWH0LlaSIprTAE19Y8FTZUH987fUUgkyVauJBum8iH 6fEVs3fXHBzRutX5Jw1xrvh+Jm/4sRj0Jusuv+WUqWCUZe71JYVLsBhGpL41sclJ5L2eaUNE/fIg QSQ/AttOx/Ykx2rXKG28+HqIHj1WGhSTUAAX4bQS+v/Awi7rfmy/mH9Ll5KDC/uQDF2TmPjJVz67 E5NPWt81JWqzoYck+bdVZ7n5YUwHCaOLXdH4tMMvYE6/fkKjrBxWuOU9ZGEpM2QmoW8Uuu4PbsZx lKhUXPkAbJR0Ms6TQ6y706iEUjqsnKODVcpm4bTaQUVd2mCAwjQF9WOOA5iqP+fTArwr/WB6uW4F OxEZaBaaOB77sQhTSqZPavVHTxXTzi6OGVb5FwO7UH7bkdRfOnRCTaS1s2u0xNNOeCHFLhQSzh7p jMZ6vNcCTHYX3Zs4L4Xdtpr5EZVn6lnJ17qMNIGR3BRql8sfrnvDJIIictDz1a3EELI5MzNfEO/s Ro8ulZjAuWGxZu3xBYJIzVc9OvB7STTIRsHf2lAojs9rwu6fRgxZF0AMrTq76jbD2EXWucOo5+ZO KDPuQmKZ85Unl4Ib3TWlWXB8lzkm8GajmZXcgR+VQt5oyeWe/t5S2cqVFi9Twmp3fsUjAiPAI89s Ps0cywuqMv/L2vNgJoTbbfkFe8hLpogrBQtWrxSMf6ixbaSrLNhm6RrCEat3juHy7xu0OTrbp8GP Xiq8mH6GE46HoJXx+t+gntS7vCVqAuddKZfPha2HFiDS67TCazqZ3snZyQNVIJSh7WuqMVs48a4u ynjmDPICijj/j3NgdrxH9o+AJ/2p0ra+ULfgZ76n93YqJZJd3w4J7uoOepwGAufxP7DuEfkdW84U +jI9MzCmZy1ts0kXqDtObOGTQUdyziiDfTRmsGzw20joNnNBHYfhz9qYQ7rxguINEUDRPcJhXad0 iN0h/AjaFgT96zmFv62wudP7gVEf5/IVx9OB4e1xJ3UhFLq5NNm3ASE/s/IqJt4GOSBBunfWM0gj +WY/QWYt6BpgcVy7t2Q9MRNSPxwyk5Da1SnPZi/hFANiCPTlsVkATbe1XgAJbYtlKN1gKT3S71HE w2BKDcCJT4bXaZ67YCj2RXMtQvf7jMf3fw8fprdiFZgXToHBfQisCx98tTkfjC1xZKHHzmBtj1zO f5IYRuBEjjeaG/0RnJkxNtewxjVf7TCfgS7mxFTAaaW37zIjCtbfUqeTK5+5/jR63BktDPEyIGXm qY575bN73i/RkhAnhfqnhZKCkB5l3sAfLL2K20/NKw5dOnXcBk5+TwU/lB5ezxxe0ap2BCjonPMA 0nT+BA/WTtmxFCPIsP0tk8zRkglLcQBhQf86tbaIR8XA8YTU+DgPjnYORjMqeEPW4J/IoIzNq4jW eoSojfXoEkfcTSXI2kej2nGiCh2L9aDlhFfoULUR7R2Yh67TjCOD/K1nL6hAu5rBPGgwJ7tUl/6s fjBcZzqDJSYWkj1IvOGQ5E3+p10HAAsifILi1gWV0WZJCtIUVMB8WinIdSPifggPjmgOY7k/rLWQ Kr6+egIQNv2S/xj6lX5a1Cjt2oUJqYVVenSnwaVzbXJF3COcPiFxPqlj4yW/2eDHSogVS3WorLQs Z3pNq6VE/reY+tPJVu2pKiFXBRRpgvohibZh0/nhoANz8/UZeAD3+kf7BwDlEsvZZNuhG2QXMCk2 nZTJiputCOnSH4tVmAUEiABNeJNrSw00G7VBz2e742XUwfexpAUXIlGMqJevQnekin8eezPL6P0B nj4s0tiLL+vwadF+XWucwxKU4aEFK1Rw1Y7c6mj1uXQYIeHkXPgVPwjcbZkwa5exDUNJmgIr9W4h prETZk0mFd2pEw+L1uLnyh8lTClvu4k4CrT05N0is6R6u48LkxzK08tr/usynqcYqkNJcZZTxa+h 3v07TRm00dWYWqL++8lY7VQbp4NcCErim7QlqZ5RWPfA6/9G9F+jIh04gdtjBV+qTpRkark+GPnL msnw/evadIVpbfuiYEt2rmTQsTygw971bh3zbqFwtCaZHrqtepscyd3PDHEQjLve0BPGaLHLYWBt SPWo1XIVOm+E8hI7xTrXajZHnIA+3pju7n8/1UBjwDCVZbjywxgnx6r9Op6GtumkSzlPWubuMb1t 9VtRHZ3TxNeUqk+7tBGwhSakw3WHP+lZduBUU67PAkPH8wsHyUD6kgHKEyCXW4FnoN90O8JWGtUs 07z5w6cdlq7acWWrstvGej+PC0pFj1J8PkhVcL7dwuJ86FBmZzpUVPbveD900hzonzjYZr/4ucgf XBGPes2TmjyTrQSuY3CTC8p43BYveBHO4AMxrTPm51OgeYJkUe6HSgYxmz2GMP+0/S45McIpihOy 6nUSJaWgU1iXR9y6IZkos5tIvGRs9oJ/xI26id8nD3nkuVntOpDHYXrmwClZ8NoddEQ6e6PIJm0H k7YWHGgXAvUk6dM+pnXJE1AR/LVdAbIia5YH44N/zd27vIS16oz27CYM97h9DOWu2HdiZi2NUXz6 CK1ETM2uPeM1Txh/Iq/lbsMMGN5ZL61k//zBbEVFmInwDkl1oiT5DnH8/yBz07qi7fpW2sQseHBf ZaofQwoCIXK153S0IoQUZkb0MvRw3Y85J63PJYkSB4XdhWt0/XOWwencaQBhcOMyBFpT5ahRgpLT +AjJ91RZU4OQepSzYri1aD8A0swA7A9GPswU1YR7qVmWwJZwmbkfEX/W983A2BHxSo5g59G9g4Uj Z12Sk5oILFMDVJWxZ05ysq9hiaVCmx99YcizN/rrOeZiPhncxODOgVeYMdOVS3uS5fLAikxbxLLg g3jN754i4S95c9/1xu78akxvH+BQVdzQnoERppcHeQr6ynKgOMWlOL6jMuuktMupk8yfxWwoebjc ZAocjmkzft/t3Q7pwTCB/Q/F42WXrE5T3kUW9hO0ebvDtvocEvP8nfJhiEcwq/hCsAJgI2DUMAVA kp4SwR3VGUyxvC2OVou5vev+8hOWWqK1abtIVpWQa3r23BZ9Kzx2YU+t1PmlG0k+j3Z0/ADI34mp c11IprV6NnC+s1Ns/bJdV204wCOaMqT7scvZMXk/wAGhmacZ4KG5rOzoCt6AJ3eoumoRYbX2KD1L 2DzPi9J+ZMz48HBWTaxOuysHv8lsg2chNCxg24RvbCeVRTXgsheiux49VSLfNK0QmU/CreXdyv2U NkHADVZGJxk5vavWfvbU4OOotGO0FAfLDVwWFCb8629To5Sbsm4ab36CSXHwqRTFakBJZB1RXgP+ tOPI3JGq/8p8HFsjguuvRzt/6qwy4XHx/WNnwkdAJO7QnXZFuGiMqpO3Hk8VWDx3Eu/Iz9rm00xp xJPlJYf2jQx5IIUsadg+gnYSumf6+lekHdUtG9XNXUd5Yve/zEW4OdbTOBXjjXOFGexymQytK+Mw +wstzjMruS/bqeNczxIcnPfqUwiovhngiTY1XfCB+JELYMo8xNoAneDZpmqK7ywcnWhpyCS7AJsW 8Q0GmuIJislJi32McUooacomwQ6lOF+N1aR8V9sxJ/lbB8SFWi+d7VzCBRzqabewsMZrHTmN+H+j aEzmpeVRuBZwECnwKh3Xt65C7R7nF6WbsJ3JOd6UtMfad0fxx4h/z/uPvtvpPFVJu7S+z+XgeM1G Mscu1CTThYuVD2jRcrLvmcgY790Yrm69k+H/Vfu+3ALFRdCzhx8hpeXLnRCeZcJuTFfVOoYAS5ao Nan1nxBT7ewzq4tJVq3qV9K2lD7p7P1BpEFef5TfWE2yozglwXMk2LBuq2sraIP6VaTkfK+Mx5So 6eNOp1ERzsXOmvuaHNYSOrXNCxxZvlbR9/QdL2kvzT+gbihrpyS8Oq7mCydNGHJsDsVPPvMRU4JG cJZ4GKmDmR8Gc6Ou/WmZ58uykj8idMdOrBNbNQeyj2F4E7ZQB5gQXUUSIcjWY5HD2N8r0+hqupO2 1sgbC6A4ga3T3linhOaihDyB++064mE2KT1LiA/deqSmR4OdDOtez+OwOgON3qYND5eaxJCiQJzH uO+PJn3ni0IlGXfNZyo8EG82xY0CZlrdIogUiu5VUH6RgWyqLG0T2EtASENG3FRBdkwxYbMD31ch w5UG2SFwlRTX+zRGax3NvGQHabqMXKIgVaUHp967NaryYBNV+Vbkd+jwyTSbvFvrAnkSdxIIcDMY z0o3hTEmp/EHSdNLdaaBTiU8BLbqjdlOYXarPoYzwLoKeNP2VeNVS0sfLRi+E6N8+NpNorihyW3x nmgx+82wx+MyAPN0Bl+/J5Wmia/qko2kfvaXeKuklKuE0TK4xR+jC1X7go4XRlOrTN18zDUPxnex owIwwITL4odbctohvq9K2hrz2RKUfJobrY0HIEunbgeYPhMe7vXOj8t3tgL23RoGQhMonBKKcKbg +Bci425uMeoV481hqHQIOVLOm3K9f11f1cxnYMYacrUriAQNPSGvpkh1Hs/RbuIJy10bq//HEnJ7 fAtRMhjL5GvMtGp37PpfNQq0tLtYq2BSMcdUBsELrGvR/NcBcv7vL/tcCYNIBsbTyyH+yIHa2vtg GSTzOiq1Xt4hUVXF6UqtexAOA9lv/Zjyy7YPSuGPam6I0LUroxSbGjxn4r7N8PblO873OQOzMTjJ ef5jLZNZYtqkVfXATZptMjHugkzFrNWvnocjNZJCVmXjaklonGSdsNwJtPJvzRL4FbH2IzmHdF7Q m98nq0qCmgS0vD6QhkCRgaBgq/Jef8trl6tKY7KdMPM0BLjS2XrHADjofhWKzVbXLeC7UZgIAHZR blWOax3eYJ64712XIZ6LGCZ/fdMbeggb5qALngOoXH61ckBjgumrQnr/LzslKzemS6E0G4xRJEuy GMGnrwKHy0AAlx7eLa1534626LoEkS4AK92FdRbwJgYnNsCrmmr5FVh8SHA+feI1+UT5FxBW++/i DxKonlBSs0OZDTJKqP8yAef0WchQhXOEQ7bFYW89C1+dP1YtcsyFWcZ/Jq5iL72D1XvC8CyQQt79 HtDriRLAUaP5Cgl3GEdXVfno8JETstZklzwIL7IrBl8nL9VGl6MoJGAQ0cfVQp6FZEUI+zlycn8v k42V9i44GlNsYdjREl4pUwAufPeOb7rLb6J6nhotixBGwXhciu4GSNmCy37xJFTb6+RF0b1NbE/W 3PIpTU9iQoZDBukUxzCQnJVhp/MYplcc4C+uhdBQgO5k9z5BOogZkC7/7e41X44NLmepxrK2rsE5 nkUs5KLSb174Nyg/PrztVTKz1l5sQLNA9cE4T6iXo3xeRStPZhtQ6NEN4CdgPTOkQvn7ayNfF5Uz phW2t1i9P6EPAuPcSTuaRhxZgaw502+Zz96x0KcvZbi+8SW0L55lt2cTE5k3EAYqtig5v9VKeRV4 GONiugnOP6/HRoY9mOXh7rk0Pnp2icwOXMHBh7grUhCsR9qr9ChCog5hwmDyoOJeu9WX7IqJYeEf CON84OWQQui3BtupWFRfZ4PQiDMA0aZARwBn4EEgG6yCdDqSg/c0K0SfHvwAb0P6A0dcGoVrCCFf fP8IdL9B3Rw/+Nc0fmSOVhNnh9EHmtncl3bsfKA79yz4neuCyq5UIGNNwpvEn+L2EUIvPxitD9nr jpSCtEz/wDKw0cPKktYPprZOdZku8FSY6dOWjtmAGFvG4SBlmF9sT+1UrW3pbXLh/Z5jeegAlwF/ Mi1Z+SzRqmMBqKSXM1JmGAk88ZFu/9592vR7e6Erop8UU3f8BbJTXJdR4NqKH/gLGGH+KYAZuVEe BTIYfwRo8ngM7KQsY+6BKKRIIejpyBertTaMoNXEODyjrEmVnKcMGYrNR9yidnSdntHRKtSm4abd +zg6XTSTODfUVbZtHSwqqByYxKXKAbhUDWk4HIFQsS2l2lYzBVm3K8fnmYGK8M09MJ9lnXSpaGDI KybFpIfvGfwB/pMOv6AQqSmqT3jD/n+yYSx7D9TDJaJbs29kHFx98umFeTGSuSCjNjs3iSwxxDKl 3TkmnULtF+0ok1eS7GA33j3V+GgkysKlBej2dw+eyh2xIwAloA6JDHvfMwLA497IHx2jhxKeI5oC J8IW/myiztmcrZ+1pbgomvGSkDnC4f9Vil5FuZu/k+VJaOuPYlIqBdhgj4LcV6cChCGKuZcz9iOA DxOLKprbaYrVnYX+ffXx5jpQ2/Tvm1hQlu3CAh4bheRwUSlJsma6OhU39lmkatqoyfOHxhUzwODO ALmfGmdOrlmh4Oz4H2qKzCDbZEcohEv1aax132RHqCiG3WtD+65OFrKh+sf5T7dJzjnx20B455mo GdLBJzmzx/YALEbYzSnDhOGyQLbG3Krjpwg8iGv619JPeHHgN/DE15CHtnt4zsoceDI15i9jw80F B6KQwXo2HPTKcuPSzUU/X/RTB6vp+9T3NhL0014nGui3EaPaIiCpOoMQFQRR3VCK9R9ZxXoRVCgq nAsnfsKpu0Erc+lhF+Rkzy8HJ+AyzD7addCIl7kOHMmHsrjRKJfcL02ofzhhVaFwyOsQS2/gCMTa sMr/3sqbizBLhaaF9K3JWfrFA0vxRi2ic/EtvhZH3h7A35R3+A4eznaf+MGdekjSDbzxvUHb+W8Z ZpxbE6kPrpVynW8CF0i1NoRrB9y1TUdT9lpuQrnEM2V5RBLaOzD5xZhS4r59XZuzSaONUgTkWybJ jPEy6yphY/KTKgH+5/HigQ5ov2rOVz2TTN/GMoEPvocHSyocQruBN/UcsKJOQXNwFE/xskSVd9Lk abln502PpRm0n/wVJWBjVWIeCXAbwhQzBmNpyRq/q+E35PcgqIOVPmR3cqpJbIWq+1ikM3VNWo8/ cVjz31uAHz+xlDMLpH3QnQLqvDkQzuz+OI5Tzsh8HRu23iwAOTECInEYPn2EfQ2bdETnCtqHZzOG 7WcAWym113mrLQQc7zjfoqYHYcSQfSsKqzqF+hvHFWVfpMttc4xKxcDMjvf5uWKCPVhuqrDL8Wgj 57PPYsIBgTz3KBYHPs3kbMeXHutR4+JdT49D5FmQqGQSW05vUnoX7ASpcPrmO7DlHYgN8+3fhhS0 jHsE9nvBHCC1bjN14h1wynvbma9A2TuS/aT2GZxblG+uiQFGLwSPPUCzx2qzZRJU+lPrFyHE+f5O Ibb/3YHQytLjXM98VrM7XjxeDwc8uvjrw1PY9vGQii+H274x0MRlG6gIEpGAMMYCsDNn5ejU/zUg z/HP7XxXG+tgBmupJm9ozvXg6mu1IJJwbYrBivHDTpxhqcWG7ZHA5KPKspGSUoxdM7UptRWPPbyx il6jCEHYXeeTQGl7AYxoPdeTJURhany8IAeLEbGr/7LeChVi3GpYQ3cQlkyVT387XhXoUjwHFND2 HPxGS0UWgpp8WT2/Cr6/b4KxYT7R9tNVBzM3CKxkS/fCV9GTjzgXo017kmq0Z/zHiz7rPpSY3Tu8 JK8tmZU5kCzPCeM8+0aUK65bvBuBT6IjaZj9irJz3ats7j0Rm3fmKyzIZrnNuWK06ILOhO7m40G5 P3/IVVifjNXAigeVvvoBwjUQg9WtyP2ks3FddGQq2dlpFpJO2VjfsHCFv5pCwO1Gfi0BsXCMgVY9 VWZX/OQ8CbtLkECNwgfANvJ5sba5689IgdyXM5xuk3VpdK3lNzOH+FGZyCPNUPXuc46+Tt2m7oik TP1btdSqoHvgRWGC8h4qqZQ8UvXRj3GojXuslWDtkqH+J4wti4ZgshAeYqX4iP3tRac7Zc8af6eb WUlZmsNVx7Yb0at5f1ub8yhYkAHoPT79RxU3G3jiYEuZu+P/gYYa44U9f3oPTc4YbuM8p2q1p9DZ LBrwPYClgzzgJoB/81g8lMNuVVKe2/k75aUo23sRLsRYWcVCQZgsaKoVvwaUjkmAIFAXDNC/d08l 3vKNE0Vy8mELKbQB0uTBVUja7/4UDwvpRwhQQps+ZikJT8K2kNKljxQZyHituhfCOgh7sHPDJeZY xPA650gNm8o1sizW1LY38AhSFzmPpImKpATWUQgro2kcL2IpVzI5MsWG37Pb8hjB5AtKlu7rG3h5 sV8FWTGNbc4FLmTlOAPMLxtSqF8vOivCk8LOngHhklCQ28nzTaEuWtwD9Dcw2RR7X5+O4v/5nTQ6 nKlI1ERWfkWfBXnENKwQtNwBhDQzvaq0vS4d0T2516LWQfElx5p6ZbOn8lf7uwx9AaHJPaVJJ/sR ys5jVHF1Q44UBvBvgiJ7EVhezth6p4RZE3SBjvAtJBExgWYWHeSVEUyWE6N/T7xjsMbxFA73ciKL CH4JZuIdrinbJm0GVSHKZtHd9hTudIy+fx6cKScgyq/RC3IBugzZrMlNTIkw06wvgclT71c3+//T z7/JmT6wHYbrqTHUpCyVqixmA66HhCTF7juUvJJQy0zBS6GvTRnzopOvOP4lil4vnYRwKp9loRTy mRdNubeHAsiZg3WpNuRkBOvD463eqMLjgIbEotbOpIIYJsoG+KioO0MwcVS1WWxG/ZHvDz1c57f2 ugUw0fdOLcChdS3LUwLNeSXwnAIWemjzar6+sgX4TNXWt9q9h2PtwTw6/GYejeHMEld/BwHBCAUz ozbEDByuD5gCNZu5xrAhPnzA7oPum8uKQZVTtbQvdGs9M3kxpLxDVucSz3vOkvUf1BNEfZmcbpKm 54B5ZMFGrpIKccb0EvQ0I++kMA6b3jHQbRAFOZC1gtjLD6KGp0hfkFqF9QIZJ3/Csp6iBe/UcMeq XgqbaT8rh+akfWN/PilBB7sX9zOVlZUv7DI7JqpRd3B6TbSr/SSdnhisPXQZ1MFVqieu209TnlIM lUcGw89ETxb5MBVs72LfZKWMQIPBuj0T+EbSFbW78Ju2uJn80+O/zLPLS0qOFzPrUDJVNb9vsALB 23xt7fSNrHY8S5HrlnxXb7UApAv3/9pAr6dtMHmB2QjHRAaDBM8GaSMT7oLNRDvbdeMBdPUrBwVN iM4wTwMlNMFZCuYGkCwBeIRDsHJuP73ubYlZZ4/1MP0n+1/TLKh8d11F/fKHdMNkt7tiUo/l6eEk wy7mHkJKnE1O/CVVhPuyMJfblRNjHzWc6xDBPELa13pMGLCqa0Vdbaagj/7/+wKxbqS0wTrdxTjD e3+pBygQQoGQChb5Nkndo9OrDOd5v5e5SmfCS0I4Sw6TckWroTWixm31OzAX9wZoftGgh25C7XGI rQQIAw3lGkakv8fUDrkbJUL+JZXsCdw37d9pipZYeI+Mbq4rcvhDugp34hkFoaxB/gWxmMnEFsDB QbFWl3fMhoqDIBNiyEk46RZPhkbOIdpooRdFC+syx2JNzUnk6fd2KIxQey5oPdRXKmXq6i210Rhv vpy8KChGFbV7R/C0kwelNPD98mFxedENg2VLm23ejyXibbqgIcPqzsZ+ewIHdGOvuEX/JTmZWOVw kJUX0EaIPMFhrNGYP2dEN9ofXrB1QEUJCm/En4PsJvgF7qul5277W8hDXOXz4FHQR48kTYQbBeXy 4GUHbwJr1sj5DDAAvfCxS1/gD/BzQR8GibRWs+lT8BX5T55gtO4Hi5bTjKBWaT7VRWmfWK26S/JX KQbrUQ1PFSFMP7IZJRDscW0r5dBpKdg2SoAjAu0MVlf3KX3zbjHUezyosTew4FY/cYJgsY4T+Rkh MlRZrFxJgp96De04TCvslSRunC80/6pPlK3WiRS2YK9gk0kWAFO7zSVswBkPETEzwtBP85uaUHWW 4kFfn+ubnkGtgI9chF9Ucn4x6WjOcwOQdVbK0/g0roMBUU/1bj5GpSsep39MbMKlmfqfvvjWr+wF Cy5e26kXEa+x/bwmOmfrL1S42waHDwuSvemmmJ8bGEAJUb0Jklys52wcY8sOFtvgkPyf3JGvQIuT 1CuxR78v2VELO275Is1wZwlYRWfoqqkBpkDB0K3MKvB9HScyQrTFCfwbKkwiTnfLU4L/A4UF3gYn e4qXJVzuDn6CJvQicK7jgoM9xtWoxEVvHZZY1u0zKFjr699JfP+yrZcL5S9nUPK5ryJ+TeT3LyoF nwT/vLbXW2c1/D6L+/K/LjA6RaLjiyIZQHKiAYsoIFusDxR9utujFTt8R4xpFEwAAuIzuPM8f9mQ oRoN5KDQO1VBtm98ljnfBvha8PhcMXNu26+jK5Z6wfRrikSeCQr6S7AD6ciEuZHeANumhOcxg3nA OXzWK1KKQY+vYLwzWaE3RuFI28ec0Kd95N9LSA9x935uMZmVBp3eQhdnnL06xKvGQfbk/ImgbZNO iKBJtoxCCvBHc29fTbIy5I5YrMhklALgOvTiv1hS+Ug5yycIKbhxKjfRUpPAVUcftctKQnAa/N2n vb+eNdXvNt8FnPxMw5etLmB3kAqy5Vlzb5wmud7KNjUglCje2/VuCeZNzbONYcgvY5csko3LxKKr 1b8vQ1s0eTH7SRGoORZ72dywqcUyPfpWOA08zOUHw9vZi/sgJDy45Cu3yTqNgpSnViLib/Ju6TBz kBHDR1fbzqxVZyAcVQclgbZ10pDheSV5d9l504XIAuRstXOGwxh7kEf+hIpwBmE0WSvW3dRh7z4Z PkSCmV7D7jgx6RZeMWegZUNBuRbA1ivFHo+3YFjNz/ePZkFaqgoEK57SKAz9dNLOf14oDyoiPHH2 yxxdr2gasFc4EsAVCgYysJ634Xyjgd80A2mSDW09jw5mmbOUhoNRgi97s/L3x+l3oRkJ+tfhIHJ1 YPx6DR84sbNV4oeh8gAuuKsS8WGJv03i1bsp4vSkIA5u4QZzz+EfCEyojxq/mWqVONtvsiSiQWwS 78I3Hw8yrj+Q7WPztTUek2UynJO5/oJq8q6Uynbs2vquc1eqmdX7wn3atMK9E3IscFx3X0wT+AJt sYqfRx14wRsf7zq+Os8riONMj91h5q9b/NBjF57D1Mw1xPx0alEi8G6XM/ktjiv+X7jNB3bglFe1 1GllXcqCRKfDT3RO7lQBV8rfgOphRcaGaBa97t3l+mrB7mD0MsAoHAdjDKRHpA1Wf3C3WD5QdE6S 83X2v791cd0rc8XBKJlLcwrEKir8T5qIl5x/okjm68P3gVc/iCyuN1bHIlIHsOBlfrQtqb6cgZls iv0xcBCMatCqtHXeRou3N7EO9aHAjHPliua0oCE01Cv3XTq+X1f27BKX1lozuXObkbydV67GJnPK H8Yx+0C60tx6vneSveENnX6jUS4j4ldpXn83Hsrg6Rpf+U4qMpcj1EIu7id/sNZWWsyw+eVYn5om pyrzabD6ptqLCHC9rAxnom0/W3AYFlRFzorRaKGYKLZLmo8M6GHfwfDSkQKzaNyKF/eJqlb0ycCk J75SRjEsMiamLd86hmlgeKdnTDl0EKSjuiXmIOYqUfDdphU+8GO52iKmifTZMWheGYdLd6ru+8WZ fWxFJo5KMi3mNny5vQ3Vjd8DFTEEo2/Z7AySSyKe8NaxAWrOZa4YN3SIEffCve/ywYoy9z8e5X+O G24WclcCoo0FG0BlRk4DF9IjPxlKyPW5wEZacQ59+3m28h0TEL4qudbKut4RxSJsM9f6JHANOVrE S0BTSN4Mi60SFQZYvFBJXHJL8o/gA5Yyi68pphnSB1UN0LuKNAOvCVwIrckHToMIM/vOIwDkk0sp rfX5vK7nmz7eT/ULyraKoAcvaYarqnXw4e/2pKXgZg1lcidLXx34Ysg+QR9LgmkLtCYAXdMm1CaI 8w5YDKy/yEBAJbThJGfYrATnguodnyTcwy65CsbVqqNXLn8jg2p4Dd6XEs5H3Q7ePh8k4x2qff1V /aIuqe4kGjLvPyYZXiAfylh1wTv4dP6eajVBVTRzYFhEfTXpoDjtZxjyehMRRjqjzpAjHlWDG+v+ CofT15hduzOvCugNswVN0ngj2pnhrS/pzBj63DeFWCWMLCPgP5bGLP3wrYXNyKBhoS8HryTteDvr WSzR2J/xcgCZowKiOKWE5BQG1ko1OshcLLYAl9WFWbvVBmryl7DFUUjuH3SN6rve5XEaiS+YdmT9 OsKOb86kRZv2PpgFQQ7NOghFH5Q3ZqDF9ddNnkPjDSHGCUbwFFtOecgzcI9dxHkZrfsTXc+DkMol pwQvAO5NnKj/E2LFbrblBKLKpK81CCJBhYuFYRWmpkJdidEgYu+4xy1UnSo5MnZmAgENiJ7cOQ0E 7S4LhWL4a758Jpb4EfJgGiesnVOW2AC4ns3dD6vDglcKwCUwd9H5VMUmPFayKBGsLOKZbY45GxIU HKKBW3jUR8byBJwMOLSD7uN8bVG3AX04xsIZgg6UQxX1j3OSOvIwstiQgD4JjTEzZwQQB/gW2+zS drcNA0zalJM0F7Y+jCnqn6i0q7gOx7LL3UBu8n02LBKGwuwvFbtClcg/lX3XxQaMjjjfgYYaMqiV iO7zvuU5qQG09hX4ZVmneMU05DwZpMDxUUbEl2pclDW3Iq+Z+xqOtbEPgfz9o2yaKh5tK3w9mOhf Cn4H1mtEWCciVboINrvta5xvoHDkCiElFZiwvFbJ350moTH4KlVu+1d1GBn/Iq1Ga2SmsVuOw/Ue ZaryE8G39fdC3WFYbCGtHhF/sGal2owoXyGoobSmn5exd9if365hgq10ab27Z53+rMhRknN+AirU 3aHNMzuOnDuuKjn+vvaSrtnPBPLK2cXXIqRE6ddjUgo/DBeD0H4dyxfVjEr3zftOilD+8rKqNvLu E4agW+rOTXREJshkwCIxP47m3uB8tW6VLoBTPwCrwQ0DJSNPKyhVZBwp4sb/8fvzYbn1lETAymBj VuVEdpBwSl/vHYQPESgTlPnizcpC7kwZY+4uz9JmXMcQLpVJWcxUk3CNmfXbf9rWa/5SOFNtG0KA d5bblOplhMEoriHYHxpotD2bs9VIA9T7/FRgO1AUKlkaBrg6kzoCpL6LLsAsK5BSUU6XqkLCRgcp /tF3cVsOnpEWfaiVHafM8BL4qGx1vgNNu/R75xKwIO836Up2RPI0icmzB8+3GbYlspETlZgKkzp2 4o4OHqYo4g24DlEn7WRK4vseEXApmpqUG6N1pc6QIvwW3qfnVarpxmcl/ug5GJ/RruOA6pbN7wMD c//8pELZLgOQA4XNlcgsxedbk1vyzv42pqkLmhvNy3ewdc044yGahVxX4ey7f3oCOaeaBOGvMx2p KeQAzOjjdbyDg9s2CXQUvBJAZZj2YI2eQvl2dmrjZmkbi6qCRP6tEF4Z4bhdNubXLTuQMVkkrsR/ vYiNhp2JdKwhFYFKZldJsWauT3jYqlnXqR+U/7Iy3DGyjc9kNFhKOJkGi5BhR9kVgP6IQw4PpqR5 0J351kofxhqnSrsz2EpJLecnQLrB8dcDXKN5M9XwR2TyEmIeIv9UkYvbD2uaWVnVk4kCcljUbKwU C1qyaxMY+0UO5Ni02Ia21+nSyqxATo7UGQZKxuAlMsPI5WaaEnzakoGk7gqT/hcpz9LD39qlGHNN V8q+a0v7ItykKTHWSsjJs3StN2u9tzTT8kJmDB+opUnv5qjq9S4PmIRIzBDCFjmacUg6nKrIV6iW Fql+RgeyhWnx7NjeuvIwWIaMBxchnoOyOV+0Nf8oVYI1N0WhOjkeWiWIZxCxvxwSOPx6clMfUPBu +bsfL/Jf7A6rJD/IrELU63Y5+oCAl7m+q5y0gysG4hhiQJ6F2jlm/MBKyGCGVwAZFX3u6wSb+2QC KMj/h1DjeRKFPdrBYaBkQW8OSksYrqLsgaUmw8B6pZD+KQSfuizFDkZeqUC12ucNZOg7rUx+vt6S nAkt2tMEM5bNNxZgFX0CPsC2x18zawh6nbY7hU+4a/vQLyUUGNFAf0xxy+51OS9MF0iud7Lu7Jai tSXPQUCe3ebNIqls99Oc2nbfDy5zEYL+NfvxXVp2FCUgU56WQucTjkc4Q23MLAITntEARy82JvRI yqEwq7ss0RNFviBiIcGwXFfn/agDiq0+jXgzi/ZU4XRJ4IjkLg9b27FHLuuCZQPqDtX9Or8JBQzy 7XBxQCp0cqmsTWVTlPLH1mZf+/FGRbw60RDzHZqGpHIFXdgS86I/hq3HVZpaILp/rJnglk9oM22I KXxKmVlHBi0AnNfuq5b6mWE8IzkmXDOLqmuMdXY7WO00/gN5h/hAhOwGFWFJxAH15rzZY2eEzUKT hep26s2erPg0xYCC887zdBfz8JZX9KOFcmtpWQmKW1VdcvAkXJ93/q3q8UWSTNSiWzI6aFbw0Ryt PMCxinVgWP/vDZSNg6OEj/fj90v8EZ0TiA2MaaxgI7xl2A86VgFdNh2Uqdj/paFSGXx+jONVskmE N2qkjY647kzh/O4w9N1vlAFwh9VQ4gupmrbfAkymIiiaXMgi3A2/FQGjCqkimIQUkE74ec6m3+Tr EbK2SuEj+hjCRS4EAXvtlIAMam3R13gKAc4RLDvfw2ghMSX+cLavuqKIUy4v+LPYJxWsOu1PurvS AKQ80X+DPlFIP2dQZ6MhdEpwBmz/D2CFvhLSZVeXoAk7BlOlT0ANswZqBfItorEJ1hB1F/2EUrdm KzMRymRuYtOMqIZoN/68Z8LDaUfl3z4gBBh8ty1a4X3vIgPgqC8LatWQS2Sa6q22WoT7/WSesBbX kojwD/L/8y8OSeSPIxa9071B72BkiX3vNEjgn+bYYkkY8mK9vIwko4Lk9gMOCnJ8Zy/iGB4n1hn+ EJiQA+fgAn0exUMq1W1APEmZKH048HcPLCJwTVaMfV6/wy+9ejx8f/lYiOR6fkOQPLN5riQwPIo4 vYjJ02FXrtkU3cK89Nrn6+i0X2zjP4EOq5F8kRDVUYweWaXVyA2XQQLqzPSW0fSosO1E+nM6316U tzNkCLMbtfPqEvFo7j2mEIrDdvQCB9z4DdlQvrUVoBQHbx2MHTDg/Lt/wITU2kQY+pYhgVy65jzH JVlNqzSsdq5dsA0mPaGGRPUtTBJv9+DEPqiCXs3bcigg70KSxzfigtdgGqFxbSw3Hvk8dMJxOeIS C8Kx1sWR11U6dLy8lRR1RPN0R2vH58KuvyHC0Eb/kplpfDmloFH2ZI2ZLeQAMHH/iaUD7X0aLWMn LDSI+I/8ZRJwOpjR+cEmqW6WMyVYg/vgbgNAsGFYHW5dxwpzPXoaPKrgLle/1dyLscIIPY7jvovY odlgIphRmkm7AqX9hy7G/C/BsL3DvEzorP1oDGrnWmG8C7ezM2Kka8wMk+V2ccSOgUfOTlWxhHiX Z7xfxAu3febnGW4ytQLkBHZmU85RfoE2NgdCg2eslGcbPJvz0AfR8w1KLAUjkgItrvXvYHGGPjPm 0DbQeQxbe76V/RyrJxpD1/rZV2Ney1DlEoFVs82xp8C5C8EOGO53A3iC59aMXuvTY467pJPz9mQX bBVhY2vJ1p0kvV6icoQfhcX+9qseTvv3+EMNF9amyzxB7rp2q+fugCuFaDj4QIFF/2S36EvTE7C3 7bc45A1oRfpg9CekFAgtFKifY8MOZ0GVd/9aaCoQeo1s7ORm/qdGJR1Wmfn80KvfnTYw5bn0JxX8 NlgT8SvfTWu7ijXI8WorCoNulDLuCDVTi5fP0QwLuOZ4+AedXCb+YPBmpDO4x4yxxmeL8vdOQtCT iEQySktGKXBjl4GGvY+mERb7aThKCqRjGud+tPIETwQcwRpX/24G2T2KlH9ikfdjk6lp6+2qljd3 VmAP7D7rqzrf5vnzIVT8Wp3FMRwCCuavQcdUdsu2C7yncjhxQgUiwmL6dAdMqoaZZQX8YdwDM3iK qOERgsuk0LeniP2FIEY2zkvJs5oyVmksL9K+v3HMjkcT52Z5oC36xkIWUT2e7gq3w0ukwA0Ie3lG FGMj4/IvtI+mn8hu3EWTCTRJKNTij2o8DUJAxzE1PxwVVX9MI0R9AfWeUpOM4waoRSZ1zt8YnKr3 wIX0GtThwwSMyRuJmL3ne1T3rlDfgT2fyNBtuyxbeUgk9w74ATCHFCW9qo8o7SMwYzBzLz+Qjf16 5YCtSO9X9KNfEFSWbdCe3rU/SHeeppHJcIEPI5vM70ONmicnUxtbIXeN9XFHbN+foV9/DIyj4CFZ EMNBk3NVHcxQRpEyk7T9dRu7qRxwHcm8QBvjXAzKzTUmeol235Y+w/TzLoqyuCpdOLBkfUHsutaF XcnBgg5nBF6d4TrO6SCYl9zPpBEAEKbQAvZ/6CfDVlHgEAPHc5m3sKUkOuPkpJhYQ8XvyQH68pkW KrxiFiKKZcnRJ+n33tq0rC9nVe8UnzqL8uWOv2hqS977UMFrOcwOZni7DOfR8AqH+CLDZGXkJ7Fk +m9t20TG3ZCRkzfshCdLYJ4GLtusos9zlsVNUYqvmjJqOMr9Dd2mRYv5ECerykyA46jprZjpwIeq 4BiBexTa3VYRkolU5X04kUeX2A22DjVDw2/yGw/DG5y23SJz4l+NQJ9osu7jFwd7k7s+/xu16NBn ZBUv3H/hCUFpXKqbncK8zNp3mlgRU01bohByUOEv/z1drRi2e4d89yaIuda27k2m0KyIwy3e2nJQ mxvS8xkEvMDr/wgBKDTcqTdNDIfZsT4tEZwSWLyrTVbMav9QifHSTtn+32esB/6f40Lz7TyhggO1 CHULa6DwVJWXYDsgR9Yi1xI4ffIOxT6PjCb7zD/L3FhwJGPdwz10a8VEoj1F4Fj7UKzHB8QEmmGc vyLFtNyeijEcqmP8poTWHFgYI9Uenb3QSWM/QSyWOcFvVPB4c9MfYV+6KZ5bLuDssfseKyaKbDAm +ldh09bKofQVhNeupfjcgNVqoyIl3VCCaG83HvRtgi20xaDQU45UFY36RzE1z+gXPyCsro0oPajF 6G+3OpfcDjWZviORBu2vvrYQEd+cHcGBw+I12f/6UhaxkNZnUVg+OIHFIPUaaAnNcHkYhed9pVHi tFy4nZzhqFdoJyeI3zvhbj2QbiPGw4V5Di8P0fNU1ic6czO6U5YmAuiv5yUP6FI2Yq2mhsaFDD5h jymEvpcEML3pvj4pPCGBSeMozdZH8B58/yhnszfI3t8yruZfe0QsxJRdT5YQLIOKd0g/gwHFwppi 45mBi0F0Vxve/9jOZP/hmipsktbG0suRhohruIuHdQbjgJphu+by3l24hVRcdSj+YhebrlrNqPu3 erjkbal+tF7IxDLxkE8nFDJXIl6Xs/lOFNM32BjzZLnC5vTxFtcFUI/CACQNhQXE5WYCDod0uGAN iUadOy1/zaVh5Jiffxb//QbpaYxvZV/M/g9cka/Wm6/9zw6Twxs+g6NamrhNSPEb/D3UAL3d5nd/ ugp9vDQwH7MYuN8FJfw5Q9HixBt6f4d5yooqAEsE5TOLpS7h/I6R+3KJvHX88RK1RIUzrr3lHKri vEo3livO2Ub0d719HeIF1e7u15ovdgGP9g97/2LcGuTPuTF98fZ4mU7edC4pN2ij6bdIrL97Zo0z NQx61cZ5B8jdn6+JUpKyTx0HdV4htmlW7jOgfb3+nedYu5BqyqEBZ61yGWJpkmPnBeUcjFbJy8lz kZQwPpScZNuWJWqzcB7OooBL1az1g24araulpWrrQWHvKFiVBRbYp6mhTltcYGuF+I0UaVV8mO+c wakclT4mHJWCf7WkO+5tvGKiqgun8br7UUlYVCgmfwM6IDxFxAkOZQakoPVjOp/8ccXYLUnWfomO DgECNBd+b3ZDpnhdj6jH8nFIwMcwYlptv9GNDxr7FzoB0VJCPnxaLHymSlfDEWMjdYjfZ+hLcODq G1c8DzbznIcUN5BTXK4C/F+gHWYuMzxIbO7lR1q5GD2KMnxLx3q4/6lbNmdCx9OVgDF9sPiCPXU5 HSgbgAMOEUzdHB1xoR1OokynWp49fc2wIeN+wrsqqkjCXsC44EgbYNW+PAeWzS/p4LHF3+hEsznE WXUze7SdEhakJlhg/85b9hVGu+Trle/8qrwaBrpU9ue+80hF3lG5pY9/RJGt+xbjk5iro7av9CaK rjnkcZrUlbdKz7WFrNKhuu1MFn91iV6zzrBmN0nEsfSkpJ/gufrX/CLiVHGy80CIx1sf1WaKFUex kU2A9YX+UJOr4odCACkoGCqRpMYKbhLd6OmzAL42sQyF4PATlpztNDAS7cLLDqIfxFEL2u7JsYyV F5KRaRjX1nOGwnnZZaDt4VXyTKUPL1aLJJz61awjmXhbhYG+1/sVLgshZlf+IGBZpOXFXaOl3Dg+ KJCwpdY2wa4sqlRc3UX/QMWRyS9h+1y/curgbdaLHS6SkeobVfVIjzPpH5hGkMsCIN3hAQeGHnsY aVHdA7oQFHHSQMZPYEp7RfRVkS5JLtu0egfw/xQOgTq5lUFK37NntIW+fOVTOFXycDL1/SLXzY5I hh5Vu8DgdXgktMaRS9BCucfYaOCg3L6teNdK6y7E9a36Y+jRdVmxnnpHbqBe1QqmX+ZN+a7RZip+ IGwu3vDQjdt691i1ZCVO9m0RqGltbNqRDIo3mL/Lfr/ndhToDGNjUv+hS6C2dbKHmtVjexoT2K7Y FnCm8YcYqTL6cAVI92FjCFugjb5CmhZqJKnfxVJ0wv15GmPK6QMoWSEbwUrymJ5OT8YwyijoVa6D Ewthohfuz1nf0s02GRmK6cKJiWN/6Nqi+mopbPWyMAtf4KufpeD7Yp4kiTkDsFkWW56XgCM3vEco WwsirPNBbynmc0TajkDfAWWpJGGe+7nv4zVvVirfBq9MbYDrh6sEQKbCjnsCOo/33dJyruDgTua/ Q10rDDjCZeEmv8QV+x9MjwmTuZsGenlUw8SMGaYQK4s1Hvv6g4N9jr+Vp8+1ccCRLe0ot1xGVKsu o8enwRT/VZY/SgVSK7GSELwwCyETp/dCxXEwwPoTuhm0skCrEvbk+Ibzrure7TqmA80pVntZp+iO Ge2TzJs2QCr1omJF38E6ts1BUdWAZapi2GxzSL66nBhJimtvYykzaZYLN5iOZi6eGT9g+YGLDlw1 SetL+mxFV9M1LjgVI2g2PgbKuimsNlSa/yiRE5eL4SlbBdcboBOVI3OvXFL/aN9AQBT8441uHATE pKtf1NM5CJVZzasL95780Wr0VrKUaHIkbTr0jQ7HHxjhLMgOK03QoALEZfDvyznuFC7et8tbG3Qz RGFJMUtuO+XLuHv9xnYwr1Lv4Dpsm5a94YDMMAPkS1si6+IIna16O+16YybQk8HtdyLzC3SVVEou itDFFC+puQ385oc04Bh5csgvMZrKDg6Y7yy8ymyzONA/WbAb0ECul9xIl5VAbFoZv18yJIMrHWVG MtxW/4LlHGoCi9rc9/YXbI6U5lMqNi8DWgbBBzSyVublgA4lFn4fjx30DHPOw8PlrMNYCoLMEVIV V15y9lXVe9tzLHj7OoBlRNjTgNxv0KBMARjc5OlPqa7M3bQVdPqpklkyn4CexgUEKD241ZKfgkqW LPVJ8igf0gHCBuSDMYDt43SdM7QGvsjig+IFfjsCEAuCGR1chvoxEO5ktq1sUkoWGtLPgmxBoFKG AiC4fdch8tz/C1hKh9fRnPwh5bUUxA2ieGqSNPuZDsO22/2rdk85vS/tgXZdonilv+iwJbyGToUy BmcMRPDE/qum3xnXi93xDG1I7uQUB18HhtXxeUo4Mh2GcrBb+1J0dM37nofeevUsbfnsH17e6112 QhptmcJpxhnMozQKPFLOEl55l3NlaHba+GNm2PEug12JWH9jIfCspVxFlJ/uapDasPtUWZur6BeU CkH7QvPDpPgQV4Uy1uOC+aRxNrmyhxr0cwFiy/vbPC14LPVOwjqo4xj4U5qQfWEaULQ9yaKkrWK1 1JRurYban3j2SlCtkchBYzhjYkuI2hcMpI3QQVet6sh9r5yunSFxJ0Cr292wgmuYZvmzSILrcixV 9+EZToXRWeyv/+ZGmGS1hz/GC0/0qCwnMitzq5Ef0d1BTgkUrrkIEyuimZCNjLfjLZiWy4OycuaB zc1qpH3TGVJFBDlgMSAegFvj+zDRP3KfH/YYqramiraY9xRya6hBZNHJ9QTj4JDSIXWyUNm8W5Vm KkiyR7TpCBtDvVa3mcQit+Hkcwd+U6pXkZdSgYkUIJfv0WIfuHx1jaifjcuFkA+kuDIVhOS8TTzP sfUPl17Px8sFxiMsDQZj2Or0izcl5n9yXbmvPDfsTiyPxFt+6wxRAMgsGqWRa1wO2l454nQ5cJgJ 2nIFrIaaEB9ZaY8VAfzwzlXu+TW2IQX6IpwlQjYcx5hRDFwd8ORGzx97SXx23/pYdwb8bDOblKHO VSp4sx5xNDR9Pv5tcoevQg3eiGf2W6E9hctAzaVhQOKeLvnvwaqZxdp5B4cn02GgYtAIMu8UuC8z fRxZzWk52GrCz5CC0F2rEDIpxa4Fr0cGbNilKSpL+t6B++3JYJMsS7JY01YOGe8HJVtP8ZURj4zo kicdAu2AuA9+gVN31DFkyZarQc7I0EtZlB7SQvfaAUfAurFCG1Um8lm4SUzXhBSnWk7f2r7khBke 6RWurznUfhoafngHpx6CFUAR/3aLyc3K2C4qGe0YF2P+z2MJVjLaQloZPuxq+kMl4v8Ht2WJPUxb KQ5wFCNrpzgEZ6XsDoe2dlIWJ9j10jEI8FiHzjhCsVmxB9XUnmec46Lj2Eas2sst+QzyG8OAWnDG s0tl5gZc5KQJxQmMqG1JCZaSjY8oMZc1GjjLhFvxYIbGwYcTxV1F62VWtMok/9NDhxn7/iTW/T5y VPECwRobu/EEM5qoz8pWDVcsjIGXQ1QcEKlZ2jmz/e424BGNf49rWhDFDbi0nN5e772fnOgZfg5n MDtJmTzrIMC1TWlfugBaeHZ6t0ZK7npyhTugo3tAIQCcXqJ2NeD2MDUGFM0FOVsD3Y4pwfg+eQLE JXAU0i6ii9v3BJhlokJ33OHQ+y4ZNoAmMjeRpPRhi4fp9gaSvuNIOkMJU1C8u2VWLLejf/Xowl1R jKyNAJHDIqxhS4qBFtI84zE3wutJHUb5tb6wbHpSWTxH91oimj6Mb5+3QPDLDSOET74cQ4x56kRL 6w2pGdgsnjV9+QU1t2pNk4GVGIE6+F6BIcW5umhdG5/SakiX6sG11g5/KjfZxfR4FGmQZHR9WorG wvABs868D9uhyR0DKHJN4zH+p0aEtJMNR19t0ulCbKqLXwiBIQo9qu2bSPe1o3ej8zIAoprJX56+ xqhp/I1mlf5jDPv4/aoIurax2T4hqK2ahcQ9jwwTkRKiHGsf+m2q3/E2dlOngArFFVtWwFPsfOQM j+LUiP574mrL2XbC+3QR3TSC55QPRP2KanZIjC8BCjViwRw6oFS9UtXz/fm28zEkl/NGUlvnTQb2 4Vj9iu+2Fhd9SjYmvQV8uxFeHNyBJg7m5UzS8xrzF+puNzWGm5VHCeOn+HK9X79cuX8h3XVl+1st f9zjmw3mMtbkmvqWtwWFMaecFxpTZyxOf28nqmTOpJp53fvzWBrRq2qDygrJYafv3XAgoYovdF7L ffbXoPBuE0U1g1C/e+UXaczdNAAe7gZLphRwl7O2Z4iCSZ0dsLEiVCyVeumJTMRPWyqGmNDMv7+c lfaPBs0NADLHxmkbr9OgavPNHnwSBH3E4d636azmxhqF8vV2lz7kmZhoDm8obDk2ZGOhUS1jQY77 A8fPzUBsRwI632trz6WWnCVlKLx4ICd2uDjwpw1aIjwRCv6nNFKeX6LdNEftmaU5GD3w3Avmzsy7 xN5Mj7Y5+ysPmtOqPbKTJhfy5O/FPHP8KbyTFO8PzD9v2RVo4By3vm6hIuIrqaJTAtWqRORGDMRN AKbuqlQ6As+py1SEEMbM0LakpDfaA3a3TRrCce32a99esm+bbaHeC9JpSX0t+RQV6AS3LUord2Z2 3sgiNb7tR29o/25VBmGnYNpwmHMpfCM3lwKJ7/8vpHtUtRnKPflc/EbYWQYraKi1PUI9ncXGgtaL zAYA6Rh3AtzjN0LOR9GEVAbVKo5DEPqqDWfAyxfa6DAYd6ZSaCu09KaXNqgiwFKf+O1OGAtrwKxu zIMQ8BLFsE4J9VvL4OLkMT11LFrodPMI/JJ1BdrEbE1i7758jqR38ZZMsPiQDDV+B64HTivh0ojW 5wKD9GFB3vs/7PEVvYipytdCaTPBCTCLFR0QTiOal3BFyoqdwqvy0rig0GiAP+t1MJdoYXIK04Rm jFjVrarwPfRzUq90gW9jPhiyBL1ZMDJ26GbleIQX8751kp8AyQk4eHaGjC8angTHByIvsI37JmKp 2cKVvZCvGsXw5u0Lt/MugGsgCJOqGRI56tVm5S5BIkaGSG31kDr1AvtUn6I24psm5QZZATuVlTrU vci4245spZ7WDaT3v265hfFH6mljzoFqWO3fiH7R3ZZYhheElebWz9SMrtSTDqxP3ErxMqqXoYhX e96246XHx3hZYttfsmdfwJb9m7YE6fynJnFQYKSrC9w8sHAhODuR0ZRyGUuxQa5hSE2NoY2M8H8I lUb/NBaPJCUiCavHnh+EMDQd9yyN0V805oGlf8IWb+YvuFQybGjFpFZdvT62p+p0h0XAt7zPlUf8 qJCwzO6QKjBvbl7ryqqGQxTCEqNwQ0jVg/xHoUMHmj6CbsmaplBjdRK1LVMLypQw0c1PCF1wkMyS 4susDLGxrp9+S679mvYwJrz39JlvhwvpK3buT9kf3SCdiXtHemEPytNsYFtrcl6TLumbTIW/mTTC vjQJkSXuFNO5cSbf46Jh87IPFCbJzuBF8VBZeUpDZkA6XBLMH+68p0S6UMFgIMxIZ/alUCWLTfIl UGL1r4R85ZV5fqkWCQcSbcJYv1urqHuy2J+lAGUsBVWcEZhgmDvl1GhmWdWvmCjyW30+zQ8w2jQY YwoCtZhFtV9sLanHqs50l+q8x4wfaN/VXVA3VTF4r42qBzOuAm+OQo9FsrJvHbl5CwYdanaAgkgV l6wB8zSWlaYZdT6QsR92GzJYjQEDaYD7KUxl9rDGFIhNRaxeTUhU1mG7FsRDifuK41dvcy92XUkP P+SeJpIASJaOPM8SLKS/EHAjAg86MyYcVQ2gy3YSUsjm3anqwi7uRtDZTVi17nZGP8R4FupMBPNs MwfhHMXBlUmyYEUV1UcS3WJQbi3nQWYbXSYxda3HmJ7QCkKSMoTW+goO4jQLDcLLFTOT/CbiAmrf O6cffky8fdM/E7oxBzjoFnEMuQS/fYm20kzLZBdlE8Rm/q0YkCxGYHmU3QKknzEyO9QUyx98AIja EXRIT4wcvH4dVB22aNUeLRb0/0AIIzMdq6LRuXqAl5ROzCCgdUMNgFOXveiKn2nIwynQ6+Otd+SY XPG+lA4RAeCG+rGKnbRv0/zC9D/GpYiFOh4iSEUXfwbHKkJKxWLS/sU4b9G4TBTDpfmTlTgxp1vq hkhrAHwyVAq/M1/0g5f2tR7TG0OlAmKWYV1I4nJAXsYYlTDUSdGNKS/9NwT7RYEki5Lh35Ln0OBs jIKSNfIRaoojAoG4I+y4F4Wj8PRWYC0PU28grn0f27F3zevUmBeeHqi62h4rj6K1TkBWkssuCw7x QKxovcefv0s4YrIJutzsoiPRlWA0D/Mz4OHSRXZDRkL5QBfizRJc2C3nLhzvZhVcf4OLjWQPkcPS 7+avaZvhrgW9QhgrUEcRKFwIA1+ettKzJ40r03Rb4EQeyK0G0HC4vsvkeRqxaddZ45116kjZ9Ak1 J76kWpYmdj3pS4rtau+/pjREd60mJ6DWx2dyylbC+tBjSngylziWMZf/QF1A9DcrTVI+YeWse8hX vdzQoK8nAzIw1Ziz2Q7CXoVmDXxlLpLmDDuoUwzK9dR5iBKGPrDM109jVIKd61WnTMgH9RB8eUKT fBDtlWAq75NEVdZM0aKHGXc022jruATJlmNxj28mRGUddU0VyzTyHpczumIYKBegxKse8VAqrCKq te+ft4T/Y9+Fct0l52nhwaA7URGR1AAfFz6pw5oNjS0Kpuj2DBsObJX78ZeFIuAT0sRWAUDi5lHn yqNeoMFtJQm/gTGUM0h3l1P4MbmcQLyW25kdRbySX7FYLrETCslUlU6O+3M8kJ0bWimqfIjoR8wU xSdFHluphNWF+T/Iy4itBcrULBAbUI/FBJR5q9Gbsvua7HMQqD0KPIlg+aQmiRYqR4U8TdfFFOzc F/KK1xuWEn+3e2+OIQei9QeIuYYf/WNpMrDKnSkKo7suR9JRqwfvzjrUd/v2p2IfLrZElMaJED16 ZoqF3y0VWsAOPL+b4JGewO6CH7qzFI5FAyEhKdoV6FQrZMHUeE5TeEVn7tWXTRCCSK6Y8sIZlzUq kjxkgXgpNbAGjZB63qEdrVOMltV77qWzsmXJHCC49ntxDZqowa+ExVBysYQWNI6fCHG3XBoPRT1i GKTrtRqOa3c6/T+LG7d/WWTDlTH7xKQ/m97oPduiddDT5I5+4RnObPE7yNHJmQy5SwZW/eBDZWkv WxVh8+hr450HphsVtpNwAKuWreCUdtA0n+zgns9SRKPEgbSfQiYMvCByiSRU1xhWZLn9TZBa9hab cSb5KsfG0xT/Q8gblMHP1f3r48LoHU1Ly5YJ8tLARaQ3f+4VnHDXHSKLiLD5gwgNFWm7r6RNNbPk 4IsZLAasbRVW6uQvvmK6DvFXyFylQHc1uLThN4pAkqu3xZZasLR11/jGul9xPObVDeu2xGOuHxPj V0DtGjXHZIp60g9xXFynAyarHkZYtWqlVBHW+wgLADIH8yplxiVZtet5ljQvpXJousAtiI8vgiEE BFD3Y/m9tspfluRDTKPWr52+1ijPG0e2lJzKZK2cdV6b9+Nt1u8fKH2YYqdoMJkJtvoJPXxYsVOt bd50608fqAzFjim2ScgllN/O6HQvXOP4MJoJ2/HGhMk0k+9Zo+9YYJ78hUYMKPsAYwcN4OkPUDJv fy9fN/tnAEmFc3I0brYxfLuRzHqGW7ZNQ0VXVjipZDuRyylcJ8tSPiid/m9D6W55isIPYMZ80HzG WmyNbNX4QFQLpQy7VvpijgBJDzRhyoSa8FsFd0tS+AUZ7LdX0fwV/E/XrkR0vs4Lhox+yro/Xtk+ ofte+hZIbBOGmlfe9b/bCLPyKKyz1O1e4z7Nk9VvRw2cXZY8Q39WCzFLqpJCwybN3yflsOxbCqm0 dLsHbmPYJfp1hbz/dze4kadvtC8oGOdrD73Au3T1CVNGYa4v3wql5OhwILSdNXf98kAfSJln8wZF VbvJmRszfWUWsHmnTIlCThOe05SWHuHTUyoAT9h3NNMx++IZgizEe1KujIvQnzt0f3+HfpPCAe/0 yoZSvmzyvkAdTCKYVFoPRXB5UaJ6OVeXGVGs1j6xHjlqn+00AV/LNmjRl2EKdk7uJgMmKNcBCVmI t8sMlW8kO4VN95hjPHAs4L7Qdgaj5QBqHPXc3E523P3mFG+jCyuUhdUhBiRNxnk2lHVFb2H2+E9i RjvtDoTKZWdC6/87yBsuz6KGZ739ZRZ1UmFAegWfNaW2S1p6l9A9ndwErpt9i517SyjP3GfHYi6T I0kiWi2TFU27vw8Dcx+bQk5NpDs2tyw7jOTFmy+YnIETG9WkyYZhCyfQ6e7j3K6jl6qv0C8CetTL y0jHYpOxl98gGXCAq6ulkZ4RsGJay37BZPgtszAu2aRr+y9t5qph7heXQYSqySYmQnMjDMrxHitj puBviXVx7unfGeGtk9DKQevPPXnCJ9oyG6upAJXAux80DgwmU2gj9/uZvCXciULNgP8HpuoAnsZw WZFMvvAUHE8lB7pCnqKdp2SsfRRjOWdcDs2X4moqq9trTc2g8yGot0yVOYSixgSoCq2d1Q/VGSV5 0XAtB4A4OYyx2ovr9Qg804h1foguYMcW6YFglXcxXTm0SfAnXXaSvaQwqiDiUZW7eX+IriHYilYv 2tHeTki/sC/Kk7Bxzv3YsKLbITdmjYfrj0w4BMA14SH1jNxW6knGCvDiJPj7y8VX9IIHVX7qN4KI f8d2KIsGrPeIYdrq01jzVUE41e7K+tFFRMX9YzYvuyW4jqKt8c2cGGDs9YhUbFEstKzzCowDll1m Lc9pMqzNq42rNX031M4Tq3hE2TNW9P4UfaicrNLjeMYofJK1afIjE+8JISUoye/voURBy/1/UXtA Csedygb+0/1Bh10DHHuqJE+cr1hWFWtCau/m2TykPEBc1/8+++FY4yeJJeGXZTSIIN6XIVP6NNB8 djd/eF2SzBItq0S3lDUzR5EAUd5rx6PBKSAKuWSCy9/I0gRU1FtzgdG8R1gZaE0aX/xsQcANbGvV xpF8iwPTYm+FUbd+aXLToOx5by+VNX7pzl2QKFmeslSvVHDWLR9cqBA1B+Lkcz04wczOsbkOnl4a vQtVzSSm5R/fBtFQ/3QWDZJ+wraSBSJVMTAA4SVkC/tmfsnLBuAAiThal/RXP8Sb9iq1OTTs+5bi NUHx4maNHbt+UdYp/I9qHj361mNgi7JOJgM3RrZ8EY8u9oAFFvmi+WxMjkhlP7q/WeVmHy/5Ybrc P9NB0F73almAJ8C2mA4WYcjZHOOkcMvmngLZECtUDVyw9ZAsyQz/tIu6Zb4Ma2LfNTWU470+j0cl tXMtbhUi4CWXRrh5JYWIwIq9W4OXk2NQZzmCETc0Ma+xfw89DuvazbKWyIZvWq3sw6XAtaaqPNBV HRjSWuO54ZurABmEBv3D35Nq8IX7lcWazyLB8J41O3dWpNf5a1MGq5Z+74hYpTmBYgqHzck4TdJ1 TbXQQqALkvBbpdEUYjRwkUd8N4tm5UxUt9MwaNDEG/f++2c+F8rjEEjMWwbNS9HZphXt0tIGqKzO tDekfZbqxm5EuETKi01kADVmmsZV/HCipKd8fhCYkKStjOmwzNKnSlQgQsJolbgzAypWvBft8jlc cRwzPN95loDetUFmi+rOp5BijH1oJog9XSPbaVz3WNz3ARjvZ3Dg5iq7sKQpFpYuAPGAh9uVDnHG 484ggFezgHT1aFOBmSxnmBFtqbPkz8VZ4MermYE1Vo5vDQyCNH/OsGLUW1UiMSsrZ9bD3wSIupWa 8DKHjiKwGpU6U4ChRiTxhVqtwwh2FJLAjWBwM3TmFH9EFpLfFF4KXV2039iFRNxhJAL0WK5HY4aD 1zwSNZatR8zGatvyBLP9XZLO+I7oY0AvSWI1qAbqsiYuFafkNpL8wkscN5vMDdnVsSJCpmosfSBK gN/9Shx8jLSQad059pwsz6TDkCqKmg1Ag2o4RRn71WxavcKfDs6KjWL6I1RI3oCba7fCUf+bQyEt xJdUANmK+HxsW38p7yM0E/bnwH79ZiDt1es6PhMe6k7DGo89Rvf8d86+7lbckvfdxg4Sh0Tuks6j 4s12lPkInpJZsGkTPUezT5EXVwIjybOJiKESi5zsA1MmAI+OezfS6iIQJLx208Lb/uRGxjTLfWu7 HN4Ued8l4kXtYpiZBETy/dABf/+DTv5CiFFL+w1H2HRbYlfQ5nPU2bRwXlaFzHYCnGnlxYHxQFCv f/qrB5iI8fXUQNmMI4VS9EMqFHU614BvHoLZs3LiF5q1II3CM42KZUPIrwnxXR2rggwAx+Av+9tw DXF/DCxMES0EmMMIoPbwhTAm2PQozDuqc2MvFBROae8HWgm46E/rrNtazAwMjGMsIwzQfuly6OC/ HzsGaITZpGfFS+ug/d7J7M4Rt65F4nlfQqTzTlIA4juao/InQwIuYg4Wexy0zEmvSGUgv6SVFP+x k0xhgqPUL2vWKsmK6LSKA+wJOAKid6ZBfP16vN6rp4IHY7QpkZrcAWezheCJuaBIN3zssjP0A3yX U850BCbo8xXo5jEZzGjW1QqThSyJ2EoEv0jvFuNqsklKDRQSTMjtFaymIjOeXzwV53HzWUgfhFCi jzno19ke6AHMFD++AsYcr+ICn6MZ7HXabEhA4hMMIaPUTvOujyaUwJIW1a2BrjXp+jiuaBjf8jNT s4SQCmC89F1o78jZ4XdnxNQj211wHk6SxrRv0nhiDLvcFpqiIi7wC5gV20k9yCUy7xn+bIcOg1Q+ /b/l8cqbCj0dJ0oSYTaAGfAPArgh6hks76ERux2ByJOtjpvEB9h+MOXqRD2GeJQY8LRxkPFgLMVc BBNLzmJ1AAvI1OJvQVlgUyWGMy0/FyNvaTAMe0tuQ7Fi4Bwff1jI+CwP1z5KKs/ndatf46v2wL70 87EkfNBcJGSvwyQMKpQDi3a4VnD+/N0fz8J/wzX8yNxEL/6/loWkcfugv8DJQwhbcjrv4F/6Bx5A TsLKgM7sF1Y6tZLgCnbztFUuM0+KR3quzYAOuPieknH+LqKB/8utytD19o11WYn9lIvI5cz91wzd R3/BjXDmDE3Is3eoXvHO0cBD7Ts8erar9Q1OTSnx1qql9IxQ267uNRSfrt9KmBWoLkMgDtEE+9po REH/wo/xLMPtkmzN2r6vLEbG9/oR1kpxV09Fy/+yAu+17EQPJ+IbNTptnsXA4mDi44drjtKQUMWn 5dhvTg6EeVjYb+vxKBMgc0g07FhyrDvmD1E9UfEyMtzP1tkwwZIAmJ6JzqoeRGFTDvMhgxxaJsyC WF1gaFtENQRSXjkdRPmv8nppiqT9FJjLzww7Z00/JKb1dXLb3lQLXgCCIgkgid39n3oM9NSdSuxY Qc08dQv5PWdO1XQvgf8jkut7z/fDHaag5oaK4lzdGK2UW6emDcqRXj6wqK0eLXNX6CG3Ef1k0UtG IknJh3RE3SQ1AOuYJYqRQJ0X45KRuzKy4LeGvTiCKo2Sew7soD9oK+AW+p/h8k1lVG6ZBfUdrN3c CVqhmRujbI9F3BOM0h8UxTaLfOvIFSNugc2+zVt3SLUlIXG7oYCNq1gLWWf+Zjp5C0OdpSO4rVXZ fI1iZNOezvt4oCHEfPisidWr15d3sYww6YswgThGNnaABu70v9cci5f2/JdBQyTGi5WPzUUYydUN 0v6tVrsz89cGYJnd3TFRbAcp98jUPJd8KXwpnRW2rLWQom6n12rzjmiMQh5KZxgBKnpe4AWhpXPd uV7bglV2ocfz2LxHKb9WZUwuJm4QBoKSkhsdtFfWEW+t/Lu4XDrhemULBGuW61OBzDvwnmEEzHJQ 6u/2+HEjLZRMMmilzaHoMm6VtL4mxuC4KoJh/Fp8xhVd1mVRQYTEiWLvUq4PX0EAioyyCu1CvfBE m9ga8FFSOEH2KG5a/QZtlZB5K3XENcqXedDorZmf6MdyQoDff5IPppgydzpv92AGQtjbFhCn7S1t pUBBT9OdUviDev6LFUORrIcGMwvNI9LH9FYqMT1/e/K9bfKimoXVP0o5VPC9IyV1MntDAnJXDoc9 LRlfXsaH7J2k581NSekb4GdIcL+10m9ZnFjS5b7EJW8g6wsmkLH93OvxkirvBsR65CRdS2ofWFp5 +YDGEOyBCB3TfZY0+CNlq1IVWtK+KfIcZs2hnnWdBrjye54HW1ugHAxj6Se+GfPWrkSFA6BsbwWl 1hWTk7hQBoxslDBr+5B5vIR6MKH49HYsLK1LSp2MkgrMJ1X4j9Ju1403A34EfkBt+DPq0uj8zMge jda4KEG1DQkUlzRnFdbC2t7V6lFoIvkqqv2LpDQ1H6hyPGHkULSak4BUkCgFgwFNFNGgTlAba8L0 9RLC0VBVPEVjlGgxRyf+CNA/hga5beF5rj45EIe/+8DK555VFDLRfG2vfIKLctVSLrkOOB/D4Grb SItUFHy+tATlBHfKVRRtZwHphHhIoCTdk53LpwHQxiWDIpRTtSeDa8VxwvTXSdZX0U/EY0B2BIWu cyQJ/MrxYy9zueOhEe5w85JIhfKE+CATFsMNxMiifxRi6VRoDyrIyi0k1YE/Ut9N+nsk0sjgtP2M 9BT4zjAY1dDgq1o1AMoo71LS5HXuizEZlGXIKTuzRPXD08zy/LvqYu1WXF4sdWyP/Pc0ZPaN1Gmh uVMcVB7cr+QmzF0ai7o5sUGnO1IVCBh+z9leEwyalfduwhjq0R7MbX7vGd1H0J0G27dTtpTtaGh9 nsfOs3RrEfByh/E5j2DcEY32Wm5rr7QR80vFFH6EYPSClufOWRQHg6eRn+c0ZzUBImeR1K4I7TyT K3llAIjY1v4mtKuslp4MKeCKLWITBMdN7vAZwjaACFmamkUjI+g2iz/3wWgI8ZYhx225Qw6QRuSf 5B8e+nPueNotTbknlmDoqvSsu0+wKvN67mrFOECDyXLU+wCodgJ5vp2YTGENwEiiHQEQLzUlb+/t zOknvQzQftR+jfRhNuDXei9gTru0ExsZpHhF6tzyOHBWEa7CALXsUtMshVZq/euOnHWq0ErM5agM y1nR1LHjyu2hVhkdAPdjfJQjAJHtFY3BoJVfRwcr8gv1bxXAz5IzJI5h3QY1G2wfzoMgZWHfN+H7 difB1J299R/lditsnyrA1LMFnXD5aaXjesyvJYXF1gGD7+8TwDDaAHuBDXEKzcdQ+V3nfWFhNtPM fWhiDx3t9Q/x9aSBRQT5SslLjDrOKWKNN+HOcMDZs4PHTdQ1Bem6zlMVcDe7Oqmg6SYD9+KWwgbT 1QqyxqYMhnygHmWpHLiIHykXqp6ha23YprBeuphCQIEUzU+PpO61ZVmcBQydetTyriRHaz4aoie2 nLvS+kR2SN2zFw6BfkETMULKAeJQkIIVlvYm38Y/XZMYWzXumrkBwJvIa35OzurfT16SwIUQ811P CFm7KhXUt4d/0bGX8nmGrq0TIImwzfB7XKZcv+E1Jfn13Y3c/AiAMcKsXNY9ARGXIgqw4cCsi5mt 9ymnkZ4+S3Q5CK73y8I+kCOR8DLsU+N+aC0GVjXsCWVQDugoYTsP5I+lQ5BSQJbufSJ1l1FUAXIU cFig3saPXr/AgpzNay2AvvJ9rw79cr/Rxd0M8F+VdI7lNOphsbU8OrrPGUMKOvsCJ2K0s9A0mnfU IDEjmd9nZqnUvBx8mBG/umPaIvz9GWDIhakUt5uRn1RHV+DF+m6KdmaEKr0smOtnBj/90VohKmpV 26bjdQUDXllFoCI7qOwOPgX8Zspr3H1CgC2aoognWmWF31/6mCKflhiIzBDbEXYu7qMJGR7Zm9jk qX2SQPpBov4Fv7kteEhaCNdWrd1Xxh8sEs2mEc5CLEpfxXBVLWX0w0C5XH8aKvhwx59/qOMHyzZo +EWlJDy85JSQTAo1fNsuUOJ8emYuMesdjlbLz+HKK7/3rzWmYDethNl5aUV5AOXskTcE8uoG1FMT Mzr30r8ftQYF20DTcv7uOis3eP3nZE2nRHa31Sm5fC/DeGB7luUf+ikddwaK46uHzv0T4o18g8PU 3VLuXQ5v88OaJQgGJzZm4mefFDn2TvAU88rIXBhN7Wp7/I5tJZx/pY9iOXlvjZWt647EIAppXyM9 AbzJ2e/05+zB2oundJBPTZwaGLUO4VWiA1F0sc16CuOsyXND8jETJailTkvJn2HPIwH7+2IzOAq6 iOVLZQs1gfLAHzUxhwh6JfFrdqbVrnRe/XsCgyRIgmEPYGkfky0oO0R4lo6jvELZsFB6vWubtYY7 rRjJv89jYnYVXnKXu84KyX7notfSEPh28HpOf9OWV9Au4GJen8EtKHkHdJKeGjHBscpeE0W4jOjk K3lP1tX35QyIs9Xor4smEGHqm7qz5nPlqNvMSlmooiBLpPvFuoTZIwBlwZ0tcYG3Fa0EYOjlu/ph bvFzT/FCVcpgaBC3L2OVJJiqDy0bpixzopQWNi13CMRj3vVh27PCuXEQnMAKHg5E+w9eZgn93JAU C5hUozn5dqxD7kIuTi91jYoY9f40zmXRhW1Rq0s792A4JwKu4nYUw0SdbQHfgNvpO5Mykh0/wCp4 r38W933t6U3zUzIA2SU+KM58RMjE3dl+5fQuzIDk9DCWUU3diveLoih1w+k+yIswCJ5Bl/BLevDW R0JXR2aCuuT6cl0zb8dEX6GEugOKbfwPrfM8NtYt1PCkDfxN0ZYtNMZNhVh+MEgTZ39g1HEsoAha bV2sClWZH2rUiLdRxr8J+dmU50sjd9RGgYdCS/CUlyBcUbIJ8SxGeX7TxKhwvDP4NSECaphqhHuT /n49erbD/zFjtLGA0NDue5M5ZPwORcblVcry1iSkVqbUXvQbprAsCWq6HA5lyXufnwpTTIqjKhny Su0i4oeqmN4uYR8GmteCsFka7lK6oqWGqcwAtdm6Owo4AYtBdxoDZPOvGCLtIn+edJoRgE1/oyJm 3ENDLoluPBqnZjGXaQaIKgDQQ/dGVdPrQY7rQ47KVKbvtMi5VMZbiOmvz755yAl5cc2bWg9nj8Bg f0/H/ITWu/DTH7a42keLVNn8kGILIYmKY0PQ2EEFqL1wWE3v5dgKNkSW8hn6rYEt2P9zEwynVbQW ftydsi4mXRif0/zVl/CwhEXJosHq7X4eUjnBKJo3nFUJLAkAFpT9oG1ybC2S/F95+5JnObGxcqk+ 1h0GdxxD/1timWYC3i4jvPKJr5oqpU9pTD3Da0dleB5AkfkY7YM6yjyTcbHuPbp2RyiEgd5rNsgk qeRC7DrwrQj6tCJ7TzmuIWZTx4M9Z3kJO1s+RfMClm1yFBj/GUupssY2e9kIDbHLH031d/DvWkN0 g4omiJiW7e2kIVAdZMFS7otZpG35PuGMriGCXVQIbaSEkxMOMn9tix90gNXNxyEeKSC7Pg455bL/ qcVyxAqB58r1PaYEnRytaV8GrtojFlOhoNGZdGUxf9uzyGoVyYNgTRLi+rFtZ6mAm5LHDUt9UbAT PzALlq9fQYSweDK+STa2ogSNHzavv+P728VbCUEo/fl1PciT/etKlzPvp88HiU8JTOlbVgQO/uDF Uuvg/5uN7QZH46SWYpc6VrlRhuepaPJ9/vAPqjBOgvZiKRbkvFF0d3n35NlnMGFb3KqSkQrQopdu sk/L240vEh52PYNgOihrdJuBwdSyk7IY/hkqAaa7dz1w6QixwFxMtKU7MNxFbm8Tu5KJzlnWAms3 rYt+bo4UhPMkBrAXsVJmG4bxVNVQvN4EEZZyTzAt/FgBxsqFDyotzaoR2wTCyzSOVDfTog1yk9Bz t8IyoXgtpXmKM48NSp5j6SW29To5LRHP+cLtqCiIvGY1quuYqkTKWXcLfVrBB7CzcWHZy1obiIBF 1tYBV7tGJ/3RS9Cf+uLkJo/GCy0w+0g7sgnsS4wnOxotdJ6FFgN0OKDOWVFbUvrrliKsJ4Dc2CpK zqzNkFtPkIy3tNrXYiAvSGNoqEBMITTn2uxeuuqCyYkqpHdso5wk5h1XbrycemA/5XAUESlYnH7e l5p7qnyR7yfywmrHnwik5hvjYk0f6IxRYA1VZJulUGGEb+Qjua/90Ju6r6+1dWuYEzXfdNMM1mB9 N6B+Nc5Fq0CGgGVUZEHZxFA3x38XmP7w1XWxSChiDV6GPHlXrIk+QLB3ZfOw4x4ho4Iz00776Moh EWQNDbNoiX8lkkuwLChO4Euh+7AUUMqqgiUfgYz31XNWfYENdwB8392ETlRyNWWJRhKZgn4dbWuY stR5uFL6aWBS6a66SIcOZgM907Vm5tw4m2x6giZIjAMpgJA6yFfKTP5ya9lbsAaC5rXssj590G8f zEqJ9Vc8k2kb7y54SR0iEvLA05dbZrUDhpZyETjbkEAlf1ZG7vJMW/s42JkSw1YYa41OyVpBxyLT qAzWQ3woGrwvlMBdfprG8f15PrRSSL5cy3ThTsbiuEgjqk7HsAB/+uoBPQ9W7gHUZkWCbksMj/m/ IWvoOC/hZepU6/BXAAHgO9+plmdQQiIQsYXDrkppWWgMEIoNj3EZU7k7yweD0I6DngKxJ+sRarxL rYwguEc15ZFJDOvpGw4LpChWlFl+53Qnt1gj2apPQ0unwcTtsWHvlfEIvXaClp0I/GyuDAE4bcG/ blPKx6Ed8nihDjbortyqFkZNAjYmiQPhy8LFcJv3SjUyRGBaIpyRyzwsbKM76dC2ScTXDAfVPGqe yw9UfypQQe6eXjSAZozPS+PUd87wG0z2fJIvMa5DAm4z1vvw5/rzrJdxoCgzdbd0FFk+CFWSQwbC yk5ziv6orA06OEhdsIHOTiF9lTPGJzlHr3e353zwpFjWTZsPm2MTmR6VdKXmLm8IgMhcOdOPkrCV c0TpBig4xdl1hxlM/CBWvdRrug+4nZdOkL3N7o9W/v/ke6giV9hUf4r68YmpDpVfysbd9n09Vyks uBcisnpqq5Hu0dFvRVvnK/pidx0IQNnwdHJeD+Sh/DdJpln8ngIiipVAiRjxns0k1MZnmCr9qXbq si+S1QhD3fOBt3h5kvZLGY4JjBLWxVwl7Uj29F1UBfx4eYTbZdN9MitM5rZ4Rtc4yHiwNFhzhQAW 2SFvef3zX1WTmfjlSxQvAGxmpYJGYaW/RRm1jrwQ3tmW3jq7pExoQKWPb3zuaoiBXcSoRQJfQwXD dP8qxVRTpLI7V0qr0cW3bKoyswvoBf3x31FNjOhN+nALV5kCBQP4aWgCMZvDI43dnp9JvI1/fTSQ Y9Ojsy/ojD3q/HhvfRJGWdqU5gaqFs+49EDMtMBpV/OIKDQOUTirYDRIptbvLi2Xc5TOP80HD3zR PZxEjxnL15mdsEYNP3BO+5hrOIy8SmkshXofm6oX+tFOF5xjsqn6RdQuSGEYkD316ZEOB2BVTD/U uM0mLroXIklNH6IuKASZi1KeA+ALwk6Wijn0qBPVoZw2RRGqj7+ZtYdwQBj/nKSdb+UtSKkAnDIn iA9PCjO9O2KWrqrQLvcVbmQ7BEtNHiwqnm7X4V3ODoL4QB9aK1yi93UfEQjcMB5Bxvwab9eSTQF4 SntZjE/z7I3JYzaq6KWkKtkb/9V2XodjlJBW8i7hWP4Vqp7uZjn7dtfmVpq4cx8J9Al+SkF3lZZQ J+WtfnaqiLrv2OTTqg8mltCAI678268aIfBsOo6tYISnZj5BKBd+px1Gg5Xa8Dmab22TPrje4LV8 RYxCmEgL8qCGUXx7UIuXXTgQt5Dtrm3Oyp22HrJV62hBmu/iN8Imo9nUCDiEIXtKL319+nuLu1fR eZji+Y/riaGTKlTtrX0exwcUp4/gI3C2CaSWFRLOGKEbO2gwSq+VBEr9syOoqY15GU3v4wci1DCn UwK/bgr/a/rf2q9yIZunhrOM6JePkzkRhj/ua966gyT4OJOtIijagO12b0BMK8dWEhGTWOWWeYJ8 5WCIpyD4ONZ0+6igmtqSeHRRtiE+V8L7QOsthRCqUxJ+Y+d4Re3Y4OyjxLbhCzKxQWCPJ84UsWsg CMYmpOsmykE9bIqaNqxrqpNQUKldFKQ+jN5eWMxtuHqZG3aeRlFwoFxwz6xSxv6SrTxrXa6OIexL iyPEvEJ5Ik6QhN3o3ElfPuAKIqdiFIEpUFlwq8qUMrhaMYgOJsrVXmitbjNEzT4TzG0cltPkrZVm foMP0q7fcQt6b38Ym/xGEhqEvblDdHo9WtfvqI8+t21LU0Oazlnrqkn/DVzV1yee7tbrDUkWqMU8 lDgbfOpsBxOAjv/nJuFySScdYWuL4GQrGVff5Elv2Av39ltAVmsZhsVHDarkva8h2fS0R5Jt9xet FM94nrEcJu8cKrRSIL7nh2IYiwLBsEDtJArEkcg4X9KY7F4NpbYHYi+tH/5Bdg2vMJOvpzJJqY/G WFzxQdXF9YRBK2CpIBhtyRDO38nntpdh6z/k3GBKtoL17FfW5gmezYOVjrDatgoJRdYk6HViJZEy kollv0rnHGhvtrjiejoe26aTgKJb5hmTkXc3SpKEm/Hrm8Ogrzt5li54cGPDJ3cNkiaGQuNgNQK/ fromdYzjSvMvnVKSeo8urPQ2/kdBa5yhRhT7ucw6q/5pqJaQUcuJPvysEzBK2gD6lvFBQHbbxkg1 com3K8MB1HwvTmHqIQ93xBjstJQ+j45EStig8jUfV6mlq+NXvlbwH8kXHoRV1vAvoGMSSVV4mZEe 4ZqOeNKaQ0jw3T+VBy6NQarybpQglM87Eu2ZKn6nFKslKDC7I6Qz2J/eyTYiVHlgsi1bIgbb8iQV 78RlUaxBXklFTOfe7ootOWkVftwtJZGfYOPp6bGOJ30ORrt46TQobUHDrlTmWWjJLo+03KCfRTsg xmLHfdwa/fYuQPDLK9A9iaMNBd/4bkF1otZb8ze/D2pPwi9KKa7PnFdsbAIVPSjsIwCu+LDTWy3+ wobkxYYzSyK/uupvf8MMLV9SsKKhYyDdj8NUWONy9EiOY2Jpk1Nty0JLpeS8jqLm8dt2Y6tJRAB/ VDkNn61a/OSHCw6bGcDXQvnV+8NzATanjNHD65wyEx4KXtDuaMqo2TP8hqBaWqeMznuSUg/lQqdt EOoi46fByKog5cxMBJNZ41Yoc8oPJlE/r/4tAadNx6aqXXJo8O2mtO9t/fOn3ft8/qbGCrcqBLo3 fZCBeeXmhclpjPcHKsgsBbSZd0vFX7s4kkrao4uh/iBCCVCuLwzeuvc7UHNkZiOg1FhxjqT/N6Nm 9MR4Atc/1Z4Ag2dw2t8+ZP75x+gU6xhlwRYh46w+Nz+gGVMZ7Du6iQNsF9BhTPrAusAFaih/G8Nw nnbnZn7DGNn01iqxuMtu1xvTUquCGtLRRJqjITJ99FiuTvxA3SZtDdOUYFzhWGLig0yiNh0HafU4 nEDblgL+2A2D93abYSGYJ4F6tu1dZbWYcLLrGNp9Un9ahE12trrlV6Pu7f3ih4P9bJkwkfRkjIVh ceb+df6gVm6RTCxnerKXThA7PVrW5P0g2isx3KWe0O4EHGM8UmrCXmeCiVXTggLCSjCCvulX6ywJ 6dXcyOmRAFtmoS8E8BwI0UNmhPKjLkWKNIrVo6hf1dccoBXgTEaAhmVpH5MvmpqwKmFxac4/m45J WSruYFm8351opkbCOAGTMSlAUbhsC01Y8ISZdhkwPOqELaDzQ4b3LAwgYT6V6EVUfBLxIV95aOVQ Dfd2zVeGR9MT5EqF0QJqTGHgWz9F+aIjhM1l7IW/gVlqWKjYm5GmtAM2FlItJ+MXn4t1Gp5KfLQJ OUxE1qYO7SDdxWRzuzEJ+vmbKmKN4JfuM08RH3soxgSLaiBc7P7B3JGiDsZC2f9rfiPxj6ax55Gc lEf1gKilm8UKSjQR+i4K52grdOG+pkyB9EB9+FT3jlankcMHB8nTWyHngyJe145N9if3W/+RVy1L BPlMh7Ds+PGs9eLmjVTDImGBZdeKwHzMNU4K+4rvX4E3Nu7I9gpmaNLeNpzs3Rfu544H6Hr5ru4p ev1jhKtYLX68Jkb2VdAQa4BzRrkP3jaoo/b7TMW99EPm29DG0EIdyokPWJdDbqiTrcjS+lb/qKs6 5Twm6db68akCfDOC7z9I0/7bCFbgSewjBuyAmZo9+D9ObozMbhKTO8+VZe1U/rMk2Z726i2kIuXu OiWIeRfRvRzW+drYzXGVrrysijiXEs3eWcl+3pMYxGj3RNnh6HqRpGb6LfPPn1eq0R+mSSGOWOfq VoSXhtGY+KFSDwIIv97Q/yFul+Er4qTnKWH6s5BjLjzlYZ7jbXwvrX1FmmI7AQAN+G7CR8Ra+iPq pSNR4d++URyFecZ7v0HZ768whA7pezN4OSlo4N+6xVTiFrjzQJTjnqv+AR3DqwC+AmJ1M5gl7WKq NNScwgQ+4gJlCHnZyZA8tvxpMQ589jy/Fqt5UhiTLY4nSuSHrpjUqzZIdQlU/JGgapEpGHiN8sqY ojVwUcudjLHUR08pEWINNbTAK+cBUvSeB5H0P0wvtldM8uvp30Y9Mi3pJ4FZ9j18x8Wo+KG3a7/1 +M4PXbzHGDA/8ewjFwjojdv3EEuELLyzq5fCc6WkItYzwSCs5Z+lRus9iC6/OeSqKgEqraYype2G dfnYpRo1Nek8nnjPLTxY4RKNgvufdSb1LGDls/DVrVnIF29vQXekn5oTn9AlCECPEnQr8hWEhl1W F+7UvYhfeOiK+00rHTM1uN1vnXNTbmForo1roDqpk2aZWw1oMiOzkfadFUNEHO+6n8wv/Q8vMQKd usSw300WJvVQl5fr+43gyCYKJiQKFaGtPU/BHG5gw5hLvRd74vCCLLc0Zbb17ewQw6AV5v2KqzPa B0sFt1PuAXGwE+Wm5UkKZpdNx19ninn7+ne07SA5MxqfSVpKh0vRPay+4exRYeQTaGnI6SjslaWl FOtOBRbAHVFuH+osqtGvRl7hklLuzCT0zyTkq5bl1P00RAxse6/sdZLXD9MIyjC0kUQ5XlRwPug3 x9gc1GaxmuKGOaQWbeTb7v3brHZwOohHlwoGFGmx3+pyP3cLgC8nNha0OJR32Dy9YNuOpLDQVJOa /x+IE2XKMrja+eaY0tZuNeNWkOO2rrKq1lKL/r9oRgW4P+0Ieub4xIn/Q/G57SgDakWh0qggv34y eiR8WgiC4wgdyIfgBlv3fxycV+//HJRsPaibUljViYp/VgAAZ1k8qXJw6NGMXE1SPfbMsytuFhz2 h2Hpwowy/ERUP5GRC4WH9zHb/DYEL8LWm40OS/VPalID5Zi+D73dnJXlZWE/m2V9GCYL0vycDQ6S 92ogfNGuQBe5eqYxoOQqv/o5j+lMLoW7HRZ5Eyz0sLwV85t9pF8izFObZSTqbCTuF0i3gDY7D/DZ JR3BFxl6sCBdWQeUmo+EKfGcTeN/8FKmYvcJvg4+e52RiBmCqSe0T3VZKZqKpMhNt2AQAvDWKgtE p8rk4DU7Jlpxqq79FtssEpTp7leGCROjZ/Hatlz07sbAv5LYiFsH9MlGQfhDFI+asJFIxuDBY3Ue 4WmrjJDanVtyDwGLgFhPKFf3uFBBpqEi3RN0vKGFS3X79Gmdtw8HPO7ciuNQ+eoyqjgx1/3ASMZI 0L3sSVVasdIzSGz36W0/HHgFBsOJrjSuZGbYgy5W7hOk/ZnwDD6pAqdh5WykXTnwLFDIVad89r7R 24GH1OaHtF/osllwDuatHAjMXLTI8kXL/m0hnDzqSDuHYp0MYQASuqA+JsdtAO7pzv46kebBffhg heKCL3o852mLtUCAUOI+y5izdKwc2DqwgmR/Msrt6msMCkQHeSmr4nFjQFc+vY75yx72EzeeSEnA i+1oye6SjyoLAIbM7fxPIEGG/Q9/2peKIAF4yV96ltp34dtlBCQK/pGlnV1bweP7vP3taJluKb4C noZePmF1oT1UD4RbnR2a1k7jmDq6ICVlSKwrYCKGqLqHoVNx7fvnlJvSdRSLbj90fsfoapGYTgH1 hfZ85JYvpA66sG31Pe/SbVrKJBBwVzxpN7utV53yGMkMpwwsk4ZAkGKUQ41+AYgN7niWctpn2IjY 6TPSV8Nf+CJtV+Y4UieX/s/9fwguxGVa9Ta4VQfd+NXBXx0KvJCHnaezSbKr/0T3ecoOCb0roNBx l6PYmAuP9h1g748blq56pdiG4zmnFA9Gt4MVNUZ33Cbg9gld0IsJBmw2taeLhZC9yN+45bTLEe84 h30DSkJOVZ2b60EtqpaxwcmFFHJ7NfmwCr+35dZO+QvRWyuxQbINRVVyNKgEy4p57o3ei9jEFyx8 82+srvpMN9j4Qu42aolegKI04Mii1BmjqcKWz1APv3UZSg+sV/pyEttGfLtO1R9yfFVbAZ6PxADb TnuicUhzOX45n0SGuJZN9agD56ntXoME7k29pebSS+2amy2mTbzZZTUp32gYkFKSuGQFWt2KBPcH 5qzrM1ulemXGEkxoNUHcGABatzndF5rvCTGJT+R9IfdjlOLnWxs9iAHmUY7Z/V6mXKOqhLeouvtC vTb+Yt4D3F4xoU5r52EBZDklIZI1k06DXY2x7qOApJmVBvsCyrdnBSWFYFT1Qi8PZudC7ONBQvVS iet2P5ToJtjBaCrVngQZa46dVRjhjsoBvYgOZwsxPskrUC23ZnqUHgnNzWooUNSqkm1H4Mv2b+rQ 4W/NacOjTmnI1wB64JUIPmHy9wYhXrG5BcN54FZGxO4bw1uQ6dkNliLkiWAHm8itauULOj584Hxs j4upxHZViw9kWrHrbwi9sYGNmj/m5wDlSmGkEenN56bqqm5g0SqcXndK05jficQFIqu4iIyM6967 fkJf+FmIy2+uJeTseBdPynrb6BHyalN66XFEwaaUPgd4DorlspXp033HcEkxPrV9cv8LYSFQgH+5 3UkzCpN83DuM25VkCMwI5Slazsd2mpLlu6Wg3amSMOnjoUihQmrUt4Hc66pEkmqojWvvehPJ644h HtbVk4cm00jhDNdSC3u2PEjMiNJGVYm3S1thYZHKVo8/k2UIp0zQ7nwg4bSqbfc7x5tVx1y/oscc 3wEGGCWS729WzcR5mu8Ux0BftgiIsuVyXDquDNOLlaOGXN8vrt1SDJIlCcB2mjq4dugHmKFRUpzX VJ3hoJac3ifAnClK6CzEbKSxFzY1dO07L/EvXg1EKhQOEu7lM8MaUGgk5jjBCxLu83bnyvrgY3AB HoZDahdhvDhJHixjPsUhsnpnd9agXL9kHhIN+uXUqNmG6NLAnYas/JqJvXbf1BXC0mQ2Z5DjajQp 1UaGPYjs/UrdJNDUWj1aYVkRbriYweul+fc9J+8plxg4+Qemg1lSBxsMQoSUoX3fEgznZdrRvHpS fEBW48H2ZMre7YgC00drqPZwxzq5vnGtj3tqCHJeVUaplAJ7eF7g7vQkpXnONqrAACYI5bFU2hB5 qGpz5IPt63v/qx3YE6495PWdbdcXEtt0VlymkIG+aZroj/KUeY5qLN2X88zRHc7Vth/NeB9h9pwr d5JofokCk+STUfrZfUxs0NJkEf+xqJ2iFAcMhOg4jmpoZVkq2dIyEsqFJstMyDfsFtJMUyIvsNfa TuiDSslh4Itjy67RFDhjUjzGZuddtwcqwkX0N38QnEjTPJsjkYHgliBIKySYDRhNyq9P2lds7DWj valIt5D/ZgpfH0LR15ccx2YeWjXNEXu4Czpys1Ol1YmFrSdB6eQ5FzmVQMPAnjGSaWFjKw6gkU+j +SzLvd4RU4Jf5Ge7nWs9NJ/SLCsq6zzrzjHNt5cs88VID0eApqkmqFH7giJfqBYGDZV+81GYojXk yzgKqc6uS/fQR+ryvRcxyOTGVZS1ek9eqpwTFxjzirYG7gBohoST+34oGZim0fgZRVZFjfsoQW0Y C0iNPyr3i/3UrOn9spXD2WINS/PDp2v+e+/r09uNmereJWh6/66sdIpveJG6hzWO6udLRynviYTN MK2ZY2od/H6KLxOgb0qVuGRKG6sxDsRZzJjNaAuf77/txpGmYYhb368DTfFSu8jLp9Z2TAurZWVW KN0D7cWh0dCrzowhBtjYJsDfY/A3TparYEFwZco9dGj0KZP6CODJCU5roavJ2yPNbhuLBlCvG2+l en9SY4dkIeZa5tKMOus82YU/FYjmT773lCLJSTVneW1Do25UHjmrOoW8502p7DR5DTsvQl2724ar Y2dF2HkdK0NCGCyFpKkR8bHimNVSgh+zEuNOfeL+AqrnUAqeEBr7jA2pcD/0c2pwekKnKVE3CFwT +toxGCc23KKPRt+KbqKaGOfFciGHOlk825ajQz7FX6hIUaqb4BVlCAuwKQSCoqVdQK82/oiQr+1E gNpxHQNscYA3jQeGdKIG0ZDBFjkSNY8xS8ugP2J2EnNrOuaAFy1m4iJQCzFBqQLVSMaZbOPH/cWU /DsB5TA6INs4Dcan3s1RDHyw2trQcXBNelBgRw6gTD14eLMq6n8t1UJ25YowLzc67SDsNmao956p g9k7X//uNNWGWGn97Nhn5KZUGiM0Y3ZW2YNoQ7Naksni8oNpVaWrwgO7OSQ63mXRT+70rKZFEzRi KtEJHtZruCeZPh1AGjhlVmSCqPrYGY0s3voR1cYHh6qwDe/rMFWLBL8xYuGfaITxnRzuWnczpamV Vz73QeJI5G63XUwu4eca9nwDBZ6ws9v2pZbgnnPBqCgTM9cVILEv7V6fvU/8xbrJklAVuNp0IzT7 FmhOp2JvsLm6Bit0L1533LtPK4FfgJqKWblYciJHm2LmCXDSFXCXK4jME/X4M+mS93+ookOMCdQc 2tcj3ExTHLye+00cCRP6fwcM+KNdWIg4ErSyDvC4D6ZdGmiCD1HRxlKsNKQ703+wVdKm9v57/Cu2 d041GSNyfGhf7OMBisUAT3OupK0xMsotPm/G3y8wDxRMFgSVwQme3HAVzbKsdkzWKh5Tbtl90iQi rrq90VabDrd0w/nhuV67S8tdBEgC7fkhYGtz8yRmmC68XjcTlNOzKvC2GP0SCQt+HlLeRLJ9Yt4c r2E/x7fpJH5VbZDawkKGksZLGRgypMDEkHj74ICZ/MFiMR1CurCFgRwuQDci+TjXIBn/1I3Tx7Mp mXKw3tzvauX1J7l0PfMnGAaiE6OPcMxIWA6FsMIwwnT32pf+oihCrJF9SHE1CDdC9xTgqA419BNJ U0DDvd1fB4kw/G/uiCk8ZM+lV3GEkLOJ89Nn3ItX1n06YQ9r2Tgk1QscxWONjMgnaycS01iBFWqO VTNoJgnK1JVNt27P33TJHbeOI+bZabpDqdwu8q3N4AL85+/lWvH1Ay1X+kD0NFip+wP7p1giCWSw v9jsSDGISkfdQrEG5KL8jZ+0AGkpLe0U9ruPf72Hr5rasX3ZJ7avpy8ql/Oga7sFFjok7WgG1TC/ /ot3sys8h8EWp0DQjlQ+ZVq4iDHJpffxX8FoxwwVF953j/p4Y5lHXWs1V/p846wTSlIbfHkh4L/K ZnIFkovwllXLETVrVYAwL3IhPXP3aBB7hWcME/9sEw7V2Ikfju3EzlwOMYRlusDDlWcEUv7ldrmx 11mvW5kJcLmNkISM44VdoZRvfgT39XzI9IShB49RXPlhomM7m+foiP35onOTfXpFsyR5EmL1OL7A iDeWZMHTYiSIKwXlzmeHVxEow/+VvpBt7QzTXvEV+krxCbkfoqLyj0dxZkpSsHdvXERia1lMkdr8 qygFQO7Eiks8ojakafGWXBF4iaP98XX0xcAIrHYawcWhCeaMBSrO6q2gdusOxvCuEI1Wcl1CA+y2 vofiEk7QyTG2xFT+gNAunAtMQ1ybCrQ7PqIpTIxLNNRgwOSotmS3ep+q6rQ/5GntdZ51WJ5CJhMa Oh/L1bHOHqyWcwRH4cc2OGqUEsGIvOTu5nZCRLR+1FRMgRfu4W3Ry4wuSHm7nWMqdwYnHKtZPO3p rRtUxefpk88drX5E4so6MM57+Ef1hvlMBKgSx8Tatk8JREL5b5oBB4GTA3KhlKUlbnIHRy3yiR59 ppyiw+Ws7u1j+gwA1PrTAlYf7qOvK8tvS3Qx3bzd/q1WMwL+Xljx0GOtdiQejEnMSN2VMPlodyJp ruvbIjayW6hbanQMQ3iI9wMiq5uOPDSGHh6NYmMQezllP4VJ1DVuOYCZATroF/eYIclX0UuFRJ9U R5Y3m9IwrEvSMZCGYnpVxRfhUFZPvJDzP2NyKm0MbMIVwWMu0YaJy/Kv530ihBnG4rNndZD8t+EU CKABNJHSbIJaLZHvFxxt4BYQ9jzd3M2nZZKzkDNJwfWJlbjgUXBf0A8jgbXMUc6H2IOMqKTLscbs eR9EGYqLZ6uviRaVvyLaVT2JXR6CDoamSiZ1GOgWUz6VAET0/AIHpcblbawho3xaWqLAJ6rO0yQN SZPneC4mlk1HRR/lKOVLxNWOwZ6dSlkuAPDIa0VNJ035j84X+4TZYaPYixjVEnSQubmnxIrQUcnP NLYcmw0+O7PpOvHYqBUeeBp56FddA26eGz4dVHllDWI8McQSrND/USrK2xDSYa2ChTh+o6JqUA8L uh2rB1NFhNHJC0ja/6nBxmJ43UXiLHEwtzbIjYe7VueA+KlfvIgFr1ceFyde7NW3opgozNinZ6oA cTcF5cV1Wb2+FU210P+V8eBVmhHkdmqXWO0yemSmNMSpMW7TSO9/WUPaaUA8t4Wgkm4jIkhZcVab FZqW/M3y4izYBKEYiSHDXvR40M9CKhrkHf81VxXAioFS2+KE17Qk8soXq9PN7cCHkkPv9Mz++Q1n 7O0VX09ZLBdTcipa2lNVFYPFxSpTLxn1t3TC553vknbVqaaAoFblzyEs5niwZ0jMCOJemCs7+OwZ fuk8DDxFt+V56O5V8VQ8ol0OMZUxA5Satcapm7fvz3DTw5PYV74kayuoqgt5W/2rv4tsx73adhIN St1Gi/zz2nzkhFZxiyohiPZXXXZb2rhdW76XPtmT+9QOn9lTcyaC370YsHobrzy3tgT2zZzK2tIr DPyLRIa3EEsb+/RCXYYdNAgyOUpfPP+1zkutGaMAY+wgviUxZSEc5JzS67YDpYV8EXpczmfsAeW3 WdzyY2E93oPS0ycWdH0Z9ju20ekWuV0hpKROCDX9S4GRZhnk+6GQNVDDKyr3BOE92ExJvR7SLXnY PKMkVpuVcVv4lUX2QJGb9/x4BL38t0ag5PPxdADRvyXZ5dAhe6UD213Mo8Hx7DPSQstvAtZM7Q52 8fL4opyaZoY8ZSHkuSdoFRHq+GGjwig6Ixn4nkyoQiRltoVos2KXirBrvTy+xGYqHKBycI6pXJ5X n9Yp6+NRcg8sS5cKGSuPi289QYxjeQN2ByK1/0fHV4DkvIzjzXOA7vHzaLX4rSoHntOdPG4tcKDU FIC9C701vJSKXzSo+p5xhpQmSS7KM9s175mSpH43dwwxdxHD5eJJx/KvNvfPSf5EBl0HrNDmoEvb PY3ERXrgR31q/LWigjlI6cLLQa2L41V9zhdjKXubbfmL3vgwVW0DccgbOf9kkK2Z8AkbyDeLmJIV ZNA10IBFWUA3w4lxAnESQuWElTgguBrKAr1d+FIOfVZbigdmbDF8rFW+xttiOMk+jh7VyiAca43s 01oC/2DfpU4poza+ECAsqKfQEXrxmNHsti80VCWcEIzujNter3RFEr2FvLoo4KMN82Skr97Le0fP GHJ7Zfwg6Qetjb/WF6AWp1CSgib1lOuixOM2KjjJS7ULB5KQAYHadW5rUSLmBlCz4u2yiz9Idk96 rCTUNUIDbKLyCVfMt2Ys5TdycT2h3VLRhpMtVSoi9fVKXJK1sgUCQvjf60UlCiCe315ere+KjDRV Aw619zxZpfqkIOYD6YWTrHYy6OCqFMj9/GRBLXpGaFgLQ77/7xRdUDkeejjPtDGD8ksc1Ax+qn/E cxzUK5pGBbEeo44PwtbefmENw+MGJ25F2hTb48KFPGC92tzq5NhHPMnJDe7Z2uYpKg+TAxiEr02w haXr4QTad9Bi+WCc7Iuq4RzOAzx/Y9GKikcB9i/Cpe69EzMyXqn+P4guNYrjbnowAb2jxBm2Hh0L k4DyBlnaMZSou3yYcn4mXo7t0fiVxrPoGbALM4XmQdxNUU+bFcjpXQBP/MICfjVwttIX+4yVBVf3 SsvoOV0ptvafqJotHbBe/eQ4hkPQI7D84te7WMrC3acaffXlzoQzymYHYq4pj7zggFzy5tw7Oxbv xBRfpacgVa8yBXVnwHMl9fmCIaVDXada8NydKCkCDez40pPkBFZXu4eUWfi35knpG+7uC+eTbtrT xs8/GQCxmgRGebllsdbxxmQCFOk/dwPwbQsK2lSnaKB0SZfAjr+0B/VELRLxaStTKWUkqtDPU0HT bJQOYX1zHTEWWKGEkp5RW0kvA/di/nRCq6s9q51oQjk72POX9tYtKQPngy4mHdN/EPDjWiM779B8 8SlzsrScoZQKr16ulWU1y9gnzSDgunEZgLjaSf9nBtoLKqU0eeaywwcQUIg0kicqqDSKoApWGsCm FKifPBR1Eo4Mr+IOXSf+on7U93bC/dY4kFsM9stKpAJg9txhI9mMVna9jjn4RjseF75jasb1AAPf f2cJh+rSsC9U+nR76jPEqEDwllkHrOjxSqS6N7eee8k/Zp8bhVkdzzjXNL5j949APq1waehlpZsd pJXBnlPprxFZgdK8jsg3oopdi6SwO0GxC8FP6YIsrhO6sgPvEJKF3YEk/CLUb1MKqFFrZ/tDMOSi +zu+XjRtW+5+mfbaSDWHhpGq8XCp+vW5JB4QYuoLoah+52TYwE8njRDoFpFVZ08Og9cB4xvoJYGE 9XWVZwW8SpvhKLdf0Br9QqllV2+sOOnFqqOBKp2oIQekdKtZW+SmnQxlbQM7dX/i58yiUCUNAh0r G+WlIXhG3fBFx76ychxJAWPVaA9yKFkCWRSwSZvkrzxI0vjOWa0rgUvinIsKiIBVjoaWsFHU/rRs w60TbLAvi9KpOFz8haWDQAsDqZr46u3ocy9SXpRzOsFvE1LHJ2HB8jsQvAyjBKJx5jKhLB9HOmyH +Yzclwrz3jWGg8SWgf3ztipWQ9Mn3mCI0i7gL3mXaQ8z92UJFEagQxKdSeCXB3AbEUxSpbD/o5JF sNmkhOWbCfQ6tJddL1oPzp1kA5CNcju6N3pTm/n1rMOnLIk5eKX5ofBb96JyQoQBsNa+7er5zBE3 PtyqHCH4PHaTEpnp1Uq4EzrAjs0acjFDUuVWP1p0x/qB/g+assCI6ZKM0hWU59Q9KM1RYTX2BDwa k4xrffZxueAQDZVKM6knnplPJn1kCUYaD6ijlLGaOEFJmAIpjNQ3agulA5o44zth4T1YTR2EWn42 yD5FOEuAsUrytxKufW3/3Zod9QadEzUJAYfexy8cLlrhDtJ7GiJVlBFjx5We8weOe6UTWV7WFgUO 8Zf5QmdcTvCq0nCKTcnbpTvyTbQ+DJGYmk6qeFk/1CS1up8cT3i9GTt+f1lTxq2vTI8UeoLmZX5+ sBWi+ihb2+jWbiVV7ffiZuwrygvshhjwSNWw18tuHWtFy3wR+JR98HTvBkoclaEBSA11/S9QVVDq niBEwzJ7M/NpNy7w4iDUAJVbGeGWgQ2c7HlqSl+PUihr9EHTH0ZWMnz9AdqGEXiRrep/KIu2/hke NO7gNSm+oNcpBcLsg8XBPEN4P9JwnY/CPTA8peitu8Eh2TuTe8Omo21TTwW+VQrN1ZlqsF5YqptP If0RDYqI8hvqHNkvdlzUZ+uy0dtUYF922f0vx/ShxI2JcQ9ZAshTFv4mPGmPO4nDGHEM33pEsTKw 2v/HcqAILXd9N7FbfqLycLT/4hWhNAnUeQ4ZF8mA3kJje+tJwlnmqOJOa/MlOXNBY8zWnr4G8EEo KBOS/NUJZGD0eADd1xj/NLFE//kCISqtS6B0lGAYcoP0a4SSWzqCQznHCZDyi2Lc3LCxVNlTzFnV S0iGzSyJ+HSiBDe/CVwCk636LOuIXU/5XKwABozgMYMg/lZ/3k+3iWzqJ074DZxMre/XA/9SIU/c ftJDG9zgVuKjmlWPlp8tmxVF6tOlvQsyif38lHCiYxj3NnbOWp6n2tnKpZyBaLwraN+vtvjehBN3 fndcfApdT4OAPl5cG/niPYbBMVAPpU0Ej/lXaqAmM00sUZuDSAqQ4f+Y6abk9AKEuk2Yx41vSfij OeI6X/bVHo6EV9IKJ00tiyk/IH68b6cGPMG95BGy3IATETBSaNuRn725LosWxXROn6rBY9na1lzF eahTnxVjS8HyBgY5ivME93hTkx69gDAr7GCCdYRntWqDycsB2Na1wW8ulZMz83iMRYBW7XuKyq0B zX2GUYYk9paJtNCXoRv5uTA8irmPP30s3PzLb4inULdErN0szON5BMDPRSOBe3Fk/XvqueoFSFoa MFrYfdEbXGqR/Ehdmk/D5QGSfx9tEUg7/r8A8OCkS641dKlWEHuQyDdb6xzq77F58Po7Y++1S1C/ QMU/qSZ0WGuiKDvOKs/iC7lLnNMp0SF4w4OHtflV/eDo231or361/lyOp1ZS/1HhpTB3SIjKmv0o 8RhESrYY4o6kXUnpzIC5Vyecna79U0FhDUjGrCJoaVxtnnrpANrNd6peCT9XjIpD9W04gkl2LTDP xWfY9X8WwUmPvGD5smRyXVfIJesxcmO5BTyVObQqetJxgpeB2+1LD6tnhKJbSy/WqILUbEedbOyo hVJHIm0icYJhA/FJQ8nhGSiptUeK5L+5pNh8PxeAGjEUMkfH3jBy6tw6N6YD16hrApYsIoDfNQGo QaganSD5OgOOo9h6/U5rr12xqk5mdGRJz8Urrgg8cq34Y0nXwML835kmIX4uBHc0/5kKNimK0rI1 AczoZzaTdtuEt88fFaajVu028eNe4wKJIPruJWsblhmomhlqP34fFIYXyfCACe1oEAvg15sJDySr not/qTte3xQKtapRdydO9Lf6VECLmRrnij09k/fK49lZuppj9e+HOcOPFKSxTXVdWLt73ajAnrg0 D9eYkbAjrPwQqBV0vLY19CJOuGBq2m8eTe6T9OCJYkN/C8Blu0UZ2PokTrPvG+CIsjl42y+zxjIg QO3Wq/CavS/sUr6AHswzWbO95IRUYt0uxHV2btYtWLMyyjOpAyadJAhq+zsD5DVzgUNxAZVZ4Icp VuFSw/IKN97nmRq4llzCtoVMhzUBUbItewqs/kOTnliLPPqMXyiuIZzSiePjWSjdydpw0aBzeDFc xOtyM4beeit2fKm67D75bNYHtZk9byS13CAkq2IgcM/XqbrDHCVaDoEk08W9fc29Y8ZFf6ET8dg1 al78aUpp9ixZlvV2WjSaAsrykUoLuDyUeOGm/TQ788HUfVRk0eLBYvJascCqJTu55OGbZvcYzZ9W h0fkDdKqpu8e/XotobHu6nsMiSVmLh2yhgiBhvf6i01TdNla+AAKWopvLn3kMAUoXF7PY3jM6xe4 eCfaD+sBpCiP5uMl1iJ74rwun6wgQwLx4Su6OM5Y2D4c81bjCVKbyKp27lmlFF8HCH/H1AyfiQKq /PVnWr00lupLW+Y4MolichfYnL2k099mBdkxaeBknjKlCOn0SM4TSLumbEgfGxeo09TWk24p7IB9 4+h801k4ZTf6dvxW8JV3dHzWSey8wjJzmA4ZdDfwj554RibArHl08orTL30CNx5uoOW0CMDKjFT1 Q8co0OtgurCAycOMYBSzP54+BlBlhcgrL4up6S+bVeRs//88U/LIzA44SuYXhhVbcyKKVlT3T48k Jr05zdH/wZIQsxKCqykxFkvKAMry3KBkE/xOLT2IW0F9gL+H1rvf6MSREwudtIWrL5vQOa2nPg6N kZQNpLZ9io9BRf2QwhCv/vV1O2CYoU4l5n1KnOsSdKpKvSbS92cl5K0jDBqaetzaEaKPKsl9qLCc a8M7zbMlTMR9jEWY76NNwjiNLmNMcVTycQmPwWGaO7ULkMG4CW6XrHzIdNGP/QmNQakLzQ/ZDWWw GZfO7sRcVHW26XaYqbH285F21GtB6eWXmt3O72n9MXmP5IhuXc94ObHKHdh6FhTEZsshb6WLsSgS RQ1NOrp7kJCA8Kt3toeIx0KP4ZM8jQaYi4PDcYAAH2tNMqct7eTDd2W9K6xo8TMA1YC12lAfawgq /YIuEp2CTNlrS6qaw7FE7N9cpEzTzgp9V0sQ6+yZO+Lkr0EdIL7mVdyH44BDCJxjXkaY86SLTPDH QnmkCSijs3ZLE9IJL8ELZI4fYOD1xyABzxh5GGjN8BIU32+nR8A3z31soCSjGq8cuIhCrwpYZNV1 ELIbErjnUEN/EcUJ3cCBFCqwg5AK5Xr+p8+nRmqK3U390r+peIfSC/h4SDEAuESWhrr8be+08zng GehwZgKavtmOQwDXShOrlsEjC67yU5SwP2oW7vscNNkg+x5xP61sZsCumqknctZN9mS6dkUS/KXA 19XohlLIWTXUCvim1mc+zMLe28yY0iaTB0DBnaag3NzcNPSG5SV2LMLwZZX7NJarRVAblgn1wzYs lKBoiFUiajnU1Vgc/PXbvzdfxSr6n+HBzg83zAdeOzxzLiaRtyOVi5CoszPqPT/q/+Jj0bML1S4V 0igwEMHRSwJrkACvWnPpVYjh5aN0ucjag9nFlWaxOcfCQPsU7vRsmRcmIi9m0arfay7q5WGWBJVI YAlLYGzOz7vqiX8LNIqERjOi7A60QfesudCX2sXjCRTqTtv93Un+NSQ7mlVLTqlnlDBRp3v96QEB eEYeyaxmwjz41KPs4IawAIsHW8gjA/lX6maYdlRtQTh6GD7YogNPuMG7Wbb9cA/FuUn48GeWO36C 09joJal/mT3u6EdMW5A5brIWC84Zsy3laE9sj9ltYIY0tUKJStvt6Rj6tHby9lEclIPqRcjuORzh SEBa3mMBhBCU1BRcpo+KKbIH5tRrYV+Nalrj1nE8Gry89d+GBKmUf01QZprcjKSRJLIshudIUIDS /Wc3t5Ww03mz6zDk+nH5xWhasc3Y0j0MkWk50EN+2WwKXckWzR1oS4GVUWXoAE8k9oJGyOACi8aJ 3bMWLqCpwOJ+Ystxg2OTWCdn9mlT58Jqiqrenl4vJ0FvgWvTX8j0DhFgynMmbTrRsrnr55BVNfPQ Td/ak8GcYByqE5xlxAG6r4jAby2fMV0kTdunES1+ND70RQO0fFWaBZ+1y/17mkjx87OqpbOFYlG4 oLavAdQV2Q8KJ7fdMqrFASx2K9Ldw/Hkv/eCsnjbL/s0/LPNR+R6K0+5nRKkASceA/nuPXiqTv7u P/RHG0A0FpXDb6I+lml6/QLi72bBIA7cmqdK4ekqD0NJ6j91ZM6kLCGmmc36acIZHzc94/eJN8Yf Iw20HlokLucDnm3kgcjQecQ3nc5lkNXGugDpMTRULJHfNKoHCbAgzJSUSvrrd4FgHC7FRALAhpyk WviyFb/R4PnLPkDT0zptL9CpZSnjbSEmygeeDSC8Fx7qVfxZwZaGB5KVowfqrNV++JOW4Y/NU14G Rm0aT0V1IQsZ+Q6X1XUy8VhuvZF/XOSTbIplfzODTnd9I4xeM1NBs0Ob0ppkBBwX7MN0Xd/+F9Dm I1ojbIfTXbEo7Eg53/anaNQo48iViC4LpwKGK6qinXQv5UH7p45KoGRJWrs+vxfiRzhjq9Zf7fha bgbeXvTy0gvwysRlwCEsF26dod3KBxMZIGPFAHDMXgXqg/IEoxozH9Yjco8TvqsRQ0Y23HEr0BqQ 9yEtugQYeWuOhP68NFewBk+4xVNko47SWXdHx6JumTy86A/X9zWdL/lHCJZM8aUPhEp8Mo5Y24+6 nmsTfRnu4JRn9TayzF/D6H9HYITmTaNQt2LRBDpzhprvZSXDqYlaqC9vd0lfQsjqiP0McpJJQ2Jk fin8Oqgd1YlAoj5Bvti/nQ8od244g08lB3lw+8/t4NrqJ5eR53zLi6A6+CdPVUtOn9hj5p3mhhGG tF91A+YgmJUI92/Pl3I6LpBq5607lhGLQvGzi/uw6LqvMfjxVZ44DgIeVI+nVm5q+Z3aZcwkrO/h 4g9fsksi8jc7p2f69Qkj5omERAOkDfH2/UnOa19q6XfhZtpXhEr2HaiP74h4zITZzYgzZmM1dHPX 01WYY1oXzjEHmQeL86RWOEk+oyVBOa37txwblproWz7dSxD9iB1QqWrlUFvRReO5nUkjlPe4Fvvw zQqhzMx3r74Gd3fh6qxJ9IP+5Pcj2zin7uhncYRV7xWluLSIbTlrASsfKTxZEvXUR+zewFVmgeO/ 1OVZ7ww3zcbDqcM9x8K6074EyB55ccBskNO1CAXTQl5Z4yeTpyXCSWH3khFkJWkw3WEKRm9kjrKp xjLp1omQF6zH5IWCjbwzrQ709KMe25IOp3vYmC5rY1hC2Jb4U/DOAvH0ZbVJ7snqL6k+tmIzxuEq tJPKq8R+uBuGN720JzKVEQc+ULJvGqfPDZN1KKs0M3djcJcJJxjY0YflJcreWBGkliRJNl0ZQe2e +XDfIr4usjSG4SvKDk/0d0Sz0WvXddlg5Oe1DaQYwc6FgmABE0jcCJt82J1PnBk9LoE3JQO5xtO5 YyfKl7G7r/YB/DtICdysGqNAyuf9OQBWh8zIS6yCOywPihZfbSTOF6EEU4pWQ0uf4p+cJO/wP3/a E5EVTI6mNZMGVkUAhuXM1o5RNmgKyoNFlc01m54aq5bZAStNOTLlOv/HdgjrQ4m+22pdoFQq125y 87/hmYQmiSwZSayVaDSSLLyBJXJBCEbsdvDMQdtPSLBmNFT8z7XE2mZilpieBqMpAbvlTe3oyRGX FrXBlW/JqyldbXeSAWol3S9brcHmRD8bqVzTjAe7sdEVES5GFSbzkp+Xdkqm/njWmMfCZMBCv2At IPHV69PtGBYAgBWOJgFyn6MB/GeboI/ZZAEic+4eAxSTLirFncL9BkK/cKATqKDDuLE5FElkNWlA eA7UuBLd39POcfG9dBOGOXvPgO10Vbn3TcZtYfHVElqQEr5fyndJVhnD+9rsVZ2CiCj1jdaQFLaE 0skRfcP09gKxzaJpcw7VKF8gi7A88agKI00bqDox9wVMTkUZUqBEyGG28GaQ/x2sttoiwUWuTeZR uNoZYkE/uy0EDpA9l/MhRLB7LaNmd1NleDyEF+p9p1cSegG07SvhGQEtQBLSJJD/oEBk8uYcbHXo NFZ2kbrENm6J+q+2ca/njBNyXeg71jc553Pycm2EoD2pOF4UET0S1n6HrELozWpBrmck8uJF38mL xIbB60ywfHmgvJbCBA1wP9BJD6hBE4KCGkTLWDxrlBxJfQgY7QIRx9+o+moi4Adf5LieDlo+5Wlo 3E0eHGeeMn2fuQHhScv3Qm8gPVQwuBEXe8LBZV2KhOdv/AbWC/LLpLwfjNME554gAZjeqetG6GYz 0SC9wMyn6THNFyR1q1ASck0o/wiblyfJlmHYc6WU/91kClgSMqTxUZSGifBqQKalN4GdqD6tlFLY UE0Dn46Qz5UIPpCkhqJrTtuRD7cmLYZ+oJYXAiOUFhPBncSASh3iF38YaK4DUnQA8asoAMv0gfEo WsdJA0dOeCGSF0LhYH0EczQYPqq8qNIGnafJAE/QPwMVA31+wBD8vPUVwAgMhwyvi7wiTJ3Emtt/ tQ+z8P4EORMX3+Azx9B2hhOlkTdD6HtTDcf2Drbe+9uXdeDGtGISmXn94dWsJx1YNsrARUc4RB1s +2+5Q58P1pSdN5nHqk7aYL99sGNcA2w0ao/WA6PwoYeJ2hQt+ZprnSLt8SfVBXaE7rk2RKM+dein W533fN7mCrt7VGeUvB7WSiDFB//1rRnyeVsSzYFHJTzWKAOOmAlZ5cbkE6j4OsIGkCo0TLQc0veO GsgHeRnJNgvgaqSksvxEytgJGRTSU8Hq92lq1IrmrjPr1H2PsHxgI+OC75IX1o2lZb/0hHqyG4ko VuhljFcq1jd+zCb/pQ+zjcvx7dUkKdihbQ+Gaa1l+fW9VORBY6zELiY2cVVYfHXXEDlFHEym2M21 65OKhy/+C/eTWehhBPfw0uD+UtcsbReHs7gjpDmtDRZTBnMgUGk124MAyJoUne4Cjr1uGaMny7XK fz8zMhNUxF9QlYSCfBR8TQy15CR/1cDYq+JieDz5826BbnzE2EP/OHN/9mzKresBm9vlQnLaUJtI jDsidEYVFS0eWU0jlFpigdiAWW3+G2Owdc1ngf0FN8Y+PIVX00u4IhPEgBwBY67dY3DLQP7kKC3I B5siDNWSe/W3dCZlDqWo2gJSShKvRIfXgT8zn7QiXxkZ7HhlL9azh9IZod1WXypwtdS13U9FIOP8 IJeK85TOfjSNKWQiPsRBEJYwlvmCoHvkG4RCrlBlOrjhO8Yj43URiRhVeMfLwTFN3kFHbOrNaRy6 3PB5m9Fc0MMYCtVueEVg3cZNq5KdIKXJENYjhA93qOKevUr4xSnxC0OPq+DRTkwsC7TAA75zR9xv NmsreAJf9eNxzDqT1mRy8EvuS5C6KUTFXRwkwN/cwOgla7g4b3wgJi2oNTub2wue53JmcgciXOKB 72934UMR7ty6dW7UrTlDX6+2lGwdzofXM1cbIVcPFjbfaUjio/t398rbCP8WhtiuueVxTdeStU6L 9xz1elCe+sJWUnaUj9tlZuckL6swD+2qUxRJo2OWS8lEzeYdma8pcWjXCClVE3gdzSpWwx6TA2kA 8dlvMrdW7iRd/E14iUvp8hhCe8TerJz2y9nHtxLszsAi/BJsAcCNsfqTInRkDnZL6Wb7HnpGptG0 CWoZ4WKnkxaseHHztMMO4Np+J0/L9aXV6peRkGHQaIg1+vLUzpL5WQEt9Bi25fGjTn8SxwM613kN Y2hohY5a1l8I4RsxWn5PUMGaO0bUPXPyJRjhJu91jQl0nvjBHsn9aE7O+t4uO7gP++Ye1nbaD6vP pDssNySS90DfvBZEp41/4wISa6DCrLWSXjDRAUp11ctZkPLfOod6KUECWeHCstsPB2C2M5EWl1Wj esTAi1oheLIKZX7Bk6M1OxNoDSQwSxnLLLdBO3WARhtIUwvCV31wlH/PRr5r5HRp97C+X9saEzB5 oWS1b6i78Yss1s6slJN6wRGs+gzDSmt8Hljunrx7SAKSsHsX2uHHnGpzxeXwpmuRnRwImYi68DDV pJOHGCiympwxat6SRA5Wg20/MZV3uEvxa5yS2RmGzWAxjhnO0l+jwAcaskXjQIlKAajazdNQEdzT mpNCIHsi4s040TBZBo5U6YdNdh6O2EzDjpLVGAt88GzF/e49lGNERAqI4m4cB4ijKwXQxG7bf+eO bA65AqP02sq0CzR3QkC1X0+zUbNc6JSZTmnwGFSaJay3cFOyuJ/8f/r2gMxA9mSHzb2J7Yu0pYQp zES2sYTTQblTFMU3bqx/qfVBcUx3JEebWTNWG/Zn8P+m4KING6Nds1+2QVoi7bblATDPXHohXAPz LFhyzauFxH1lixp/073hiGeMaiZIxl0fYbgxRBqPoWFlxY8tfRWm651qydIWCCLMn1HMr0lF5bRp YU6c/UloBKtvS+w3mFA9ojaSxOpu3cp7/0KK/RaYwJjoPJcOYOE+E21vRA43mJEgmmU7obUKsM6S s6x5nWR0Vqev7py4xQpWy4eQlX4orNdd3adgwTDywbHJ8dIj1xi/LhgN595iy+oSN8zQOL01D1q5 t60NT6qXXg9xXj8OrN8VVeO291rLu24PaRJ9lxDM2Uk6LCc2o1gaUe8Q3+5mSsEkcijmy40b8nlL itX0/OEqJOJcI4eW5QHLPb1lFOFvItrVmHGfdczs7oWnKEoQ3W5/6sSZ1DMEJqnEzu1WCyFcoAWD /1teYr2EcCbA9iYWOBDrb/NEkrUXJl5JURcqQWI4xaWRubT7wFwyuZlQ+/TkPFuJ7pQZdPHmXG/t /og7LpYOBThEa0spaf8pwqEChhiZ+/6XYe0QTvkY3yAzsZCgi+mhAbQPsCPavkQmC+GXxclXrBaH 31rl0k1h9l3AUafi1SKUFBCxXtTdrWyrtyOMtHgsN7lbNYXDXvQfDnsqzbYwD1GKcWTeyFE4bz+x ozgLht1HhKLDD5TM/lSPqvgs3Ane4HNdbITc5wkm5POXdJuNWno6Tftaal6xERaXSvpcJqoS3MrT Rmes80j30aaPjJmAbZe/G6ShebtyBbk4fBootVB7M1vz0BlYOivYDC95VYuK4cYUoebC9eoxhdVg HgnYsWO9QRC1rEjLlLBgXFkQ0KHDZjNcFvExKDA88mpDRY8rcf5wL1JdxLP8LquyEd5ApJrzuQpj DiEM8fy73E6bHICCS8lVTNlB0/7J/W32xBiCxm6K2bIirY6iswf64NmND7TJzmYeOcnAYLHSRYoI u8HSPbQW37ubKWVk9qJx6gabHSe4fBU0DBB3fkOPeOlOsGIFzwf2sN0SGkhM+ZWFSrHKbkCvafvB /eSLAHqb1WJ+ocfH5UV1yIL8aFT1d0ndi9eg9DT3wgOlA4XLRBI+kKfjFs8JsaVzEmo82XSh8GgD 7/TUfdCz3iR2/0cTqbp6jfivQjzI8Gxuxhe0+xvbZl4EEpxFSjH7xBPARJuaUWnpTjGxIpvDTi8k +DOmmoahmlNCm2NEZSxiSpW9rxJMUSuQlmZ25OOpZu7d5PGsA+UIADaII5UZgIAXffqYm/XGlDTw PrAJwd2mGgfqJMZoHmmAj5FRr7q0kGHJS7Fj+L4P5IbXxnYCN4cHq1lgfVGIK8HI1YPSaE2rp3IX Jh0kqghL1Su3hjZtu+P9v7S21IY5eds14mU7pDpxcxP0LFTFQwDtmPxlSzF/cDM5vNS+YfqpI2te w/M5w9vg7fIZJsbU7/1Ldm2m1OF/WNKfptItGQxN72fLQIslJLR2hudHBkihFLbkfFccwdAEgPWD KTzQK+yRKw6jPSBAXMBU79MzVSaf/o1Gd4YXpRcy4UmQFzJmV6fQZquIGeBWl8jXDxYmNivS/TUM vaXGLyM8n2xYdo4kHAKyZqIk7ipstL1LRomnUDLsmXEkl1XdK15KnfNaobMmFpU4wRaJ/v3O/7/Y cw0XVeGWyObQs/Yt4nYlRtQ0IeY+k+w/4MLPxIe1kHchOjSyPGSyhXa3eOHUPDWExoECsBlH54ma KWB5aVjrl621tioIuaiNgmaLquvnO3Sv6nNWZAYNrUpGo5yUnXCzqg75gfigKzuOK563odOYCoqJ TpH91WHz2pVxPgvDNC+TyFTCEe+7TYggfnY52pYPDeOM1E0WcsLZK5yM2ohljWiUWC0COcIS1saw 4RBVjP6BOPu6ZE9Tc+e6o1zMojqVzPGWWMpsh8VLZ69udedds/NdTW6ILnFw2QzjYKg6AxIJedNo GLTg/fv7OxKRbRo7rrpdvSdVFXqPT1i73X/mhxDp3SGSfZtb/5oVI+kyFpYIi7yIr4C8almRsMYZ wGrJqQj8g5OPaRw1W0veETw72/vF9njtGZWw9uPEMXwaCGJBSI8xGZV3N/FoXMXQgxaOlLbDr6Iu 0CE3l1lV1GRA1jlbdz3RlqHVdHvqzpASf4bnerAIyks9Yb2+BhdrenK0XB6onukXG7lY11wkPFUg 2GvbSjnL8f6RG6eBPut0ykJ2ePAkQLjjRDXfMppmPA3D3GC7vYIWsUhgN9Ymppbi5h/R08vyA4er 80t++DGi2jj5z4ugHwdIoWXCtEM33v2MsNv4TwspnmO2lA9PPr3hUHtn5+CU+OzsQHlRF0GhTk8b WkuRrI3hOySLu9qgwgE63cGs2BzFB6moOkZILo2V+SFv9Qe/KmgF91BS8pfOA8CZrD/iS/PiI9QV /RYMNrij48PvcPFj2yMcjC0ivZTYL8XmxYZHOUt1VDELU0hP1zOJd8mLSVBeSgCjCj2dyEdDXtBE XYkkJ5YT+KmdMJzb8NnSGe0J5DwdoM5Qcx7/yUb0JPnPpdHyy+MbukAJGZAh29FaliQi3p9LbZZE Y3tFzANm36YwsiEGluwDl427ZdaRtY4ih/PCdUp++J5WewIITOyn6q62rvWnla+o1VIq/BM8meL6 D/04IOMu3GTqAenJ7t0M1rHeGh2K8QR5rGEjLmpo2BKlwRxtOXgJoLtO19L0w/rFtjJZlz742jVM oCvV/q7RrQLtud5fIzdOBsjNT6YTKY+XhZWIyzg0GuFb6FGemYQ5eeN8e8orYeSpjXFIqY71PkaW IWvQyBN83uY4IvBifWznpxjQwEyTVSrzKl06v7eSOSBh6BMy9SuLXaIcQ2LQ/c2m7Eb77XH7WmFM 3zoKAh9u5/9w9CFSPOxAViCciaLX7m+cViTz4/DuYdF5OJTgml0upd9xejROUwTncAnfWWudnZtq 0KHU28vo39J6/kJgxdhky5/qd/a7iiWbLmSmFsbNuajAV26AxGEs6ATakS7mt7UpgcSZgU9qj4hI v434dUEyoXsHl+46dNLBn+DofCnq6XCmH4IxJc1Ce65ba8twJeJeOEWLndaucECF2UkzC1obdc83 3fGp3KLsQZtbedoFs8Pmz3vEw8hXuwPTLbqQA9XoMd41aygJBInjf8/pa1wEojQrs74YGzBkQ624 7WmVyH3G7VZbZcJjyUhR8iFLiCon4VtT6iZWV55S99PkhahySndhhYgDtBmnXnaOiY05IMcOpgeU VDExFjF2xk7XxyOeiAWadQ2aroQW1JVYOTA+cEdyJKaEsI+u7bGmxYHZuiFv2NsnG5O8gSDuA6Ec 1eyzSlyXUeTxIbjViDnOJBBoHfTHVa37or/gjhczh1kxLiEkr4kFmNNv5yiDMoTVisbnFemxBwKA vNDQ/C4QEmw9MtzkcWSAHzAGsjJzlbzFKiOWf51Vk/1vKl2hVpsXlXAn0XfyFD/Bw8+SBWEjxH21 +Jn9jBvCpS4o0462AVOlWikgWqNP/5IohW/D/LToeHWQw7MrHKYgksvRfts6okeTy4efDWx2HEds dh4A4L4TTIyip5SJNlLHTTUWnEAqFA6vHR0L8cNlE3kyfARbh9UENLj52uQTdUAhO0b5XDNPHtrG OsXd1bKR9DdSROAIWea+4vYs7+RarDGezGtHIpQy3SIkLvSnaNoGxr7cRtGqMODizxgRdmkFSeNK sjJS0BRrnaFC5b3qPXpZ+DSOqfKL4arF9yZcPr9/f8gctEwTNP/S3DiHpzSDvsBOyLe3QTixk59B Q+6NSQsvm/qc4kXrLOfQj6ZTqJAvEhx7K/HqNnDoWNsY5jvAs3rMJ1wL+lbvhaLlkTqwkLSYbOR1 cVy6Xnuj3CJ2u7WgzGL8NQJkwZKODZ37IMVOturDZxqaYve/pbgJIxSAQtvcmP6ZSLDhhZdus8/w D/W9nlYdQcscAbmNiukUfhyE4aRw8keuOXKEsOhL5w4/dheMgWLKQm7rLVsGTKotnyJg/H27rrhY hcVaqnkhlI8ZYyI2JAUjLkIL8jD+RWzxQyyci4Uar7J1UeQcdkcZYhAYRkxJhssArYoY5gUtIJsi dGD+SsF0h5WOfKnKRdJjuVmpmYmoo+h/MhGwLhz5FnYhmbJct9m16R2hUgYRXjVZ9GFSBUGKsk0q Fx2FNHqvGsBI9524ZBMHu13dBNo6yNZUhzRF8OraPauPA/UTKu9sPUc/QHKvbi88BHXL/Yhft2H+ zyiuHciOa3vnWH5VM0XgMwioV9HRj4pKeUmKzD6A9z22sfoRqwifelf9mDMwkk9Cawr5ZDJQyhVM FWfYmZzm12g8LRi71nweNiIkGVmySDlkF/MrCTR/f+aNS8RmJ9HapDZ0eMTglYfXynhfkMvN2UgL YXluVkv8OEThY9x+f6YDwR5ZCzv5azMbnva/sHZjQvDxkhkJPtOVPII6S+9paES+bRmajSsWHPNk VVtgh5f/I/rLKlj30CeoH/R8M2OWAzOflB0kO6+gM47relR/Y+ZceUefjE6BIW5Wqiz9WNiDEQh5 IRJinvq5sA5dxfeGhmi4sB4eiG7jUNeMENZ9iFguMkhMXM864CJd6I9LxhACckjNt6j3Na8cfsDX 3z5NmHXgiGpNCRAIl8T0FILcj8a6pQ4efumBeZt505vZGY/yLOFqBhZW9pL6r0hQ1BaKxN36wKV3 lTcEwBi/EBtVAjY4dIrdiLG7EMAbkNP/VZSbN+8uF410e4GiHe54YoworYdhBD41mkyCi/UG4kTH F6K66u0GlGyOr77vSNPdrde3kmy+swpZaBvmxDurScUqzQhSwxkGQPRZtJvPhqh0Ml4Jbgss+JcW RtrlV04Kx6n7hqnw7ZqPfHkfNEkULyxNJbxOnvrS7G/t0/J9cmcnvKksyBKTYt/ZT7f4VDNezunC 8tgw4rfw5cXYqGN3fxFVO3QeM+s8X0sNY/dwDIRJACc1CmTe8cDnpSdqefOHGmRuv+CYOsbfJGCm GU7MxqyHPlJNIANZq3b6DEETW3Mw+lgHfc2Mm8LUfnNs5FWipcLyg5umwvDWrtzL4X0MJr1K2FJS Y9KZ0ML+afd0fN9n+xrouCQtAx51a7kX5YiaRSD+OE8qpgYBt685EoZx0ktLa67RMuqjnvkPWXS1 1XhuwGw6YJVuNBn39UvPg0hjz7lrkoZ1CwFzwUPiLbPoKvP+mTo1Aebv4wXA8fyucJDtHgM5ONCl nOPkRoCDaZVGlvsO8SHo0YTHzzeArtqP7OrO6vwG9bXDv+uabeiyxR7swBRWXF6fEvMY+9SMOIrA osJWJ0qHzRyQ4QnciZa8OxCdlJPIwqQ7mMlc28cqlvSX51ABoCqjUvCuKnOFm6T4iKL4jlZS3xIe HOXPG2eSD5Rtwmvw7I/2M+GMEJ3zGv9ZkhZ33l+ElzwFDwGBCChRga0y3ZIulGGtyZwuAu/ObXJQ bhIfRm8gpTGDMFdm7UEvX4M+HgYdIo1ky2m61ncI9g91pmMNoFLYbPaFLI62ydTIrg1YN0ykUho+ JRTGCnyRFAaQlGfu9IRA87/X9Ul3+Ej9cng3ui07jRaBA/1lOMKc9VTy8oZTC4NBi5oSARnovHp0 9khEyxohCVu4DKegsXZ+IDw+OWgdjjl1Ox1iqeKFNDzgb39VvuRK9fRZlmgD1H/xG6C4ycI7RUZC K0y+2JMa48V/1xCDG6cKrb/daMTkc4akOI4lopMFVE4ZLdjuzEBKa7hr4W4fmpMJpq+v6WV8enxy RDSgnnMSjS9a5b2b1WPB4I7irwPbwLr3Na26/QTKkLJmJaVRxSk0plEEabGJY782njOlHTE2Fn6A 3gBLImm4gc/vaUy3ASoS5fnSGWFBuy/VeVl8TW2aXuspiVICOD43tcyHalvM6wIp7codnQo3JFqN Vwrgb0mJhmyhU6NeTHZ9DW/TQLR0aBQyIvTN/3IptK72QvNIr1AHm4gOCIIYe1xSQsQxV/ApzZJx 6PCES88ji5o2M/0X7SP3PnNXdvIrmboyXycgM23+acah8tj5pzA+Jm4o+2Gys7bLVFGeoZ3gEU6X mzRe4eBiBlRXTiXFTUp9vWY2ZfWWlQ00pZxVRjKvx+7NwnAQeVG2gYUElN9D6IFjiFgMikqi5Sht 3zGmXs445AWS2aBseuKPNYH5BX64CDWJkPLEgqCHbyBev4zmE9E2ZzjZddh4M3Zhsb/rEx7rKBGJ l2Fts9tthlo/6vVzNWibjBPbvz/AO05lnjEkW3c5SNfjOnFTiV/sixd8Pvd7SQKXMHs7bmzahyQ0 FiE0Wo+R8OypuQZsR6Gz8iBgMyxS67bJmV/8qEFdmXe7oApIQwXLg4r9hwfrhuA9JgwmV/l0oX0q IVHDvn0V6jw7Ezovl4d5l5ZqYWMEFzpbfSlGNds/KDGQ2MIWSOOjRbvYDxlupm6muLJJLdXqEefB EaNpJdLhjVIfZlG4Y09Oc4UV0TNw0rexKlymCQr4pioyFKH9vCNt7raTp2h33R4pFeDoWu7eFuYm 6pO3TgooQBiovrlpdYeYiaiGBfnvWt3YuezBy+dz8/WURFnzQxtBbyjid+7aTrI3rWx/Nu9rM9AL 65zt48+Dq8RJZeUqHuVxZKNp4v5xThcIrqppAdjB0mwKgMicyV3EOc0JVNfD/PkE2spdrTMM/iDJ tjbgTh6luxRlYU8XPNbnoHO85661MWX4sxEqRJCpOgkIfTgb9ARnnUQUB7YVSTrmttjkfUL7Xx7b gIqyDfwhN5hmQvDL4vYsYrYIMN0jRhnhTVuLXxb8CqD/zrgWHBpq0oTDm2ivaw+Px4/v0rmqdnW5 FF6UZ8MD2HulDZk8TZOWlcFjMxecySKAY2GagqFYyuw6HxhM+lSE7bs+qijv9X1Q7CfOCtECn4Tc eqp/LBZ17vQALuyQtE5mzJ9sUsYWToOf1ev4gzpKuKjq07raJfckg7FIjqwYp0QXFGxgsKeEmPNm HsAhSfDKOey6UsfxKNZaywq1wyzZ5u8Yz+eDc8XU0FSoOCIM5LOcjuWHHyl7ZNKKHQPwqYDU+HXf gP7jpzpiwke++X8YxDZuGz3vslz2/tFAMlVSvphOCFfJKDTZNgFk32bvxYWM9Rqj9Ru3lA0UWZAg +pFhXAx1kre6l76X6/+7gTEMgJ9ChGUweSM2gwqzn/SDmXrYYZHRiWnljnLo+6XdsSzk6v+WMb9c x4N5jCUEzUQZTx2gkGcahi9Atzu2AE3f0Akm7NZ9pwo4+/vPqIf/WJ12gFz6MChNtjXbiNUXaCPh V1GWrzSi2oQMPaJKLOtRfqWrZt1FGb0cBTD6c1Wh4HWOjgZjEw24C4Y/zneibvGIEFPkw5nC9SDp W4iJep4OuoaGn6lTzVLEnwTWI1gcdEYf6wvJD9k+tXlRxx88KALO+DhLSzLD/jfllITrVw3imO/L dR+6i8fEspW0WtMQ2Ir76UYpM9mVVU4YtaA1tjy8I4aGarm4pEHEqA+h573VyxkSsLPSQsLwJsvz mTArDBW754ZMdVe/WOWdC0g1x3PzYmFIfQ95BwhJohJluLKMl/uPJCu93YX2zQE/Xig7CWTBcyyr vYglVnKWTxkcN0dNzUSPrBCSv1IPqfyRyrHVY4jfPSbLpcmF6C8CG2nQ7nBq6YiR3SAcwVXv3RLR WsNrpFYQlZnW7c2HkylCZpdLaGmRN0q08DpVe8Xad3Ig6b0eKKdohBU9nhDOtPPFKaJoVyJQxmsr H9uaBswFjkUUeyQfe2SkYPTxyyr/EoXRaxTzCq8Fsm8BjVpvU4A+w4cfe1bm3soMiRobbplCXP7F SD+47Ob/9NKAmuKlPBIh3nHH/peeMfIfdxaoUQkNce9KmkUTr0FmLCy1Ue1XBIbNcCLRwcwCnsaJ TcPuDvrFJd9YDjWxuFr4pZzvFYEDoHULYGCIDgbyGR3H5b4Qk5PIHZd2SuZaDjfGRy+fdtWtJh/Y LCDZK341iHp6ySnGxdo/z/FNDjePa/YtOaMJyQePkiYumFuK+okW8Yg0fBbGL+TW8fQFGZq3X9Hf zkJY0671tEhQrApjbb1ADWEG7Ji7jjByX2FHP2PQ3ws4TuM9PQigzLxLFUqMG4Loq9zubdNWYy0i AXSHuEuP+JXSqf/XdJAT2W2IeBG8Jbol0m5lLRWnXwJwt+su6/sY/iikvjUVFv7+Xc2ieDlHUYoM iZ/ZgULPM6tRSF2CU5UQhhbUu2a1qL3lI3P4CKzNMdbf+k8PdM7FpO/wTF2DHVLjRgfAZeHA4jKl ODBlhTuk2b0poeI5nk0BLR49WVzrYy/1q3T97ibvnEkn+iLyXOlDPW5OeHViwW/jib0EL+LONR6V Y1M1HKBz90ER2qF9FXiMj6H5gnePW4xvAdCpceoqs+H9qlZUOrHZWpCym0hX8zZvpiH92nLgZCEa QrwnI6KQBZln1zSg1AoLH2Xk+x0g+6JPTb4+U9ze8BdqTdjwfVix+6z1h+zYx3aUxjl0ooRBx70E hvvfuYMW1LhaAeyk5CI/F0CcKS9optK0NykcUiFHrMliln1IGbpSseMrk1qhLkVmYKbdQTlV0fLk JK/euPl+uusl6bxhZD0fWC7VxPoDyrzcw08nJ9zfD/rwsFQdmx6QjB03tWY7KN5BxnW73oOjqlnY hYPSk4Xg6zda8fEqK124Yhn0dV+wTbNQjlwysMA9x0GWnH1QnzZgJZQTFMrx8R3V0wBD4UCFE26k H10b+3utXU4kPRPGc32JTqVn6JZv7cr+o4iXiH8Km7VLXF9Q671XzmMqkqyNnxLMPlK0sf5YdXHK lvBbMx/cdKwxD0NrDy2hWNeVvTqiOFbORkSGuf1UuPG1LxQNOnmZRKrZdI34B3RILYSR7Or/FiBF 7qgmE2CFsM785pkbIMN8/xcPBpQv26e/hE87OnwuTGZADjVCkev/+iDbaugffl0RWudyVmYcHg3L K4/iRpa61XuAZPzcxa2Wu7MW8x6/qWDTOPFq0OKvwI1LgN40rQ5aBPPMckAga1cvN2x2zCgcaaoe pkqmBhw2H8Z4NLajfdSB5Ko+fUsPQFSjT8zlW6tepxQKnMAV/G+SR9mmbIlQKApsmz13uVzHNgLv alcdMSfgh16GWSRwBTWFAGah+QUGylHQd5LZmfAzun0xnxTsmd7oW9cqGxB69BrchGAz+ER/DUGq K0MJ7VDNzO9mFD+GuKYLD1VLvVAIqstv7gp5/S+7P5AWIfg926zLqftIImnLqTrtMrRHgsNTRQC4 7C8eN3RCVJwd850rF9llFQAzoqaqmaCpSwQ7ZC8sIquJUoJtGTm0g2knOZ4jfrVRef70Z/XNOavr 81SOiaVxqwVHyf3K0CCFynvtITLrVGl8HBAvzgyYe22/sVxdkLiLW/ZUwynScfEsDSN44lE4Y0ly Xk8Sz+YZu5rzuhOvWjgqObFbz8ENvy+KySKR6FbuaM8IngBpQCCweQZ4HhylKh9lskhKTGKSwj+H iaDE6RbrMRAsqz1edkPJ7iPpE++kJ6rLk7VVIhryRyQKfkpiP0kL2LLbGxhVpxg2m8xZFn7pQ8oS YIp3y2USE5HYjneUOYuoSIw/arSmECLaoHPL4cMxGTymtIV42uW8HXsrQfpIoyU+TxPyAEdzE+HL 4JRDxkQsIhj/T2FKD/+XZ1FY4Oeu6aD69bkbWaXqrPWanJMWcT5oANnkH0+DBCu/SOwqeqJPC9kv 2VUpNBc2HlMil8YL9O8imOBPu3RD8l5Fgu1SOnwOmZ7zf1FizNkdNUplWgEBCHPinvQuU6doU47P 8oO7XK7D5IYIf1cWjdsb6JOogb2YY8qXgdHUSH0AW2Wj0CFiM1Dqc4/tZYyNC35opaNM2FpYxiTU 7nBNbOjuoT/R9SbylKx60zHDNvI0UwbgGzPuwycNcK7TRcIGQgryeVJMZkvgsjEx9OXbJnDjx4kh iuYxH5NX8HMBCS2jjpQSvQGqeIqLXVo4U+BFJEd/+Bow2dqUTKW2EhV1jRY8eCIwLLAw4kDKJqvb 7/HwhRBzfti/frOHznIvMySjzM5LgcUexzIYW/gcu24Hb4md1M5t7B/CMjdJPGKYvYxRqDA9A85d +XvzEMphE56aM8A/VYRVhQR4XhTuMHJyY8St64b+gfGobFT6Maft2uThERGOwV21lxm3gC8WyYdd RkkCJo8+gq7O7hN8+EtOYc8fWUpbFzboe8dLXq5LF6q/ENw8vGV4pA8incSrS9g5Ha0Wr+0oQ8G6 EOSvSxH6F/V5sAx+r3NIXuf7PMIsTeLDV8yZwEut9t38OxfJ3pHmbbLQd5qqml3pzTmbe0azGL8R od2dG6A/3F5ok2Ky+7JVNFqN+re/7iOzc/KvBaWfOn7kCfKIBkfqTWxtyvc+wK9NTewv/llzuTnO gqUzNmhKDJyfd/OIzTuUGS9HwvBrLoSsO49N0hq3+HfMHlj5h+zz1pDYpn0C8Uubxrajw1bBoNC+ hCwEMqt53LoZhB6s/ghlsIheEuPYPX6EJhb4utuhSYt3rtSTpQgCnkcG19PKxibqzomzGqtywtnF EqYtFm6AIqFoYPCeUyFLGsrPH5Scqk5vvWLFYJakYDAwMSmLgn+IOltyYi2XAM6S0KASQV4Whwqt lPkL/AuYkk0QX2jGMupFpoULcQL4BUtmFB3i+UyovF1fYoKyA4P4faD1P54d3b+V2kK83eF6wuQi 3u8Z88rSxmZmpaHmLTMz7fWAFdSFJYZb36/uE2I3MHYAO+P2jdfiOcOi9NWcwfmpi+ybhnTybW1q CBkW8MCDV4X6gUTMRnr/p7//29s3uHIK6H03wQj55GXuEbClgZEofp9eN/C/8Kl2/HZZ8zeYy8CT Ok3oqO5K8CYcYu/oT9HIoWmLoMd2WcHS6M7OxP/txXFs7RuqnMHMvfdCoeblZhAgajFF6cREPj5y cSvO9DsR/DSB4tOwPFm1cqJilm6ra55dAY4Vtb85InVAnpEyjHkBTCPkaVuhHuLCOg4d37BDwW1e dsb9BSwzuhXGD0kmfDTpj6BgoqdlhaHE5g2a+11Fs+QjLhe6biEC3RERU15wyf6etwd8Pl/meDDT e2WgbCpv0fEgBSN/wOU+FbdZIrRuUjCwIOuZVnC9AHA5Q4kpqbFdvCrtrbXRMLWFvgxzeZsrzNlX pncYwukVwqHBAs7BdN5UcSfUinMR7sfPP9YdFucH4luDOgQSOAZK6xHMdk33rzo8I3CrH1KgXq/y znqFqXMT33NOE4jCYezMrRU1rigLkqyHRHPcL9QN2sZI/aB9HR5iVXNatL21CDLyJE9ZOGGC18PQ 1eTzT3HaSHuXA0Rt/fs/70td+wyJrkTkv4+0aFt4h6ERx2u2mZ7CkqoQ5t67W5T17CpsEEQQuXY3 WZqP0avVHoMmcVlIU43LgzgfWcxXbjyN+DsLhYiWY7bqyGWJYygLVpeDsx4/N6F63tTEY5OA9oZE V4OM970fsSkHqATDoBN0UyqNadP+zoEobf/lraT3QATq8R1zgP6EP63QWUNBnYKkHtOweWT7pTJr UBVKUGVyJmTIzs+Fp+J4HuS9MRqyRd0iKBfj1K8WwFpmiQMvRQNokzCjlv23xwAkkrcSki0d2GuB XiGAFL/WX1//OTiGa9u6SyeekwnqPakk71LlXFAE7mawjXv0pp+4xofvzbt2XN+T7P1ODArgZKge OhyTCnwG0DFi4VweihMTlt53WbkzNRHiF37GEDjFYZtLMaz2H1T7FeXNTnvmcPY7pQ0gpTcvkhdi SGSRrz5NaJc/7cHCvQwynkhh9wytfq7F/ivLALyMDdh/6xwtKbSOxg4jrjcYM4fCh+r6pqlhhrVh WnxKnYDiEHc3gmB9hXZWl0/QoWXP6QuiedNdbTifZXy2l+Ong7+JK+M8hA5BCBcSDphSgn7ol4mH xz1QdVYn1KR4lI94neNDaH5HmVUclQB0T8lwUbd9nVJu6bIS640KAUfUoC7dCaml5Hs0awZdQk30 9PTaRHUgon4j0RL7DnXYJ8DEFmKYvsDbmiBOmUyyU7P3W4TtGKuzr/EchIPfSzVdsXuIcbrmK6Z8 PRGVclqQIOg1nCX6QJIaEKlR3aNxjxRrQzMWY4n3req/qy/S44TiA7CwpmhuNAFPOeMEa5Yk4/Ua MlmsVGkQtduW02yheZrbBAcuF0WuPsT9MnaK8pEsKY6i14i+Kvea71gx4zqXmDKWgxTpDKJV8nx2 uUY/re5oF1H+vg3jHg6bv9sqalGh6nicQu61Jqvfgt5+Gs4wjAhpinaFjfl6j/C3SiydzfEh0/PC xGY3tVl1QJVYHhqp28CA5jvAmUqf+HjbAhHnG2bYV1Xdm6uI0VF0BJnJonJcnJjor+Hyx8aNF36B BLJx2CI5vfxXaAt3a5ecu7rCKgyN+2OOFF1MSS7f9iojreSVMPMNXsKTShqtQbYP9cHEjViYp0dp R8H9WvhNrlmZ9tgZSvuf8LlPPn5msljG7/rffjotjBuzwZqN7LFHPGpHm6Tg5STyu3hhZ3hxLY8g rOctJ3U2+WQEp3FgBve4CQpnjaLUz0qmlt45n/TrZP6JbJnfbnOM2TrSykIZ2+3XcjWHxZMTRTfW 4Al6EYfAzUEFbfHLSe+mLGN3zwES/+guYS2xzUy73iSYdLdrGvOE+ncuJ24Rp0fhr+np/BPJiOMj MJyrSdLHOlZ+053s/AdDR8tVdrUv7DgSqRSQk9nRC9LPvhrDlTJAbb1VM71z9jZkiWVvAlFGwE6F 5D283klxMVhd8chBeKAFdUUkF5jH+jNbb7sYWg1x3n6zSKAdqq9iGvVauX5RlPwlyHnycsAciO46 qmf2qWEMhw5dK0BYgAtEZD9IkfWnBTPuST6ij3ePBgeme7cvvkqa+pjJRuESWynrux9/LHCMfONE 3vLiK/rZwg/JQM/GAwTq/nbgCfdELRVHvhSAq/RCyAykdsNf/qIXrqUveekY+oxmSCJw2cSwQHdh jYaetiASx1h88U/+WqR/z1VQcVfS1n4Hi5OR2gGpeu6ookAzXSLl+3xM+Mxojfdc7vzSXpQhht/l f8Ocfyfc6yUo65XCBHxlE6kG8IJ5nvDZ9UC0aL11NXD/+wKS2ij1vWQq8/OQFLbwnAlU7+Bw3D4N uR5jqhPerqlAuOpbre4tiT2vQfOP1LmT1VC9tnSR77zkeK8zzbjiHUuVaQwc7qg+RquhGqW+vQVZ INrMxO9o1YZsskb+iy3jbBZpsfNCFjDHB938KatiftSbykE85nMIhRCqDPJDruJeVUFL0DQVmgtz FAKGclxj4Lssz9tlvPnO20kQWOfEAmTsvyibvCmV3LywmmSxjLY6A4DtbtRXnpJoxKl4zHNnE/L5 S6AEBEQ7w7jjFsOB1irc9YUbhnpuFshV1Te+iEFC+7hLRGOQqtN/z043i7g+7dZLOnW2Z0lPehcX 2R+GKsMNRvUX2JjgnMViRGACMmAO9HbI+zHMSbOsWNzx1jFf0Ehr9ivBQfgnebiTWl1jcEQH6Xe1 7MTiMA1U/eTIfCZL0fJ8EIWH4F0nE1wQUiFnMAojqMwGmAYIasqmi3AO6nTFXvWPIGEW8/pq8QtW kUKy0KXRlDb0x5M8BYGotUqqLIONSdqXsIYxGAOEv4NzQN+tax2IR2yWQVPT5xo1iji+pk7y8LWS RXYdoa+X8D+ZCwzIPWu/frWF43Ih52IjkfpAx6loxlCg+sAGyLgQkEjDrXH74wtyQIxXTcUGQqBe RfVuJpzWab90EoKP5ej0DooGJNECUBlIpr57s6k0zyZd0vLNUQlNJG8qIh3iN89xvqTFJpcpKAvb mAbPySeO+lYRhDUGO6YsCJNzlsuTejKyilMhtHwNb/oxJVQfmvuzZpvWsnRodYeZpg6zCTVf6DYi U6XtTl4X0ZPHtklmGX8mdLiVZ6iS8F1MV3WXiPZYDZ10mrrEfJ9D3nEzeDSAJiurll7mjx/C3ttL pViVZcI+Gx8M/cECtoBFaNyftv0u2FKCwijSrds8MA8Gd2Y1aAeSbCAPmXH/ylxJgABb71Oq1XJn jZuYegtUS1EMFJ7GkXJJROh53OOaUzlhY9t/QBNHUiMF037Chmq5UPEUMyF7oIK51gjiFtHNhZ1R 5rTC6rrz4RC2iitsPbLGsm1gpy0DG0b4VPZpVjhzpfUaO8THg+Fj1hdVOv1RkPRYbQqB0O8jqpYa VnHC2rmdMqHEmhisdDb4s0tqGip0n5z6FSNBwJwScZal+pohkxvRmKAUg0L9cVIRuxHkhB2OLHin x2cNI+MiZ/yaFzl3ySqjMN3DF5l3lqH1hBkm58fp1bDqRjeNXZCoXf0h6Z/55c2u0Bfxr1lkjvq5 nK1lEUs7DFqFhTWH7XotPgYuPyrXz0iDFGbp+dPLkvgmsVm2wAsqi8NTOJYE7xZuinWm8xOHKvNR 5DY/PdDFO844WUIu2WD11/yTamDdQx70RDjHmlIutpXNwoXOGmd4maL/hNqacTrykCp7ieonRh33 nxjFkUAEV80Z+0o0qawgBUSCV2+VgCJ1uBjwowbIofIQ3DiRXxKcnZ4Ab45/OXmv6PQOJYVTqtuu Vw2bamhHRSsEX8xRMKokvK5k/MEa78H3exOspAjn+dguiEt4Y9gg5kewxi1uxUVvr/jzrGhm0vw+ O4so2WiSjO+wvJgjEgF/1lrVb4NvS0nUjAmTRav+WESzF5RCmQA2I+59vAKlMb7aDNjGdZWO3+T5 RVK0orO++RKAcrdoKxrPwb12F9J/Ks8M60uly6FY5YgeyaDf9NySg7z7MtoGCWE6QCSNnancxbXe QvBaVZtkpUNIOLbAjAyVpLosFXKyakUHWYLs8+LPvsQ51e2LZ1NMxLZEsSUInW/gsb8xymwyChHR uKwJd9IRa0aU616MSDz7ssu5PBO9Vg2vCf/kL1iXViQTD1s8pCyGT2uI4R6IwUxlRzB3hlo4nF1z VykDsWlQfzRe+xU9JPj7mvHoKIjNMyhaZnKI/VWl3he2GDh9nLcj1fGvADwK3ORJXOOPrF1xlWNU rzI+7fJpVgWLdafT5GFIcGVGVfXCYlNSmE6pTaNyHLbRyjNkuS9s8YNa5921WeBXmSy9KEjgeL9A dhXnxnO4FC/aQB8Z8LwjSOCO5iaq47QewxTWfYQTwh38aoAYKDS3zB1F2r9uGbARjuHxlVm0nHZ6 0mgFljU4A/kWhY95uTAMZimBMVpXVbXwd/9AWM0njUioJyUCvGQA8byKqGYlV/cgqFVs7GbezGM5 BuPReyAN90qh1kwbXhe91CJY6pxiVomNr0lTk01Wu/ayQTa5T2BYNuNFZ1eH5g66tHTilMikoe9u KwPKAVADyMyPg8O7XHJZ9GSaiofvWSaETe4PmVdcRu0L2QwB0nmLo11gW5upm2VYFQVHMDEpwV4J J3li/UmtGPKWP++JCoO/KecU54b2ofYbQRnVEJaxjx17G+7KviGZwCDrgB0CVnDd3FW9JwQ733Vq I5D7ZhZufIUwwo7bN+1DAXIHh5nCWjYgoVXXihJvG95+VEk3jfGdzsvFRqAFDFU6p0e2hEXl727q YEIMuMb7nlaptOphInuMYyQAVfL0fuAoCzN6hqaqSErtU9iFuK7ZiXE75hDKQ92ZZqGq27n2Du5F Oh+vz7rUQYV5YWm/dmQWCIO1dhPqNbHCZxbEzO1gGhatdyZ1Qq9ELqpK5anlNTmvdJkHQBRwr019 gO85iVSJf4V5FGGayRX9ACqgZp5xll9Vba6S5CC3nN7Dp8nNyMCIN2RHPMN0/pi+d29iL7tyu/Hb GkAP+wCBbl+Lvw/z2r3w9fVyJONuck7DmAwHnrX+0NbtIOrvylVmusvnq7+mHXBwBmBN98AQxgWe sf7cowZTZJU/OSEt6ovkeBpU3D6MlCeC/ZBWpI7T9vKA2LwHJkW7+G9dMgT/XrLO4puxneB8/PsC 2xZD+5apaJ1iPg2YgZ3BT8v0m9jfwDTkJZwNA7ettKlgT9W28phJ3qPP/9JYFoHYjYUvsnZPaWYJ ilivEqzu9QdzqiFFGGexSfYroH+SfRhu2MLzKjgIopKM3pgzswAgrpvsZykRCU8YkyDVKBAzGnRk FRRYRO++SVWhXIU3xLJvoQZfNETYOtjcFSeo/jPEful4Rcm7ryDX7zT7ixTY5hdeWWZRU0ykRbTa 7lgJZakfsC2dlCYoKYmSp0cQVRXf+bDeuKkV3Zop1YTu3R/tLssRRT66twdRWepFDEYe0rWDV7jx OCJyhpyN3mCRU9389KDKzG0wBHIzyFIIhVdRT1F/dn2t4eeklYN7His0Zm+bNMizJrCigO/wSfYs 1PE8oWijV0twp0Zj8XZ3nVWYWWVVeYpbOs6BsjEJezCI/1swy/fynFBDeJuW8EaZmKivqg5h1kGT vDVHuyfFTJpN7LJZHj8XougQweZqJ4L85QWCwwiE+ab9fyQ4WK+BZBRthxYwrPy5WwtafUE958T5 hvJLgQ1ul+ktHadTmzI2YHHalEcdTrIO979ZyksHufpHIzfrh13LjbWoDlEmVBIpi1kjOOWWWMx1 E6WVxHLeR/qljtsI3jVt8br7i9cOI7rcWizifO2N3vV/1G9qvZr4pp7iiRl/t7rZdUM64PNKQ+aR e41sJjUDS0hDRvPOxpceeMsidy4QFuqWadK21um+OvW/+fUBdV3G4LisSSkZMDJnvtFco7gjj6k+ 7gqoPdtWaj89ZklVVvbfgKNQSWcRrv7ERut7Aj3b7tkPkCON6dtZq6GzEtJY9QghNqXExivVz+rk F66dhvbe3eTARpHNNfF1AGcrbNpNqB0gqcKfSt3MNOdUE1tZyg41rbm4WyAcVhsCqp9eFp8Z1li9 cPz7Kh41gOAzikOaQl7dmzSlwcPFMod1VVv8F4A97Lr2/xajMbWL9m3HWa4OEl7hQnCWW8/2XAHh jnys141fjDeftXJFbJKPB028XYK1hcGX8tGR0dLq6CKVoOuHeSD/lSp9ofIX30jlC1wWsxa11DbE tvYyU7b5zwGJPQnlTHswlhlpBhs3FcG9m//CLhqlst2Aaf9jSaJXDMoXqnH3fPehWS6D1i3nGShj 5cmOgTyKddSAlQ7koNCahQWiSNdT6XecUtvrV5P1D3zNf9P9kW0IAZqM+OmcBSfp7fj3sHeHQI0J 6iViH9OBsQqyGTIY/KbX44ZXHYW1BBf9p2xmw5e01i5JqHmAGTCMAsRLwomOZv/8Uf5jAecoE4RD 3IntAb49m5ygFvzAJzvfmX0wxR7bzWy4dc3k0FiUbmFwiMNIt6r/PpiaSEv5BmTiPivzS266bGjY TB5zS3fOVb882LcyC4mdyqIX8UIQqQFNwSdPPJWmvRhGeWamqHZx6Xmeh+U1RJM9ctsrEbic4TfT ktMAwYr4HKl8brfQx3OcmQdPw/fYU/pKfGWMVXSqoXpxyvo2UtqeQpNY3G8Cu0g6FA1H1zLh4IxM 6seUZKLE14eiQpdW/KwqMbYVFTSLvHsJwYWdoZtw0G99OVBxq0FrfJQxFjpAfJdVoZdcYVJcUkPk YMtgoZsTBvqqoANtn6zof9feusl7xmmvPKjyEy/V3znjixqGmm3WCJyxBBXCynviLf3SjNe1nccy 97rzXzM7e+HvbRpqjTMeagvnTiUKDRlei9oIszVbRphukYxnzMyTzsS8hXJ4KCsZLfZB3you0a/W ICyaOSqB0fpbJjrHbJSOopxQe+l5e6Fe3nP0ePvwBIZz93I0Yxo5tElNnkOWH9nUBTSgEtt5V3Qq fGdDwxHtHZA0tvi2Qt0LxQLsEovwuGLpunvUvcUKgEbdV/UOzPx0y8rx7qTwNZzjG8dKHjgDSy2k 0rbhyTcjrTYDmOKivMsli1xGNo1vY85ixT5G9ZhAgSOmYdAH3BrmrnR3Gl3HFh2ECZTA5pxiLlwL 6RZNs2LtgSEes406XJ5TNBfsohUpifiZdHavLcAo9fvbtjTMVnYq6YF2tVA+bRSqgfQy0t0HK14B Sed+bupK2c6QsiFZfX++Z3GKI7CfrR5+zBtQgc/L1xybee5fbPzhtPC7i+TKNbld3GtYCiow7UbD 3BPPPpCk/5vk8wwIMc+VNw2W3rFiChXhCAis/4mCgVBfDC01J9z3WjknljRvb64POviPp9vIRnuk PrszIFMNnrW7dXNDJH6xxCA5Ak8Yn4/if5fnk+0SRyYbT6PoI5tpemg93iu7jeEWNOG/3eUGokI0 2ysViZCP1p/ViUpYZk9Kp4pqdDftj2WlldkgI61/GSWWysA/3nCvEaANOD6ukLifcIndXMT98xef ntoRGCl/wXNqQVNO1EBvNm77nGIddL52IVqx1U7qHGe7fRLaeGfA5r69EVa4C4b+vF4KBJgt8gYH IxaW62V5FSljVv3XjBCt6G7CW+/NgvD0Rao2mk0GhAN0DR28vOlD7Va3oR+yIZ/Q7N/h0VCkirAl tFIhYsJ2FKUSh6/4acY7zH8hyYrRHk4cMOkYKPCBFUJhwHlzkqrpEIeNRruq26dYiUdzHCArvxGW GsWSdUvh11+f1fZlm/ia6VS9ZND4ndZ4EU1U8OER44S5YOS6E3qxg/PliaOXVu+g77yDUPKiYL4a ppo2Mi9/XnSNXeygr1s32SygnnLR3Gk0n/8lv6AIP4smIxn36m0Vur9tmxMm42HFoH15n438mo4/ LFGPbdoBlloe50u/IlcjytA8pcxp58Y2ZpBNRcVcHV4eVUAJ+DcOVGcZ7swu27tjMxA1KUZNJi6z j1yD8Agc2dAnWS2vHXgP1MIjSUAAdFQkn4RM69LKedLGwB/l9ANSaG3C2KCkWkC5QGTiOge/YjOZ 70mRicFNgCOwAi0fmCKuh6RdKpHLPq5iFdXySR4TE2iCjfpoZiJ8RmU4IS820nYlXQvSf24G3Gtf fLGVpVKoET+lgCsthlSgQd9SRT7wRwvbWYDCvxLMJvHMc/ytNK5ocYtyk/eyJmotYh4rWqTqWa8i pwKaMCcobNn7YA/mBUBspk2UMW18/rU9Df37Z7wdfLW/dEQnDPF6QZ2R9vV3EkZHZ788+ueokOzV M5BHP4CYV1rTEwpoehThrjM6IUXwvp4duPpwABbMbBzDPPYP66rkwUeYmUa9NX+lBbiTnIc9Es9t Ey49WDrWT4TTUpChNWYNNMmm+hXjGasG/jIG6ZIrp4nlDHbHxdr574tKJ41HNUgEC8WYnl1xx61l smZVSwKohKUFRAMnmnMph4H0IEviy9FpaTPtYEaAJUKUzq7XkizhBhsFCsPrGaRd3+u0RmbYeKoW l+XD8aHf1PRbG5+/Dey/MIlKHB4MasB5lUbKj36wmb/KCSzeZ8R7shDM3Kqj0W6OjfdZ/m7K1OAI o0fvhFCJMAqcnZwmGwtdz7Y/iX6s8kM2/GknEUQCNplPIievJMgewlWAR92II8ds6+MyKFrTE29n VkFCD7GMMx5Iahncx2j5KPC/JKkyC1MjRQo9eHbtMsOz2jesYbmmKX60C7/7iraBi+K8g8EaOOlj kgwhpiItYxVkQJsNX4JJzidS1aBalm4hewnmnts4QMDEBQU9xEK/Otm+nJr016f1jYbU3BBdwyux LI0gagCM1BRSjORR15fFEJqGE622LAj+Pg0LrJyX7mtBcbB9eX7lsdgZwVDVWU9LNdbpv5zvblyL +HOfKieYLuDSnubI9B8ZFkdM2toia4wEQCD9g8Z2kFb9lH51WPLWUtDyJxkc5zz7NfOJOdNGXQiG 8C2MY5wcOEx2W9qb+v+Tp2F2Kt1aFdtio+4bRjuLm2J59+qLUQq86VBlMpu0HVzZYGljsKJrQPV5 4SXzOtimibgRW85fQAN8C2DyDnUE+lLPy46X86B1/IzoKpBUbPNaltr6QJ2t08p6AA96OPqzCcAX pwNLyxkfbKRt4p7XKAHTjBOllIwedEw0aKE+vN5Q8L5g0eTh/eHBorm3prjMFZ3/UWqzZFrMkpXA 0FENEaD7jo1LPb+accM+2+7LLiX6r7ksE6gp84nprYGMziYI5wbaGXwn3ITpsAmagD7QBb6i0qH7 NOc39Bc2otc5HdZPi0ACTY9HJMY8n/oqz4sWZWeesprJLkpo+96PN9vmPnj9TpU9Ukm0+H+yH+Jb qz09HQLly4gBMIltzU8BOGFXeOqjixgnxzXL36pX6zOLMwbVhHCHC47WJ+QWWomvaHlkknqRrWQa pH56pEWw0HmPycZuWTRfxNUXFd3nzIfaJ/Kbl2HWt2UD7+xLWQZi9Fs+in7g3QnTFTH33pJAdt2c k0sRfGBkkFXec1KpWjKTvqI075A3dLOBhfYwB+fNvUiRb0XbBjlTKiN2f6cH77vN07XxFjYiNMDP rmxG6t6Sz8Vfg4wRJtilVxRbq/Nr/FnIe22B07klotsfqFVKvUhh461pnjFpYO1k3p9VuV3WqxEk M+zHygUhJB77FblfC6Uj18rWO2SbmYNGI1a8YUqckC0N+T90trFhnoQa4sfHVHJxz9bCBY6KMikI gCedBoQfCxax3LGUMf2CzGruLVF/sCT3RQBvDC8EAU1DhiBVZ6jv6FGmMWxqsCV1nPvqCJgvb8RN xKhRTGUgZIUQuGwkol8sGyBDkGn72ktOj2t8IdzF/JTH2Ifv+OBsZ8BpZIo1fNxjwuZZHvlrcZqz miENUUEEwh1fCY97NXYxa/Xd+8+0dqDRKnbfwmwveO1LHsgws+OOWFrqo8gBgtlBOBmUaTfgeL2i XNsc7Q65Ov4iieUTV3d7SWnSgR+VpCIlvVFV6eebSwc1mBIRZuGwMJcQpBRSkE1o3dRjwr0Fqhsv ZdWy7b0vw3Bs5KXy8YNv9bV6LRTg7q2LMSb0npGeECPN6H7U592hfqAFudgqMQqTq5WFLQSd2whZ BhPKWSZGDQlXvKxylu28bT3g748KQLH+P2HOyven/wEm8HJtuq6Ei3W5ppunCZRhuys7OisVnwGd ryeyBEuOI6M2TPRkZfsuUPZtZHPVpF84Wzc3VSO6YxpKIPO/HaPeOiAF1uFCQNQQgbpTVRaOBIwj tYOhcaHbepRc3PNGaGW3TxbvyH4Eq5LtyBXxLHaSSL+w8eqpWzvibdKLOW745Ohk2jFx5txoUK5l w9+ctB6fpGcsOtvfpUTB7z5hHvE502nIgo1enB9WjNtKkt3lpkXhEXSvRJFSOMyoqLORD3eVqUE7 WzyNJW+Ogv7MNglhsMsC6JFYwxSXi4gPBcMpJSRB5gVO9EXBxhOV/A+GAH42F4ntqTHw95XN2BSX qv2Ej02gyqVFWjBsVw8fbbzKVqcq3dBjbB87dgyWsrG64hBtK+pea/JW9WyNR2FQVUi5XriNhxU6 fuTaSAlTAZXT21dLAPbQIAxr1hTneifzT0mMPKV1hi4yRZA49zl7JhWivfJ5of6DImFa30ZeiaIr RrymnsDomDdP44CyLlvJOJvRFjlzpHjMmgEEeREmk2WKgvN02vIBH9b3eJLxSwefVoAY4sBqjScE bnLifNgeror/NJhzANLjq2x4aLfqE/QnW1aCXw8zs10TXzXylZX1UCKEsZJfFJB9Ym2ys8DwxGxM 0KrC5QPnmgSx1BOzDXMh4TPyRiFNV0GCJrWdaNmZT6Hz8eKso6+75J4T9GPuMHqkC8vvmVu9oxT2 /jtJvPjtRyckt5YVIZBFZATeyN7MHunWxxbqa2dMxa3Spa65fLg+DSY5K9TRIoKb4oITdhOeM0hZ 2X5GUih1r2kLAFELavUii2RdaUtFvnBMmM3cYfk1IvqheOer3nr0WXA86dmT/QbwsgXnJXVKCmim auVZuQhPdUQPLMlVQGWc0svZS+JldXOEx0j9asFYX39hKTgdUIQMBAG2pd7gUCYfXpwHIudDx822 tpLlxTMJT+6tcIDqRBFbpkFEH9rAu26TWCNm9Iqv7K6AispzFUWZb5oJ7rWBZJBFJucnAKRqoFKt e+ADmOtnwmOE6kw2SB2+6P4Q/sNK+EzAEHaqX6Bq4OI83nt0ag03Slunvq6EiPnL3fcPsKj0IO5w o/GtrbhUd5ucExTcFKShFczTJQsQzP2l1YKROhzzErDpbUkM4k680r2f0Qhcm3CJGUTqmk1g/Obd 65bdCz0RpJPwdgTd243IwyB9KJ62pVxCv3CPuBpbSdj4mDssZR9O7vh1oc6fPjkwm2+aWL6eVHcC r7RApmg8nCMxC9L3o14XwkD4hsQ/GLnkpucxWf7GKHBkmrpjkG3B3/I+nolMaFIs73JfhikEmCDj yr5Kgr4DIkFyGp/HrhxkaFENeEDVpMDLCOMdgR/DIt+Kl6TgOpGHQHv4pPpKmAF3TYa4oveuX2bC lSEyH9tzTnMevKsh8j5nx4ZjeyKZblFf6e1ZAiwIiMmnmGtkdSwwSz4KNy9XHYLOCEtrNbgZZ/Sr 4acmkASSkx4LBHN6xbL+XpYi27mNzZOtQmjSh+0x3YdGo3yopBKCOW1XVJcYgDj4aqZcZiJ7mbyM jN9zG0QGO4P3m99z6+bev+YfB8R26A65Riu8Pp0NQNwalZTYcBcrdT3gomCbKzNHWjmPwzVpJnQD dv/x6b+/DrjK92NPciiMiI+WretGBgz8cNapv/mykZtMDQHB9GFtVNdN0tE06JOp/DVqlCJ933Pl gEh+MOTdNXea95lMY7uoTDJInpRuCzkJ3k24AKLz+v2A7+DOHIQxcjUy40cFhcCsVpmbI7CM3neD AqJAlECmA3lRrW9vYjHDanK2093tkP+AX6j2+mudWgpZNr8a7/pwVry5e1KlfIJzKbMAkD1G4IyU t8PELCxTyvSZpzaZQjmCJ9VS0eHBmzv8fJmEJfWP5tiDDwRUh6M9krpmNqlzI1w6l8bq24JVCNM5 iCl3w8cM5I2xUh2Ac53kqJahu2NxRPYM/09yx/25094Bhu23Mvi8WWvfNn/N1k62sEkQIsmOgmmJ KgJZL+INvePZmwKQXSnEUyFJKzx2EG7/YK7rS7CFI0r/hK50sPJG+bFNnQPQOahRoLyxegO5lS+V 0SAMi3NX6bMEWGN5455AR14JH04ZjVE3vOuwJ0I0En3z/tEI2GqH1sJIkgS0KdjthpKR8F/SYYqB pkdpPxLjyMbTvmhFrg7quDUtuNY2yxwTUwA3FWw9wkKiGjffjBO3SM/TSpX6D4wolwBnW8hGYvaC /21q8T98+rQ8A0p/5gh+XJT8LXjYw3fMv5z7gWkuW2Yecn8ZBh1USp8mp3WejkkRW+HDoJoq1Dwb 0WFSgMMCUCq6Ve1zX9SZplkK4u1J7lOoS38yreD9gSbVFfQ1ykXOMiMTzDS8cJMIeiwgFQk8GVUE KgHCHfA8MRE/VLuHRJTx+GkQq6gIvOljqvd5Lso6fDWg8NdG0h033GMs8XFYs/Wbby2NuQb+gaqb CG0BeZDBq9vEus1hwqBspjQ25P7O7DKDWBrQ36+2xjrNUS7HHpZ31Sd1IEKTzDzUIjTb/Gp4bMbX 5HJWSn4LEgtkkl3rXmftQXfQpfCqsU4fNZA12g2kHs+WX5jPju9aFaInB2y1FrX+MvQkACsJ2jnQ bR9td6u2C2Tk4ZrTeRHJuG6LfLo8D7hN3JYxPNY+BxxwN8+UYbJdNwLc4x+p0Hh3mEE8XJWq6u0q EattyMUqzaE7Z68pn7U/kArLYGv4g4kYM0crf0y6UjJ0wwuQMW28Er9kmgPv53xAO6mXFkKRp/Sp hD0TlveQyNgycv6BKFwFdSxUsTNraFOafWn1Mrk+lTm/pLk8/K89AIf8seBU7I7cgjHhm1I+ky5z n8U4gEWVwSGEF+EkehdnvWBNkKTOFtdQa6mYSj8INkODMe9uRJfekpl1HMZjd+oYvg/83bbVg+Jn Xrnnr/2bVhAD8ugVJSnGIfi1of+G2hoj/dsW3BH43OcTpz5Fi2Pq+JCumFwB2URdwJ3jq9Lz0+cW LmxapLJat6Dn33cU6NULyF6Qh4PNCOUgniFPlrz/Sh14naJkbhMzen3sNlmCBGvsyDaHSXEPoZni ZvOC1bxJO9iEqmpYrKM9xThhK68EgfMjGtGZoLO3L21pzN35z7lhXsXpvZvxVZZcCu7GFuN1QOJH 4fTfsqqwYSl5yYnhoCu1lcSvMmrehupY+BaKPVJ+6vWp0sxDHCyZqVoyfhCy3XFNYDErx0ZH3jR8 T7gC4IcdgOMGmYq26wgOE5bmJQ9SeRSCLnjhEkBJ+X+17FXTaGAQj8Ce0IgdFZWTUUQApl4uizss nqPwqOxffeDJ/kk8zJmkk033MfGz1VqFDSPb2vkUKxuzW5Z3gZofJ/e+VzvWINCx+7j/1LMFm+t/ ba8SjXg/Cn3/3irwtxQSqSX7v+5cUx1rEnhveu0jODeGnQArj+ecNRl1UVyMrxXm5CVjXk3TvcuF 3llQUMttYFi+yJyZv2u/8D3FGFKWdiXiJ7cq9hRy5UolY3J3iPw4iCzRhbbblpIotDrRmJphuZ8a 7Xds4TxQhkO7L9aOfg1zMzlfogEYzjR/VLOCTlIwhtb7hkocgxfI9pnd5JActupBlLFb2FvnbFPh 3rDlFGWAuXX1JxqoUNzP8edNw+Fk+E7DF3Y1J0ijB+EzTChpDE0gpEoa8vWhxhcXVmI+lJq0BYtx dClhsvxo1NSZOPQC+7ZAx2gLkuZD2e3VML1vBTOg+6P5LTYLJThvWREZB3Xka5vg1r19TBf3AGii PQhmLg2IdIEObtkDd5aiRVUnv01I7/FN/DyS/VeE2SxSNf12S7LdegLpMWwIpKWwqKwPHf1NkLg+ iWMx5T61S6o5gYLKF2qfYPRGakQn8gkd/f06F5joePFkYZPYeTpwdSqAr+/fUGW0bBKM8hTiPg73 58lrM9onO/xTLwUL0+hMzaveIZZNnpxgnEGFonepP4ejl9R7+qXT1WSZM09NeVYd15s6qcJIPyih RrzE8geWn9TMdGsH9DDDoFlWYuo8NV6oAlOrtCp+JdWnPeVdKTyfBsCalyLJ+EKy5sv/wLOPedmD iblC6cAUGuUKUxmbxfQ+Dz3AVTkcY+ptUszlfylfeWQaZrYL5Ics3rDcSTzfOHQYHHAu6EDRf6gl CrP9DZgf69vAK0+VdstQZNdAryyPC3KXkJ0el+Bgyqq/W0EYHa01vJfa86kAVKl86+Xq+PszdnlL kyItycszghxUwLTK4YKrQA+K6A7WBieO2iCugPcHGxtJBiKodKbaPr90a2YfY2hNSO4QTNJdptUj RQMcAGpK37+kw2ucU0qNj2FW/K77kO66i1nNw7Z6S3Jnfzmri12wT3PDFkb6Fu7brx/SG+5KE2Gb +aKKzevAGCz+Vk74jw4noaVL+fxn3Kow8Mqx++pDC6oc2nawqU1kn2ZvhSeHurOjY+Ub8Tzw3e7m O36aNByDhYv9X633j3c2TLL3xCbfEW+Jd6bYqvHt5id+3X4KFcRBDFIwqB7YQsXDOKhFW4m4hwO/ D7+YNJd6gsPQXLVbgjLHGdSiVlGak4/tNMcZ7+NNs/9SRtBsrXMO8DFYc50H7FmbTe5nxDb6XvLM tvEtkNSVgNgIS62CeI1sGst9xqeaMFRCMZOppPj72cOhFsKLFGkNqHNL6yJCR2pOIvTvunC27fkP ry1TtZt5sbmladepchkcEB142zYf6AWqUAGDkSP8jhRQQN4ZEVsrbKBLgVn3T7SVaa4fSXg38o01 Ml81PRd2RKoH2p0KLKDD6MddeJNnQyzGFnWCWEN/oDlQYFmKXilXV2GaTbpMOl7C30UAP+vfOx2s t5vrzXK+Qkg+oNIqgxqhutCp4kCAxC2rBxHWYz/2RCN+TXoT+Z+9ugtQyz9nyoJFks+EkQgLPDJm cB7Xer63aH7thYgxenrk4u5NQ9bOzggsmAc1mx8f/RBedEALDo68M4Oq3sKHEa86SllmCJSeunZP NWZTSsCn8lYLC3SsrnmwcYDqxo5GUeUINipItX9awmEimHCpZX53C9bZbaqaKBjou0UHkeccyaza APfMzwnSQ0F3LFTGlE6A86w2/Lo8baN+TZpPili+GJ4/AZ9Qj+9a8ba8uD4UYMQqtvkbJPoXbvyE qZkZkulKB+bPwdtsJvCNhlsNWhd1eOxhYsiZ60+D6z00LZ+iMLgbNlnTG/QIR6Uv2njrnJL4+1t3 ZM6xa5oEfCLRPp59l0VT6b/o6r/4jKxMzUjeERsYE63xZvHlE4w65mDNgDz3ofz3ebdaYaMBp8UH euub2/Ed+iQH5dpD0H/s4YIXpz9DVmeZMzDq9Ipaq3pXDWTVLtkV7hvmuedIL20kVuV/6kCwnaOt yrA0NaFw5Ba/OPkGCLud5iEMeGo7G4Gl5hvHCG1NTaPMR5M7EX621ZhMdzvdYye+mCsE0QL5XF2D 15BIZj0Rxvr7H73Za/9cpDiP7oyKTIWOD6VwugHxfQbT6DwWP6xmhP0z7EZFQ4OXl5i0ij0dP5yp Ergr/GFk39tg305YCv2PeIUkaTrJM3VcTqLnUUp0e9EWD2CvyGsv7X2PKBc38IL1+NYj2FaJvwti nBgE6vt8V0jrc/S+EdMeiJ7ZHRJi/McFrxC9YUEGRzBVCUHggBr0pKnMev3MeLw8HGKjmumiMfCl W1cdYhIfdXBFpAyjKdOkWE5wz8bfKPBcrngysWte2yiHL73wRgmJy4di9HVvuVpdJtKT1QTG93uo g9r9MMHB7HcUYhZ+bqux75qTrIWpyKN71X/Vb4S5WrS2Sp+crfa2oSELmxmfKOjcvFB79ytkIQmw Az0A2oTB6ULF3HdLke1PCIgRR/uVFXgT4dbGfkbp67xK720KMYv3bYulxtjm8rY23ZitD+drkXNq S6BWRBRrHWqpUonv0UH3byYO2SJoC4x11m+kkJuqDmEOtlKq77VFJW7YLL43/mdQwtA34OR2If4g OoOZYvnVl9c7bK8qi5SZVJmCrj94ZYw8nwvNI09VA1DbcdjTTLGBlCRoXzdalt4IivuW/zLN0ovj +5JRXEomc610OqjT0K9bOW4QDx3xHeYCHTJP5w/KYn8XN/bgOTczoSVqv8fwGKadRE8B+BMMtHAS SH8jZuX9YWyf0RZKsf3lTiTZIGBHKODcPiPh21cOmDoRVqAdIb9M+9X9tnVsMYOLGh/u/81oEwvC zAYffQAApL3n6pirQrUCIWl2BcZFrxrS7nE8UIRhuAmwzNGB9CTBCnUJTCRi73gIACTRqBv0LyYn 6PxLxfIiG7GJXdqzxub8wfKCNpUnR+ivMEs2cH/yfuwtfH+P9HzEsmIK8X9I4uvyVkqUtyMQm49C l4ko5cgZIBVjy4GweWsBq7O2qnwDmr6vMJNd5602ErRGvQJlKq7w5VpDzqbVIuSm1yhzDapPrshZ YLdqrfqSa/7H7D5XvXFbg5MKNfplqno5XUF/A2synExNV+LkOtCPfOJ8F03mYqrmrURL8MXouFUK TDMSDZScTDbdDKSHGydODQf/1TbnZOH79zy0N/Un5rsMAuXm43oL39N3F3SZrkSRqs3PfDacCUw+ qEr2XLAjAkiuH8UW9GUOLd3jdE7+Jf+pl4NT/jEmd3cKTlEtz0c+hOYCIWU1Q5hdb3w7pdBO2L8R SpnjRDUQlLwsM3qTyu7OAgqnWZgdbOzv7zqag/vpW/tv+/vJrdSUMwUU474zG7Z2FGhLfOZQYv1E c8fSSAW5znYNeNyBcfiLG9u1Am15o7zdF6nHUSrq4Qsh3kBxKu4lIUj/wXol4VL5F0I10JpCuxVM Hx7ufx+X4J5QoZ7iLsTBvULx3Bjl1NCNELIz5nDk+BPUcgs1kzzeLoxkTU9OCNe07lXPtpjgclX/ oLn96AdD/G3Ub+OSbjmtm9qjpW8NdyBzGecGRd0CSB7lk6NA5fICtbB+eJe4yTdiHiPgYA65reJj XU/BDPsRveB8ROva/kCLYUveffrK4tBNwvdpbnGsYPrxelNSChWjKxOjp8vOI+pAOSPiqZWUj2rg rR4KevOHnA3ZDd4493h010OSeRLcFbQHgLRqjOZzUGAMM8VxzZEOh4HzfK0VH2b1V7fcjyyMBT13 V7IVHVfZa7L9xLMQ62hyHBWmIPA/zf0hoUWKska0Ao8B0Y70M9oMxcb2lDhvstYpWKYJpK1hdPeG eSWOS3UwTVcn6cX3uoVuNrGVKyAEz1OkWYwXiRsMYCaEkYp3/cgCEyk3Lcr0D+QRTyaIYkek0D/5 fh5ceThCpJnaycQpujgfCwCn3PNFXeCNWwR8bN/+dNptJtJyriN1+raVUIQjw1M4qVl+Ejc2eMhX Knjhj+iIsR1C7scCU3NdgmzUIBg7l4qAV2lAabpCXajAdtpFSfAyVHL08K1p9xhVkP3oufSNY3xR t/s80WuieHHQbpZsbfJ4GNJCcmJrlaxf+BfTF0aZGMVxa22XfheO4rIRrzdEwvkv4MM0UJFlGI8w wz4nrwICq2YbD+PsjmNat+Um21eDBde4KBdfdkB8a2MjaKxp58N2cc0NEefMMhz4J3gBjVA72yTt xC9/NvA2BAHTe5GWCONex9y4x9X/kIIE9lLCbkNQ7RZf3A2dVzVFyQWdVKayRbPznxAA25Zszxqk 3OD6YidsaxxHFospEOh12DSiv7DYXUj8a0IMzFnzWEq/q+e/TX3I3OKikojTHF5fjo37ZtdrAvMm Lz83aAx7s5bghOjbCOG714ZpMFQNzBkRvA2IMzL0YYjkWvfttV8/XkgrCMC8Bd5eYMFMfp7Gn7BV lmr/6Q0FhkdS+TJ3PdzydpRy8JKGN9jZDJwKWXr+9IrSXbsPlqazDZh8a8PyD0vnMxwzMbXpVn3+ V1UgTwtR0MCY9VH6CG6wWvy3HQgfU+pyXUtNr/Mlq+TFXY7b1wWWYR72yERuDhHPqnKw4ZIelsjP BOfrtxCnl502LOmZsI+grJfWGLA81OTp9vSGs4+hUn2ALIvu5C5JtsjvMNzwWgiIsG6deYYvJCsX ygRigJbNQx+AQs/ymicLg40Ts4o4Cay5J/LgMEZDwjOHdz1UNndZ3vyImtaVq+36aK/Ix/hlSRQd rIpWMo62pdQXsSDcAN2DTPOMHSGExv/jlm91f1Xp/92obXr/vr2JcjT7+wI2AnNzUBIDRcpNHGM+ T7311nEjJgzAHS9jo4MKrMJgyYrbUb4RPjtJKU9svIyVww6Hz8UAM1d9zTPxAOXUihdsozI9aZx/ kJX2f0IXnUMkjzB2vyl/cKZD5u3LtldmMdrXpC7s9u/NE77ys9mIPXVOE08Z33pPnhBpcOnc8cGF aIE0UF5jhhxEKF3r7bc/rIHdPKzien+XsPyUTaO2WlM4hCvFsjLD6zQ9+qxwkTbpgORyyrmWNMpW s9L2EOowidG7sLuSdoRIEXDTkdKKYoXP42C+oue+nJi+83lAzByxjGBO3+yGhOVlXczk3wn4oXCK ebkiwwkKfZb7wBfeq1rVwpyGaqnisnDXEPxDvH/NxqN8sq0oCDqqZuEsez7dc3nyjBo1YAXyNips a7twkYbr/drXebdcIPOc2BhjZcGmzHr2EiAqejTsZzAvKgo+3L8MBDHX8SJ4ZCF9gRMt+l1LHwxV bpzziy0gNcNpLrYCWmXY9b1rjusKnrzKYY+kb+ROIgajJsMVASsv020HkRc3Y3nkQZgkFKEgih6v 2vYImbk3Yl1FesUvLktoH8Jxo3CqvtMGKsgasGoTn7E/rPy8p6YmmBEiOti/Qb/ZU0ammiOcxEH4 7oftQr4CgmysjMn4foaekZrAxyzWpsPlXJ15M0ouJsD5jQ1ZhWTlgFa504qMsElqzJhgX0tz2Dwa By5zTNtZUSDsvvss6bZhBSrOxovyfx+GG2Vh4YjdKQZCOZ0XvS25hSzE1utwpG1AK+22pb+hwlza uh+Di6B8Rn0GlQqWg/R8yxTSXcJ+CTeWrK/x6xh2EKaCZedSR8jf5i0iFhVgJ2sYbkodjWrITVlY UbnzzX7u5IiaHyqcsHbwO3EKLqg2a/AF4wccgKQS7eyJmzmwmeAi7VYuRY2dE+36R/2Pd9AlyHXh Cp3xhmtVmyKvjhyAkgTwYN9Bx9KKRRsSxhl4bQq9KDwUWIsQWiEqByyFFXp1/7fFsftxkTWXiCcJ eR2683/pyx5DMpIs+LWCq3TweJwvDos02h2sQNz9icaNP24IyawwCUPbg1vPiAXLpQ+d/WkOiYtT YjdqeU03QsxA+Dqqhbb/TWWF1621pCZFuonMmKNKuEMQdBd8jqAbEb2mxZb1TnA1p3vu6QPivDcV Ykkvw/58ysRBMRbwNglVImP/4T007jw3domVIlrmcO5KU71ra+yZ+Wa8X32sYi2T0dIMwAGt3ffG w2AxsQJgdTwt4rXJfYHxHheRSg6zmzqIGMyUhCQvSWeQjGI5f7KRWE1uyB9tUh9a4oGzRsI8UPOj WklGy5XH3B1+hOQaM9lm2kxZmWy4i1V0+3GKU8UdICIeVFcRt8CDd68ylZjiS3HQEgU4hmrzIMw0 Tpu7ZBlNKgrkJpKERQ8knOu2wAHckdMGBbS7c8DXdDd2Ygbk2y6IvLtPFUiVrmGqHIhvyxtP1mV8 L+QxntlZJx09TvpTz9AaHUIPRHR+tT+G68XsMwRPwrSIB7v1q0rzfn/6yut+4vIVCfx5yaZS1Dy7 hl5GnIxheSufHDpJ6Mlhr1qePXF2DMcHkqVBW4yKVImtAXH6rX6lYbUx0nN7F1OOwLefOkkJUVgl EC+hgmE49ZdVuC4lTtK30wMCzKNBE91d4uO/Kw/UL3Y8s1Bw4HLTOW+w3s+fIeYVujbD4iLBk6p/ tF/y8fkSLlJfhXOicjiNp0FXWs2Kl3neJGXP/UslODvzTFkDwtP9BrV7SxBH2M9LXlb0dIhb6DSS obwCqMs/jwA2SElDYMNTPAuuCwXk+rp+V+7zJ4LW9uURcoJekZpH8t7XzfbcKKCRiP6qaoDYzLUl ULonas2dbp/NgtvRuvzaKJrL0veahdH2WIdqNQaCx9IWU7EYVUSZnIUvQWkwAUwjLddyWzzHA4gM SY1TsSsrT9xwIgFnKR5vDZrcsrQmklQZMPwr9OCnAI1952l1cYFHaKmhbHObHq1gfAJVgaj6cSA2 sWQYPFMkzFso+1PtUW8inV4Llf+tRFeU+FhbXJe3DACgwkAifMd+UVH6ir7YiM0Pk17Tu7KDRBZj AdaeqoXv7wGEC1jwpLi0DXEkx3ixG8vLNsZJXQXCsd7nOhi+o0CYCFiC2A6UCIB6Bwu2DiGdqXDI 7iJNM9QEB1g4yXp7iTkdGkyXlzo9b9jMX2LFet1ut0g/4GWMoRVRg9aLMfRasPuiLG+l9RFN2aRD 3rKwlAsEPhJoaWQh9+AYTOYAFkYCqM2xLv1ywsO3ljuabiFOR8ZcS/ZbufuxNVZ4g0rpwNR9r1Z9 Y/o4DcV0dVGEk0e37G72MpZUAicUHd7bIOO2QO+GceYOTItjX1i+ZpdeMglywenzgZ6/EfyFjvQo fv9l2i3mOGSWqSy6DNCrogGk7GP1bOSXwkLK7P5c `pragma protect end_protected `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif