-------------------------------------------------------
--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
--! @version 6.0
--! @brief GBT-FPGA IP - Tx gearbox (Latency-optimized)
-------------------------------------------------------

-- IEEE VHDL standard library:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

-- Custom libraries and packages:
use work.vendor_specific_gbt_bank_package.all;
use work.gbt_bank_package.all;

--! @brief GBT_tx_gearbox_latopt - Tx gearbox (Latency-optimized)
--! @details 
--! The GBT_tx_gearbox_latopt module ensure the frameclock to transceiver's wordclock
--! clock domain crossing with fixed and low latency.
entity gbt_tx_gearbox is
--	generic (TX_OPTIMIZATION									: integer range 0 to 1 := STANDARD);
  port (
  
		--================--
		-- Reset & Clocks --
		--================--    
		
		-- Reset:
		---------
		
		TX_RESET_I                                : in  std_logic;

		-- Clocks:
		----------
		
		TX_WORDCLK_I                              : in  std_logic;
--		TX_FRAMECLK_I                             : in  std_logic;
		TX_CLKEN_i                                : in  std_logic;
      
		--=========--
		-- Status  --
		--=========--
		TX_PHALIGNED_O										: out std_logic;
		TX_PHCOMPUTED_O									: out std_logic;
		
      --==============--
      -- Frame & Word --
      --==============--
      
		TX_FRAME_I                                : in  std_logic_vector(119 downto 0);
		TX_WORD_O                                 : out std_logic_vector(WORD_WIDTH-1 downto 0)
   
   );
end gbt_tx_gearbox;

--! @brief GBT_tx_gearbox_latopt - Tx gearbox (Standard - Read/Write control)
--! @details The GBT_tx_gearbox_latopt uses a single register to ensure the clock domain crossing
--! The reset signal is used to synchronize the counter with the rising edge of the frameclock. It
--! also implements a process to check the clock phase and the data integrety.
architecture behavioral of gbt_tx_gearbox is

   --================================ Signal Declarations ================================--

signal txFrame_from_frameInverter            : std_logic_vector (119 downto 0);		
   --=====================================================================================--  
signal address : integer range 0 to 5 := 0;
signal ready : std_logic := '0';

--=================================================================================================--
begin                 --========####   Architecture Body   ####========-- 
--=================================================================================================--  
   
   --==================================== User Logic =====================================--   
TX_PHCOMPUTED_O	<= '1';
TX_PHALIGNED_O <= '1';
		 
		 -- Comment: Note!! The reset of the gearbox is synchronous to TX_FRAMECLK in order to align the address 0 
		 --                 of the gearbox with the rising edge of TX_FRAMECLK after reset.   
	process(TX_RESET_I, TX_WORDCLK_I)
	begin
		if TX_RESET_I = '1' then
			address <= 0;
			ready <= '0';
			TX_WORD_O <= (others => '0');
			txFrame_from_frameInverter <= (others => '0');
		elsif rising_edge(TX_WORDCLK_I) then
			if(TX_CLKEN_I = '1')then
				ready <= '1';
				for i in 0 to 119 loop
					txFrame_from_frameInverter(i) <= TX_FRAME_I(119-i);
				end loop;
				address <= 0;
			elsif ready = '1' then
				address <= address + 1;
			end if;
			TX_WORD_O <= txFrame_from_frameInverter(WORD_WIDTH*(address+1)-1 downto WORD_WIDTH*address);
		end if;
	end process;
--end generate txGearboxLatOpt_gen;   
   --=====================================================================================--
end behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--