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--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
--! @version 6.0
--! @brief GBT-FPGA IP - Rx Gearbox
-------------------------------------------------------

--! Include the IEEE VHDL standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Include the GBT-FPGA specific packages
use work.gbt_bank_package.all;
use work.vendor_specific_gbt_bank_package.all;

--! @brief GBT_rx_gearbox - Rx Gearbox
--! @details 
--! The Rx gearbox module is used to ensure the MGT to Datapath clock domain
--! crossing. It takes the 20/40bit words in input and generates an 120bit
--! word every 3/6 clock cycle.
entity gbt_rx_gearbox is
  generic ( 
    RX_OPTIMIZATION           : integer range 0 to 1 := STANDARD               --! RX_OPTIMIZATION: Latency mode for the Rx path (STANDARD or LATENCY_OPTIMIZED)
  );
  port (  
    --================--
    -- Reset & Clocks --
    --================--    
    RX_RESET_I                : in  std_logic;                                  --! Reset the Rx gearbox (Asynchronous)
    RX_WORDCLK_I              : in  std_logic;                                  --! Recovered clock from data generated by the transceiver
    --==============--
    -- Control      --
    --==============--
    RX_HEADERFLAG_i           : in  std_logic;                                  --! Pulsed during the clock cycle of the header
    READY_O                   : out std_logic;
	 
    --==============--
    -- Word & Frame --
    --==============--      
    RX_WORD_I                 : in  std_logic_vector(WORD_WIDTH-1 downto 0);    --! 20/40bit word from the transceiver
    RX_FRAME_O                : out std_logic_vector(119 downto 0)              --! 120bit aligned to be decoded
      
   );   
end gbt_rx_gearbox;

--! @brief GBT_rx_gearbox architecture - Rx Gearbox
--! @details Two gearboxes can be implemented to ensure the clock domain crossing:
--!     * *Standard mode*: The standard mode is based on a device specific IP in order to simplify the clock domain crossing. Nevertheless, this method increases the latency and might be not fix depending on the manufacturer.
--!     * *Latency Optimized*: The latency optimized mode is based on a single register where the word is saved before being pushed in output at the header flag clock cycle. 
architecture structural of gbt_rx_gearbox is
signal reg0               : std_logic_vector (119-WORD_WIDTH downto 0);
signal reg1               : std_logic_vector (119 downto 0);
signal firstOut           : std_logic;
attribute MARK_DEBUG : string;
attribute MARK_DEBUG of firstOut : signal is "true";
begin
   
   --==================================== User Logic =====================================--
gbRegMan_proc: process(RX_RESET_I, RX_WORDCLK_I)
variable cnter : integer range 0 to GBT_WORD_RATIO-1;
begin
		if RX_RESET_I = '1' then
			reg0        <= (others => '0');
			reg1        <= (others => '0');
			READY_O  		<= '0';
			cnter       := 0;
			firstOut  <= '0';
		elsif rising_edge(RX_WORDCLK_I) then		
			if cnter = GBT_WORD_RATIO-1 then					
				reg1      <= RX_WORD_I & reg0(WORD_WIDTH*cnter-1 downto 0);
				READY_O 	<= firstOut;
			end if;						
			if RX_HEADERFLAG_i = '1' then					
				firstOut  <= '1';
				cnter 		:= 1;
			end if;
				if cnter /= GBT_WORD_RATIO-1 then
					reg0((WORD_WIDTH*(1+cnter))-1 downto (WORD_WIDTH*cnter)) <= RX_WORD_I;
				end if;
			if RX_HEADERFLAG_i = '1' or firstOut = '1' then
				cnter := cnter + 1;
			end if;
			if cnter = GBT_WORD_RATIO then
				cnter := 0;
			end if;
		end if;		
end process;
frameInverter: for i in 119 downto 0 generate
		RX_FRAME_O(i) <= reg1(119-i);
end generate;
   
  
   --=====================================================================================--   
end structural;
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