library ieee; use ieee.std_logic_1164.all; entity tri_mode_eth_mac_v5_5 is PORT ( glbl_rstn : IN STD_LOGIC; rx_axi_rstn : IN STD_LOGIC; tx_axi_rstn : IN STD_LOGIC; rx_axi_clk : IN STD_LOGIC; rx_reset_out : OUT STD_LOGIC; rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); rx_axis_mac_tvalid : OUT STD_LOGIC; rx_axis_mac_tlast : OUT STD_LOGIC; rx_axis_mac_tuser : OUT STD_LOGIC; rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); rx_statistics_valid : OUT STD_LOGIC; tx_axi_clk : IN STD_LOGIC; tx_reset_out : OUT STD_LOGIC; tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); tx_axis_mac_tvalid : IN STD_LOGIC; tx_axis_mac_tlast : IN STD_LOGIC; tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); tx_axis_mac_tready : OUT STD_LOGIC; tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0); tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); tx_statistics_valid : OUT STD_LOGIC; pause_req : IN STD_LOGIC; pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0); speed_is_100 : OUT STD_LOGIC; speed_is_10_100 : OUT STD_LOGIC; gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_tx_en : OUT STD_LOGIC; gmii_tx_er : OUT STD_LOGIC; gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_rx_dv : IN STD_LOGIC; gmii_rx_er : IN STD_LOGIC; rx_mac_config_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0); tx_mac_config_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0) ); END tri_mode_eth_mac_v5_5; architecture rtl of tri_mode_eth_mac_v5_5 is COMPONENT soft_emac PORT( reset : IN std_logic; phyemacrxd : IN std_logic_vector(7 downto 0); phyemacrxdv : IN std_logic; phyemacrxer : IN std_logic; clientemactxd : IN std_logic_vector(7 downto 0); clientemactxdvld : IN std_logic; clientemactxdlast : IN std_logic; clientemactxerr : IN std_logic; txgmiimiiclk : IN std_logic; rxgmiimiiclk : IN std_logic; emacphytxd : OUT std_logic_vector(7 downto 0); emacphytxen : OUT std_logic; emacphytxer : OUT std_logic; emacclienttxready : OUT std_logic; emacclientrxd : OUT std_logic_vector(7 downto 0); emacclientrxdvld : OUT std_logic; emacclientrxdlast : OUT std_logic; emacclientrxerr : OUT std_logic ); END COMPONENT; begin rx_reset_out <= '0'; rx_statistics_vector <=(others => '0'); rx_statistics_valid <= '0'; tx_reset_out <= '0'; tx_statistics_vector <= (others => '0'); tx_statistics_valid <= '0'; speed_is_100 <= '0'; speed_is_10_100 <= '0'; i_mac: soft_emac port map( reset => not glbl_rstn, emacphytxd => gmii_txd, emacphytxen => gmii_tx_en, emacphytxer => gmii_tx_er, phyemacrxd => gmii_rxd, phyemacrxdv => gmii_rx_dv, phyemacrxer => gmii_rx_er, clientemactxd => tx_axis_mac_tdata, clientemactxdvld => tx_axis_mac_tvalid, clientemactxdlast => tx_axis_mac_tlast, clientemactxerr => tx_axis_mac_tuser(0), emacclienttxready => tx_axis_mac_tready, emacclientrxd => rx_axis_mac_tdata, emacclientrxdvld => rx_axis_mac_tvalid, emacclientrxdlast => rx_axis_mac_tlast, emacclientrxerr => rx_axis_mac_tuser, txgmiimiiclk => tx_axi_clk, rxgmiimiiclk => rx_axi_clk ); end rtl;