-- Contains the instantiation of the Xilinx MAC & 1000baseX pcs/pma & GTP transceiver cores -- -- Do not change signal names in here without correspondig alteration to the timing contraints file -- -- Dave Newbold, April 2011 -- -- $Id$ library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.VComponents.all; entity eth_7s_1000basex is port( clk125 : in std_logic; clk62_5 : in std_logic; gtrefclk : in std_logic; gtx_txp : out std_logic; gtx_txn : out std_logic; gtx_rxp : in std_logic; gtx_rxn : in std_logic; -- mac_clk_o : out std_logic; rst_i : in std_logic; mmcm_locked : in std_logic; locked_o : out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_valid : in std_logic; tx_last : in std_logic; tx_error : in std_logic; tx_ready : out std_logic; rx_data : out std_logic_vector(7 downto 0); rx_valid : out std_logic; rx_last : out std_logic; rx_error : out std_logic ); end eth_7s_1000basex; architecture rtl of eth_7s_1000basex is COMPONENT gig_ethernet_pcs_pma_0 PORT ( gtrefclk : IN STD_LOGIC; txn : OUT STD_LOGIC; txp : OUT STD_LOGIC; rxn : IN STD_LOGIC; rxp : IN STD_LOGIC; independent_clock_bufg : IN STD_LOGIC; txoutclk : OUT STD_LOGIC; gtpowergood : OUT STD_LOGIC; rxoutclk : OUT STD_LOGIC; resetdone : OUT STD_LOGIC; cplllock : OUT STD_LOGIC; mmcm_reset : OUT STD_LOGIC; userclk : IN STD_LOGIC; userclk2 : IN STD_LOGIC; pma_reset : IN STD_LOGIC; mmcm_locked : IN STD_LOGIC; rxuserclk : IN STD_LOGIC; rxuserclk2 : IN STD_LOGIC; gmii_txd : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_tx_en : IN STD_LOGIC; gmii_tx_er : IN STD_LOGIC; gmii_rxd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_rx_dv : OUT STD_LOGIC; gmii_rx_er : OUT STD_LOGIC; gmii_isolate : OUT STD_LOGIC; configuration_vector : IN STD_LOGIC_VECTOR(4 DOWNTO 0); status_vector : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); reset : IN STD_LOGIC; signal_detect : IN STD_LOGIC ); END COMPONENT; COMPONENT tri_mode_eth_mac_v5_5 PORT ( glbl_rstn : IN STD_LOGIC; rx_axi_rstn : IN STD_LOGIC; tx_axi_rstn : IN STD_LOGIC; rx_axi_clk : IN STD_LOGIC; rx_reset_out : OUT STD_LOGIC; rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); rx_axis_mac_tvalid : OUT STD_LOGIC; rx_axis_mac_tlast : OUT STD_LOGIC; rx_axis_mac_tuser : OUT STD_LOGIC; rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); rx_statistics_valid : OUT STD_LOGIC; tx_axi_clk : IN STD_LOGIC; tx_reset_out : OUT STD_LOGIC; tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); tx_axis_mac_tvalid : IN STD_LOGIC; tx_axis_mac_tlast : IN STD_LOGIC; tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); tx_axis_mac_tready : OUT STD_LOGIC; tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0); tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); tx_statistics_valid : OUT STD_LOGIC; pause_req : IN STD_LOGIC; pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0); speed_is_100 : OUT STD_LOGIC; speed_is_10_100 : OUT STD_LOGIC; gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_tx_en : OUT STD_LOGIC; gmii_tx_er : OUT STD_LOGIC; gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_rx_dv : IN STD_LOGIC; gmii_rx_er : IN STD_LOGIC; rx_mac_config_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0); tx_mac_config_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0) ); END COMPONENT; signal gmii_txd, gmii_rxd: std_logic_vector(7 downto 0); signal gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er: std_logic; signal gmii_rx_clk: std_logic; signal phy_done: std_logic; signal rstn: std_logic; -- signal clk125, txoutclk_ub, txoutclk, clk125_ub: std_logic; -- signal clkin, clk125, txoutclk_ub, txoutclk, clk125_ub, clk_fr: std_logic; -- signal clk62_5_ub, clk62_5, clkfb: std_logic; -- signal rstn, phy_done, mmcm_locked, locked_int, mmcm_reset, mmcm_reset_phy: std_logic; signal status: std_logic_vector(15 downto 0); signal decoupled_clk : std_logic; begin rstn <= not rst_i; process(clk125) begin if rising_edge(clk125) then locked_o <= mmcm_locked and phy_done; end if; end process; mac: tri_mode_eth_mac_v5_5 port map( glbl_rstn => rstn, rx_axi_rstn => '1', tx_axi_rstn => '1', rx_axi_clk => clk125, rx_reset_out => open, rx_axis_mac_tdata => rx_data, rx_axis_mac_tvalid => rx_valid, rx_axis_mac_tlast => rx_last, rx_axis_mac_tuser => rx_error, rx_statistics_vector => open, rx_statistics_valid => open, tx_axi_clk => clk125, tx_reset_out => open, tx_axis_mac_tdata => tx_data, tx_axis_mac_tvalid => tx_valid, tx_axis_mac_tlast => tx_last, tx_axis_mac_tuser(0) => tx_error, tx_axis_mac_tready => tx_ready, tx_ifg_delay => X"00", tx_statistics_vector => open, tx_statistics_valid => open, pause_req => '0', pause_val => X"0000", speed_is_100 => open, speed_is_10_100 => open, gmii_txd => gmii_txd, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_rxd => gmii_rxd, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, rx_mac_config_vector => X"0000_0000_0000_0000_0802", tx_mac_config_vector => X"0000_0000_0000_0000_0002" ); -- Vivado generates a CRC error if you drive the CPLLLOCKDET circuitry with -- the same clock used to drive the transceiver PLL. While this makes sense -- if the clk is derved from the CPLL (e.g. TXOUTCLK) it is less clear is -- essential if you use the clock raw from the input pins. The short story -- is that it has always worked in the past with ISE, but Vivado generates -- DRC error. Can be bypassed by decoupling the clock from the perpective -- of the tools by just toggling a flip flop, which is what is done below. phy: gig_ethernet_pcs_pma_0 port map( gtrefclk => gtrefclk, txn => gtx_txn, txp => gtx_txp, rxn => gtx_rxn, rxp => gtx_rxp, independent_clock_bufg => clk125, txoutclk => open, gtpowergood => open, rxoutclk => open, resetdone => phy_done, cplllock => open, mmcm_reset => open, userclk => clk62_5, userclk2 => clk125, pma_reset => rst_i, mmcm_locked => mmcm_locked, rxuserclk => clk62_5, rxuserclk2 => clk125, gmii_txd => gmii_txd, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_rxd => gmii_rxd, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_isolate => open, configuration_vector => "00000", status_vector => status, reset => rst_i, signal_detect => '1' ); end rtl;