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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:32:59 05/17/2019 
-- Design Name: 
-- Module Name:    DSP_counter32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

entity DSP_counterX4 is
		generic (use_sync : std_logic_vector(3 downto 0) := "1111"); 
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(3 downto 0);
           q : out  STD_LOGIC_VECTOR(47 downto 0));
end DSP_counterX4;

architecture Behavioral of DSP_counterX4 is
signal P : std_logic_vector(47 downto 0) := (others => '0');
signal C : std_logic_vector(47 downto 0) := (others => '0');
signal d_sync : std_logic_vector(3 downto 0);
begin
q <= P;
g_inc :		for i in 0 to 3 generate
	C(i*12) <= d_sync(i) xor P(i*12) when use_sync(i) = '1' else '1';
end generate;
DSP48E2_inst : DSP48E2
   generic map (
      USE_MULT => "NONE",            -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
      USE_SIMD => "FOUR12",               -- SIMD selection (FOUR12, ONE48, TWO24)
      CREG => 0,                         -- Pipeline stages for C (0-1)
      MREG => 0)                         -- Multiplier pipeline stages (0-1)
   port map (
      P => P,                           -- 48-bit output: Primary data
      -- Cascade inputs: Cascade Ports
      ACIN => (others => '0'),                     -- 30-bit input: A cascade data
      BCIN => (others => '0'),                     -- 18-bit input: B cascade
      CARRYCASCIN => '0',       -- 1-bit input: Cascade carry
      MULTSIGNIN => '0',         -- 1-bit input: Multiplier sign cascade
      PCIN => (others => '0'),                     -- 48-bit input: P cascade
      -- Control inputs: Control Inputs/Status Bits
      ALUMODE => "0000",               -- 4-bit input: ALU control
      CARRYINSEL => "000",         -- 3-bit input: Carry select
      CLK => clk,                       -- 1-bit input: Clock
      INMODE => "00000",                 -- 5-bit input: INMODE control
      OPMODE => "000001110",                 -- 9-bit input: Operation mode
      -- Data inputs: Data Ports
      A => (others => '1'),                           -- 30-bit input: A data
      B => (others => '1'),                           -- 18-bit input: B data
      C => C,                           -- 48-bit input: C data
      CARRYIN => '0',               -- 1-bit input: Carry-in
      D => (others => '1'),                           -- 27-bit input: D data
      -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
      CEA1 => '0',                     -- 1-bit input: Clock enable for 1st stage AREG
      CEA2 => '0',                     -- 1-bit input: Clock enable for 2nd stage AREG
      CEAD => '0',                     -- 1-bit input: Clock enable for ADREG
      CEALUMODE => '1',           -- 1-bit input: Clock enable for ALUMODE
      CEB1 => '0',                     -- 1-bit input: Clock enable for 1st stage BREG
      CEB2 => '0',                     -- 1-bit input: Clock enable for 2nd stage BREG
      CEC => '1',                       -- 1-bit input: Clock enable for CREG
      CECARRYIN => '1',           -- 1-bit input: Clock enable for CARRYINREG
      CECTRL => '1',                 -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
      CED => '0',                       -- 1-bit input: Clock enable for DREG
      CEINMODE => '1',             -- 1-bit input: Clock enable for INMODEREG
      CEM => '0',                       -- 1-bit input: Clock enable for MREG
      CEP => '1',                       -- 1-bit input: Clock enable for PREG
      RSTA => '0',                     -- 1-bit input: Reset for AREG
      RSTALLCARRYIN => '0',   -- 1-bit input: Reset for CARRYINREG
      RSTALUMODE => '0',         -- 1-bit input: Reset for ALUMODEREG
      RSTB => '0',                     -- 1-bit input: Reset for BREG
      RSTC => '0',                     -- 1-bit input: Reset for CREG
      RSTCTRL => '0',               -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
      RSTD => '0',                     -- 1-bit input: Reset for DREG and ADREG
      RSTINMODE => '0',           -- 1-bit input: Reset for INMODEREG
      RSTM => '0',                     -- 1-bit input: Reset for MREG
      RSTP => reset                      -- 1-bit input: Reset for PREG
   );
g_sync : for i in 0 to 3 generate
	g_cdc :	if use_sync(i) = '1' generate
			xpm_cdc_single_inst : xpm_cdc_single
				generic map (
					DEST_SYNC_FF => 4,   -- DECIMAL; range: 2-10
					INIT_SYNC_FF => 1,   -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
					SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
					SRC_INPUT_REG => 0   -- DECIMAL; 0=do not register input, 1=register input
				)
				port map (
					dest_out => d_sync(i), -- 1-bit output: src_in synchronized to the destination clock domain. This output
																-- is registered.
					dest_clk => clk, -- 1-bit input: Clock signal for the destination clock domain.
					src_clk => '0',   -- 1-bit input: optional; required when SRC_INPUT_REG = 1
					src_in => din(i)      -- 1-bit input: Input signal to be synchronized to dest_clk domain.
				);
	end generate g_cdc;
	g_no_sync : if use_sync(i) = '0' generate
		d_sync(i) <= din(i);
	end generate g_no_sync;
end generate g_sync;
end Behavioral;