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-- Company: 
-- Engineer: 
-- 
-- Create Date: 05/19/2019 09:43:11 AM
-- Design Name: 
-- Module Name: DSP_MUX - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity DSP_MUX_C_b is
    Port (clk : in std_logic;
    			 ce : in std_logic;
    			 DinA : in STD_LOGIC_VECTOR (47 downto 0);
           DinB : in STD_LOGIC_VECTOR (47 downto 0);
           S : in STD_LOGIC_VECTOR (1 downto 0);
           PCOUT : out STD_LOGIC_VECTOR (47 downto 0);
           Dout : out STD_LOGIC_VECTOR (47 downto 0));
end DSP_MUX_C_b;

architecture Behavioral of DSP_MUX_C_b is
signal OPMODE : std_logic_vector(8 downto 0) := (others => '0');
begin
OPMODE(3 downto 2) <= "11" when S = "11" else "00";
OPMODE(1 downto 0) <= "11" when S = "10" else "00";
   DSP48E2_inst : DSP48E2
   generic map (
      USE_MULT => "NONE",            -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
      -- Register Control Attributes: Pipeline Register Configuration
      ALUMODEREG => 0,                   -- Pipeline stages for ALUMODE (0-1)
      CARRYINREG => 0,                   -- Pipeline stages for CARRYIN (0-1)
      CARRYINSELREG => 0,                -- Pipeline stages for CARRYINSEL (0-1)
      INMODEREG => 0,                    -- Pipeline stages for INMODE (0-1)
      MREG => 0,                         -- Multiplier pipeline stages (0-1)
      OPMODEREG => 0,                    -- Pipeline stages for OPMODE (0-1)
      PREG => 0                          -- Number of pipeline stages for P (0-1)
   )
   port map (
      -- Cascade outputs: Cascade Ports
      PCOUT => PCOUT,                   -- 48-bit output: Cascade output
      -- Control outputs: Control Inputs/Status Bits
      P => Dout,                           -- 48-bit output: Primary data
      -- Cascade inputs: Cascade Ports
      ACIN => (others => '0'),                     -- 30-bit input: A cascade data
      BCIN => (others => '0'),                     -- 18-bit input: B cascade
      CARRYCASCIN => '0',       -- 1-bit input: Cascade carry
      MULTSIGNIN => '0',         -- 1-bit input: Multiplier sign cascade
      PCIN => (others => '0'),                     -- 48-bit input: P cascade
      -- Control inputs: Control Inputs/Status Bits
      ALUMODE => "0000",               -- 4-bit input: ALU control
      CARRYINSEL => "000",         -- 3-bit input: Carry select
      CLK => clk,                       -- 1-bit input: Clock
      INMODE => "00000",                 -- 5-bit input: INMODE control
      OPMODE => OPMODE,                 -- 9-bit input: Operation mode
      -- Data inputs: Data Ports
      A => DinA(47 downto 18),                           -- 30-bit input: A data
      B => DinA(17 downto 0),                           -- 18-bit input: B data
      C => DinB,                           -- 48-bit input: C data
      CARRYIN => '0',               -- 1-bit input: Carry-in
      D => (others => '1'),                           -- 27-bit input: D data
      -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
      CEA1 => '0',                     -- 1-bit input: Clock enable for 1st stage AREG
      CEA2 => ce,                     -- 1-bit input: Clock enable for 2nd stage AREG
      CEAD => '0',                     -- 1-bit input: Clock enable for ADREG
      CEALUMODE => '0',           -- 1-bit input: Clock enable for ALUMODE
      CEB1 => '0',                     -- 1-bit input: Clock enable for 1st stage BREG
      CEB2 => ce,                     -- 1-bit input: Clock enable for 2nd stage BREG
      CEC => ce,                       -- 1-bit input: Clock enable for CREG
      CECARRYIN => '0',           -- 1-bit input: Clock enable for CARRYINREG
      CECTRL => '0',                 -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
      CED => '0',                       -- 1-bit input: Clock enable for DREG
      CEINMODE => '0',             -- 1-bit input: Clock enable for INMODEREG
      CEM => '0',                       -- 1-bit input: Clock enable for MREG
      CEP => '0',                       -- 1-bit input: Clock enable for PREG
      RSTA => '0',                     -- 1-bit input: Reset for AREG
      RSTALLCARRYIN => '0',   -- 1-bit input: Reset for CARRYINREG
      RSTALUMODE => '0',         -- 1-bit input: Reset for ALUMODEREG
      RSTB => '0',                     -- 1-bit input: Reset for BREG
      RSTC => '0',                     -- 1-bit input: Reset for CREG
      RSTCTRL => '0',               -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
      RSTD => '0',                     -- 1-bit input: Reset for DREG and ADREG
      RSTINMODE => '0',           -- 1-bit input: Reset for INMODEREG
      RSTM => '0',                     -- 1-bit input: Reset for MREG
      RSTP => '0'                      -- 1-bit input: Reset for PREG
   );


end Behavioral;