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-- Company: 
-- Engineer: 
-- 
-- Create Date: 03/13/2020 11:17:25 AM
-- Design Name: 
-- Module Name: stat_reg_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ngFEC_pack.all;

library UNISIM;
use UNISIM.VComponents.all;

entity stat_reg_block is
		generic (sim : boolean := true);
    Port ( clk : in STD_LOGIC;
           ipb_clk : in STD_LOGIC;
           ipb_rst : in STD_LOGIC;
           rx_wordclk : in STD_LOGIC_VECTOR (47 downto 0);
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           cntr_din : in STD_LOGIC_VECTOR (511 downto 0);
           rate_din : in STD_LOGIC_VECTOR (255 downto 0);
           stat_reg_in : in array_512x32bit;
          test_com : in STD_LOGIC_VECTOR (47 downto 0);
           ipb_mosi_i : in	ipb_wbus;
           ipb_miso_o : out ipb_rbus);
end stat_reg_block;

architecture Behavioral of stat_reg_block is
component ipb_user_status_regs
		generic (sim : boolean := true);
    Port ( clk : in STD_LOGIC;
           ipb_clk : in STD_LOGIC;
           ipb_rst : in STD_LOGIC;
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           cntr_din : in STD_LOGIC_VECTOR (511 downto 0);
           rate_din : in STD_LOGIC_VECTOR (255 downto 0);
           stat_reg : in array_1024x32bit;
           ipb_mosi_i : in	ipb_wbus;
           ipb_miso_o : out ipb_rbus);
end component;
component DSP_dividerX2
		generic (use_sync : std_logic_vector(1 downto 0) := "11"; 
		pattern : std_logic_vector(23 downto 0) := x"000000"; 
		mask : std_logic_vector(23 downto 0) := x"ff8000");
    Port ( clk : in STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           q : out STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(1 downto 0);
           rate : out  STD_LOGIC_VECTOR(23 downto 0));
end component;
component DSP_dividerX3
		generic (use_sync : std_logic_vector(2 downto 0) := "111"; 
		pattern : std_logic_vector(15 downto 0) := x"0000"; 
		mask : std_logic_vector(15 downto 0) := x"8000");
    Port ( clk : in STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           q : out STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(2 downto 0);
           rate : out  STD_LOGIC_VECTOR(31 downto 0));
end component;
component DSP_rate_counterX3
		generic (use_sync : std_logic_vector(2 downto 0) := "111"); 
    Port ( clk : in  STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           load : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(2 downto 0);
           rate : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
signal rx_cnt : unsigned(2 downto 0) := (others => '0');
signal ngccm_cntr : unsigned(8 downto 0) := (others => '0');
signal stat_reg	: array_1024x32bit := (others => (others => '0'));
signal rx_wordclk_div2 : std_logic_vector(47 downto 0) := (others => '0');
signal rxframe_ce : std_logic_vector(47 downto 0) := (others => '0');
signal rx_frameclk_div2 : std_logic_vector(47 downto 0) := (others => '0');
signal rx_test_comm_cnt : std_logic_vector(47 downto 0) := (others => '0');
signal ngccm_status_load : std_logic_vector(47 downto 0);
type array8X16 is array(0 to 7) of std_logic_vector(15 downto 0);
type arraykNUM_SFPSX8 is array(47 downto 0) of std_logic_vector(7 downto 0);
type arraykNUM_SFPSX16 is array(47 downto 0) of std_logic_vector(15 downto 0);
type arraykNUM_SFPSX24 is array(47 downto 0) of std_logic_vector(23 downto 0);
type arraykNUM_SFPSX8X16 is array(47 downto 0) of array8X16;
signal rate_test_comm : arraykNUM_SFPSX24 := (others => (others => '0'));
signal rate_ngccm_status : arraykNUM_SFPSX8X16;
signal ngccm_status_cnt : arrayKNUM_SFPSX8 := (others => (others => '0'));
signal ngCCM_status : arraykNUM_SFPSX16 := (others => (others => '0'));

begin
	stat_regs_inst: entity work.ipb_user_status_regs
	--===========================================--
	generic map (sim => true)
	port map
	(
		clk					=> clk,
		ipb_clk					=> ipb_clk,
		ipb_rst					=> ipb_rst,
		reset_ctrl				=> reset_ctrl,
		cntr_din => cntr_din,
		rate_din => rate_din,
		stat_reg => stat_reg,
		ipb_mosi_i			=> ipb_mosi_i,
		ipb_miso_o			=> ipb_miso_o
	);
g_stat_reg0 : for i in 0 to 191 generate
	stat_reg(i)(31 downto 0) <= stat_reg_in(i)(31 downto 0);
end generate;
g_stat_reg1 : for i in 240 to 511 generate
	stat_reg(i)(31 downto 0) <= stat_reg_in(i)(31 downto 0);
end generate;
g_ngccm_status : for i in 0 to 47 generate
	ngccm_status(i)(15) <= test_com(i);
end generate;
process(rx_wordclk(0))
begin
	if(rx_wordclk(0)'event and rx_wordclk(0) = '1')then
		if(rx_cnt = "101")then
			rx_cnt <= "000";
		else
			rx_cnt <= rx_cnt + 1;
		end if;
		ngccm_cntr <= ngccm_cntr + 1;
	end if;
end process;
g_clock_rate_din : for i in 0 to 47 generate
	process(rx_wordclk(i))
	begin
		if(rx_wordclk(i)'event and rx_wordclk(i) = '1')then
			rx_wordclk_div2(i) <= not rx_wordclk_div2(i);
			if(i mod 6 = to_integer(rx_cnt))then
				RxFrame_ce(i) <= '1';
			else
				RxFrame_ce(i) <= '0';
			end if;
			if(ngccm_status_cnt(i)(15) = '0')then
				ngccm_status(i)(8 downto 0) <= (others => '0'); 
			else
				ngccm_status(i)(8 downto 0) <= std_logic_vector(ngccm_cntr); 
			end if;
			if(RxFrame_ce(i) = '1')then
				rx_frameclk_div2(i) <= not rx_frameclk_div2(i);
				if(ngccm_status(i)(15) = '1')then
					rx_test_comm_cnt(i) <= not rx_test_comm_cnt(i);
					for j in 0 to 8 loop
						if(j < 5 and ngccm_status(i)(j) = '0')then
							ngccm_status_cnt(i)(j) <= not ngccm_status_cnt(i)(j);
						end if;
						if(j > 5 and ngccm_status(i)(j) = '0')then
							ngccm_status_cnt(i)(j-1) <= not ngccm_status_cnt(i)(j-1);
						end if;
					end loop;
				end if;
			end if;
		end if;
	end process;
	i_rate_ngccm_status0: DSP_dividerX3
		PORT MAP (
      clk => clk,
      ipb_clk => ipb_clk,
      din(0) => rx_test_comm_cnt(i),
      din(1) => ngccm_status_cnt(i)(0),
      din(2) => ngccm_status_cnt(i)(1),
      q => ngccm_status_load(i),
      rate(15 downto 0) => rate_ngccm_status(i)(0),
      rate(31 downto 16) => rate_ngccm_status(i)(1)
);
	i_rate_ngccm_status1: DSP_rate_counterX3
		PORT MAP (
			clk => clk,
			ipb_clk => ipb_clk,
			load => ngccm_status_load(i),
			din(0) => ngccm_status_cnt(i)(2),
			din(1) => ngccm_status_cnt(i)(3),
			din(2) => ngccm_status_cnt(i)(4),
      rate(15 downto 0) => rate_ngccm_status(i)(2),
      rate(31 downto 16) => rate_ngccm_status(i)(3),
      rate(47 downto 32) => rate_ngccm_status(i)(4));
	i_rate_ngccm_status2: DSP_rate_counterX3
		PORT MAP (
			clk => clk,
			ipb_clk => ipb_clk,
			load => ngccm_status_load(i),
			din(0) => ngccm_status_cnt(i)(5),
			din(1) => ngccm_status_cnt(i)(6),
			din(2) => ngccm_status_cnt(i)(7),
      rate(15 downto 0) => rate_ngccm_status(i)(5),
      rate(31 downto 16) => rate_ngccm_status(i)(6),
      rate(47 downto 32) => rate_ngccm_status(i)(7));
i_rate_test_comm: DSP_dividerX2
	PORT MAP (
    clk => clk,
    ipb_clk => ipb_clk,
    din(0) => rx_frameclk_div2(i),
    din(1) => rx_test_comm_cnt(i),
    q => open,
    rate => rate_test_comm(i));
end generate g_clock_rate_din;
g_stat_reg : for i in 0 to 47 generate
	stat_reg(4*KNUM_SFPS+i) <= x"00" & rate_test_comm(i);
	g_rate_ngccm_status : for j in 0 to 7 generate
		stat_reg(j*KNUM_SFPS+i+512) <= x"0000" & rate_ngccm_status(i)(j);
	end generate g_rate_ngccm_status;
end generate g_stat_reg;
end Behavioral;