create_clock -period 3.119 -name TTC_rxusrclk [get_pins i_tcds2_if/i_mgt_wrapper/i_rxusrclk/*.bufg_gt_usrclk_inst/O]
create_clock -period 3.119 -name rx_rcvclk [get_ports TTC_rx_rcvclk_p]
create_clock -period 3.119 -name TTC_rx_refclk [get_ports TTC_rx_refclk_p]
create_clock -period 8.000 -name refclk125 [get_ports refclk125_p]
create_clock -period 24.952 -name fabric_clk [get_pins fabric_clk_bufg/O]
create_clock -period 8.317 -name tx_wordclk [get_pins tx_wordclk_bufg/O]
create_clock -period 20.000 -name DRPclk [get_pins i_DRPclk_bufg/O]
create_clock -period 8.000 -name clk125 [get_pins i_clk125_bufg/O]
create_clock -period 4.000 -name clk250 [get_pins i_clk250_bufg/O]
create_clock -period 32.000 -name ipb_clk [get_pins i_ipb_clk_bufg/O]
create_clock -period 3.119 -name GBT_refclk0 [get_ports {GBT_refclk1_p[0]}]
create_clock -period 3.119 -name GBT_refclk1 [get_ports {GBT_refclk1_p[1]}]
create_clock -period 3.119 -name GBT_refclk2 [get_ports {GBT_refclk1_p[2]}]
create_clock -period 3.119 -name GBT_refclk3 [get_ports {GBT_refclk1_p[3]}]
set_property PACKAGE_PIN V12 [get_ports rarp_en]
set_property PACKAGE_PIN W12 [get_ports board_id[0]]
set_property PACKAGE_PIN U12 [get_ports board_id[1]]
set_property PACKAGE_PIN V13 [get_ports board_id[2]]
set_property PACKAGE_PIN Y12 [get_ports board_id[3]]
set_property PACKAGE_PIN AA12 [get_ports board_id[4]]
set_property PACKAGE_PIN V14 [get_ports board_id[5]]
set_property PACKAGE_PIN W14 [get_ports board_id[6]]
set_property PACKAGE_PIN J14 [get_ports Si_SDA]
set_property PACKAGE_PIN K14 [get_ports Si_SCL]
set_property PACKAGE_PIN K13 [get_ports Si_LOLb]
set_property PACKAGE_PIN M11 [get_ports Si_IN_SEL[0]]
set_property PACKAGE_PIN L11 [get_ports Si_IN_SEL[1]]
set_property PACKAGE_PIN BE17 [get_ports {FF_TX_SDA[0]}]
set_property PACKAGE_PIN BE18 [get_ports {FF_TX_SDA[1]}]
set_property PACKAGE_PIN BD20 [get_ports {FF_TX_SDA[2]}]
set_property PACKAGE_PIN BC20 [get_ports {FF_TX_SDA[3]}]
set_property PACKAGE_PIN BD17 [get_ports {FF_TX_SCL[0]}]
set_property PACKAGE_PIN BD18 [get_ports {FF_TX_SCL[1]}]
set_property PACKAGE_PIN BA20 [get_ports {FF_TX_SCL[2]}]
set_property PACKAGE_PIN AY20 [get_ports {FF_TX_SCL[3]}]
set_property PACKAGE_PIN BC18 [get_ports {FF_RX_SDA[0]}]
set_property PACKAGE_PIN BB18 [get_ports {FF_RX_SDA[1]}]
set_property PACKAGE_PIN BC19 [get_ports {FF_RX_SDA[2]}]
set_property PACKAGE_PIN BB19 [get_ports {FF_RX_SDA[3]}]
set_property PACKAGE_PIN BB17 [get_ports {FF_RX_SCL[0]}]
set_property PACKAGE_PIN BA17 [get_ports {FF_RX_SCL[1]}]
set_property PACKAGE_PIN BA19 [get_ports {FF_RX_SCL[2]}]
set_property PACKAGE_PIN AY19 [get_ports {FF_RX_SCL[3]}]
set_property PACKAGE_PIN AY17 [get_ports {FF_TX_RESETn[0]}]
set_property PACKAGE_PIN AY18 [get_ports {FF_TX_RESETn[1]}]
set_property PACKAGE_PIN AW18 [get_ports {FF_TX_RESETn[2]}]
set_property PACKAGE_PIN AV18 [get_ports {FF_TX_RESETn[3]}]
set_property PACKAGE_PIN AV19 [get_ports {FF_RX_RESETn[0]}]
set_property PACKAGE_PIN AW17 [get_ports {FF_RX_RESETn[1]}]
set_property PACKAGE_PIN AU18 [get_ports {FF_RX_RESETn[2]}]
set_property PACKAGE_PIN AU19 [get_ports {FF_RX_RESETn[3]}]
set_property PACKAGE_PIN AW20 [get_ports {FF_TX_PRESENTn[0]}]
set_property PACKAGE_PIN AV20 [get_ports {FF_TX_PRESENTn[1]}]
set_property PACKAGE_PIN AR19 [get_ports {FF_TX_PRESENTn[2]}]
set_property PACKAGE_PIN AR20 [get_ports {FF_TX_PRESENTn[3]}]
set_property PACKAGE_PIN AU17 [get_ports {FF_RX_PRESENTn[0]}]
set_property PACKAGE_PIN AT17 [get_ports {FF_RX_PRESENTn[1]}]
set_property PACKAGE_PIN AT19 [get_ports {FF_RX_PRESENTn[2]}]
set_property PACKAGE_PIN AT20 [get_ports {FF_RX_PRESENTn[3]}]
set_property PULLUP TRUE [get_ports rarp_en]
set_property PULLUP TRUE [get_ports board_id*]
set_property IOSTANDARD LVCMOS18 [get_ports rarp_en]
set_property IOSTANDARD LVCMOS18 [get_ports board_id*]
set_property IOSTANDARD LVCMOS18 [get_ports Si_SDA]
set_property IOSTANDARD LVCMOS18 [get_ports Si_SCL]
set_property IOSTANDARD LVCMOS18 [get_ports Si_IN_SEL*]
set_property IOSTANDARD LVCMOS18 [get_ports Si_LOLb]
set_property IOSTANDARD LVTTL [get_ports FF_TX_*]
set_property IOSTANDARD LVTTL [get_ports FF_RX_*]
set_property PACKAGE_PIN AR9 [get_ports refclk125_p]
set_property PACKAGE_PIN BE5 [get_ports c2c_txp]
set_property PACKAGE_PIN AU5 [get_ports {GBT_txp[0]}]
set_property PACKAGE_PIN AT7 [get_ports {GBT_txp[1]}]
set_property PACKAGE_PIN AR5 [get_ports {GBT_txp[2]}]
set_property PACKAGE_PIN AP7 [get_ports {GBT_txp[3]}]
set_property PACKAGE_PIN AN5 [get_ports {GBT_txp[4]}]
set_property PACKAGE_PIN AM7 [get_ports {GBT_txp[5]}]
set_property PACKAGE_PIN AK7 [get_ports {GBT_txp[6]}]
set_property PACKAGE_PIN AH7 [get_ports {GBT_txp[7]}]
set_property PACKAGE_PIN AE9 [get_ports {GBT_refclk1_p[0]}]
set_property PACKAGE_PIN AF7 [get_ports {GBT_txp[8]}]
set_property PACKAGE_PIN AD7 [get_ports {GBT_txp[9]}]
set_property PACKAGE_PIN AB7 [get_ports {GBT_txp[10]}]
set_property PACKAGE_PIN Y7 [get_ports {GBT_txp[11]}]
set_property PACKAGE_PIN V7 [get_ports {GBT_txp[12]}]
set_property PACKAGE_PIN T7 [get_ports {GBT_txp[13]}]
set_property PACKAGE_PIN P7 [get_ports {GBT_txp[14]}]
set_property PACKAGE_PIN M7 [get_ports {GBT_txp[15]}]
set_property PACKAGE_PIN L5 [get_ports {GBT_txp[16]}]
set_property PACKAGE_PIN K7 [get_ports {GBT_txp[17]}]
set_property PACKAGE_PIN J5 [get_ports {GBT_txp[18]}]
set_property PACKAGE_PIN H7 [get_ports {GBT_txp[19]}]
set_property PACKAGE_PIN N9 [get_ports {GBT_refclk1_p[1]}]
set_property PACKAGE_PIN G5 [get_ports {GBT_txp[20]}]
set_property PACKAGE_PIN F7 [get_ports {GBT_txp[21]}]
set_property PACKAGE_PIN E5 [get_ports {GBT_txp[22]}]
set_property PACKAGE_PIN C5 [get_ports {GBT_txp[23]}]
set_property PACKAGE_PIN BD42 [get_ports {GBT_txp[24]}]
set_property PACKAGE_PIN BB42 [get_ports {GBT_txp[25]}]
set_property PACKAGE_PIN AY42 [get_ports {GBT_txp[26]}]
set_property PACKAGE_PIN AV42 [get_ports {GBT_txp[27]}]
set_property PACKAGE_PIN AT42 [get_ports {GBT_txp[28]}]
set_property PACKAGE_PIN AP42 [get_ports {GBT_txp[29]}]
set_property PACKAGE_PIN AM42 [get_ports {GBT_txp[30]}]
set_property PACKAGE_PIN AL40 [get_ports {GBT_txp[31]}]
set_property PACKAGE_PIN AH38 [get_ports {GBT_refclk1_p[2]}]
set_property PACKAGE_PIN AK42 [get_ports {GBT_txp[32]}]
set_property PACKAGE_PIN AJ40 [get_ports {GBT_txp[33]}]
set_property PACKAGE_PIN AG40 [get_ports {GBT_txp[34]}]
set_property PACKAGE_PIN AE40 [get_ports {GBT_txp[35]}]
set_property PACKAGE_PIN AC40 [get_ports {GBT_txp[36]}]
set_property PACKAGE_PIN AA40 [get_ports {GBT_txp[37]}]
set_property PACKAGE_PIN W40 [get_ports {GBT_txp[38]}]
set_property PACKAGE_PIN U40 [get_ports {GBT_txp[39]}]
set_property PACKAGE_PIN T42 [get_ports {GBT_txp[40]}]
set_property PACKAGE_PIN P42 [get_ports {GBT_txp[41]}]
set_property PACKAGE_PIN M42 [get_ports {GBT_txp[42]}]
set_property PACKAGE_PIN K42 [get_ports {GBT_txp[43]}]
set_property PACKAGE_PIN T38 [get_ports {GBT_refclk1_p[3]}]
set_property PACKAGE_PIN H42 [get_ports {GBT_txp[44]}]
set_property PACKAGE_PIN F42 [get_ports {GBT_txp[45]}]
set_property PACKAGE_PIN D42 [get_ports {GBT_txp[46]}]
set_property PACKAGE_PIN B42 [get_ports {GBT_txp[47]}]
set_property PACKAGE_PIN AL9 [get_ports TTC_rx_refclk_p]
set_property PACKAGE_PIN AN9 [get_ports TTC_rx_rcvclk_p]
set_property PACKAGE_PIN AT2 [get_ports TTC_rxp]
set_clock_groups -asynchronous -group [list fabric_clk tx_wordclk]
set_clock_groups -asynchronous -group [get_clocks TTC_rxusrclk]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks TTC_rx_refclk]
set_clock_groups -asynchronous -group [list clk250 ipb_clk]
set_clock_groups -asynchronous -group [get_clocks clk125]
set_clock_groups -asynchronous -group [get_clocks DRPclk]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks GBT_refclk0]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks GBT_refclk1]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks GBT_refclk2]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks GBT_refclk3]
set_max_delay -datapath_only -from [get_pins stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/CLKBWRCLK] 24.000
set_multicycle_path -setup -from [get_pins stat_regs_inst/*_DSP_MUX_*/*/CLK] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 6
set_multicycle_path -hold -from [get_pins stat_regs_inst/*_DSP_MUX_*/*/CLK] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 5
set_multicycle_path -setup -from [get_pins stat_regs_inst/S1_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 6
set_multicycle_path -hold -from [get_pins stat_regs_inst/S1_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 5
set_multicycle_path -setup -from [get_pins stat_regs_inst/S2_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 6
set_multicycle_path -hold -from [get_pins stat_regs_inst/S2_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 5
set_multicycle_path -setup -from [get_pins stat_regs_inst/S3_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 6
set_multicycle_path -hold -from [get_pins stat_regs_inst/S3_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 5
set_multicycle_path -setup -from [get_pins stat_regs_inst/addr_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/ADDRARDADDR[*]}] 2
set_multicycle_path -hold -from [get_pins stat_regs_inst/addr_*_reg*/C] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/ADDRARDADDR[*]}] 1
set_multicycle_path -setup -start -from [get_pins stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/CLKARDCLK] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 3
set_multicycle_path -hold -start -from [get_pins stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/CLKARDCLK] -to [get_pins {stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]}] 2
set_multicycle_path -setup -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 6
set_multicycle_path -hold -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 5
set_multicycle_path -setup -from [get_pins {*gbtbank/*/*/*/*/feedbackRegister_reg*/C}] -to [get_pins *gbtbank/*/*/txFrame_from_frameInverter*_reg*/D] 6
set_multicycle_path -hold -from [get_pins {*gbtbank/*/*/*/*/feedbackRegister_reg*/C}] -to [get_pins *gbtbank/*/*/txFrame_from_frameInverter*_reg*/D] 5
set_multicycle_path -setup -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_descrambler_inst/*/memory_register_reg*/D] 3
set_multicycle_path -hold -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_descrambler_inst/*/memory_register_reg*/D] 2
set_multicycle_path -setup -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_descrambler_inst/*/descrambledData_reg*/D] 3
set_multicycle_path -hold -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_descrambler_inst/*/descrambledData_reg*/D] 2
set_multicycle_path -setup -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_decoder_inst/*_correction_pattern_o_reg*/D] 3
set_multicycle_path -hold -from [get_pins i_tcds2_if/*/frame_pipelined_s_reg*/C] -to [get_pins i_tcds2_if/*/lpgbtfpga_decoder_inst/*_correction_pattern_o_reg*/D] 2