0.7
2020.1
May 27 2020
20:09:33
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.sim/sim_1/behav/xsim/glbl.v,1590624368,verilog,,,,glbl,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd,1591886064,vhdl,,,,dsp_mux,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C.vhd,1613269450,vhdl,,,,dsp_mux_c,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C_b.vhd,1613269477,vhdl,,,,dsp_mux_c_b,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd,1591886104,vhdl,,,,dsp_mux_b,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4.vhd,1613269575,vhdl,,,,dsp_counterx4,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd,1613407140,vhdl,,,,dsp_dividerx2,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX3.vhd,1613269783,vhdl,,,,dsp_dividerx3,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_rate_counterX3.vhd,1613269934,vhdl,,,,dsp_rate_counterx3,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd,1613997534,vhdl,D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd,,,ipb_user_status_regs,,,,,,,,
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_packX48.vhd,1611313940,vhdl,D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd;D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd;D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_tb.vhd,,,ngfec_pack,,,,,,,,
D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd,1613494827,vhdl,,,,stat_reg_block,,,,,,,,
D:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_tb.vhd,1613997613,vhdl,,,,stat_reg_tb,,,,,,,,