n %s %s 410* simulator2$ Vivado Simulator2default:default2 2020.12default:defaultZ43-3977hpx q %s * simulator2T @Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.2default:defaulthpx  Running: %s 333* simulator2 D:/Xilinx/Vivado/2020.1/bin/unwrapped/win64.o/xelab.exe -wto 2e51a4e140b64c3ca29be3922ed730c1 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot stat_reg_tb_behav xil_defaultlib.stat_reg_tb xil_defaultlib.glbl -log elaborate.log 2default:defaultZ43-3449hpx T Using %s slave threads 377* simulator2 22default:defaultZ43-3493hpx B Starting static elaboration 342* simulatorZ43-3458hpx G !Pass Through NonSizing Optimizer 685* simulatorZ43-4537hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx  #index value <%s> is out of range %s922* xsimverific2 152default:default2 [7:0]2default:default2h RD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd2default:default2 1472default:default8@Z10-922hpx C Completed static elaboration 280* simulatorZ43-3396hpx M 'Starting simulation data flow analysis 341* simulatorZ43-3457hpx N (Completed simulation data flow analysis 279* simulatorZ43-3395hpx d %Time Resolution for simulation is %s 344* simulator2 1ps2default:defaultZ43-3460hpx ] Compiling %s 389* simulator2( package std.standard2default:defaultZ43-3505hpx [ Compiling %s 389* simulator2& package std.textio2default:defaultZ43-3505hpx d Compiling %s 389* simulator2/ package ieee.std_logic_11642default:defaultZ43-3505hpx a Compiling %s 389* simulator2, package ieee.numeric_std2default:defaultZ43-3505hpx j Compiling %s 389* simulator25 !package xil_defaultlib.ngfec_pack2default:defaultZ43-3505hpx c Compiling %s 389* simulator2. package unisim.vcomponents2default:defaultZ43-3505hpx d Compiling %s 389* simulator2/ package synopsys.attributes2default:defaultZ43-3505hpx d Compiling %s 389* simulator2/ package ieee.std_logic_misc2default:defaultZ43-3505hpx ` Compiling %s 389* simulator2+ package xpm.vcomponents2default:defaultZ43-3505hpx b Compiling %s 389* simulator2- package ieee.vital_timing2default:defaultZ43-3505hpx f Compiling %s 389* simulator21 package ieee.vital_primitives2default:defaultZ43-3505hpx \ Compiling %s 389* simulator2' package unisim.vpkg2default:defaultZ43-3505hpx \ Compiling %s 389* simulator2' package vl.vl_types2default:defaultZ43-3505hpx c Compiling module %s405* simulator2( xil_defaultlib.glbl 2default:defaultZ43-3953hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(autoreset_patdet="RESET...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2j Varchitecture behavioral of entity xil_defaultlib.DSP_dividerX3 [dsp_dividerx3_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(creg=0,mreg=0,use_mult=...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2t `architecture behavioral of entity xil_defaultlib.DSP_rate_counterX3 [dsp_rate_counterx3_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2x darchitecture behavioral of entity xil_defaultlib.DSP_dividerX2 [\DSP_dividerX2(pattern="00000000...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2^ Jarchitecture behavioral of entity xil_defaultlib.DSP_MUX [dsp_mux_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,adreg=0,alum...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2b Narchitecture behavioral of entity xil_defaultlib.DSP_MUX_b [dsp_mux_b_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(creg=0,mreg=0,use_mult=...]2default:defaultZ43-3505hpx w Compiling module %s405* simulator2< (xpm.xpm_cdc_single(DEST_SYNC_FF=4,IN... 2default:defaultZ43-3953hpx  Compiling %s 389* simulator2j Varchitecture behavioral of entity xil_defaultlib.DSP_counterX4 [dsp_counterx4_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2b Narchitecture behavioral of entity xil_defaultlib.DSP_MUX_C [dsp_mux_c_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(alumodereg=0,carryinreg...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2f Rarchitecture behavioral of entity xil_defaultlib.DSP_MUX_C_b [dsp_mux_c_b_default]2default:defaultZ43-3505hpx w Compiling module %s405* simulator2< (xpm.xpm_memory_base(MEMORY_SIZE=1638... 2default:defaultZ43-3953hpx w Compiling module %s405* simulator2< (xpm.xpm_memory_tdpram(MEMORY_SIZE=16... 2default:defaultZ43-3953hpx  Compiling %s 389* simulator2i Uarchitecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2| harchitecture behavioral of entity xil_defaultlib.ipb_user_status_regs [\ipb_user_status_regs(sim=true)\]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2l Xarchitecture behavioral of entity xil_defaultlib.stat_reg_block [stat_reg_block_default]2default:defaultZ43-3505hpx  Compiling %s 389* simulator2P