# compile vhdl design source files
vhdl xil_defaultlib  \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C_b.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_counterX4.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_dividerX3.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/DSP_rate_counterX3.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/ngFEC_packX48.vhd" \
"../../../../ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd" \
"../../../../../ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_block.vhd" \
"../../../../../ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/stat_reg_tb.vhd" \

# Do not sort compile order
nosort