
{
Command: %s
53*	vivadotcl2J
6synth_design -top ngFEC_top -part xcku115-flva2104-1-c2default:defaultZ4-113h px 
:
Starting synth_design
149*	vivadotclZ4-321h px 
ž
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2
	Synthesis2default:default2
xcku1152default:defaultZ17-347h px 
Ž
0Got license for feature '%s' and/or device '%s'
310*common2
	Synthesis2default:default2
xcku1152default:defaultZ17-349h px 
Ñ
The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2021.012default:defaultZ17-1540h px 
[
Loading part %s157*device2(
xcku115-flva2104-1-c2default:defaultZ21-403h px 

HMultithreading enabled for synth_design using a maximum of %s processes.4828*oasys2
22default:defaultZ8-7079h px 
a
?Launching helper process for spawning children vivado processes4827*oasysZ8-7078h px 
`
#Helper process launched with PID %s4824*oasys2
140122default:defaultZ8-7075h px 
±
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2!
CrossClock_RX2default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
422default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N15K132default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
382default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N15K132default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
392default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N15K132default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
402default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N15K132default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
412default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N15K132default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
422default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N31K292default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
392default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N31K292default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
402default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N31K292default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
412default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N31K292default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
422default:default8@Z8-2507h px 
Ø
Pparameter declaration becomes local in %s with formal parameter declaration list2507*oasys2%
rs_encoder_N31K292default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
432default:default8@Z8-2507h px 
ƒ
.identifier '%s' is used before its declaration4750*oasys2
sm_init2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
1652default:default8@Z8-6901h px 
†
.identifier '%s' is used before its declaration4750*oasys2

ST_TX_WAIT2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
1652default:default8@Z8-6901h px 
ƒ
.identifier '%s' is used before its declaration4750*oasys2
sm_init2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
1682default:default8@Z8-6901h px 
†
.identifier '%s' is used before its declaration4750*oasys2

ST_RX_WAIT2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
1682default:default8@Z8-6901h px 
¦
%s*synth2
yStarting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1464.160 ; gain = 255.695
2default:defaulth px 
ª
Sactual for formal port %s is neither a static name nor a globally static expression1565*oasys2
reset2default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/tri_mode_eth_mac_v5_5.vhd2default:default2
732default:default8@Z8-1565h px 
Ü
synthesizing module '%s'638*oasys2
	ngFEC_top2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
792default:default8@Z8-638h px 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 
›
,binding component instance '%s' to cell '%s'113*oasys2&
i_GBT_refclk0_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4712default:default8@Z8-113h px 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 
›
,binding component instance '%s' to cell '%s'113*oasys2&
i_GBT_refclk1_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4722default:default8@Z8-113h px 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 
›
,binding component instance '%s' to cell '%s'113*oasys2&
i_GBT_refclk2_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4732default:default8@Z8-113h px 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 
›
,binding component instance '%s' to cell '%s'113*oasys2&
i_GBT_refclk3_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4742default:default8@Z8-113h px 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 
™
,binding component instance '%s' to cell '%s'113*oasys2$
i_refclk125_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4752default:default8@Z8-113h px 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_HROW_CK_SEL bound to: 2'b00 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter REFCLK_ICNTL_RX bound to: 2'b00 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2(
i_TTC_rx_refclk_ibuf2default:default2
IBUFDS_GTE32default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4762default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b1111111111111111 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
i_pwrup_rst2default:default2
SRL16E2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4772default:default8@Z8-113h px 
e
%s
*synth2M
9	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLKOUT0_DIVIDE_F bound to: 20.000000 - type: double 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter CLKOUT1_DIVIDE bound to: 16 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT3_DIVIDE bound to: 4 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CLKFBIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter IS_CLKIN1_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_RST_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter STARTUP_WAIT bound to: FALSE - type: string 
2default:defaulth p
x
 
–
,binding component instance '%s' to cell '%s'113*oasys2!
i_clk125_MMCM2default:default2
MMCME3_BASE2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
4902default:default8@Z8-113h px 
g
%s
*synth2O
;	Parameter SIM_DEVICE bound to: ULTRASCALE - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter STARTUP_SYNC bound to: FALSE - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2$
i_refclk125_bufg2default:default2
BUFG_GT2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5122default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2!
i_clk125_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5132default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2"
i_clk62_5_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5142default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2!
i_clk250_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5152default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2!
i_DRPclk_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5162default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2"
i_ipb_clk_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5172default:default8@Z8-113h px 
ó
synthesizing module '%s'638*oasys2$
eth_7s_1000basex2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/eth_7s_1000basex.vhd2default:default2
442default:default8@Z8-638h px 
€
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2)
tri_mode_eth_mac_v5_52default:default2x
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/tri_mode_eth_mac_v5_5.vhd2default:default2
32default:default2
mac2default:default2)
tri_mode_eth_mac_v5_52default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/eth_7s_1000basex.vhd2default:default2
1382default:default8@Z8-3491h px 
ý
synthesizing module '%s'638*oasys2)
tri_mode_eth_mac_v5_52default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/tri_mode_eth_mac_v5_5.vhd2default:default2
402default:default8@Z8-638h px 
è
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	soft_emac2default:default2q
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
402default:default2
i_mac2default:default2
	soft_emac2default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/tri_mode_eth_mac_v5_5.vhd2default:default2
722default:default8@Z8-3491h px 
ê
synthesizing module '%s'638*oasys2
	soft_emac2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
622default:default8@Z8-638h px 
ê
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
EthernetCRC2default:default2n
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/EthernetCRC.vhd2default:default2
552default:default2 
i_tx_CRC32D82default:default2
EthernetCRC2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2082default:default8@Z8-3491h px 
é
synthesizing module '%s'638*oasys2
EthernetCRC2default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/EthernetCRC.vhd2default:default2
652default:default8@Z8-638h px 
¤
%done synthesizing module '%s' (%s#%s)256*oasys2
EthernetCRC2default:default2
12default:default2
12default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/EthernetCRC.vhd2default:default2
652default:default8@Z8-256h px 
—
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2
rx_crc_d2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2172default:default8@Z8-614h px 
™
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2

phyemacrxd2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2172default:default8@Z8-614h px 
ê
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
EthernetCRC2default:default2n
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/EthernetCRC.vhd2default:default2
552default:default2 
i_rx_CRC32D82default:default2
EthernetCRC2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2672default:default8@Z8-3491h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2
SRL16E_inst2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2772default:default8@Z8-113h px 
\
%s
*synth2D
0	Parameter INIT bound to: 16'b0000000000000000 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
 
,binding component instance '%s' to cell '%s'113*oasys2"
i_ce_rx_crc_dl2default:default2
SRL16E2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
2892default:default8@Z8-113h px 
¥
%done synthesizing module '%s' (%s#%s)256*oasys2
	soft_emac2default:default2
22default:default2
12default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/soft_emac_AXI4.vhd2default:default2
622default:default8@Z8-256h px 
¸
%done synthesizing module '%s' (%s#%s)256*oasys2)
tri_mode_eth_mac_v5_52default:default2
32default:default2
12default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/tri_mode_eth_mac_v5_5.vhd2default:default2
402default:default8@Z8-256h px 
 
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2*
gig_ethernet_pcs_pma_02default:default2•
€D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/synth_1/.Xil/Vivado-15164-baby/realtime/gig_ethernet_pcs_pma_0_stub.vhdl2default:default2
52default:default2
phy2default:default2*
gig_ethernet_pcs_pma_02default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/eth_7s_1000basex.vhd2default:default2
1832default:default8@Z8-3491h px 
œ
synthesizing module '%s'638*oasys2*
gig_ethernet_pcs_pma_02default:default2—
€D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/synth_1/.Xil/Vivado-15164-baby/realtime/gig_ethernet_pcs_pma_0_stub.vhdl2default:default2
402default:default8@Z8-638h px 
®
%done synthesizing module '%s' (%s#%s)256*oasys2$
eth_7s_1000basex2default:default2
42default:default2
12default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/Ethernet/eth_7s_1000basex.vhd2default:default2
442default:default8@Z8-256h px 
O
%s
*synth27
#	Parameter MAC_CFG bound to: 1'b0 
2default:defaulth p
x
 
N
%s
*synth26
"	Parameter IP_CFG bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter INTERNALWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IPBUSPORT bound to: 16'b1100001101010001 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SECONDARYPORT bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter N_OOB bound to: 0 - type: integer 
2default:defaulth p
x
 
Ø
null port '%s' ignored506*oasys2
oob_in2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
2572default:default8@Z8-506h px 
Ù
null port '%s' ignored506*oasys2
oob_out2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
2582default:default8@Z8-506h px 
ß
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2

ipbus_ctrl2default:default2|
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2
412default:default2
ipb2default:default2

ipbus_ctrl2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
5862default:default8@Z8-3491h px 
ö
synthesizing module '%s'638*oasys2

ipbus_ctrl2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2
902default:default8@Z8-638h px 
O
%s
*synth27
#	Parameter MAC_CFG bound to: 1'b0 
2default:defaulth p
x
 
N
%s
*synth26
"	Parameter IP_CFG bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter INTERNALWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IPBUSPORT bound to: 16'b1100001101010001 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SECONDARYPORT bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter N_OOB bound to: 0 - type: integer 
2default:defaulth p
x
 
ð
null port '%s' ignored506*oasys2
oob_in2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2
842default:default8@Z8-506h px 
ñ
null port '%s' ignored506*oasys2
oob_out2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2
852default:default8@Z8-506h px 
ó
synthesizing module '%s'638*oasys2
UDP_if2default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_if_flat.vhd2default:default2
902default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter INTERNALWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IPBUSPORT bound to: 16'b1100001101010001 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SECONDARYPORT bound to: 1'b0 
2default:defaulth p
x
 
ƒ
synthesizing module '%s'638*oasys2$
udp_ipaddr_block2default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2
542default:default8@Z8-638h px 
¾
%done synthesizing module '%s' (%s#%s)256*oasys2$
udp_ipaddr_block2default:default2
52default:default2
12default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd2default:default2
542default:default8@Z8-256h px 
ÿ
synthesizing module '%s'638*oasys2"
udp_rarp_block2default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2
502default:default8@Z8-638h px 
º
%done synthesizing module '%s' (%s#%s)256*oasys2"
udp_rarp_block2default:default2
62default:default2
12default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rarp_block.vhd2default:default2
502default:default8@Z8-256h px 
ý
synthesizing module '%s'638*oasys2!
udp_build_arp2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2
542default:default8@Z8-638h px 
¸
%done synthesizing module '%s' (%s#%s)256*oasys2!
udp_build_arp2default:default2
72default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_arp.vhd2default:default2
542default:default8@Z8-256h px 
…
synthesizing module '%s'638*oasys2%
udp_build_payload2default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2
592default:default8@Z8-638h px 
À
%done synthesizing module '%s' (%s#%s)256*oasys2%
udp_build_payload2default:default2
82default:default2
12default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_payload.vhd2default:default2
592default:default8@Z8-256h px 
ÿ
synthesizing module '%s'638*oasys2"
udp_build_ping2default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2
572default:default8@Z8-638h px 
º
%done synthesizing module '%s' (%s#%s)256*oasys2"
udp_build_ping2default:default2
92default:default2
12default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_ping.vhd2default:default2
572default:default8@Z8-256h px 
ƒ
synthesizing module '%s'638*oasys2$
udp_build_resend2default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2
492default:default8@Z8-638h px 
¿
%done synthesizing module '%s' (%s#%s)256*oasys2$
udp_build_resend2default:default2
102default:default2
12default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_resend.vhd2default:default2
492default:default8@Z8-256h px 
ƒ
synthesizing module '%s'638*oasys2$
udp_build_status2default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2
542default:default8@Z8-638h px 
¿
%done synthesizing module '%s' (%s#%s)256*oasys2$
udp_build_status2default:default2
112default:default2
12default:default2„
nD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_build_status.vhd2default:default2
542default:default8@Z8-256h px 
…
synthesizing module '%s'638*oasys2%
udp_status_buffer2default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2
752default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
Á
%done synthesizing module '%s' (%s#%s)256*oasys2%
udp_status_buffer2default:default2
122default:default2
12default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_status_buffer.vhd2default:default2
752default:default8@Z8-256h px 
û
synthesizing module '%s'638*oasys2 
udp_byte_sum2default:default2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2
512default:default8@Z8-638h px 
·
%done synthesizing module '%s' (%s#%s)256*oasys2 
udp_byte_sum2default:default2
132default:default2
12default:default2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_byte_sum.vhd2default:default2
512default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2#
udp_do_rx_reset2default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2
452default:default8@Z8-638h px 
½
%done synthesizing module '%s' (%s#%s)256*oasys2#
udp_do_rx_reset2default:default2
142default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd2default:default2
452default:default8@Z8-256h px 
…
synthesizing module '%s'638*oasys2%
udp_packet_parser2default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2
612default:default8@Z8-638h px 
a
%s
*synth2I
5	Parameter IPBUSPORT bound to: 16'b1100001101010001 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SECONDARYPORT bound to: 1'b0 
2default:defaulth p
x
 
Á
%done synthesizing module '%s' (%s#%s)256*oasys2%
udp_packet_parser2default:default2
152default:default2
12default:default2…
oD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_packet_parser.vhd2default:default2
612default:default8@Z8-256h px 
ý
synthesizing module '%s'638*oasys2!
udp_rxram_mux2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2
802default:default8@Z8-638h px 
¹
%done synthesizing module '%s' (%s#%s)256*oasys2!
udp_rxram_mux2default:default2
162default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxram_mux.vhd2default:default2
802default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2#
udp_DualPortRAM2default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram.vhd2default:default2
482default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
½
%done synthesizing module '%s' (%s#%s)256*oasys2#
udp_DualPortRAM2default:default2
172default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram.vhd2default:default2
482default:default8@Z8-256h px 
‰
synthesizing module '%s'638*oasys2'
udp_buffer_selector2default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2
582default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
Å
%done synthesizing module '%s' (%s#%s)256*oasys2'
udp_buffer_selector2default:default2
182default:default2
12default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2
582default:default8@Z8-256h px 
ÿ
synthesizing module '%s'638*oasys2"
udp_rxram_shim2default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxram_shim.vhd2default:default2
562default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 1 - type: integer 
2default:defaulth p
x
 
»
%done synthesizing module '%s' (%s#%s)256*oasys2"
udp_rxram_shim2default:default2
192default:default2
12default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxram_shim.vhd2default:default2
562default:default8@Z8-256h px 
‡
synthesizing module '%s'638*oasys2&
udp_DualPortRAM_rx2default:default2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2
482default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
â
default block is never used226*oasys2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2
622default:default8@Z8-226h px 
Ã
%done synthesizing module '%s' (%s#%s)256*oasys2&
udp_DualPortRAM_rx2default:default2
202default:default2
12default:default2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd2default:default2
482default:default8@Z8-256h px 
™
synthesizing module '%s'638*oasys27
#udp_buffer_selector__parameterized02default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2
582default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
Õ
%done synthesizing module '%s' (%s#%s)256*oasys27
#udp_buffer_selector__parameterized02default:default2
202default:default2
12default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_buffer_selector.vhd2default:default2
582default:default8@Z8-256h px 
‡
synthesizing module '%s'638*oasys2&
udp_DualPortRAM_tx2default:default2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2
482default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ADDRWIDTH bound to: 11 - type: integer 
2default:defaulth p
x
 
â
default block is never used226*oasys2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2
832default:default8@Z8-226h px 
Ã
%done synthesizing module '%s' (%s#%s)256*oasys2&
udp_DualPortRAM_tx2default:default2
212default:default2
12default:default2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd2default:default2
482default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2'
udp_rxtransactor_if2default:default2Ž
xD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd2default:default2
492default:default8@Z8-638h px 
Ì
%done synthesizing module '%s' (%s#%s)256*oasys2'
udp_rxtransactor_if2default:default2
222default:default2
12default:default2Ž
xD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd2default:default2
492default:default8@Z8-256h px 
ö
synthesizing module '%s'638*oasys2

udp_tx_mux2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2
712default:default8@Z8-638h px 
²
%done synthesizing module '%s' (%s#%s)256*oasys2

udp_tx_mux2default:default2
232default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_tx_mux.vhd2default:default2
712default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2'
udp_txtransactor_if2default:default2Ž
xD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd2default:default2
612default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
Ì
%done synthesizing module '%s' (%s#%s)256*oasys2'
udp_txtransactor_if2default:default2
242default:default2
12default:default2Ž
xD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd2default:default2
612default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2)
udp_clock_crossing_if2default:default2‰
sD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2
692default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter BUFWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
É
%done synthesizing module '%s' (%s#%s)256*oasys2)
udp_clock_crossing_if2default:default2
252default:default2
12default:default2‰
sD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd2default:default2
692default:default8@Z8-256h px 
¯
%done synthesizing module '%s' (%s#%s)256*oasys2
UDP_if2default:default2
262default:default2
12default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/udp_if_flat.vhd2default:default2
902default:default8@Z8-256h px 
ö
synthesizing module '%s'638*oasys2

transactor2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor.vhd2default:default2
602default:default8@Z8-638h px 
ý
synthesizing module '%s'638*oasys2!
transactor_if2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2
572default:default8@Z8-638h px 
¹
%done synthesizing module '%s' (%s#%s)256*oasys2!
transactor_if2default:default2
272default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_if.vhd2default:default2
572default:default8@Z8-256h px 
ý
synthesizing module '%s'638*oasys2!
transactor_sm2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2
652default:default8@Z8-638h px 
¹
%done synthesizing module '%s' (%s#%s)256*oasys2!
transactor_sm2default:default2
282default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_sm.vhd2default:default2
652default:default8@Z8-256h px 
ÿ
synthesizing module '%s'638*oasys2"
transactor_cfg2default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_cfg.vhd2default:default2
532default:default8@Z8-638h px 
»
%done synthesizing module '%s' (%s#%s)256*oasys2"
transactor_cfg2default:default2
292default:default2
12default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor_cfg.vhd2default:default2
532default:default8@Z8-256h px 
²
%done synthesizing module '%s' (%s#%s)256*oasys2

transactor2default:default2
302default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/transactor.vhd2default:default2
602default:default8@Z8-256h px 
²
%done synthesizing module '%s' (%s#%s)256*oasys2

ipbus_ctrl2default:default2
312default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_core/firmware/hdl/ipbus_ctrl.vhd2default:default2
902default:default8@Z8-256h px 
Ý
5Component port with null array found, Will be ignored4625*oasys2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
6132default:default8@Z8-6778h px 
Ý
5Component port with null array found, Will be ignored4625*oasys2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
6142default:default8@Z8-6778h px 
â
synthesizing module '%s'638*oasys2 
ipbus_fabric2default:default2h
RD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_fabric.vhd2default:default2
222default:default8@Z8-638h px 
_
%s
*synth2G
3	Parameter n_usr_slv bound to: 51 - type: integer 
2default:defaulth p
x
 
ž
%done synthesizing module '%s' (%s#%s)256*oasys2 
ipbus_fabric2default:default2
322default:default2
12default:default2h
RD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipbus_fabric.vhd2default:default2
222default:default8@Z8-256h px 
õ
synthesizing module '%s'638*oasys2(
ipb_user_status_regs2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
522default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter sim bound to: 0 - type: bool 
2default:defaulth p
x
 
š
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2
ipb_addr9_r2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2242default:default8@Z8-614h px 
ê
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2!
cntr_rst_ctrl2default:default2g
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
362default:default2#
i_cntr_rst_ctrl2default:default2!
cntr_rst_ctrl2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2732default:default8@Z8-3491h px 
ä
synthesizing module '%s'638*oasys2!
cntr_rst_ctrl2default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
462default:default8@Z8-638h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b10010010010010010010010010010010 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b10010010010010010010010010010010 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00100100100100100100100100100100 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00100100100100100100100100100100 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00111000111000111000111000111000 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00111000111000111000111000111000 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b11000000111111000000111111000000 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b11000000111111000000111111000000 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00000000111111111111000000000000 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b00000000111111111111000000000000 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b11111111000000000000000000000000 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2
i_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1482default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b11111111000000000000000000000000 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2"
i_reset_addr_p2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1602default:default8@Z8-113h px 
l
%s
*synth2T
@	Parameter INIT bound to: 32'b10100100100100100100100100100100 
2default:defaulth p
x
 
’
,binding component instance '%s' to cell '%s'113*oasys2 
i_wraparound2default:default2
LUT52default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
1752default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_MULT bound to: MULTIPLY - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
2472default:default8@Z8-113h px 
 
%done synthesizing module '%s' (%s#%s)256*oasys2!
cntr_rst_ctrl2default:default2
332default:default2
12default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cntr_rst_ctrl.vhd2default:default2
462default:default8@Z8-256h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ü
synthesizing module '%s'638*oasys2
	DSP_MUX_b2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
422default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 0 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
472default:default8@Z8-113h px 
˜
%done synthesizing module '%s' (%s#%s)256*oasys2
	DSP_MUX_b2default:default2
342default:default2
12default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
422default:default8@Z8-256h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ø
synthesizing module '%s'638*oasys2
DSP_MUX2default:default2c
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
432default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 0 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
Ž
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2c
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
492default:default8@Z8-113h px 
”
%done synthesizing module '%s' (%s#%s)256*oasys2
DSP_MUX2default:default2
352default:default2
12default:default2c
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
432default:default8@Z8-256h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ò
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
DSP_MUX2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX.vhd2default:default2
342default:default2
	i_DSP_MUX2default:default2
DSP_MUX2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2972default:default8@Z8-3491h px 
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2
	DSP_MUX_b2default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_b.vhd2default:default2
342default:default2
i_DSP_MUX_b2default:default2
	DSP_MUX_b2default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
2892default:default8@Z8-3491h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-34912default:default2
1002default:defaultZ17-14h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
æ
synthesizing module '%s'638*oasys2"
DSP_counterX4b2default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4b.vhd2default:default2
412default:default8@Z8-638h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_SIMD bound to: FOUR12 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
•
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4b.vhd2default:default2
682default:default8@Z8-113h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_SIMD bound to: FOUR12 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
—
,binding component instance '%s' to cell '%s'113*oasys2!
DSP48E2_inst22default:default2
DSP48E22default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4b.vhd2default:default2
1302default:default8@Z8-113h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
ç
synthesizing module '%s'%s4497*oasys2"
xpm_cdc_single2default:default2
 2default:default2P
:D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2
1532default:default8@Z8-6157h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter VERSION bound to: 0 - type: integer 
2default:defaulth p
x
 
£
'done synthesizing module '%s'%s (%s#%s)4495*oasys2"
xpm_cdc_single2default:default2
 2default:default2
362default:default2
12default:default2P
:D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2
1532default:default8@Z8-6155h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
¢
%done synthesizing module '%s' (%s#%s)256*oasys2"
DSP_counterX4b2default:default2
372default:default2
12default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4b.vhd2default:default2
412default:default8@Z8-256h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
à
synthesizing module '%s'638*oasys2
DSP_MUX_C_b2default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C_b.vhd2default:default2
442default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
’
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C_b.vhd2default:default2
492default:default8@Z8-113h px 
œ
%done synthesizing module '%s' (%s#%s)256*oasys2
DSP_MUX_C_b2default:default2
382default:default2
12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C_b.vhd2default:default2
442default:default8@Z8-256h px 
Ü
synthesizing module '%s'638*oasys2
	DSP_MUX_C2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C.vhd2default:default2
452default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C.vhd2default:default2
512default:default8@Z8-113h px 
˜
%done synthesizing module '%s' (%s#%s)256*oasys2
	DSP_MUX_C2default:default2
392default:default2
12default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_MUX_C.vhd2default:default2
452default:default8@Z8-256h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter CLOCKING_MODE bound to: independent_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_A bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
ñ
synthesizing module '%s'%s4497*oasys2%
xpm_memory_tdpram2default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
88712default:default8@Z8-6157h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter CLOCKING_MODE bound to: independent_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_A bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter P_CLOCKING_MODE bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter P_ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_WRITE_MODE_A bound to: 2 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
í
synthesizing module '%s'%s4497*oasys2#
xpm_memory_base2default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter MEMORY_TYPE bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CLOCKING_MODE bound to: 1 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter VERSION bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_A bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_MEMORY_OPT bound to: yes - type: string 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rsta_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rstb_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
2default:defaulth p
x
 
Ñ
Synth Info: %s 4384*oasys2¦
‘[XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
4902default:default8@Z8-6059h px 
©
'done synthesizing module '%s'%s (%s#%s)4495*oasys2#
xpm_memory_base2default:default2
 2default:default2
402default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6155h px 
­
'done synthesizing module '%s'%s (%s#%s)4495*oasys2%
xpm_memory_tdpram2default:default2
 2default:default2
412default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
88712default:default8@Z8-6155h px 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2

i_DSP_cntr2default:default2
DSP48E22default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
5412default:default8@Z8-113h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
ä
synthesizing module '%s'638*oasys2!
DSP_counterX42default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4.vhd2default:default2
412default:default8@Z8-638h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_SIMD bound to: FOUR12 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4.vhd2default:default2
502default:default8@Z8-113h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
 
%done synthesizing module '%s' (%s#%s)256*oasys2!
DSP_counterX42default:default2
422default:default2
12default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_counterX4.vhd2default:default2
412default:default8@Z8-256h px 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter use_sync bound to: 4'b1111 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter CLOCKING_MODE bound to: independent_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter READ_RESET_VALUE_A bound to: 00000000 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_A bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 0 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 0 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 

,binding component instance '%s' to cell '%s'113*oasys2

i_DSP_rate2default:default2
DSP48E22default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
7922default:default8@Z8-113h px 
±
%done synthesizing module '%s' (%s#%s)256*oasys2(
ipb_user_status_regs2default:default2
432default:default2
12default:default2s
]D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_status_regsNew.vhd2default:default2
522default:default8@Z8-256h px 
ô
synthesizing module '%s'638*oasys2)
ipb_user_control_regs2default:default2q
[D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_control_regs.vhd2default:default2
212default:default8@Z8-638h px 
_
%s
*synth2G
3	Parameter addr_width bound to: 7 - type: integer 
2default:defaulth p
x
 
°
%done synthesizing module '%s' (%s#%s)256*oasys2)
ipb_user_control_regs2default:default2
442default:default2
12default:default2q
[D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ipb_user_control_regs.vhd2default:default2
212default:default8@Z8-256h px 
e
%s
*synth2M
9	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKFBOUT_MULT_F bound to: 18.000000 - type: double 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter CLKFBOUT_PHASE bound to: 90.000000 - type: double 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter CLKIN1_PERIOD bound to: 24.950000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLKOUT0_DIVIDE_F bound to: 18.000000 - type: double 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter COMPENSATION bound to: AUTO - type: string 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CLKFBIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter IS_CLKIN1_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter IS_CLKIN2_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_PSEN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_RST_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter REF_JITTER2 bound to: 0.010000 - type: double 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter SS_EN bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter STARTUP_WAIT bound to: FALSE - type: string 
2default:defaulth p
x
 
—
,binding component instance '%s' to cell '%s'113*oasys2#
fabric_clk_MMCM2default:default2

MMCME3_ADV2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
6592default:default8@Z8-113h px 

,binding component instance '%s' to cell '%s'113*oasys2!
CLKFBOUT_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
7022default:default8@Z8-113h px 
‘
,binding component instance '%s' to cell '%s'113*oasys2#
fabric_clk_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
7032default:default8@Z8-113h px 
‘
,binding component instance '%s' to cell '%s'113*oasys2#
tx_wordclk_bufg2default:default2
BUFG2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
7042default:default8@Z8-113h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
ä
synthesizing module '%s'638*oasys2!
DSP_dividerX32default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX3.vhd2default:default2
472default:default8@Z8-638h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter AUTORESET_PATDET bound to: RESET_MATCH - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b111111111111111111111111111111111000000000000000 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter USE_PATTERN_DETECT bound to: PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX3.vhd2default:default2
762default:default8@Z8-113h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
 
%done synthesizing module '%s' (%s#%s)256*oasys2!
DSP_dividerX32default:default2
452default:default2
12default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX3.vhd2default:default2
472default:default8@Z8-256h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
î
synthesizing module '%s'638*oasys2&
DSP_rate_counterX32default:default2n
XD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_rate_counterX3.vhd2default:default2
422default:default8@Z8-638h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
™
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2n
XD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_rate_counterX3.vhd2default:default2
652default:default8@Z8-113h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
ª
%done synthesizing module '%s' (%s#%s)256*oasys2&
DSP_rate_counterX32default:default2
462default:default2
12default:default2n
XD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_rate_counterX3.vhd2default:default2
422default:default8@Z8-256h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
ä
synthesizing module '%s'638*oasys2!
DSP_dividerX22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
482default:default8@Z8-638h px 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ACASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ADREG bound to: 1 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ALUMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter AMULTSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter AREG bound to: 1 - type: integer 
2default:defaulth p
x
 
n
%s
*synth2V
B	Parameter AUTORESET_PATDET bound to: RESET_MATCH - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter AUTORESET_PRIORITY bound to: RESET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter A_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter BCASCREG bound to: 1 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BMULTSEL bound to: B - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter BREG bound to: 1 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter B_INPUT bound to: DIRECT - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter CARRYINREG bound to: 1 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CARRYINSELREG bound to: 1 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter CREG bound to: 0 - type: integer 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter DREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter INMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLK_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter IS_OPMODE_INVERTED bound to: 9'b000000000 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter IS_RSTALLCARRYIN_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IS_RSTALUMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTA_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTB_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter IS_RSTCTRL_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTC_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTD_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter IS_RSTINMODE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTM_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter IS_RSTP_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
|
%s
*synth2d
P	Parameter MASK bound to: 48'b111111111111111111111111111111111000000000000000 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter MREG bound to: 0 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter OPMODEREG bound to: 1 - type: integer 
2default:defaulth p
x
 

%s
*synth2g
S	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter PREADDINSEL bound to: A - type: string 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter PREG bound to: 1 - type: integer 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter RND bound to: 48'b000000000000000000000000000000000000000000000000 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SEL_MASK bound to: MASK - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter SEL_PATTERN bound to: PATTERN - type: string 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter USE_MULT bound to: NONE - type: string 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter USE_PATTERN_DETECT bound to: PATDET - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter USE_SIMD bound to: ONE48 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter USE_WIDEXOR bound to: FALSE - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter XORSIMD bound to: XOR24_48_96 - type: string 
2default:defaulth p
x
 
”
,binding component instance '%s' to cell '%s'113*oasys2 
DSP48E2_inst2default:default2
DSP48E22default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
762default:default8@Z8-113h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 1 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
 
%done synthesizing module '%s' (%s#%s)256*oasys2!
DSP_dividerX22default:default2
472default:default2
12default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
482default:default8@Z8-256h px 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter pattern bound to: 16'b0000000000000000 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter mask bound to: 16'b1000000000000000 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
R
%s
*synth2:
&	Parameter use_sync bound to: 3'b111 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter use_sync bound to: 2'b11 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter pattern bound to: 24'b000000000000000000000000 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter mask bound to: 24'b111111111000000000000000 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
á
synthesizing module '%s'638*oasys2
TCDS2_if2default:default2k
UD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/TCDS2_if.vhd2default:default2
712default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
ï
synthesizing module '%s'638*oasys2#
ttc_mgt_wrapper2default:default2r
\D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_wrapper.vhd2default:default2
642default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter REFCLK_EN_TX_PATH bound to: 1'b1 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter REFCLK_ICNTL_TX bound to: 5'b00111 
2default:defaulth p
x
 
 
,binding component instance '%s' to cell '%s'113*oasys2

i_rxrecclk2default:default2
OBUFDS_GTE32default:default2r
\D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_wrapper.vhd2default:default2
2242default:default8@Z8-113h px 
ª
synthesizing module '%s'%s4497*oasys24
 ttc_mgt_example_gtwiz_userclk_tx2default:default2
 2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_tx.v2default:default2
602default:default8@Z8-6157h px 
_
%s
*synth2G
3	Parameter P_CONTENTS bound to: 0 - type: integer 
2default:defaulth p
x
 
r
%s
*synth2Z
F	Parameter P_FREQ_RATIO_SOURCE_TO_USRCLK bound to: 1 - type: integer 
2default:defaulth p
x
 
s
%s
*synth2[
G	Parameter P_FREQ_RATIO_USRCLK_TO_USRCLK2 bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter P_USRCLK_INT_DIV bound to: 0 - type: integer 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter P_USRCLK_DIV bound to: 3'b000 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_USRCLK2_INT_DIV bound to: 0 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter P_USRCLK2_DIV bound to: 3'b000 
2default:defaulth p
x
 
Ü
synthesizing module '%s'%s4497*oasys2
BUFG_GT2default:default2
 2default:default2K
5D:/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v2default:default2
12592default:default8@Z8-6157h px 
g
%s
*synth2O
;	Parameter SIM_DEVICE bound to: ULTRASCALE - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter STARTUP_SYNC bound to: FALSE - type: string 
2default:defaulth p
x
 
˜
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
BUFG_GT2default:default2
 2default:default2
482default:default2
12default:default2K
5D:/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v2default:default2
12592default:default8@Z8-6155h px 
æ
'done synthesizing module '%s'%s (%s#%s)4495*oasys24
 ttc_mgt_example_gtwiz_userclk_tx2default:default2
 2default:default2
492default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_tx.v2default:default2
602default:default8@Z8-6155h px 
ª
synthesizing module '%s'%s4497*oasys24
 ttc_mgt_example_gtwiz_userclk_rx2default:default2
 2default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_rx.v2default:default2
602default:default8@Z8-6157h px 
_
%s
*synth2G
3	Parameter P_CONTENTS bound to: 0 - type: integer 
2default:defaulth p
x
 
r
%s
*synth2Z
F	Parameter P_FREQ_RATIO_SOURCE_TO_USRCLK bound to: 1 - type: integer 
2default:defaulth p
x
 
s
%s
*synth2[
G	Parameter P_FREQ_RATIO_USRCLK_TO_USRCLK2 bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter P_USRCLK_INT_DIV bound to: 0 - type: integer 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter P_USRCLK_DIV bound to: 3'b000 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_USRCLK2_INT_DIV bound to: 0 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter P_USRCLK2_DIV bound to: 3'b000 
2default:defaulth p
x
 
æ
'done synthesizing module '%s'%s (%s#%s)4495*oasys24
 ttc_mgt_example_gtwiz_userclk_rx2default:default2
 2default:default2
502default:default2
12default:default2
kD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_userclk_rx.v2default:default2
602default:default8@Z8-6155h px 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
‘
synthesizing module '%s'%s4497*oasys2(
ttc_mgt_example_init2default:default2
 2default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
592default:default8@Z8-6157h px 
p
%s
*synth2X
D	Parameter P_FREERUN_FREQUENCY bound to: 125.000000 - type: double 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter SIM bound to: 0 - type: bool 
2default:defaulth p
x
 
u
%s
*synth2]
I	Parameter P_TX_TIMER_DURATION_US bound to: 30000.000000 - type: double 
2default:defaulth p
x
 
v
%s
*synth2^
J	Parameter P_RX_TIMER_DURATION_US bound to: 130000.000000 - type: double 
2default:defaulth p
x
 
v
%s
*synth2^
J	Parameter P_TX_TIMER_DURATION_US_SIM bound to: 10.000000 - type: double 
2default:defaulth p
x
 
v
%s
*synth2^
J	Parameter P_RX_TIMER_DURATION_US_SIM bound to: 50.000000 - type: double 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter ST_START bound to: 2'b00 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_TX_WAIT bound to: 2'b01 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_RX_WAIT bound to: 2'b10 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_MONITOR bound to: 2'b11 
2default:defaulth p
x
 
¥
synthesizing module '%s'%s4497*oasys26
"ttc_mgt_example_reset_synchronizer2default:default2
 2default:default2{
eD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_reset_sync.v2default:default2
582default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter FREQUENCY bound to: 512 - type: integer 
2default:defaulth p
x
 
á
'done synthesizing module '%s'%s (%s#%s)4495*oasys26
"ttc_mgt_example_reset_synchronizer2default:default2
 2default:default2
512default:default2
12default:default2{
eD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_reset_sync.v2default:default2
582default:default8@Z8-6155h px 
¡
synthesizing module '%s'%s4497*oasys24
 ttc_mgt_example_bit_synchronizer2default:default2
 2default:default2y
cD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_bit_sync.v2default:default2
582default:default8@Z8-6157h px 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter FREQUENCY bound to: 512 - type: integer 
2default:defaulth p
x
 
Ý
'done synthesizing module '%s'%s (%s#%s)4495*oasys24
 ttc_mgt_example_bit_synchronizer2default:default2
 2default:default2
522default:default2
12default:default2y
cD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_bit_sync.v2default:default2
582default:default8@Z8-6155h px 
Í
'done synthesizing module '%s'%s (%s#%s)4495*oasys2(
ttc_mgt_example_init2default:default2
 2default:default2
532default:default2
12default:default2u
_D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_init.v2default:default2
592default:default8@Z8-6155h px 
Ÿ
synthesizing module '%s'%s4497*oasys2/
ttc_mgt_example_gtwiz_reset2default:default2
 2default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v2default:default2
602default:default8@Z8-6157h px 
p
%s
*synth2X
D	Parameter P_FREERUN_FREQUENCY bound to: 125.000000 - type: double 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_USE_CPLL_CAL bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_TX_PLL_TYPE bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_RX_PLL_TYPE bound to: 1 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_RX_LINE_RATE bound to: 10.260224 - type: double 
2default:defaulth p
x
 
{
%s
*synth2c
O	Parameter P_CDR_TIMEOUT_FREERUN_CYC bound to: 26'b00000001101110000011010010 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter ST_RESET_ALL_INIT bound to: 3'b000 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ST_RESET_ALL_BRANCH bound to: 3'b001 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ST_RESET_ALL_TX_PLL bound to: 3'b010 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ST_RESET_ALL_TX_PLL_WAIT bound to: 3'b011 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter ST_RESET_ALL_RX_DP bound to: 3'b100 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ST_RESET_ALL_RX_PLL bound to: 3'b101 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ST_RESET_ALL_RX_WAIT bound to: 3'b110 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter ST_RESET_ALL_DONE bound to: 3'b111 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_TX_PLL_RESET_FREERUN_CYC bound to: 10'b0000000111 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter ST_RESET_TX_BRANCH bound to: 3'b000 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter ST_RESET_TX_PLL bound to: 3'b001 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ST_RESET_TX_DATAPATH bound to: 3'b010 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ST_RESET_TX_WAIT_LOCK bound to: 3'b011 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ST_RESET_TX_WAIT_USERRDY bound to: 3'b100 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter ST_RESET_TX_WAIT_RESETDONE bound to: 3'b101 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ST_RESET_TX_IDLE bound to: 3'b110 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_RX_PLL_RESET_FREERUN_CYC bound to: 10'b0011111100 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter ST_RESET_RX_BRANCH bound to: 3'b000 
2default:defaulth p
x
 
Y
%s
*synth2A
-	Parameter ST_RESET_RX_PLL bound to: 3'b001 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ST_RESET_RX_DATAPATH bound to: 3'b010 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter ST_RESET_RX_WAIT_LOCK bound to: 3'b011 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ST_RESET_RX_WAIT_CDR bound to: 3'b100 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ST_RESET_RX_WAIT_USERRDY bound to: 3'b101 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter ST_RESET_RX_WAIT_RESETDONE bound to: 3'b110 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter ST_RESET_RX_IDLE bound to: 3'b111 
2default:defaulth p
x
 
ê
-case statement is not full and has no default155*oasys2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v2default:default2
1712default:default8@Z8-155h px 
­
synthesizing module '%s'%s4497*oasys2:
&ttc_mgt_example_reset_inv_synchronizer2default:default2
 2default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_reset_inv_sync.v2default:default2
582default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter FREQUENCY bound to: 512 - type: integer 
2default:defaulth p
x
 
é
'done synthesizing module '%s'%s (%s#%s)4495*oasys2:
&ttc_mgt_example_reset_inv_synchronizer2default:default2
 2default:default2
542default:default2
12default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_reset_inv_sync.v2default:default2
582default:default8@Z8-6155h px 
Û
'done synthesizing module '%s'%s (%s#%s)4495*oasys2/
ttc_mgt_example_gtwiz_reset2default:default2
 2default:default2
552default:default2
12default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_example_gtwiz_reset.v2default:default2
602default:default8@Z8-6155h px 
ý
synthesizing module '%s'638*oasys2
ttc_mgt2default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/synth_1/.Xil/Vivado-15164-baby/realtime/ttc_mgt_stub.vhdl2default:default2
642default:default8@Z8-638h px 
«
%done synthesizing module '%s' (%s#%s)256*oasys2#
ttc_mgt_wrapper2default:default2
562default:default2
12default:default2r
\D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/ttc_mgt_wrapper.vhd2default:default2
642default:default8@Z8-256h px 
‰
synthesizing module '%s'638*oasys2
prbs_gen2default:default2’
|D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_gen.vhd2default:default2
902default:default8@Z8-638h px 
e
%s
*synth2M
9	Parameter g_PARAL_FACTOR bound to: 234 - type: integer 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 
2default:defaulth p
x
 
Å
%done synthesizing module '%s' (%s#%s)256*oasys2
prbs_gen2default:default2
572default:default2
12default:default2’
|D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_gen.vhd2default:default2
902default:default8@Z8-256h px 
‰
synthesizing module '%s'638*oasys2
prbs_chk2default:default2’
|D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd2default:default2
922default:default8@Z8-638h px 
j
%s
*synth2R
>	Parameter g_GOOD_FRAME_TO_LOCK bound to: 15 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter g_BAD_FRAME_TO_UNLOCK bound to: 5 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter g_PARAL_FACTOR bound to: 234 - type: integer 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter g_PARAL_FACTOR bound to: 234 - type: integer 
2default:defaulth p
x
 
q
%s
*synth2Y
E	Parameter g_PRBS_POLYNOMIAL bound to: 24'b100001000000000000000001 
2default:defaulth p
x
 
ï
default block is never used226*oasys2’
|D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd2default:default2
1802default:default8@Z8-226h px 
Å
%done synthesizing module '%s' (%s#%s)256*oasys2
prbs_chk2default:default2
582default:default2
12default:default2’
|D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/hprbs_framing/prbs_chk.vhd2default:default2
922default:default8@Z8-256h px 
£
synthesizing module '%s'638*oasys2"
unlock_counter2default:default2¦
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/counters/firmware/hdl/unlock_counter.vhd2default:default2
312default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter G_WIDTH bound to: 32 - type: integer 
2default:defaulth p
x
 
ß
%done synthesizing module '%s' (%s#%s)256*oasys2"
unlock_counter2default:default2
592default:default2
12default:default2¦
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/counters/firmware/hdl/unlock_counter.vhd2default:default2
312default:default8@Z8-256h px 
¯
synthesizing module '%s'638*oasys2'
ttc2_frame_splitter2default:default2­
–D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/ttc2_frame_splitter.vhd2default:default2
392default:default8@Z8-638h px 
T
%s
*synth2<
(	Parameter G_LINK_SPEED bound to: 1'b0 
2default:defaulth p
x
 
ë
%done synthesizing module '%s' (%s#%s)256*oasys2'
ttc2_frame_splitter2default:default2
602default:default2
12default:default2­
–D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/ttc2_frame_splitter.vhd2default:default2
392default:default8@Z8-256h px 
­
synthesizing module '%s'638*oasys2&
tts2_frame_builder2default:default2¬
•D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/tts2_frame_builder.vhd2default:default2
392default:default8@Z8-638h px 
T
%s
*synth2<
(	Parameter G_LINK_SPEED bound to: 1'b0 
2default:defaulth p
x
 
é
%done synthesizing module '%s' (%s#%s)256*oasys2&
tts2_frame_builder2default:default2
612default:default2
12default:default2¬
•D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/cms-tcds2-firmware-master/components/tcds2_link/firmware/hdl/tts2_frame_builder.vhd2default:default2
392default:default8@Z8-256h px 
£
synthesizing module '%s'638*oasys2*
lpgbtfpga_uplink_fixed2default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/lpgbtfpga_uplink_fixed.vhd2default:default2
912default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter DATARATE bound to: 2 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_multicyleDelay bound to: 3 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter c_clockRatio bound to: 8 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter c_mgtWordWidth bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter c_allowedFalseHeader bound to: 5 - type: integer 
2default:defaulth p
x
 
o
%s
*synth2W
C	Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter c_requiredTrueHeader bound to: 32 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_bitslip_mindly bound to: 2 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter c_bitslip_waitdly bound to: 40 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter c_resetOnEven bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_resetDuration bound to: 10 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter c_wordRatio bound to: 8 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter c_wordSize bound to: 32 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter c_headerPattern bound to: 2'b01 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter c_allowedFalseHeader bound to: 5 - type: integer 
2default:defaulth p
x
 
o
%s
*synth2W
C	Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter c_requiredTrueHeader bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter c_resetOnEven bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_resetDuration bound to: 10 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_bitslip_mindly bound to: 2 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter c_bitslip_waitdly bound to: 40 - type: integer 
2default:defaulth p
x
 
ª
synthesizing module '%s'638*oasys2*
lpgbtfpga_framealigner2default:default2¥
ŽD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_framealigner.vhd2default:default2
642default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter c_wordRatio bound to: 8 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter c_wordSize bound to: 32 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter c_headerPattern bound to: 2'b01 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter c_allowedFalseHeader bound to: 5 - type: integer 
2default:defaulth p
x
 
o
%s
*synth2W
C	Parameter c_allowedFalseHeaderOverN bound to: 64 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter c_requiredTrueHeader bound to: 32 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_alignementMode bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter c_resetOnEven bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_resetDuration bound to: 10 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter c_bitslip_mindly bound to: 2 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter c_bitslip_waitdly bound to: 40 - type: integer 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
‰
synthesizing module '%s'638*oasys2$
bit_synchronizer2default:default2Š
tD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd2default:default2
752default:default8@Z8-638h px 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
Å
%done synthesizing module '%s' (%s#%s)256*oasys2$
bit_synchronizer2default:default2
622default:default2
12default:default2Š
tD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd2default:default2
752default:default8@Z8-256h px 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
æ
%done synthesizing module '%s' (%s#%s)256*oasys2*
lpgbtfpga_framealigner2default:default2
632default:default2
12default:default2¥
ŽD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_framealigner.vhd2default:default2
642default:default8@Z8-256h px 
a
%s
*synth2I
5	Parameter c_clockRatio bound to: 8 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter c_inputWidth bound to: 32 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter c_outputWidth bound to: 256 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter c_counterInitValue bound to: 2 - type: integer 
2default:defaulth p
x
 
¤
synthesizing module '%s'638*oasys2'
lpgbtfpga_rxGearbox2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_rxgearbox.vhd2default:default2
512default:default8@Z8-638h px 
a
%s
*synth2I
5	Parameter c_clockRatio bound to: 8 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter c_inputWidth bound to: 32 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter c_outputWidth bound to: 256 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter c_counterInitValue bound to: 2 - type: integer 
2default:defaulth p
x
 
à
%done synthesizing module '%s' (%s#%s)256*oasys2'
lpgbtfpga_rxGearbox2default:default2
642default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_rxgearbox.vhd2default:default2
512default:default8@Z8-256h px 
]
%s
*synth2E
1	Parameter DATARATE bound to: 2 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
¬
synthesizing module '%s'638*oasys2+
lpgbtfpga_deinterleaver2default:default2¦
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_deinterleaver.vhd2default:default2
432default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter DATARATE bound to: 2 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
è
%done synthesizing module '%s' (%s#%s)256*oasys2+
lpgbtfpga_deinterleaver2default:default2
652default:default2
12default:default2¦
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_deinterleaver.vhd2default:default2
432default:default8@Z8-256h px 
]
%s
*synth2E
1	Parameter DATARATE bound to: 2 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
 
synthesizing module '%s'638*oasys2%
lpgbtfpga_decoder2default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_decoder.vhd2default:default2
512default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter DATARATE bound to: 2 - type: integer 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter N bound to: 31 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter K bound to: 29 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SYMB_BITWIDTH bound to: 5 - type: integer 
2default:defaulth p
x
 
¢
synthesizing module '%s'638*oasys2%
rs_decoder_N31K292default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd2default:default2
312default:default8@Z8-638h px 
W
%s
*synth2?
+	Parameter N bound to: 31 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter K bound to: 29 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SYMB_BITWIDTH bound to: 5 - type: integer 
2default:defaulth p
x
 
þ
default block is never used226*oasys2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd2default:default2
722default:default8@Z8-226h px 
ÿ
default block is never used226*oasys2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd2default:default2
1192default:default8@Z8-226h px 
Þ
%done synthesizing module '%s' (%s#%s)256*oasys2%
rs_decoder_N31K292default:default2
662default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd2default:default2
312default:default8@Z8-256h px 
W
%s
*synth2?
+	Parameter N bound to: 31 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter K bound to: 29 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SYMB_BITWIDTH bound to: 5 - type: integer 
2default:defaulth p
x
 
Ü
%done synthesizing module '%s' (%s#%s)256*oasys2%
lpgbtfpga_decoder2default:default2
672default:default2
12default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_decoder.vhd2default:default2
512default:default8@Z8-256h px 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
¨
synthesizing module '%s'638*oasys2)
lpgbtfpga_descrambler2default:default2¤
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_descrambler.vhd2default:default2
452default:default8@Z8-638h px 
X
%s
*synth2@
,	Parameter FEC bound to: 1 - type: integer 
2default:defaulth p
x
 
­
synthesizing module '%s'638*oasys2+
descrambler58bitOrder582default:default2§
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_58bitOrder58.vhd2default:default2
342default:default8@Z8-638h px 
é
%done synthesizing module '%s' (%s#%s)256*oasys2+
descrambler58bitOrder582default:default2
682default:default2
12default:default2§
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_58bitOrder58.vhd2default:default2
342default:default8@Z8-256h px 
­
synthesizing module '%s'638*oasys2+
descrambler60bitOrder582default:default2§
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_60bitOrder58.vhd2default:default2
342default:default8@Z8-638h px 
é
%done synthesizing module '%s' (%s#%s)256*oasys2+
descrambler60bitOrder582default:default2
692default:default2
12default:default2§
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/descrambler_60bitOrder58.vhd2default:default2
342default:default8@Z8-256h px 
ä
%done synthesizing module '%s' (%s#%s)256*oasys2)
lpgbtfpga_descrambler2default:default2
702default:default2
12default:default2¤
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/uplink/lpgbtfpga_descrambler.vhd2default:default2
452default:default8@Z8-256h px 
ß
%done synthesizing module '%s' (%s#%s)256*oasys2*
lpgbtfpga_uplink_fixed2default:default2
712default:default2
12default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fpga/lpgbtfpga_uplink_fixed.vhd2default:default2
912default:default8@Z8-256h px 
™
synthesizing module '%s'638*oasys24
 bit_synchronizer__parameterized12default:default2Š
tD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd2default:default2
752default:default8@Z8-638h px 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
Õ
%done synthesizing module '%s' (%s#%s)256*oasys24
 bit_synchronizer__parameterized12default:default2
712default:default2
12default:default2Š
tD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/common/bit_synchronizer.vhd2default:default2
752default:default8@Z8-256h px 
b
%s
*synth2J
6	Parameter BUFGCE_DIVIDE bound to: 8 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter CE_TYPE bound to: SYNC - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter HARDSYNC_CLR bound to: FALSE - type: string 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter IS_CE_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter IS_CLR_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter IS_I_INVERTED bound to: 1'b0 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter SIM_DEVICE bound to: ULTRASCALE - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter STARTUP_SYNC bound to: FALSE - type: string 
2default:defaulth p
x
 
ž
,binding component instance '%s' to cell '%s'113*oasys2$
bufgce_clk_40_rx2default:default2

BUFGCE_DIV2default:default2k
UD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/TCDS2_if.vhd2default:default2
5002default:default8@Z8-113h px 
¶
synthesizing module '%s'%s4497*oasys2$
upLinkTxDataPath2default:default2
 2default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxDataPath.v2default:default2
402default:default8@Z8-6157h px 
¶
synthesizing module '%s'%s4497*oasys2$
upLinkDataSelect2default:default2
 2default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkDataSelect.v2default:default2
342default:default8@Z8-6157h px 
L
%s
*synth24
 	Parameter FEC5 bound to: 1'b0 
2default:defaulth p
x
 
M
%s
*synth25
!	Parameter FEC12 bound to: 1'b1 
2default:defaulth p
x
 
L
%s
*synth24
 	Parameter DR5G bound to: 1'b0 
2default:defaulth p
x
 
M
%s
*synth25
!	Parameter DR10G bound to: 1'b1 
2default:defaulth p
x
 
ò
'done synthesizing module '%s'%s (%s#%s)4495*oasys2$
upLinkDataSelect2default:default2
 2default:default2
722default:default2
12default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkDataSelect.v2default:default2
342default:default8@Z8-6155h px 
´
synthesizing module '%s'%s4497*oasys2#
upLinkScrambler2default:default2
 2default:default2œ
…D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkScrambler.v2default:default2
352default:default8@Z8-6157h px 
L
%s
*synth24
 	Parameter FEC5 bound to: 1'b0 
2default:defaulth p
x
 
M
%s
*synth25
!	Parameter FEC12 bound to: 1'b1 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter TxDataRate5G12 bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter TxDataRate10G24 bound to: 1'b1 
2default:defaulth p
x
 
À
synthesizing module '%s'%s4497*oasys2)
scrambler58bitOrder582default:default2
 2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler58bitOrder58.v2default:default2
142default:default8@Z8-6157h px 
‹
%s
*synth2s
_	Parameter INIT_SEED bound to: 58'b0100010010101010111010101000010010001100011011101000010001 
2default:defaulth p
x
 
ü
'done synthesizing module '%s'%s (%s#%s)4495*oasys2)
scrambler58bitOrder582default:default2
 2default:default2
732default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler58bitOrder58.v2default:default2
142default:default8@Z8-6155h px 
À
synthesizing module '%s'%s4497*oasys2)
scrambler60bitOrder582default:default2
 2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler60bitOrder58.v2default:default2
152default:default8@Z8-6157h px 

%s
*synth2u
a	Parameter INIT_SEED bound to: 60'b000111111010101010110001001001001100101011011110000100010001 
2default:defaulth p
x
 
ü
'done synthesizing module '%s'%s (%s#%s)4495*oasys2)
scrambler60bitOrder582default:default2
 2default:default2
742default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler60bitOrder58.v2default:default2
152default:default8@Z8-6155h px 
À
synthesizing module '%s'%s4497*oasys2)
scrambler51bitOrder492default:default2
 2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler51bitOrder49.v2default:default2
152default:default8@Z8-6157h px 
„
%s
*synth2l
X	Parameter INIT_SEED bound to: 51'b111111100011000001101011011101010101100101000010100 
2default:defaulth p
x
 
ü
'done synthesizing module '%s'%s (%s#%s)4495*oasys2)
scrambler51bitOrder492default:default2
 2default:default2
752default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler51bitOrder49.v2default:default2
152default:default8@Z8-6155h px 
À
synthesizing module '%s'%s4497*oasys2)
scrambler53bitOrder492default:default2
 2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler53bitOrder49.v2default:default2
152default:default8@Z8-6157h px 
†
%s
*synth2n
Z	Parameter INIT_SEED bound to: 53'b11111000101100011010010001010101010110001101000011010 
2default:defaulth p
x
 
ü
'done synthesizing module '%s'%s (%s#%s)4495*oasys2)
scrambler53bitOrder492default:default2
 2default:default2
762default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/scrambler53bitOrder49.v2default:default2
152default:default8@Z8-6155h px 
ð
'done synthesizing module '%s'%s (%s#%s)4495*oasys2#
upLinkScrambler2default:default2
 2default:default2
772default:default2
12default:default2œ
…D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkScrambler.v2default:default2
352default:default8@Z8-6155h px 
¶
synthesizing module '%s'%s4497*oasys2$
upLinkFECEncoder2default:default2
 2default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkFECEncoder.v2default:default2
342default:default8@Z8-6157h px 
¸
synthesizing module '%s'%s4497*oasys2%
rs_encoder_N31K292default:default2
 2default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
302default:default8@Z8-6157h px 
W
%s
*synth2?
+	Parameter N bound to: 31 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter K bound to: 29 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SYMB_BITWIDTH bound to: 5 - type: integer 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter P bound to: 2 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter INP_BW bound to: 145 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter OUT_BW bound to: 155 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter POL_BW bound to: 10 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter STG_BW bound to: 15 - type: integer 
2default:defaulth p
x
 
¤
synthesizing module '%s'%s4497*oasys2
gf_add_52default:default2
 2default:default2”
~D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_5.v2default:default2
12default:default8@Z8-6157h px 
à
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
gf_add_52default:default2
 2default:default2
782default:default2
12default:default2”
~D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_5.v2default:default2
12default:default8@Z8-6155h px 
­
synthesizing module '%s'%s4497*oasys2 
gf_multBy2_52default:default2
 2default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_5.v2default:default2
12default:default8@Z8-6157h px 
é
'done synthesizing module '%s'%s (%s#%s)4495*oasys2 
gf_multBy2_52default:default2
 2default:default2
792default:default2
12default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_5.v2default:default2
12default:default8@Z8-6155h px 
­
synthesizing module '%s'%s4497*oasys2 
gf_multBy3_52default:default2
 2default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_5.v2default:default2
12default:default8@Z8-6157h px 
é
'done synthesizing module '%s'%s (%s#%s)4495*oasys2 
gf_multBy3_52default:default2
 2default:default2
802default:default2
12default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_5.v2default:default2
12default:default8@Z8-6155h px 
ô
'done synthesizing module '%s'%s (%s#%s)4495*oasys2%
rs_encoder_N31K292default:default2
 2default:default2
812default:default2
12default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N31K29.v2default:default2
302default:default8@Z8-6155h px 
¸
synthesizing module '%s'%s4497*oasys2%
rs_encoder_N15K132default:default2
 2default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
302default:default8@Z8-6157h px 
W
%s
*synth2?
+	Parameter N bound to: 15 - type: integer 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter K bound to: 13 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SYMB_BITWIDTH bound to: 4 - type: integer 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter P bound to: 2 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter INP_BW bound to: 52 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter OUT_BW bound to: 60 - type: integer 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter POL_BW bound to: 8 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter STG_BW bound to: 12 - type: integer 
2default:defaulth p
x
 
¤
synthesizing module '%s'%s4497*oasys2
gf_add_42default:default2
 2default:default2”
~D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_4.v2default:default2
12default:default8@Z8-6157h px 
à
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
gf_add_42default:default2
 2default:default2
822default:default2
12default:default2”
~D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_add_4.v2default:default2
12default:default8@Z8-6155h px 
­
synthesizing module '%s'%s4497*oasys2 
gf_multBy2_42default:default2
 2default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_4.v2default:default2
12default:default8@Z8-6157h px 
é
'done synthesizing module '%s'%s (%s#%s)4495*oasys2 
gf_multBy2_42default:default2
 2default:default2
832default:default2
12default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy2_4.v2default:default2
12default:default8@Z8-6155h px 
­
synthesizing module '%s'%s4497*oasys2 
gf_multBy3_42default:default2
 2default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_4.v2default:default2
12default:default8@Z8-6157h px 
é
'done synthesizing module '%s'%s (%s#%s)4495*oasys2 
gf_multBy3_42default:default2
 2default:default2
842default:default2
12default:default2™
‚D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/gf_multBy3_4.v2default:default2
12default:default8@Z8-6155h px 
ô
'done synthesizing module '%s'%s (%s#%s)4495*oasys2%
rs_encoder_N15K132default:default2
 2default:default2
852default:default2
12default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/rs_encoder_N15K13.v2default:default2
302default:default8@Z8-6155h px 
ò
'done synthesizing module '%s'%s (%s#%s)4495*oasys2$
upLinkFECEncoder2default:default2
 2default:default2
862default:default2
12default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkFECEncoder.v2default:default2
342default:default8@Z8-6155h px 
¸
synthesizing module '%s'%s4497*oasys2%
upLinkInterleaver2default:default2
 2default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkInterleaver.v2default:default2
282default:default8@Z8-6157h px 
L
%s
*synth24
 	Parameter FEC5 bound to: 1'b0 
2default:defaulth p
x
 
M
%s
*synth25
!	Parameter FEC12 bound to: 1'b1 
2default:defaulth p
x
 
V
%s
*synth2>
*	Parameter TxDataRate5G12 bound to: 1'b0 
2default:defaulth p
x
 
W
%s
*synth2?
+	Parameter TxDataRate10G24 bound to: 1'b1 
2default:defaulth p
x
 
O
%s
*synth27
#	Parameter HEADER bound to: 2'b10 
2default:defaulth p
x
 
ô
'done synthesizing module '%s'%s (%s#%s)4495*oasys2%
upLinkInterleaver2default:default2
 2default:default2
872default:default2
12default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkInterleaver.v2default:default2
282default:default8@Z8-6155h px 
ò
'done synthesizing module '%s'%s (%s#%s)4495*oasys2$
upLinkTxDataPath2default:default2
 2default:default2
882default:default2
12default:default2
†D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxDataPath.v2default:default2
402default:default8@Z8-6155h px 
`
%s
*synth2H
4	Parameter WORD_WIDTH bound to: 32 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter DATA_RATE bound to: 2 - type: integer 
2default:defaulth p
x
 
´
synthesizing module '%s'%s4497*oasys2#
upLinkTxGearBox2default:default2
 2default:default2œ
…D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxGearBox.v2default:default2
292default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter WORD_WIDTH bound to: 32 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter DATA_RATE bound to: 2 - type: integer 
2default:defaulth p
x
 
ð
'done synthesizing module '%s'%s (%s#%s)4495*oasys2#
upLinkTxGearBox2default:default2
 2default:default2
892default:default2
12default:default2œ
…D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tclink/firmware/source/datapath/lpgbt-fe/lpgbt-fe/upLinkTxGearBox.v2default:default2
292default:default8@Z8-6155h px 

%done synthesizing module '%s' (%s#%s)256*oasys2
TCDS2_if2default:default2
902default:default2
12default:default2k
UD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/TTC_if/TCDS2_if.vhd2default:default2
712default:default8@Z8-256h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
ü
synthesizing module '%s'638*oasys2+
xlx_ku_gbt_ngFEC_design2default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
û
synthesizing module '%s'638*oasys2"
gbt_bank_reset2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd2default:default2
1142default:default8@Z8-638h px 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
·
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_bank_reset2default:default2
912default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_reset.vhd2default:default2
1142default:default8@Z8-256h px 
á
synthesizing module '%s'638*oasys2
gbt_bankx122default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
Ö
synthesizing module '%s'638*oasys2
mgtX122default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 0 - type: integer 
2default:defaulth p
x
 
‹
synthesizing module '%s'%s4497*oasys2'
mgt_ip_example_init2default:default2
 2default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_init.v2default:default2
592default:default8@Z8-6157h px 
o
%s
*synth2W
C	Parameter P_FREERUN_FREQUENCY bound to: 50.000000 - type: double 
2default:defaulth p
x
 
u
%s
*synth2]
I	Parameter P_TX_TIMER_DURATION_US bound to: 30000.000000 - type: double 
2default:defaulth p
x
 
v
%s
*synth2^
J	Parameter P_RX_TIMER_DURATION_US bound to: 130000.000000 - type: double 
2default:defaulth p
x
 
Q
%s
*synth29
%	Parameter ST_START bound to: 2'b00 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_TX_WAIT bound to: 2'b01 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_RX_WAIT bound to: 2'b10 
2default:defaulth p
x
 
S
%s
*synth2;
'	Parameter ST_MONITOR bound to: 2'b11 
2default:defaulth p
x
 
Ÿ
synthesizing module '%s'%s4497*oasys25
!mgt_ip_example_reset_synchronizer2default:default2
 2default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_reset_sync.v2default:default2
582default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter FREQUENCY bound to: 512 - type: integer 
2default:defaulth p
x
 
Û
'done synthesizing module '%s'%s (%s#%s)4495*oasys25
!mgt_ip_example_reset_synchronizer2default:default2
 2default:default2
922default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_reset_sync.v2default:default2
582default:default8@Z8-6155h px 
›
synthesizing module '%s'%s4497*oasys23
mgt_ip_example_bit_synchronizer2default:default2
 2default:default2t
^D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_bit_sync.v2default:default2
582default:default8@Z8-6157h px 
V
%s
*synth2>
*	Parameter INITIALIZE bound to: 5'b00000 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter FREQUENCY bound to: 512 - type: integer 
2default:defaulth p
x
 
×
'done synthesizing module '%s'%s (%s#%s)4495*oasys23
mgt_ip_example_bit_synchronizer2default:default2
 2default:default2
932default:default2
12default:default2t
^D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_bit_sync.v2default:default2
582default:default8@Z8-6155h px 
Ç
'done synthesizing module '%s'%s (%s#%s)4495*oasys2'
mgt_ip_example_init2default:default2
 2default:default2
942default:default2
12default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip_example_init.v2default:default2
592default:default8@Z8-6155h px 
Ú
synthesizing module '%s'638*oasys2
mgt_HPTD2default:default2d
ND:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgt_HPTD.vhd2default:default2
792default:default8@Z8-638h px 
û
synthesizing module '%s'638*oasys2
mgt_ip2default:default2†
pD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/synth_1/.Xil/Vivado-15164-baby/realtime/mgt_ip_stub.vhdl2default:default2
602default:default8@Z8-638h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
÷
synthesizing module '%s'%s4497*oasys22
xpm_cdc_single__parameterized22default:default2
 2default:default2P
:D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2
1532default:default8@Z8-6157h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter VERSION bound to: 0 - type: integer 
2default:defaulth p
x
 
³
'done synthesizing module '%s'%s (%s#%s)4495*oasys22
xpm_cdc_single__parameterized22default:default2
 2default:default2
942default:default2
12default:default2P
:D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv2default:default2
1532default:default8@Z8-6155h px 
¶
synthesizing module '%s'638*oasys2$
tx_phase_aligner2default:default2¶
ŸD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd2default:default2
1682default:default8@Z8-638h px 
b
%s
*synth2J
6	Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter g_SPEED_PD_FACTOR bound to: 7 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter g_PI_COARSE_STEP bound to: 8 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter g_PI_FINE_STEP bound to: 1 - type: integer 
2default:defaulth p
x
 
¾
synthesizing module '%s'638*oasys2(
tx_phase_aligner_fsm2default:default2º
£D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd2default:default2
1162default:default8@Z8-638h px 
f
%s
*synth2N
:	Parameter g_SPEED_PD_FACTOR bound to: 7 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter g_PI_COARSE_STEP bound to: 8 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter g_PI_FINE_STEP bound to: 1 - type: integer 
2default:defaulth p
x
 
ú
%done synthesizing module '%s' (%s#%s)256*oasys2(
tx_phase_aligner_fsm2default:default2
952default:default2
12default:default2º
£D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd2default:default2
1162default:default8@Z8-256h px 
b
%s
*synth2J
6	Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 
2default:defaulth p
x
 
ª
synthesizing module '%s'638*oasys2

tx_pi_ctrl2default:default2°
™D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd2default:default2
1152default:default8@Z8-638h px 
b
%s
*synth2J
6	Parameter g_DRP_NPORT_CTRL bound to: 1 - type: bool 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter g_DRP_ADDR_TXPI_PPM_CFG bound to: 9'b010011010 
2default:defaulth p
x
 
æ
%done synthesizing module '%s' (%s#%s)256*oasys2

tx_pi_ctrl2default:default2
962default:default2
12default:default2°
™D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd2default:default2
1152default:default8@Z8-256h px 
»
synthesizing module '%s'638*oasys2'
fifo_fill_level_acc2default:default2¹
¢D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd2default:default2
882default:default8@Z8-638h px 
÷
%done synthesizing module '%s' (%s#%s)256*oasys2'
fifo_fill_level_acc2default:default2
972default:default2
12default:default2¹
¢D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd2default:default2
882default:default8@Z8-256h px 
ò
%done synthesizing module '%s' (%s#%s)256*oasys2$
tx_phase_aligner2default:default2
982default:default2
12default:default2¶
ŸD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/tx_phase_aligner-master/rev_0_1_0/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd2default:default2
1682default:default8@Z8-256h px 
–
%done synthesizing module '%s' (%s#%s)256*oasys2
mgt_HPTD2default:default2
992default:default2
12default:default2d
ND:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgt_HPTD.vhd2default:default2
792default:default8@Z8-256h px 
œ
synthesizing module '%s'638*oasys2#
mgt_bitslipctrl2default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd2default:default2
582default:default8@Z8-638h px 
Ù
%done synthesizing module '%s' (%s#%s)256*oasys2#
mgt_bitslipctrl2default:default2
1002default:default2
12default:default2ž
‡D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_bitslipctrl.vhd2default:default2
582default:default8@Z8-256h px 
´
synthesizing module '%s'638*oasys2/
mgt_framealigner_pattsearch2default:default2ª
“D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd2default:default2
592default:default8@Z8-638h px 
ñ
%done synthesizing module '%s' (%s#%s)256*oasys2/
mgt_framealigner_pattsearch2default:default2
1012default:default2
12default:default2ª
“D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/mgt/mgt_framealigner_pattsearch.vhd2default:default2
592default:default8@Z8-256h px 
“
%done synthesizing module '%s' (%s#%s)256*oasys2
mgtX122default:default2
1022default:default2
12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2
gbt_tx2default:default2˜
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd2default:default2
412default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
¡
synthesizing module '%s'638*oasys2$
gbt_tx_scrambler2default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd2default:default2
782default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
­
synthesizing module '%s'638*oasys2*
gbt_tx_scrambler_21bit2default:default2¨
‘D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd2default:default2
582default:default8@Z8-638h px 
ê
%done synthesizing module '%s' (%s#%s)256*oasys2*
gbt_tx_scrambler_21bit2default:default2
1032default:default2
12default:default2¨
‘D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd2default:default2
582default:default8@Z8-256h px 
Þ
%done synthesizing module '%s' (%s#%s)256*oasys2$
gbt_tx_scrambler2default:default2
1042default:default2
12default:default2¢
‹D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd2default:default2
782default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2"
gbt_tx_encoder2default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd2default:default2
692default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
Á
synthesizing module '%s'638*oasys24
 gbt_tx_encoder_gbtframe_rsencode2default:default2²
›D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd2default:default2
312default:default8@Z8-638h px 
¿
synthesizing module '%s'638*oasys23
gbt_tx_encoder_gbtframe_polydiv2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd2default:default2
332default:default8@Z8-638h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_tx_encoder_gbtframe_polydiv2default:default2
1052default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd2default:default2
332default:default8@Z8-256h px 
þ
%done synthesizing module '%s' (%s#%s)256*oasys24
 gbt_tx_encoder_gbtframe_rsencode2default:default2
1062default:default2
12default:default2²
›D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd2default:default2
312default:default8@Z8-256h px 
¿
synthesizing module '%s'638*oasys23
gbt_tx_encoder_gbtframe_intlver2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd2default:default2
282default:default8@Z8-638h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_tx_encoder_gbtframe_intlver2default:default2
1072default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd2default:default2
282default:default8@Z8-256h px 
Ú
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_tx_encoder2default:default2
1082default:default2
12default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd2default:default2
692default:default8@Z8-256h px 
Ê
%done synthesizing module '%s' (%s#%s)256*oasys2
gbt_tx2default:default2
1092default:default2
12default:default2˜
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd2default:default2
412default:default8@Z8-256h px 
ú
synthesizing module '%s'638*oasys2"
gbt_tx_gearbox2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd2default:default2
652default:default8@Z8-638h px 
·
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_tx_gearbox2default:default2
1102default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_tx_gearbox.vhd2default:default2
652default:default8@Z8-256h px 
ú
synthesizing module '%s'638*oasys2"
gbt_rx_gearbox2default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd2default:default2
512default:default8@Z8-638h px 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
·
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_rx_gearbox2default:default2
1112default:default2
12default:default2~
hD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_rx_gearbox.vhd2default:default2
512default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2
gbt_rx2default:default2˜
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd2default:default2
542default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 

synthesizing module '%s'638*oasys2"
gbt_rx_decoder2default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2
572default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
Ã
synthesizing module '%s'638*oasys25
!gbt_rx_decoder_gbtframe_deintlver2default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd2default:default2
352default:default8@Z8-638h px 
€
%done synthesizing module '%s' (%s#%s)256*oasys25
!gbt_rx_decoder_gbtframe_deintlver2default:default2
1122default:default2
12default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd2default:default2
352default:default8@Z8-256h px 
»
synthesizing module '%s'638*oasys21
gbt_rx_decoder_gbtframe_rsdec2default:default2¯
˜D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd2default:default2
462default:default8@Z8-638h px 
¿
synthesizing module '%s'638*oasys23
gbt_rx_decoder_gbtframe_syndrom2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd2default:default2
422default:default8@Z8-638h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_rx_decoder_gbtframe_syndrom2default:default2
1132default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd2default:default2
422default:default8@Z8-256h px 
¿
synthesizing module '%s'638*oasys23
gbt_rx_decoder_gbtframe_lmbddet2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd2default:default2
422default:default8@Z8-638h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_rx_decoder_gbtframe_lmbddet2default:default2
1142default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd2default:default2
422default:default8@Z8-256h px 
Ã
synthesizing module '%s'638*oasys25
!gbt_rx_decoder_gbtframe_errlcpoly2default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd2default:default2
442default:default8@Z8-638h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
€
%done synthesizing module '%s' (%s#%s)256*oasys25
!gbt_rx_decoder_gbtframe_errlcpoly2default:default2
1152default:default2
12default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd2default:default2
442default:default8@Z8-256h px 
¿
synthesizing module '%s'638*oasys23
gbt_rx_decoder_gbtframe_chnsrch2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd2default:default2
442default:default8@Z8-638h px 
¿
synthesizing module '%s'638*oasys23
gbt_rx_decoder_gbtframe_elpeval2default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd2default:default2
412default:default8@Z8-638h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_rx_decoder_gbtframe_elpeval2default:default2
1162default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd2default:default2
412default:default8@Z8-256h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
ü
%done synthesizing module '%s' (%s#%s)256*oasys23
gbt_rx_decoder_gbtframe_chnsrch2default:default2
1172default:default2
12default:default2±
šD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd2default:default2
442default:default8@Z8-256h px 
Ã
synthesizing module '%s'638*oasys25
!gbt_rx_decoder_gbtframe_rs2errcor2default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd2default:default2
452default:default8@Z8-638h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1302default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1552default:default8@Z8-226h px 
Ý
default block is never used226*oasys2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_fpga6_1_0_patch/gbt_bank_package.vhd2default:default2
1552default:default8@Z8-226h px 
€
%done synthesizing module '%s' (%s#%s)256*oasys25
!gbt_rx_decoder_gbtframe_rs2errcor2default:default2
1182default:default2
12default:default2³
œD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd2default:default2
452default:default8@Z8-256h px 
ø
%done synthesizing module '%s' (%s#%s)256*oasys21
gbt_rx_decoder_gbtframe_rsdec2default:default2
1192default:default2
12default:default2¯
˜D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd2default:default2
462default:default8@Z8-256h px 
Ç
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2

RX_RESET_I2default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2
1242default:default8@Z8-614h px 
Ú
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_rx_decoder2default:default2
1202default:default2
12default:default2 
‰D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd2default:default2
572default:default8@Z8-256h px 
¥
synthesizing module '%s'638*oasys2&
gbt_rx_descrambler2default:default2¤
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd2default:default2
572default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
±
synthesizing module '%s'638*oasys2,
gbt_rx_descrambler_21bit2default:default2ª
“D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd2default:default2
562default:default8@Z8-638h px 
î
%done synthesizing module '%s' (%s#%s)256*oasys2,
gbt_rx_descrambler_21bit2default:default2
1212default:default2
12default:default2ª
“D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd2default:default2
562default:default8@Z8-256h px 
â
%done synthesizing module '%s' (%s#%s)256*oasys2&
gbt_rx_descrambler2default:default2
1222default:default2
12default:default2¤
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd2default:default2
572default:default8@Z8-256h px 
Ê
%done synthesizing module '%s' (%s#%s)256*oasys2
gbt_rx2default:default2
1232default:default2
12default:default2˜
D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt-fpga-gbt_fpga_6_1_0/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd2default:default2
542default:default8@Z8-256h px 
ž
%done synthesizing module '%s' (%s#%s)256*oasys2
gbt_bankx122default:default2
1242default:default2
12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-256h px 
¹
%done synthesizing module '%s' (%s#%s)256*oasys2+
xlx_ku_gbt_ngFEC_design2default:default2
1252default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-256h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
Œ
synthesizing module '%s'638*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
ñ
synthesizing module '%s'638*oasys2/
gbt_bankx12__parameterized02default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
æ
synthesizing module '%s'638*oasys2*
mgtX12__parameterized02default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 1 - type: integer 
2default:defaulth p
x
 
£
%done synthesizing module '%s' (%s#%s)256*oasys2*
mgtX12__parameterized02default:default2
1252default:default2
12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-256h px 
®
%done synthesizing module '%s' (%s#%s)256*oasys2/
gbt_bankx12__parameterized02default:default2
1252default:default2
12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-256h px 
É
%done synthesizing module '%s' (%s#%s)256*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized12default:default2
1252default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-256h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
Œ
synthesizing module '%s'638*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized32default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
ñ
synthesizing module '%s'638*oasys2/
gbt_bankx12__parameterized12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
æ
synthesizing module '%s'638*oasys2*
mgtX12__parameterized12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 2 - type: integer 
2default:defaulth p
x
 
£
%done synthesizing module '%s' (%s#%s)256*oasys2*
mgtX12__parameterized12default:default2
1252default:default2
12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-256h px 
®
%done synthesizing module '%s' (%s#%s)256*oasys2/
gbt_bankx12__parameterized12default:default2
1252default:default2
12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-256h px 
É
%done synthesizing module '%s' (%s#%s)256*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized32default:default2
1252default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-256h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 3 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
Œ
synthesizing module '%s'638*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized52default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 3 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter INITIAL_DELAY bound to: 50000000 - type: integer 
2default:defaulth p
x
 
ñ
synthesizing module '%s'638*oasys2/
gbt_bankx12__parameterized22default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 3 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter TX_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter RX_OPTIMIZATION bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter TX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter RX_ENCODING bound to: 0 - type: integer 
2default:defaulth p
x
 
æ
synthesizing module '%s'638*oasys2*
mgtX12__parameterized22default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-638h px 
[
%s
*synth2C
/	Parameter BLK_No bound to: 3 - type: integer 
2default:defaulth p
x
 
£
%done synthesizing module '%s' (%s#%s)256*oasys2*
mgtX12__parameterized22default:default2
1252default:default2
12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/mgtX12.vhd2default:default2
652default:default8@Z8-256h px 
®
%done synthesizing module '%s' (%s#%s)256*oasys2/
gbt_bankx12__parameterized22default:default2
1252default:default2
12default:default2g
QD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/gbt_bankx12.vhd2default:default2
1042default:default8@Z8-256h px 
É
%done synthesizing module '%s' (%s#%s)256*oasys2;
'xlx_ku_gbt_ngFEC_design__parameterized52default:default2
1252default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/xlx_ku_gbt_ngFEC_designx12.vhd2default:default2
1652default:default8@Z8-256h px 
Ü
synthesizing module '%s'638*oasys2
prbs2default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/GBT_tools/prbs.vhd2default:default2
432default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter seed bound to: 20'b00101010001000000001 
2default:defaulth p
x
 
Z
%s
*synth2B
.	Parameter inverter bound to: 0 - type: bool 
2default:defaulth p
x
 
X
%s
*synth2@
,	Parameter hbhehf bound to: 0 - type: bool 
2default:defaulth p
x
 
™
%done synthesizing module '%s' (%s#%s)256*oasys2
prbs2default:default2
1262default:default2
12default:default2j
TD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/GBT_tools/prbs.vhd2default:default2
432default:default8@Z8-256h px 
õ
synthesizing module '%s'638*oasys2 
ngFEC_module2default:default2{
eD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2
582default:default8@Z8-638h px 
ñ
synthesizing module '%s'638*oasys2

Module_RAM2default:default2y
cD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2
472default:default8@Z8-638h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 65536 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLOCKING_MODE bound to: common_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_A bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_A bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_B bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 

synthesizing module '%s'%s4497*oasys25
!xpm_memory_tdpram__parameterized22default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
88712default:default8@Z8-6157h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 65536 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLOCKING_MODE bound to: common_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_A bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_A bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_B bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter P_CLOCKING_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter P_ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_WRITE_MODE_A bound to: 2 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
ý
synthesizing module '%s'%s4497*oasys23
xpm_memory_base__parameterized02default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter MEMORY_TYPE bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 65536 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CLOCKING_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter VERSION bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_A bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_A bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter ADDR_WIDTH_B bound to: 11 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MAX_DEPTH_DATA bound to: 2048 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_MEMORY_OPT bound to: yes - type: string 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_WIDTH_ADDR_WRITE_A bound to: 11 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_WIDTH_ADDR_WRITE_B bound to: 11 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_READ_A bound to: 11 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_READ_B bound to: 11 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rsta_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rstb_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
2default:defaulth p
x
 
Ñ
Synth Info: %s 4384*oasys2¦
‘[XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
4902default:default8@Z8-6059h px 
º
'done synthesizing module '%s'%s (%s#%s)4495*oasys23
xpm_memory_base__parameterized02default:default2
 2default:default2
1262default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6155h px 
¾
'done synthesizing module '%s'%s (%s#%s)4495*oasys25
!xpm_memory_tdpram__parameterized22default:default2
 2default:default2
1262default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
88712default:default8@Z8-6155h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLOCKING_MODE bound to: common_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
ñ
synthesizing module '%s'%s4497*oasys2%
xpm_memory_sdpram2default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
84042default:default8@Z8-6157h px 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter CLOCKING_MODE bound to: common_clock - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter WAKEUP_TIME bound to: disable_sleep - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_MODE_B bound to: no_change - type: string 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter P_CLOCKING_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter P_ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_OPTIMIZATION bound to: 1 - type: integer 
2default:defaulth p
x
 
ý
synthesizing module '%s'%s4497*oasys23
xpm_memory_base__parameterized12default:default2
 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter MEMORY_TYPE bound to: 1 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MEMORY_SIZE bound to: 16384 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter CLOCKING_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter ECC_MODE bound to: 0 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter MEMORY_INIT_FILE bound to: none - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter USE_MEM_INIT bound to: 1 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter WAKEUP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter VERSION bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WRITE_PROTECT bound to: 1 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_A bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_A bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_A bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_A bound to: SYNC - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter ADDR_WIDTH_B bound to: 9 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter READ_LATENCY_B bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WRITE_MODE_B bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter RST_MODE_B bound to: SYNC - type: string 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MEMORY_PRIMITIVE bound to: block - type: string 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_MAX_DEPTH_DATA bound to: 512 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter P_ECC_MODE bound to: no_ecc - type: string 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter P_MEMORY_OPT bound to: yes - type: string 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
2default:defaulth p
x
 
g
%s
*synth2O
;	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_WRITE_A bound to: 9 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_WIDTH_ADDR_WRITE_B bound to: 9 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_WIDTH_ADDR_READ_A bound to: 9 - type: integer 
2default:defaulth p
x
 
h
%s
*synth2P
<	Parameter P_WIDTH_ADDR_READ_B bound to: 9 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
m
%s
*synth2U
A	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
2default:defaulth p
x
 
l
%s
*synth2T
@	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
2default:defaulth p
x
 
j
%s
*synth2R
>	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
2default:defaulth p
x
 
e
%s
*synth2M
9	Parameter P_SDP_WRITE_MODE bound to: no - type: string 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rsta_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter rstb_loop_iter bound to: 32 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
2default:defaulth p
x
 
k
%s
*synth2S
?	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer 
2default:defaulth p
x
 
i
%s
*synth2Q
=	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
2default:defaulth p
x
 
Ñ
Synth Info: %s 4384*oasys2¦
‘[XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. 2default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
4902default:default8@Z8-6059h px 
º
'done synthesizing module '%s'%s (%s#%s)4495*oasys23
xpm_memory_base__parameterized12default:default2
 2default:default2
1262default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
572default:default8@Z8-6155h px 
®
'done synthesizing module '%s'%s (%s#%s)4495*oasys2%
xpm_memory_sdpram2default:default2
 2default:default2
1272default:default2
12default:default2V
@D:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv2default:default2
84042default:default8@Z8-6155h px 
®
%done synthesizing module '%s' (%s#%s)256*oasys2

Module_RAM2default:default2
1282default:default2
12default:default2y
cD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/Module_RAM.vhd2default:default2
472default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00000 
2default:defaulth p
x
 
ƒ
synthesizing module '%s'638*oasys2%
buffer_server_com2default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00000 
2default:defaulth p
x
 
À
%done synthesizing module '%s' (%s#%s)256*oasys2%
buffer_server_com2default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00001 
2default:defaulth p
x
 
“
synthesizing module '%s'638*oasys25
!buffer_server_com__parameterized12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00001 
2default:defaulth p
x
 
Ð
%done synthesizing module '%s' (%s#%s)256*oasys25
!buffer_server_com__parameterized12default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00010 
2default:defaulth p
x
 
“
synthesizing module '%s'638*oasys25
!buffer_server_com__parameterized32default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00010 
2default:defaulth p
x
 
Ð
%done synthesizing module '%s' (%s#%s)256*oasys25
!buffer_server_com__parameterized32default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00011 
2default:defaulth p
x
 
“
synthesizing module '%s'638*oasys25
!buffer_server_com__parameterized52default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00011 
2default:defaulth p
x
 
Ð
%done synthesizing module '%s' (%s#%s)256*oasys25
!buffer_server_com__parameterized52default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00100 
2default:defaulth p
x
 
“
synthesizing module '%s'638*oasys25
!buffer_server_com__parameterized72default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00100 
2default:defaulth p
x
 
Ð
%done synthesizing module '%s' (%s#%s)256*oasys25
!buffer_server_com__parameterized72default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00101 
2default:defaulth p
x
 
“
synthesizing module '%s'638*oasys25
!buffer_server_com__parameterized92default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00101 
2default:defaulth p
x
 
Ð
%done synthesizing module '%s' (%s#%s)256*oasys25
!buffer_server_com__parameterized92default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00110 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized112default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00110 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized112default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00111 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized132default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00111 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized132default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01000 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized152default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01000 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized152default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01001 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized172default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01001 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized172default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01010 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized192default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01010 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized192default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01011 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized212default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01011 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized212default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01111 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized232default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01111 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized232default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b11111 
2default:defaulth p
x
 
”
synthesizing module '%s'638*oasys26
"buffer_server_com__parameterized252default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-638h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b11111 
2default:defaulth p
x
 
Ñ
%done synthesizing module '%s' (%s#%s)256*oasys26
"buffer_server_com__parameterized252default:default2
1292default:default2
12default:default2ƒ
mD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_server_comNew.vhd2default:default2
462default:default8@Z8-256h px 

synthesizing module '%s'638*oasys2$
buffer_ngccm_com2default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_comNew.vhd2default:default2
482default:default8@Z8-638h px 
¾
%done synthesizing module '%s' (%s#%s)256*oasys2$
buffer_ngccm_com2default:default2
1302default:default2
12default:default2‚
lD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_comNew.vhd2default:default2
482default:default8@Z8-256h px 
‹
synthesizing module '%s'638*oasys2)
buffer_ngccm_jtag_com2default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_jtag_comNew.vhd2default:default2
492default:default8@Z8-638h px 
È
%done synthesizing module '%s' (%s#%s)256*oasys2)
buffer_ngccm_jtag_com2default:default2
1312default:default2
12default:default2‡
qD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/buffer_ngccm_jtag_comNew.vhd2default:default2
492default:default8@Z8-256h px 
²
%done synthesizing module '%s' (%s#%s)256*oasys2 
ngFEC_module2default:default2
1322default:default2
12default:default2{
eD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngFEC_module/ngFEC_module.vhd2default:default2
582default:default8@Z8-256h px 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
ê
synthesizing module '%s'638*oasys2!
delay_counter2default:default2o
YD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/delay_counter.vhd2default:default2
412default:default8@Z8-638h px 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
§
%done synthesizing module '%s' (%s#%s)256*oasys2!
delay_counter2default:default2
1332default:default2
12default:default2o
YD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/delay_counter.vhd2default:default2
412default:default8@Z8-256h px 
à
synthesizing module '%s'638*oasys2
ngCCM2default:default2m
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd2default:default2
942default:default8@Z8-638h px 
í
synthesizing module '%s'638*oasys2
SyncRst2default:default2x
bD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/SyncRst.vhd2default:default2
342default:default8@Z8-638h px 
ª
%done synthesizing module '%s' (%s#%s)256*oasys2
SyncRst2default:default2
1342default:default2
12default:default2x
bD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/SyncRst.vhd2default:default2
342default:default8@Z8-256h px 
ð
synthesizing module '%s'638*oasys2"
gbt_rx_checker2default:default2t
^D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/GBT_tools/gbt_rx_checker.vhd2default:default2
442default:default8@Z8-638h px 
a
%s
*synth2I
5	Parameter seed_length bound to: 20 - type: integer 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter nobReg bound to: 32 - type: integer 
2default:defaulth p
x
 
­
%done synthesizing module '%s' (%s#%s)256*oasys2"
gbt_rx_checker2default:default2
1352default:default2
12default:default2t
^D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/GBT_tools/gbt_rx_checker.vhd2default:default2
442default:default8@Z8-256h px 
`
%s
*synth2H
4	Parameter DataBtoA_SZ bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DataAtoB_SZ bound to: 84 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WAIT_STATES_A bound to: 0 - type: integer 
2default:defaulth p
x
 
‘
synthesizing module '%s'%s4497*oasys2!
CrossClock_RX2default:default2
 2default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
202default:default8@Z8-6157h px 
`
%s
*synth2H
4	Parameter DataBtoA_SZ bound to: 1 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DataAtoB_SZ bound to: 84 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter WAIT_STATES_A bound to: 0 - type: integer 
2default:defaulth p
x
 
_
%s
*synth2G
3	Parameter SHIFTA_MSB bound to: 3 - type: integer 
2default:defaulth p
x
 
Î
'done synthesizing module '%s'%s (%s#%s)4495*oasys2!
CrossClock_RX2default:default2
 2default:default2
1362default:default2
12default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
202default:default8@Z8-6155h px 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
õ
synthesizing module '%s'638*oasys2
IPbus_local2default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/IPbus_local.vhd2default:default2
582default:default8@Z8-638h px 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
²
%done synthesizing module '%s' (%s#%s)256*oasys2
IPbus_local2default:default2
1372default:default2
12default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/IPbus_local.vhd2default:default2
582default:default8@Z8-256h px 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter ADDR_MSB bound to: 11 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
f
%s
*synth2N
:	Parameter WRITE_PULSE_TICKS bound to: 2 - type: integer 
2default:defaulth p
x
 
ò
synthesizing module '%s'638*oasys2"
LocalI2CBridge2default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/LocalI2CBridge.vhd2default:default2
792default:default8@Z8-638h px 
P
%s
*synth28
$	Parameter ARST_LVL bound to: 1'b0 
2default:defaulth p
x
 
÷
synthesizing module '%s'638*oasys2"
i2c_master_usr2default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_top.vhd2default:default2
1132default:default8@Z8-638h px 
P
%s
*synth28
$	Parameter ARST_LVL bound to: 1'b0 
2default:defaulth p
x
 
„
synthesizing module '%s'638*oasys2(
i2c_master_byte_ctrl2default:default2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_byte_ctrl.vhd2default:default2
1142default:default8@Z8-638h px 

synthesizing module '%s'638*oasys2'
i2c_master_bit_ctrl2default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_bit_ctrl.vhd2default:default2
1792default:default8@Z8-638h px 
Y
%s
*synth2A
-	Parameter SIZE bound to: 8 - type: integer 
2default:defaulth p
x
 
P
%s
*synth28
$	Parameter DOUT_RST bound to: 1'b1 
2default:defaulth p
x
 
‘
synthesizing module '%s'%s4497*oasys2!
glitch_filter2default:default2
 2default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/glitch_filter.v2default:default2
572default:default8@Z8-6157h px 
Y
%s
*synth2A
-	Parameter SIZE bound to: 8 - type: integer 
2default:defaulth p
x
 
P
%s
*synth28
$	Parameter DOUT_RST bound to: 1'b1 
2default:defaulth p
x
 
\
%s
*synth2D
0	Parameter BUFSIZE bound to: 7 - type: integer 
2default:defaulth p
x
 
Î
'done synthesizing module '%s'%s (%s#%s)4495*oasys2!
glitch_filter2default:default2
 2default:default2
1382default:default2
12default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/glitch_filter.v2default:default2
572default:default8@Z8-6155h px 
Y
%s
*synth2A
-	Parameter SIZE bound to: 8 - type: integer 
2default:defaulth p
x
 
P
%s
*synth28
$	Parameter DOUT_RST bound to: 1'b1 
2default:defaulth p
x
 
¾
%done synthesizing module '%s' (%s#%s)256*oasys2'
i2c_master_bit_ctrl2default:default2
1392default:default2
12default:default2
iD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_bit_ctrl.vhd2default:default2
1792default:default8@Z8-256h px 
Á
%done synthesizing module '%s' (%s#%s)256*oasys2(
i2c_master_byte_ctrl2default:default2
1402default:default2
12default:default2€
jD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_byte_ctrl.vhd2default:default2
1142default:default8@Z8-256h px 
´
%done synthesizing module '%s' (%s#%s)256*oasys2"
i2c_master_usr2default:default2
1412default:default2
12default:default2z
dD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/i2c_master_top.vhd2default:default2
1132default:default8@Z8-256h px 
¯
%done synthesizing module '%s' (%s#%s)256*oasys2"
LocalI2CBridge2default:default2
1422default:default2
12default:default2v
`D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/LocalI2CBridge.vhd2default:default2
792default:default8@Z8-256h px 
ô
synthesizing module '%s'638*oasys2#
LocalJTAGBridge2default:default2w
aD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/LocalJTAGBridge.vhd2default:default2
942default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter gADDR_BITS bound to: 10 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter gDATA_BITS bound to: 32 - type: integer 
2default:defaulth p
x
 
ê
synthesizing module '%s'638*oasys2

JTAGMaster2default:default2r
\D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/jtagMaster.vhd2default:default2
922default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter gADDR_BITS bound to: 10 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter gDATA_BITS bound to: 32 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter gADDR_BITS bound to: 10 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter gDATA_BITS bound to: 32 - type: integer 
2default:defaulth p
x
 
á
synthesizing module '%s'638*oasys2
RAM2default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/jtagBram.vhd2default:default2
662default:default8@Z8-638h px 
`
%s
*synth2H
4	Parameter gADDR_BITS bound to: 10 - type: integer 
2default:defaulth p
x
 
`
%s
*synth2H
4	Parameter gDATA_BITS bound to: 32 - type: integer 
2default:defaulth p
x
 
ž
%done synthesizing module '%s' (%s#%s)256*oasys2
RAM2default:default2
1432default:default2
12default:default2p
ZD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/jtagBram.vhd2default:default2
662default:default8@Z8-256h px 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
§
%done synthesizing module '%s' (%s#%s)256*oasys2

JTAGMaster2default:default2
1442default:default2
12default:default2r
\D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/jtagMaster.vhd2default:default2
922default:default8@Z8-256h px 
±
%done synthesizing module '%s' (%s#%s)256*oasys2#
LocalJTAGBridge2default:default2
1452default:default2
12default:default2w
aD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/LocalJTAGBridge.vhd2default:default2
942default:default8@Z8-256h px 
–
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 
sel_sec_jtag2default:default2m
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd2default:default2
10862default:default8@Z8-614h px 
–
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 
sel_sec_jtag2default:default2m
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd2default:default2
11072default:default8@Z8-614h px 
–
Esignal '%s' is read in the process but is not in the sensitivity list614*oasys2 
sel_sec_jtag2default:default2m
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd2default:default2
11272default:default8@Z8-614h px 

%done synthesizing module '%s' (%s#%s)256*oasys2
ngCCM2default:default2
1462default:default2
12default:default2m
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/ngCCM.vhd2default:default2
942default:default8@Z8-256h px 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
]
%s
*synth2E
1	Parameter orbit bound to: 3564 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
2default:defaulth p
x
 
c
%s
*synth2K
7	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
2default:defaulth p
x
 
b
%s
*synth2J
6	Parameter SRC_INPUT_REG bound to: 0 - type: integer 
2default:defaulth p
x
 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
Ö
synthesizing module '%s'638*oasys2
I2C_if2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
542default:default8@Z8-638h px 
a
%s
*synth2I
5	Parameter WAIT_STATES bound to: 10 - type: integer 
2default:defaulth p
x
 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00001 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00010 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00011 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00100 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00101 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00110 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b00111 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
U
%s
*synth2=
)	Parameter partition bound to: 5'b01000 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_scl_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2892default:default8@Z8-113h px 
[
%s
*synth2C
/	Parameter DRIVE bound to: 12 - type: integer 
2default:defaulth p
x
 
^
%s
*synth2F
2	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
2default:defaulth p
x
 
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulth p
x
 
[
%s
*synth2C
/	Parameter SLEW bound to: SLOW - type: string 
2default:defaulth p
x
 
Œ
,binding component instance '%s' to cell '%s'113*oasys2 
i2c_sda_inst2default:default2
IOBUF2default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
2902default:default8@Z8-113h px 
“
%done synthesizing module '%s' (%s#%s)256*oasys2
I2C_if2default:default2
1472default:default2
12default:default2b
LD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/I2C_if.vhd2default:default2
542default:default8@Z8-256h px 
™
%done synthesizing module '%s' (%s#%s)256*oasys2
	ngFEC_top2default:default2
1482default:default2
12default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC_top.vhd2default:default2
792default:default8@Z8-256h px 
¦
%s*synth2
yFinished RTL Elaboration : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2000.090 ; gain = 791.625
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
M
%s
*synth25
!Start Handling Custom Attributes
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
²
%s*synth2™
„Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2016.402 ; gain = 807.938
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
°
%s*synth2—
‚Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2016.402 ; gain = 807.938
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
’
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:402default:default2
00:00:402default:default2
4644.0632default:default2
127.3712default:defaultZ17-268h px 
h
-Analyzing %s Unisim elements for replacement
17*netlist2
10312default:defaultZ29-17h px 
k
2Unisim Transformation completed in %s CPU seconds
28*netlist2
172default:defaultZ29-28h px 
K
)Preparing netlist for logic optimization
349*projectZ1-570h px 
>

Processing XDC Constraints
244*projectZ1-262h px 
=
Initializing timing engine
348*projectZ1-569h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Â
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Â
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Â
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Â
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
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-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
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-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¸
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
Á
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2i
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
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-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
¹
$Parsing XDC File [%s] for cell '%s'
848*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-848h px 
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-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2~
hd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip/mgt_ip_in_context.xdc2default:default2j
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip	2default:default8Z20-847h px 
‡
$Parsing XDC File [%s] for cell '%s'
848*designutils2
kd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc2default:default24
i_tcds2_if/i_mgt_wrapper/i_mgt	2default:default8Z20-848h px 

-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2
kd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/ttc_mgt/ttc_mgt_in_context.xdc2default:default24
i_tcds2_if/i_mgt_wrapper/i_mgt	2default:default8Z20-847h px 
ž
$Parsing XDC File [%s] for cell '%s'
848*designutils2¯
˜d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_in_context.xdc2default:default2
eth/phy	2default:default8Z20-848h px 
§
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2¯
˜d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_in_context.xdc2default:default2
eth/phy	2default:default8Z20-847h px 
¦
Parsing XDC File [%s]
179*designutils2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default8Z20-179h px 
¾
Deriving generated clocks
2*timing2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1292default:default8@Z38-2h px
„
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2 
get_clocks: 2default:default2
00:00:532default:default2
00:00:342default:default2
7974.6412default:default2
277.3132default:defaultZ17-268h px 
‹
No pins matched '%s'.
508*	planAhead2H
4stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1382default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1392default:default8@Z20-1567h px 
‹
No pins matched '%s'.
508*	planAhead2H
4stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1402default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1412default:default8@Z20-1567h px 
‹
No pins matched '%s'.
508*	planAhead2H
4stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1422default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1432default:default8@Z20-1567h px 
‹
No pins matched '%s'.
508*	planAhead2H
4stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1442default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1452default:default8@Z20-1567h px 

No pins matched '%s'.
508*	planAhead2L
8stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/ADDRARDADDR[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1462default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1472default:default8@Z20-1567h px 
Š
No pins matched '%s'.
508*	planAhead2G
3stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/CLKARDCLK2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1482default:default8@Z12-508h px
‹
No pins matched '%s'.
508*	planAhead2H
4stat_regs_inst/i_ram_*/*/*.mem_reg_bram_0/DINADIN[*]2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1482default:default8@Z12-508h px
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1492default:default8@Z20-1567h px 
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1512default:default8@Z20-1567h px 
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1532default:default8@Z20-1567h px 
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1552default:default8@Z20-1567h px 
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1572default:default8@Z20-1567h px 
Ø
eUse of '%s' with '%s' is not supported by synthesis. The constraint will not be passed to synthesis.
1199*designutils2'
set_multicycle_path2default:default2
-hold2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1592default:default8@Z20-1567h px 
¯
Finished Parsing XDC File [%s]
178*designutils2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default8Z20-178h px 
å
¬One or more constraints failed evaluation while reading constraint file [%s] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [%s] and check the run log file to verify that these constraints were correctly applied.301*project2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2/
.Xil/ngFEC_top_propImpl.xdc2default:defaultZ1-498h px 
’
ÙImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2/
.Xil/ngFEC_top_propImpl.xdc2default:defaultZ1-236h px 

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
write_xdc: 2default:default2
00:00:072default:default2
00:00:072default:default2
7974.6412default:default2
0.0002default:defaultZ17-268h px 
…
ÙImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2V
BD:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl2default:default2/
.Xil/ngFEC_top_propImpl.xdc2default:defaultZ1-236h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
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No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ö
No cells matched '%s'.
180*	planAhead2
ˆget_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}2default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z12-180h px 
Ø
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2!
Vivado 12-1802default:default2
1002default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z17-14h px 
×
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Common 17-552default:default2
1002default:default2[
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2
32default:default8@Z17-14h px 
ˆ
ÙImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2Y
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2/
.Xil/ngFEC_top_propImpl.xdc2default:defaultZ1-236h px 
ˆ
ÙImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2Y
ED:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl2default:default2/
.Xil/ngFEC_top_propImpl.xdc2default:defaultZ1-236h px 
l
2%s XPM XDC files have been applied to the design.
665*project2
32default:defaultZ1-1715h px 

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
write_xdc: 2default:default2
00:00:062default:default2
00:00:062default:default2
7974.6412default:default2
0.0002default:defaultZ17-268h px 
H
&Completed Processing XDC Constraints

245*projectZ1-263h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.5722default:default2
7995.0742default:default2
2.7892default:defaultZ17-268h px 
–
!Unisim Transformation Summary:
%s111*project2Ð
»  A total of 1030 instances were transformed.
  BUFG => BUFGCE: 8 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances
  IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances
  MMCME3_BASE => MMCME3_ADV: 1 instance 
2default:defaultZ1-111h px 

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
write_xdc: 2default:default2
00:00:082default:default2
00:00:082default:default2
8035.4572default:default2
0.0002default:defaultZ17-268h px 
—
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common24
 Constraint Validation Runtime : 2default:default2
00:00:092default:default2
00:00:092default:default2
8035.4572default:default2
40.3832default:defaultZ17-268h px 
à
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2
eth/phy2default:default2*
independent_clock_bufg2default:default2
8.0002default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
£
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2h
Tg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
¢
½Clock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2g
Sg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip2default:default2 
drpclk_in[0]2default:default2
8.3172default:defaultZ38-316h px 
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2default:defaulth p
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2default:defaulth p
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 Reading net delay rules and data4578*oasysZ8-6742h px 
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2default:defaulth px 
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2default:defaulth p
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’Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:09:37 ; elapsed = 00:08:46 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
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2default:defaulth p
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3inferred FSM for state register '%s' in module '%s'802*oasys2
	state_reg2default:default2!
transactor_if2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2
	state_reg2default:default2!
transactor_sm2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2
sm_init_reg2default:default2(
ttc_mgt_example_init2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
sm_reset_all_reg2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
sm_reset_tx_reg2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
sm_reset_rx_reg2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2'
prbs_lock_state_reg2default:default2
prbs_chk2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
stateBitSlip_reg2default:default2*
lpgbtfpga_framealigner2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2
sm_init_reg2default:default2'
mgt_ip_example_init2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2+
phase_aligner_state_reg2default:default2(
tx_phase_aligner_fsm2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys29
%gen_drp_interface.drp_tx_pi_state_reg2default:default2

tx_pi_ctrl2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2,
clkSlipProcess.state_reg2default:default2#
mgt_bitslipctrl2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2
	state_reg2default:default2/
mgt_framealigner_pattsearch2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2!
fe_status_reg2default:default2)
buffer_ngccm_jtag_com2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2
c_state_reg2default:default2'
i2c_master_bit_ctrl2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2,
statemachine.c_state_reg2default:default2(
i2c_master_byte_ctrl2default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-802h px 
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3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-802h px 
£
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-802h px 
¦
3inferred FSM for state register '%s' in module '%s'802*oasys2%
StateJTAGCtrl_reg2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-802h px 
¤
3inferred FSM for state register '%s' in module '%s'802*oasys2#
StateJTAGIO_reg2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-802h px 
¥
3inferred FSM for state register '%s' in module '%s'802*oasys2$
StateJTAGTDO_reg2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-802h px 
Ü
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2
Synth 8-8022default:default2
1002default:defaultZ17-14h px 
¢
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2.
"udp_DualPortRAM:/ram_reg"2default:defaultZ8-5779h px 
ç
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
82default:default2.
"udp_DualPortRAM:/ram_reg"2default:defaultZ8-7030h px 
¦
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default22
"udp_DualPortRAM_rx:/ram1_reg"2default:defaultZ8-5779h px 
Ì
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default22
"udp_DualPortRAM_rx:/ram1_reg"2default:defaultZ8-5555h px 
¦
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default22
"udp_DualPortRAM_rx:/ram2_reg"2default:defaultZ8-5779h px 
Ì
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default22
"udp_DualPortRAM_rx:/ram2_reg"2default:defaultZ8-5555h px 
¦
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default22
"udp_DualPortRAM_rx:/ram3_reg"2default:defaultZ8-5779h px 
Ì
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default22
"udp_DualPortRAM_rx:/ram3_reg"2default:defaultZ8-5555h px 
¦
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default22
"udp_DualPortRAM_rx:/ram4_reg"2default:defaultZ8-5779h px 
Ì
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default22
"udp_DualPortRAM_rx:/ram4_reg"2default:defaultZ8-5555h px 
¥
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
42default:default21
"udp_DualPortRAM_tx:/ram_reg"2default:defaultZ8-5779h px 
Ì
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
42default:default2
182default:default21
"udp_DualPortRAM_tx:/ram_reg"2default:defaultZ8-5555h px 
Ë
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
92default:default21
"udp_DualPortRAM_tx:/ram_reg"2default:defaultZ8-5555h px 
ê
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
42default:default21
"udp_DualPortRAM_tx:/ram_reg"2default:defaultZ8-7030h px 
ê
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
12default:default21
"udp_DualPortRAM_tx:/ram_reg"2default:defaultZ8-7030h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_idle |                          0000010 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_                st_first |                          1000000 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                  st_hdr |                          0100000 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_              st_prebody |                          0010000 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_body |                          0001000 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_done |                          0000100 |                              101
2default:defaulth p
x
 
‹
%s
*synth2s
_                  st_gap |                          0000001 |                              110
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
È
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
	state_reg2default:default2
one-hot2default:default2!
transactor_if2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_idle |                           100000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_                  st_hdr |                           001000 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_addr |                           010000 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_            st_bus_cycle |                           000010 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                st_rmw_1 |                           000100 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_                st_rmw_2 |                           000001 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
È
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
	state_reg2default:default2
one-hot2default:default2!
transactor_sm2default:defaultZ8-3354h px 
»
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2G
3"xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5779h px 

LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2G
3"xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ª
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2G
3"xpm_memory_base:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                ST_START |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_TX_WAIT |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_RX_WAIT |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_MONITOR |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ô
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
sm_init_reg2default:default2

sequential2default:default2(
ttc_mgt_example_init2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_      ST_RESET_TX_BRANCH |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_         ST_RESET_TX_PLL |                              001 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_    ST_RESET_TX_DATAPATH |                              010 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_   ST_RESET_TX_WAIT_LOCK |                              011 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_ST_RESET_TX_WAIT_USERRDY |                              100 |                              100
2default:defaulth p
x
 

%s
*synth2u
aST_RESET_TX_WAIT_RESETDONE |                              101 |                              101
2default:defaulth p
x
 
‹
%s
*synth2s
_        ST_RESET_TX_IDLE |                              110 |                              110
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
ß
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
sm_reset_tx_reg2default:default2

sequential2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_      ST_RESET_RX_BRANCH |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_         ST_RESET_RX_PLL |                              001 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_    ST_RESET_RX_DATAPATH |                              010 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_   ST_RESET_RX_WAIT_LOCK |                              011 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_    ST_RESET_RX_WAIT_CDR |                              100 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_ST_RESET_RX_WAIT_USERRDY |                              101 |                              101
2default:defaulth p
x
 

%s
*synth2u
aST_RESET_RX_WAIT_RESETDONE |                              110 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_        ST_RESET_RX_IDLE |                              111 |                              111
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
ß
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
sm_reset_rx_reg2default:default2

sequential2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_     ST_RESET_ALL_BRANCH |                              000 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_     ST_RESET_ALL_TX_PLL |                              001 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_ST_RESET_ALL_TX_PLL_WAIT |                              010 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_      ST_RESET_ALL_RX_DP |                              011 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_     ST_RESET_ALL_RX_PLL |                              100 |                              101
2default:defaulth p
x
 
‹
%s
*synth2s
_    ST_RESET_ALL_RX_WAIT |                              101 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                  iSTATE |                              110 |                              111
2default:defaulth p
x
 
‹
%s
*synth2s
_       ST_RESET_ALL_INIT |                              111 |                              000
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
à
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
sm_reset_all_reg2default:default2

sequential2default:default2/
ttc_mgt_example_gtwiz_reset2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    hunt |                               10 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_              going_lock |                               11 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                    lock |                               01 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_              going_hunt |                               00 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ð
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2'
prbs_lock_state_reg2default:default2

sequential2default:default2
prbs_chk2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                 e0_idle |                              001 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_            e4_dobitslip |                              010 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_          e5_waitncycles |                              100 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ø
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
stateBitSlip_reg2default:default2
one-hot2default:default2*
lpgbtfpga_framealigner2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                ST_START |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_TX_WAIT |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_RX_WAIT |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_              ST_MONITOR |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ó
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
sm_init_reg2default:default2

sequential2default:default2'
mgt_ip_example_init2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                             0110 |                             0000
2default:defaulth p
x
 
‹
%s
*synth2s
_       coarse_set_config |                             1010 |                             0001
2default:defaulth p
x
 
‹
%s
*synth2s
_         coarse_shift_pi |                             0010 |                             0010
2default:defaulth p
x
 
‹
%s
*synth2s
_          coarse_wait_pd |                             0000 |                             0011
2default:defaulth p
x
 
‹
%s
*synth2s
_         fine_set_config |                             0001 |                             0100
2default:defaulth p
x
 
‹
%s
*synth2s
_    fine_check_direction |                             0011 |                             0101
2default:defaulth p
x
 
‹
%s
*synth2s
_           fine_shift_pi |                             1101 |                             0110
2default:defaulth p
x
 
‹
%s
*synth2s
_            fine_wait_pd |                             1011 |                             0111
2default:defaulth p
x
 
‹
%s
*synth2s
_            fine_aligned |                             1100 |                             1000
2default:defaulth p
x
 
‹
%s
*synth2s
_           ui_set_offset |                             1110 |                             1001
2default:defaulth p
x
 
‹
%s
*synth2s
_       ui_check_shift_pi |                             1001 |                             1010
2default:defaulth p
x
 
‹
%s
*synth2s
_             ui_shift_pi |                             1000 |                             1011
2default:defaulth p
x
 
‹
%s
*synth2s
_             ui_reset_tx |                             0111 |                             1100
2default:defaulth p
x
 
‹
%s
*synth2s
_        aligned_clear_pd |                             0100 |                             1101
2default:defaulth p
x
 
‹
%s
*synth2s
_         aligned_wait_pd |                             0101 |                             1110
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
à
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2+
phase_aligner_state_reg2default:default2

sequential2default:default2(
tx_phase_aligner_fsm2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                             0100 |                             0000
2default:defaulth p
x
 
‹
%s
*synth2s
_              phase_accu |                             0101 |                             0001
2default:defaulth p
x
 
‹
%s
*synth2s
_ pre_register_0phase_drp |                             0011 |                             0010
2default:defaulth p
x
 

%s
*synth2w
cwait_pre_register_0phase_drp |                             0000 |                             0011
2default:defaulth p
x
 
‹
%s
*synth2s
_     register_1phase_drp |                             0001 |                             0100
2default:defaulth p
x
 
‹
%s
*synth2s
_wait_register_1phase_drp |                             0010 |                             0101
2default:defaulth p
x
 
‹
%s
*synth2s
_     register_0phase_drp |                             1000 |                             0110
2default:defaulth p
x
 
‹
%s
*synth2s
_wait_register_0phase_drp |                             0110 |                             0111
2default:defaulth p
x
 
‹
%s
*synth2s
_                done_drp |                             0111 |                             1000
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
ä
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys29
%gen_drp_interface.drp_tx_pi_state_reg2default:default2

sequential2default:default2

tx_pi_ctrl2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                 e0_idle |                              001 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_            e4_dobitslip |                              010 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_          e5_waitncycles |                              100 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2,
clkSlipProcess.state_reg2default:default2
one-hot2default:default2#
mgt_bitslipctrl2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                unlocked |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_              going_lock |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                  locked |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_            going_unlock |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
	state_reg2default:default2

sequential2default:default2/
mgt_framealigner_pattsearch2default:defaultZ8-3354h px 
Ë
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2W
C"xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5779h px 
‘
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2W
C"xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
‘
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2W
C"xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
º
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2W
C"xpm_memory_base__parameterized0:/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_s |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_                 write_s |                              001 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                  wait_s |                              010 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_                precmd_s |                              011 |                              101
2default:defaulth p
x
 
‹
%s
*synth2s
_                   cmd_s |                              100 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                  busy_s |                              101 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_              response_s |                              110 |                              010
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
×
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2!
fe_status_reg2default:default2

sequential2default:default2)
buffer_ngccm_jtag_com2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_b |                            00000 |                            00001
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_c |                            00001 |                            00010
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_d |                            00010 |                            00011
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_e |                            00011 |                            00100
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_f |                            00100 |                            00101
2default:defaulth p
x
 
‹
%s
*synth2s
_                 start_a |                            00101 |                            00110
2default:defaulth p
x
 
‹
%s
*synth2s
_                 start_b |                            00110 |                            00111
2default:defaulth p
x
 
‹
%s
*synth2s
_                 start_c |                            00111 |                            01000
2default:defaulth p
x
 
‹
%s
*synth2s
_                 start_d |                            01000 |                            01001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 start_e |                            01001 |                            01010
2default:defaulth p
x
 
‹
%s
*synth2s
_                  stop_a |                            01010 |                            01011
2default:defaulth p
x
 
‹
%s
*synth2s
_                  stop_b |                            01011 |                            01100
2default:defaulth p
x
 
‹
%s
*synth2s
_                  stop_c |                            01100 |                            01101
2default:defaulth p
x
 
‹
%s
*synth2s
_                  stop_d |                            01101 |                            01110
2default:defaulth p
x
 
‹
%s
*synth2s
_                  stop_e |                            01110 |                            01111
2default:defaulth p
x
 
‹
%s
*synth2s
_                    wr_a |                            01111 |                            10101
2default:defaulth p
x
 
‹
%s
*synth2s
_                    wr_b |                            10000 |                            10110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    wr_c |                            10001 |                            10111
2default:defaulth p
x
 
‹
%s
*synth2s
_                    wr_d |                            10010 |                            11000
2default:defaulth p
x
 
‹
%s
*synth2s
_                    wr_e |                            10011 |                            11001
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rd_a |                            10100 |                            10000
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rd_b |                            10101 |                            10001
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rd_c |                            10110 |                            10010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rd_d |                            10111 |                            10011
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rd_e |                            11000 |                            10100
2default:defaulth p
x
 
‹
%s
*synth2s
_                  idle_a |                            11001 |                            00000
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ó
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2
c_state_reg2default:default2

sequential2default:default2'
i2c_master_bit_ctrl2default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_                st_start |                              001 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_read |                              010 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                st_write |                              011 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                  st_ack |                              100 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_                 st_stop |                              101 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
á
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2,
statemachine.c_state_reg2default:default2

sequential2default:default2(
i2c_master_byte_ctrl2default:defaultZ8-3354h px 
™
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2%
"RAM:/memory_reg"2default:defaultZ8-5779h px 
ß
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2%
"RAM:/memory_reg"2default:defaultZ8-7030h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__12default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__22default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__32default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__42default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__52default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__62default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__72default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__82default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ù
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2)
JTAGMaster__xdcDup__92default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__102default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__112default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__122default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__132default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__142default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__152default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__162default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__172default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__182default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__192default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__202default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__212default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__222default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__232default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__242default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__252default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__262default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__272default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Û
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2$
StateJTAGTDO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ü
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2%
StateJTAGCtrl_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-3354h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Ú
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2#
StateJTAGIO_reg2default:default2

sequential2default:default2*
JTAGMaster__xdcDup__282default:defaultZ8-3354h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33542default:default2
1002default:defaultZ17-14h px 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 capture |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_                next_bit |                               10 |                               10
2default:defaulth p
x
 
‹
%s
*synth2s
_                wait_tck |                               11 |                               11
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_idle |                               00 |                               00
2default:defaulth p
x
 
‹
%s
*synth2s
_                 jtag_go |                               01 |                               01
2default:defaulth p
x
 
‹
%s
*synth2s
_               jtag_wait |                               10 |                               10
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
Œ
%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
‹
%s
*synth2s
_                    idle |                              000 |                              000
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_ld |                              001 |                              110
2default:defaulth p
x
 
‹
%s
*synth2s
_                    fall |                              010 |                              001
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prerise |                              011 |                              010
2default:defaulth p
x
 
‹
%s
*synth2s
_                    rise |                              100 |                              011
2default:defaulth p
x
 
‹
%s
*synth2s
_                 prefall |                              101 |                              100
2default:defaulth p
x
 
‹
%s
*synth2s
_            next_word_rd |                              110 |                              101
2default:defaulth p
x
 

%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
±
%s*synth2˜
ƒFinished RTL Optimization Phase 2 : Time (s): cpu = 00:12:07 ; elapsed = 00:11:22 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
¸
`Found 'rw_addr_collision' attribute set to 'no' on SDP RAM %s. Setting write mode to NO_CHANGE 
4174*oasys24
 gen_wr_a.gen_word_narrow.mem_reg2default:defaultZ8-5775h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-57752default:default2
1002default:defaultZ17-14h px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
L
%s
*synth24
 Start RTL Component Statistics 
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulth p
x
 
:
%s
*synth2"
+---Adders : 
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   32 Bit       Adders := 1365  
2default:defaulth p
x
 
X
%s
*synth2@
,	  21 Input   32 Bit       Adders := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   24 Bit       Adders := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   16 Bit       Adders := 149   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   15 Bit       Adders := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   13 Bit       Adders := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   12 Bit       Adders := 1461  
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   11 Bit       Adders := 1412  
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   10 Bit       Adders := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    9 Bit       Adders := 5     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    8 Bit       Adders := 733   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    7 Bit       Adders := 50    
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    7 Bit       Adders := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    6 Bit       Adders := 150   
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    6 Bit       Adders := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    5 Bit       Adders := 146   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    4 Bit       Adders := 835   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    3 Bit       Adders := 787   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    2 Bit       Adders := 2     
2default:defaulth p
x
 
8
%s
*synth2 
+---XORs : 
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input    256 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input    234 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input    206 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input     44 Bit         XORs := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	   3 Input     40 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input     40 Bit         XORs := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	   3 Input     39 Bit         XORs := 8     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input     20 Bit         XORs := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	   3 Input     19 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   5 Input     19 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input     16 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   4 Input     16 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   5 Input      9 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	  31 Input      5 Bit         XORs := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input      5 Bit         XORs := 230   
2default:defaulth p
x
 
Z
%s
*synth2B
.	   5 Input      4 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input      4 Bit         XORs := 144   
2default:defaulth p
x
 
Z
%s
*synth2B
.	   3 Input      2 Bit         XORs := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   5 Input      2 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   2 Input      1 Bit         XORs := 110073
2default:defaulth p
x
 
Z
%s
*synth2B
.	   5 Input      1 Bit         XORs := 22670 
2default:defaulth p
x
 
Z
%s
*synth2B
.	   3 Input      1 Bit         XORs := 19080 
2default:defaulth p
x
 
Z
%s
*synth2B
.	   6 Input      1 Bit         XORs := 4238  
2default:defaulth p
x
 
Z
%s
*synth2B
.	   4 Input      1 Bit         XORs := 11058 
2default:defaulth p
x
 
Z
%s
*synth2B
.	   7 Input      1 Bit         XORs := 1546  
2default:defaulth p
x
 
Z
%s
*synth2B
.	  10 Input      1 Bit         XORs := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	  12 Input      1 Bit         XORs := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   9 Input      1 Bit         XORs := 4     
2default:defaulth p
x
 
Z
%s
*synth2B
.	   8 Input      1 Bit         XORs := 2     
2default:defaulth p
x
 
=
%s
*synth2%
+---Registers : 
2default:defaulth p
x
 
Z
%s
*synth2B
.	              336 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              256 Bit    Registers := 3     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              234 Bit    Registers := 5     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              206 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              128 Bit    Registers := 8     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              120 Bit    Registers := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	              112 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	              100 Bit    Registers := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	               84 Bit    Registers := 288   
2default:defaulth p
x
 
Z
%s
*synth2B
.	               60 Bit    Registers := 3     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               58 Bit    Registers := 9     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               53 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               51 Bit    Registers := 3     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               49 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               48 Bit    Registers := 197   
2default:defaulth p
x
 
Z
%s
*synth2B
.	               45 Bit    Registers := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               42 Bit    Registers := 3     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               38 Bit    Registers := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               36 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               34 Bit    Registers := 1     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               32 Bit    Registers := 11578 
2default:defaulth p
x
 
Z
%s
*synth2B
.	               24 Bit    Registers := 99    
2default:defaulth p
x
 
Z
%s
*synth2B
.	               23 Bit    Registers := 2     
2default:defaulth p
x
 
Z
%s
*synth2B
.	               21 Bit    Registers := 576   
2default:defaulth p
x
 
Z
%s
*synth2B
.	               20 Bit    Registers := 145   
2default:defaulth p
x
 
Z
%s
*synth2B
.	               16 Bit    Registers := 235   
2default:defaulth p
x
 
Z
%s
*synth2B
.	               15 Bit    Registers := 48    
2default:defaulth p
x
 
Z
%s
*synth2B
.	               13 Bit    Registers := 24    
2default:defaulth p
x
 
Z
%s
*synth2B
.	               12 Bit    Registers := 3497  
2default:defaulth p
x
 
Z
%s
*synth2B
.	               11 Bit    Registers := 1413  
2default:defaulth p
x
 
Z
%s
*synth2B
.	               10 Bit    Registers := 3     
2default:defaulth p
x
 
Z
%s
*synth2B
.	                9 Bit    Registers := 14    
2default:defaulth p
x
 
Z
%s
*synth2B
.	                8 Bit    Registers := 4420  
2default:defaulth p
x
 
Z
%s
*synth2B
.	                7 Bit    Registers := 1271  
2default:defaulth p
x
 
Z
%s
*synth2B
.	                6 Bit    Registers := 157   
2default:defaulth p
x
 
Z
%s
*synth2B
.	                5 Bit    Registers := 246   
2default:defaulth p
x
 
Z
%s
*synth2B
.	                4 Bit    Registers := 4519  
2default:defaulth p
x
 
Z
%s
*synth2B
.	                3 Bit    Registers := 2157  
2default:defaulth p
x
 
Z
%s
*synth2B
.	                2 Bit    Registers := 748   
2default:defaulth p
x
 
Z
%s
*synth2B
.	                1 Bit    Registers := 33333 
2default:defaulth p
x
 
8
%s
*synth2 
+---RAMs : 
2default:defaulth p
x
 
k
%s
*synth2S
?	             256K Bit	(8192 X 32 bit)          RAMs := 1     
2default:defaulth p
x
 
k
%s
*synth2S
?	              64K Bit	(2048 X 32 bit)          RAMs := 681   
2default:defaulth p
x
 
j
%s
*synth2R
>	              64K Bit	(8192 X 8 bit)          RAMs := 4     
2default:defaulth p
x
 
k
%s
*synth2S
?	              32K Bit	(1024 X 32 bit)          RAMs := 48    
2default:defaulth p
x
 
j
%s
*synth2R
>	              32K Bit	(4096 X 8 bit)          RAMs := 1     
2default:defaulth p
x
 
j
%s
*synth2R
>	              16K Bit	(512 X 32 bit)          RAMs := 683   
2default:defaulth p
x
 
9
%s
*synth2!
+---Muxes : 
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  336 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  256 Bit        Muxes := 5     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  234 Bit        Muxes := 8     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  230 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  206 Bit        Muxes := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  145 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  128 Bit        Muxes := 10    
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input  128 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  112 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input  100 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   84 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   60 Bit        Muxes := 97    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   58 Bit        Muxes := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   52 Bit        Muxes := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   48 Bit        Muxes := 6     
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input   48 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   48 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   44 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   42 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   40 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   39 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   33 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   32 Bit        Muxes := 16560 
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input   32 Bit        Muxes := 3846  
2default:defaulth p
x
 
X
%s
*synth2@
,	   6 Input   32 Bit        Muxes := 634   
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input   32 Bit        Muxes := 98    
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   32 Bit        Muxes := 49    
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input   32 Bit        Muxes := 240   
2default:defaulth p
x
 
X
%s
*synth2@
,	  15 Input   32 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	  52 Input   32 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   31 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   24 Bit        Muxes := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   24 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   23 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   21 Bit        Muxes := 384   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   20 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   19 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   16 Bit        Muxes := 50    
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input   16 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   16 Bit        Muxes := 32    
2default:defaulth p
x
 
X
%s
*synth2@
,	  14 Input   16 Bit        Muxes := 3     
2default:defaulth p
x
 
X
%s
*synth2@
,	  11 Input   16 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input   16 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input   16 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	  18 Input   16 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   15 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   13 Bit        Muxes := 36    
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input   13 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input   13 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input   13 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input   13 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   12 Bit        Muxes := 3161  
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input   12 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   11 Bit        Muxes := 4086  
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input   11 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input   10 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input   10 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    9 Bit        Muxes := 16    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    8 Bit        Muxes := 14572 
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    8 Bit        Muxes := 635   
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input    8 Bit        Muxes := 9     
2default:defaulth p
x
 
X
%s
*synth2@
,	  13 Input    8 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    8 Bit        Muxes := 9     
2default:defaulth p
x
 
X
%s
*synth2@
,	  17 Input    8 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    8 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    7 Bit        Muxes := 50    
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    7 Bit        Muxes := 60    
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input    7 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    6 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    6 Bit        Muxes := 168   
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    6 Bit        Muxes := 98    
2default:defaulth p
x
 
X
%s
*synth2@
,	   6 Input    6 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    6 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input    6 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input    6 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    5 Bit        Muxes := 60    
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    5 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	  32 Input    5 Bit        Muxes := 585   
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    5 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    4 Bit        Muxes := 3270  
2default:defaulth p
x
 
X
%s
*synth2@
,	  16 Input    4 Bit        Muxes := 192   
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    4 Bit        Muxes := 49    
2default:defaulth p
x
 
X
%s
*synth2@
,	  15 Input    4 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	   9 Input    4 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    4 Bit        Muxes := 591   
2default:defaulth p
x
 
X
%s
*synth2@
,	   6 Input    4 Bit        Muxes := 585   
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input    4 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    4 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input    3 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    3 Bit        Muxes := 21678 
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input    3 Bit        Muxes := 4     
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    3 Bit        Muxes := 683   
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    3 Bit        Muxes := 633   
2default:defaulth p
x
 
X
%s
*synth2@
,	  12 Input    3 Bit        Muxes := 96    
2default:defaulth p
x
 
X
%s
*synth2@
,	  15 Input    3 Bit        Muxes := 585   
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    2 Bit        Muxes := 828   
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    2 Bit        Muxes := 3414  
2default:defaulth p
x
 
X
%s
*synth2@
,	   6 Input    2 Bit        Muxes := 1     
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    2 Bit        Muxes := 633   
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    2 Bit        Muxes := 48    
2default:defaulth p
x
 
X
%s
*synth2@
,	  17 Input    2 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	   2 Input    1 Bit        Muxes := 38139 
2default:defaulth p
x
 
X
%s
*synth2@
,	   4 Input    1 Bit        Muxes := 3671  
2default:defaulth p
x
 
X
%s
*synth2@
,	   7 Input    1 Bit        Muxes := 1221  
2default:defaulth p
x
 
X
%s
*synth2@
,	   8 Input    1 Bit        Muxes := 35    
2default:defaulth p
x
 
X
%s
*synth2@
,	   6 Input    1 Bit        Muxes := 3523  
2default:defaulth p
x
 
X
%s
*synth2@
,	   5 Input    1 Bit        Muxes := 3948  
2default:defaulth p
x
 
X
%s
*synth2@
,	   3 Input    1 Bit        Muxes := 8616  
2default:defaulth p
x
 
X
%s
*synth2@
,	  15 Input    1 Bit        Muxes := 144   
2default:defaulth p
x
 
X
%s
*synth2@
,	   9 Input    1 Bit        Muxes := 52    
2default:defaulth p
x
 
X
%s
*synth2@
,	  26 Input    1 Bit        Muxes := 4095  
2default:defaulth p
x
 
X
%s
*synth2@
,	  11 Input    1 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	  12 Input    1 Bit        Muxes := 2     
2default:defaulth p
x
 
X
%s
*synth2@
,	  13 Input    1 Bit        Muxes := 9     
2default:defaulth p
x
 
X
%s
*synth2@
,	  16 Input    1 Bit        Muxes := 9     
2default:defaulth p
x
 
X
%s
*synth2@
,	  17 Input    1 Bit        Muxes := 1     
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
O
%s
*synth27
#Finished RTL Component Statistics 
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
H
%s
*synth20
Start Part Resource Summary
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
ˆ
%s
*synth2p
\Part Resources:
DSPs: 5520 (col length:120)
BRAMs: 4320 (col length: RAMB18 240 RAMB36 120)
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
K
%s
*synth23
Finished Part Resource Summary
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
W
%s
*synth2?
+Start Cross Boundary and Area Optimization
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
²
+design %s has port %s driven by constant %s3447*oasys2%
gbt_bankx12__GCB02default:default2%
TX_PHALIGNED_o[0]2default:default2
12default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
gbt_bankx12__GCB02default:default2&
TX_PHCOMPUTED_o[0]2default:default2
12default:defaultZ8-3917h px 
Â
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized0__GCB02default:default2%
TX_PHALIGNED_o[0]2default:default2
12default:defaultZ8-3917h px 
Ã
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized0__GCB02default:default2&
TX_PHCOMPUTED_o[0]2default:default2
12default:defaultZ8-3917h px 
Â
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized1__GCB02default:default2%
TX_PHALIGNED_o[0]2default:default2
12default:defaultZ8-3917h px 
Ã
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized1__GCB02default:default2&
TX_PHCOMPUTED_o[0]2default:default2
12default:defaultZ8-3917h px 
Â
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized2__GCB02default:default2%
TX_PHALIGNED_o[0]2default:default2
12default:defaultZ8-3917h px 
Ã
+design %s has port %s driven by constant %s3447*oasys25
!gbt_bankx12__parameterized2__GCB02default:default2&
TX_PHCOMPUTED_o[0]2default:default2
12default:defaultZ8-3917h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[0].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[0].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[1].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[1].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[2].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[2].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[3].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[3].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[4].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[4].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[5].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[5].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[6].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[6].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[7].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[7].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[8].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[8].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ð
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2A
-g_clock_rate_din[9].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ò
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2C
/g_clock_rate_din[9].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[10].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[10].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[11].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[11].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[12].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[12].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[13].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[13].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[14].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[14].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[15].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[15].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[16].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[16].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[17].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[17].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[18].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[18].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[19].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[19].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[20].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[20].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[21].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[21].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[22].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[22].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[23].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[23].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[24].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[24].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[25].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[25].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[26].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[26].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[27].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[27].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[28].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[28].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[29].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[29].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[30].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[30].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[31].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[31].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[32].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[32].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[33].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[33].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[34].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[34].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[35].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[35].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[36].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[36].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[37].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[37].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[38].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[38].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[39].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[39].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[40].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[40].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[41].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[41].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[42].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[42].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[43].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[43].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[44].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[44].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[45].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[45].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[46].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[46].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ñ
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2B
.g_clock_rate_din[47].i_rate_test_comm/rate_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
ó
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys2D
0g_clock_rate_din[47].i_rate_test_comm/rate_i_reg2default:default2
242default:default2
162default:default2i
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/DSP_dividerX2.vhd2default:default2
632default:default8@Z8-3936h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10072default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10062default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10052default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10042default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10032default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10022default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10012default:defaultZ8-7129h px 
²
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default28
$xpm_cdc_single__parameterized2__10002default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9992default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9982default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9972default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9962default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9952default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9942default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9932default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9922default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9912default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9902default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9892default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9882default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9872default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9862default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9852default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9842default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9832default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9822default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9812default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9802default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9792default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9782default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9772default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9762default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9752default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9742default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9732default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9722default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9712default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9702default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9692default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9682default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9672default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9662default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9652default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9642default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9632default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9622default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9612default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9602default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9592default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9582default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9572default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9562default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9552default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9542default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9532default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9522default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9512default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9502default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9492default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9482default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9472default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9462default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9452default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9442default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9432default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9422default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9412default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9402default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9392default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9382default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9372default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9362default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9352default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9342default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9332default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9322default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9312default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9302default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9292default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9282default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9272default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9262default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9252default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9242default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9232default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9222default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9212default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9202default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9192default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9182default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9172default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9162default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9152default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9142default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9132default:defaultZ8-7129h px 
±
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default27
#xpm_cdc_single__parameterized2__9122default:defaultZ8-7129h px 
¢
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default2(
xpm_cdc_single__12972default:defaultZ8-7129h px 
¢
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default2(
xpm_cdc_single__12962default:defaultZ8-7129h px 
¢
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default2(
xpm_cdc_single__13002default:defaultZ8-7129h px 
¢
9Port %s in module %s is either unconnected or has no load4866*oasys2
src_clk2default:default2(
xpm_cdc_single__12992default:defaultZ8-7129h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-71292default:default2
1002default:defaultZ17-14h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-71292default:default2
1002default:defaultZ17-14h px 
ƒ
+Unused sequential element %s was removed. 
4326*oasys24
 gen_wr_b.gen_word_narrow.mem_reg2default:defaultZ8-6014h px 
ƒ
+Unused sequential element %s was removed. 
4326*oasys24
 gen_wr_b.gen_word_narrow.mem_reg2default:defaultZ8-6014h px 
Ù
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2e
Q"stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg"2default:defaultZ8-5779h px 
Ÿ
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2e
Q"stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
™
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2(
\stat_reg_reg[3][3] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[9].ngccm_status_reg_reg[9][9]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][10]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][11]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][11]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][12]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][12]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][13]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][13]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][14]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][14]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][15]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][15]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][25]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][25]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][26]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][26]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][27]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][27]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][28]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][28]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][29]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][29]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][30]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[9].ngccm_status_reg_reg[9][30]2default:default2
FDCE2default:default2:
&SFP_GEN[9].ngccm_status_reg_reg[9][31]2default:defaultZ8-3886h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[9].ngccm_status_reg_reg[9][31] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][25]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][26]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][27]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][28]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][29]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][30]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][31]2default:default2
FDCE2default:default29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[8].ngccm_status_reg_reg[8][9]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][10]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][11]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][11]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][12]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][12]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][13]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][13]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][14]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[8].ngccm_status_reg_reg[8][14]2default:default2
FDCE2default:default2:
&SFP_GEN[8].ngccm_status_reg_reg[8][15]2default:defaultZ8-3886h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[8].ngccm_status_reg_reg[8][15] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[1].ngccm_status_reg_reg[1][9]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][10]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][11]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][11]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][12]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][12]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][13]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][13]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][14]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][14]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][15]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][15]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][25]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][25]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][26]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][26]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][27]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][27]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][28]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][28]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][29]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][29]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][30]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[1].ngccm_status_reg_reg[1][30]2default:default2
FDCE2default:default2:
&SFP_GEN[1].ngccm_status_reg_reg[1][31]2default:defaultZ8-3886h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[1].ngccm_status_reg_reg[1][31] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][25]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][26]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][27]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][28]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][29]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][30]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][31]2default:default2
FDCE2default:default29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[0].ngccm_status_reg_reg[0][9]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][10]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][11]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][11]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][12]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][12]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][13]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][13]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][14]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[0].ngccm_status_reg_reg[0][14]2default:default2
FDCE2default:default2:
&SFP_GEN[0].ngccm_status_reg_reg[0][15]2default:defaultZ8-3886h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[0].ngccm_status_reg_reg[0][15] 2default:defaultZ8-3333h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2;
'SFP_GEN[11].ngccm_status_reg_reg[11][9]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][10]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][10]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][11]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][11]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][12]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][12]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][13]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][13]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][14]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][14]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][15]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][15]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][25]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][25]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][26]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][26]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][27]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][27]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][28]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][28]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][29]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][29]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][30]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[11].ngccm_status_reg_reg[11][30]2default:default2
FDCE2default:default2<
(SFP_GEN[11].ngccm_status_reg_reg[11][31]2default:defaultZ8-3886h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[11].ngccm_status_reg_reg[11][31] 2default:defaultZ8-3333h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][25]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][26]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][27]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][28]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][29]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][30]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][31]2default:default2
FDCE2default:default2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:defaultZ8-3886h px 
Ù
"merging instance '%s' (%s) to '%s'3436*oasys2;
'SFP_GEN[10].ngccm_status_reg_reg[10][9]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][10]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][10]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][11]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][11]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][12]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][12]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][13]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][13]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][14]2default:defaultZ8-3886h px 
Ú
"merging instance '%s' (%s) to '%s'3436*oasys2<
(SFP_GEN[10].ngccm_status_reg_reg[10][14]2default:default2
FDCE2default:default2<
(SFP_GEN[10].ngccm_status_reg_reg[10][15]2default:defaultZ8-3886h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[10].ngccm_status_reg_reg[10][15] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[3].ngccm_status_reg_reg[3][9]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][10]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][11]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][11]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][12]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][12]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][13]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][13]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][14]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][14]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][15]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][15]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][25]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][25]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][26]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][26]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][27]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][27]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][28]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][28]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][29]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][29]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][30]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[3].ngccm_status_reg_reg[3][30]2default:default2
FDCE2default:default2:
&SFP_GEN[3].ngccm_status_reg_reg[3][31]2default:defaultZ8-3886h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[3].ngccm_status_reg_reg[3][31] 2default:defaultZ8-3333h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][25]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][26]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][27]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][28]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][29]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][30]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][31]2default:default2
FDCE2default:default29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:defaultZ8-3886h px 
Õ
"merging instance '%s' (%s) to '%s'3436*oasys29
%SFP_GEN[2].ngccm_status_reg_reg[2][9]2default:default2
FDCE2default:default2:
&SFP_GEN[2].ngccm_status_reg_reg[2][10]2default:defaultZ8-3886h px 
Ö
"merging instance '%s' (%s) to '%s'3436*oasys2:
&SFP_GEN[2].ngccm_status_reg_reg[2][10]2default:default2
FDCE2default:default2:
&SFP_GEN[2].ngccm_status_reg_reg[2][11]2default:defaultZ8-3886h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-38862default:default2
1002default:defaultZ17-14h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-38862default:default2
1002default:defaultZ17-14h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[2].ngccm_status_reg_reg[2][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[25].ngccm_status_reg_reg[25][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[24].ngccm_status_reg_reg[24][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[17].ngccm_status_reg_reg[17][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[16].ngccm_status_reg_reg[16][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[13].ngccm_status_reg_reg[13][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[12].ngccm_status_reg_reg[12][15] 2default:defaultZ8-3333h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[5].ngccm_status_reg_reg[5][31] 2default:defaultZ8-3333h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[4].ngccm_status_reg_reg[4][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[27].ngccm_status_reg_reg[27][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[26].ngccm_status_reg_reg[26][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[19].ngccm_status_reg_reg[19][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[18].ngccm_status_reg_reg[18][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[41].ngccm_status_reg_reg[41][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[40].ngccm_status_reg_reg[40][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[33].ngccm_status_reg_reg[33][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[32].ngccm_status_reg_reg[32][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[15].ngccm_status_reg_reg[15][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[14].ngccm_status_reg_reg[14][15] 2default:defaultZ8-3333h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[7].ngccm_status_reg_reg[7][31] 2default:defaultZ8-3333h px 
­
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\SFP_GEN[6].ngccm_status_reg_reg[6][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[29].ngccm_status_reg_reg[29][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[28].ngccm_status_reg_reg[28][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[21].ngccm_status_reg_reg[21][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[20].ngccm_status_reg_reg[20][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[43].ngccm_status_reg_reg[43][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[42].ngccm_status_reg_reg[42][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[35].ngccm_status_reg_reg[35][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[34].ngccm_status_reg_reg[34][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[31].ngccm_status_reg_reg[31][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[30].ngccm_status_reg_reg[30][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[23].ngccm_status_reg_reg[23][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[22].ngccm_status_reg_reg[22][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[45].ngccm_status_reg_reg[45][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[44].ngccm_status_reg_reg[44][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[37].ngccm_status_reg_reg[37][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[36].ngccm_status_reg_reg[36][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[47].ngccm_status_reg_reg[47][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[46].ngccm_status_reg_reg[46][15] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[39].ngccm_status_reg_reg[39][31] 2default:defaultZ8-3333h px 
¯
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SFP_GEN[38].ngccm_status_reg_reg[38][15] 2default:defaultZ8-3333h px 
›
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2*
\stat_reg_reg[153][9] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][10] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][11] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][12] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][13] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][14] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][15] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][25] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][26] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][27] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][28] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][29] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][30] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[153][31] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][25] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][26] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][27] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][28] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][29] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][30] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][31] 2default:defaultZ8-3333h px 
›
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2*
\stat_reg_reg[152][9] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][10] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][11] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][12] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][13] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][14] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[152][15] 2default:defaultZ8-3333h px 
›
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2*
\stat_reg_reg[145][9] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][10] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][11] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][12] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][13] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][14] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][15] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][25] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][26] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][27] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][28] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][29] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][30] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[145][31] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][25] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][26] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][27] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][28] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][29] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][30] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][31] 2default:defaultZ8-3333h px 
›
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2*
\stat_reg_reg[144][9] 2default:defaultZ8-3333h px 
œ
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2+
\stat_reg_reg[144][10] 2default:defaultZ8-3333h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33332default:default2
1002default:defaultZ17-14h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33332default:default2
1002default:defaultZ17-14h px 
Ð
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2#
buf_to_load_int2default:default2
32default:default2
52default:defaultZ8-5544h px 
›
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2#
addr_to_set_int2default:defaultZ8-5587h px 
›
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2#
addr_to_set_int2default:defaultZ8-5587h px 
Ë
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2

event_data2default:default2
32default:default2
52default:defaultZ8-5544h px 
z
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

do_sum_int2default:defaultZ8-5546h px 
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
clr_sum_int2default:defaultZ8-5546h px 
}
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2!
int_valid_int2default:defaultZ8-5546h px 
y
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
	cksum_int2default:defaultZ8-5546h px 
z
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

do_sum_int2default:defaultZ8-5546h px 
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
clr_sum_int2default:defaultZ8-5546h px 
}
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2!
int_valid_int2default:defaultZ8-5546h px 
y
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
	cksum_int2default:defaultZ8-5546h px 
«
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default27
#"\ipb/udp_if/internal_ram/ram_reg "2default:defaultZ8-5779h px 
ð
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
82default:default27
#"\ipb/udp_if/internal_ram/ram_reg "2default:defaultZ8-7030h px 
¬
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram1_reg"2default:defaultZ8-5779h px 
Ò
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram1_reg"2default:defaultZ8-5555h px 
¬
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram2_reg"2default:defaultZ8-5779h px 
Ò
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram2_reg"2default:defaultZ8-5555h px 
¬
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram3_reg"2default:defaultZ8-5779h px 
Ò
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram3_reg"2default:defaultZ8-5555h px 
¬
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
22default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram4_reg"2default:defaultZ8-5779h px 
Ò
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default28
$"\ipb/udp_if /ipbus_rx_ram/ram4_reg"2default:defaultZ8-5555h px 
«
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
42default:default27
#"\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-5779h px 
Ò
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
42default:default2
182default:default27
#"\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-5555h px 
Ñ
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
92default:default27
#"\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-5555h px 
ð
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
42default:default27
#"\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-7030h px 
ð
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
12default:default27
#"\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-38862default:default2
1002default:defaultZ17-14h px 
ù
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26
"CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2
842default:default2
772default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
1022default:default8@Z8-3936h px 
ù
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26
"CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2
842default:default2
772default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
1022default:default8@Z8-3936h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[5].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[5].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
ù
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26
"CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2
842default:default2
772default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
1022default:default8@Z8-3936h px 
ù
RFound unconnected internal register '%s' and it is trimmed from '%s' to '%s' bits.3455*oasys26
"CrossClock_DV_cnt/DataAtoB_reg_reg2default:default2
842default:default2
772default:default2|
fD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ngFEC/ngCCM/i2c/util/CrossClock_RX.v2default:default2
1022default:default8@Z8-3936h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39362default:default2
1002default:defaultZ17-14h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[27].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[27].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2)
ipb_miso[13][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2)
ipb_miso[12][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2)
ipb_miso[11][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2)
ipb_miso[10][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[9][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[8][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[7][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[6][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[5][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[4][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[3][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[2][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[1][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2(
ipb_miso[0][ipb_err]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[31]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[30]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[29]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[28]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[27]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[26]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[25]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[24]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[23]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[21]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[19]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngccm_bkp_regs[10]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2%
ngccm_bkp_regs[9]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2%
ngccm_bkp_regs[8]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngCCM_status_o[14]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngCCM_status_o[13]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngCCM_status_o[12]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngCCM_status_o[11]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2&
ngCCM_status_o[10]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__152default:default2%
ngCCM_status_o[9]2default:default2
02default:defaultZ8-3917h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2)
ipb_miso[13][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2)
ipb_miso[12][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2)
ipb_miso[11][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2)
ipb_miso[10][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[9][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[8][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[7][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[6][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[5][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[4][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[3][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[2][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[1][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2(
ipb_miso[0][ipb_err]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[31]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[30]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[29]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[28]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[27]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[26]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[25]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[24]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[23]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[21]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[19]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngccm_bkp_regs[10]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2%
ngccm_bkp_regs[9]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2%
ngccm_bkp_regs[8]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngCCM_status_o[14]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngCCM_status_o[13]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngCCM_status_o[12]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngCCM_status_o[11]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2&
ngCCM_status_o[10]2default:default2
02default:defaultZ8-3917h px 
²
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__142default:default2%
ngCCM_status_o[9]2default:default2
02default:defaultZ8-3917h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2)
ipb_miso[13][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2)
ipb_miso[12][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2)
ipb_miso[11][ipb_err]2default:default2
02default:defaultZ8-3917h px 
¶
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2)
ipb_miso[10][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[9][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[8][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[7][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[6][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[5][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[4][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[3][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[2][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[1][ipb_err]2default:default2
02default:defaultZ8-3917h px 
µ
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2(
ipb_miso[0][ipb_err]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[31]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[30]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[29]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[28]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[27]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[26]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[25]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[24]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[23]2default:default2
02default:defaultZ8-3917h px 
³
+design %s has port %s driven by constant %s3447*oasys2%
ngCCM__xdcDup__292default:default2&
ngccm_bkp_regs[21]2default:default2
02default:defaultZ8-3917h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39172default:default2
1002default:defaultZ17-14h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[0].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[0].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39172default:default2
1002default:defaultZ17-14h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39172default:default2
1002default:defaultZ17-14h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39362default:default2
1002default:defaultZ17-14h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-71292default:default2
1002default:defaultZ17-14h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ã
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
‰
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2O
;"LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[24].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[24].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ú
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2f
R"\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
 
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2f
R"\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33332default:default2
1002default:defaultZ17-14h px 
Û
9Default cascade height of %s will be used for BRAM '%s'.
4180*oasys2
12default:default2g
S"\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-5779h px 
¡
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
322default:default2g
S"\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg"2default:defaultZ8-7030h px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
½
%s*synth2¤
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:19:01 ; elapsed = 00:18:29 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
»
%s*synth2¢
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
2default:defaulth px 
~
%s*synth2f
R---------------------------------------------------------------------------------
2default:defaulth px 
M
%s*synth25
!
ROM: Preliminary Mapping	Report
2default:defaulth px 
r
%s*synth2Z
F+------------------+---------------+---------------+----------------+
2default:defaulth px 
s
%s*synth2[
G|Module Name       | RTL Object    | Depth x Width | Implemented As | 
2default:defaulth px 
r
%s*synth2Z
F+------------------+---------------+---------------+----------------+
2default:defaulth px 
s
%s*synth2[
G|rs_decoder_N31K29 | tmp           | 32x5          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|rs_decoder_N31K29 | tmp           | 32x5          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
s
%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G|JTAGMaster        | stateTrans[0] | 32x4          | LUT            | 
2default:defaulth px 
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%s*synth2[
G+------------------+---------------+---------------+----------------+

2default:defaulth px 
d
%s*synth2L
8
Block RAM: Preliminary Mapping	Report (see note below)
2default:defaulth px 
¢
%s*synth2‰
ô+---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
2default:defaulth px 
£
%s*synth2Š
õ|Module Name                                                                      | RTL Object                           | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | 
2default:defaulth px 
¢
%s*synth2‰
ô+---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst    | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|LocalJTAGBridge_inst                                                             | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst  | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[0].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[1].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[2].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[3].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[4].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[5].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[6].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[7].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base__parameterized0:                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth px 
£
%s*synth2Š
õ|\I2C_array[8].RAM /BRAM_h/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth px 
£
%s*synth2Š
õ|xpm_memory_base:                                                                 | gen_wr_b.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W | R | 512 x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|stat_regs_inst/i_ram_rate/xpm_memory_base_inst                                   | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W | R | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if                                                                      | internal_ram/ram_reg                 | 4 K x 8(READ_FIRST)    | W |   | 4 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if /ipbus_rx_ram                                                        | ram1_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if /ipbus_rx_ram                                                        | ram2_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if /ipbus_rx_ram                                                        | ram3_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if /ipbus_rx_ram                                                        | ram4_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth px 
£
%s*synth2Š
õ|\ipb/udp_if /ipbus_tx_ram                                                        | ram_reg                              | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 7      | 4,2,1,1         | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[5].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[27].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[0].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[24].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ|\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst                                     | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth px 
£
%s*synth2Š
õ+---------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+

2default:defaulth px 
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%s*synth2¡
ŒNote: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 
2default:defaulth px 
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%s*synth2¥
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
2default:defaulth px 
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%s*synth2f
R---------------------------------------------------------------------------------
2default:defaulth px 
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%s
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2default:defaulth p
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&Start Applying XDC Timing Constraints
2default:defaulth p
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R---------------------------------------------------------------------------------
2default:defaulth p
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$%s for constraint at line %s of %s.
3321*oasys29
%set_multicycle_path : Empty from list2default:default2
1542default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1542default:default8@Z8-3321h px 
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$%s for constraint at line %s of %s.
3321*oasys27
#set_multicycle_path : Empty to list2default:default2
1542default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1542default:default8@Z8-3321h px 
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$%s for constraint at line %s of %s.
3321*oasys29
%set_multicycle_path : Empty from list2default:default2
1562default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1562default:default8@Z8-3321h px 
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$%s for constraint at line %s of %s.
3321*oasys27
#set_multicycle_path : Empty to list2default:default2
1562default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1562default:default8@Z8-3321h px 
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$%s for constraint at line %s of %s.
3321*oasys29
%set_multicycle_path : Empty from list2default:default2
1582default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1582default:default8@Z8-3321h px 
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$%s for constraint at line %s of %s.
3321*oasys27
#set_multicycle_path : Empty to list2default:default2
1582default:default2c
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2e
OD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc2default:default2
1582default:default8@Z8-3321h px 
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R---------------------------------------------------------------------------------
2default:defaulth p
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%s*synth2Ÿ
ŠFinished Applying XDC Timing Constraints : Time (s): cpu = 00:20:17 ; elapsed = 00:19:49 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
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*synth2.
Start Timing Optimization
2default:defaulth p
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*synth2f
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2default:defaulth p
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VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ø
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ù
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
142default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
Ú
LImplemented Non-Cascaded %s Ram (cascade_height = %s) of width %s for RAM %s4766*oasys2
Block2default:default2
12default:default2
182default:default2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-7030h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-70302default:default2
1002default:defaultZ17-14h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
˜
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 

?The signal %s was recognized as a true dual port RAM template.
3473*oasys2
ˆ"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
™
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
‚
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2ž
‰"\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
ƒ
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2Ÿ
Š"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
›
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
„
?The signal %s was recognized as a true dual port RAM template.
3473*oasys2 
‹"\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-3971h px 
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Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-39712default:default2
1002default:defaultZ17-14h px 
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VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
š
VThe block RAM %s may be mapped as a cascade chain, because it is not timing critical.
4009*oasys2Ÿ
Š"\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg"2default:defaultZ8-5556h px 
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Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-55562default:default2
1002default:defaultZ17-14h px 
Ö
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default2<
("i_1/\ipb/udp_if /ipbus_rx_ram/ram1_reg"2default:defaultZ8-5555h px 
Ö
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default2<
("i_1/\ipb/udp_if /ipbus_rx_ram/ram2_reg"2default:defaultZ8-5555h px 
Ö
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default2<
("i_1/\ipb/udp_if /ipbus_rx_ram/ram3_reg"2default:defaultZ8-5555h px 
Ö
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
82default:default2<
("i_1/\ipb/udp_if /ipbus_rx_ram/ram4_reg"2default:defaultZ8-5555h px 
Ö
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
42default:default2
182default:default2;
'"i_1/\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-5555h px 
Õ
HImplemented Block Ram Cascade chain of height %s and width %s for RAM %s4008*oasys2
22default:default2
92default:default2;
'"i_1/\ipb/udp_if /ipbus_tx_ram/ram_reg"2default:defaultZ8-5555h px 
~
%s
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R---------------------------------------------------------------------------------
2default:defaulth p
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~Finished Timing Optimization : Time (s): cpu = 00:25:53 ; elapsed = 00:25:26 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
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2default:defaulth p
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
2default:defaulth p
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2default:defaulth p
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Block RAM: Final Mapping	Report
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+----------------------------------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
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Ž|Module Name                                                                                               | RTL Object                           | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\SFP_GEN[0].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[0].ngFEC_modulei_56 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\SFP_GEN[1].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[1].ngFEC_modulei_57 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\SFP_GEN[2].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[2].ngFEC_modulei_58 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[3].ngFEC_modulei_59 /\SFP_GEN[3].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[3].ngFEC_modulei_59 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\SFP_GEN[4].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[4].ngFEC_modulei_60 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[5].ngFEC_modulei_61 /\SFP_GEN[5].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[5].ngFEC_modulei_61 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\SFP_GEN[6].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[6].ngFEC_modulei_62 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[7].ngFEC_modulei_63 /\SFP_GEN[7].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[7].ngFEC_modulei_63 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\SFP_GEN[8].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[8].ngFEC_modulei_64 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                             | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\SFP_GEN[9].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst    | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[9].ngFEC_modulei_65 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\SFP_GEN[10].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[10].ngFEC_modulei_66 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\SFP_GEN[11].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[11].ngFEC_modulei_67 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\SFP_GEN[12].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[12].ngFEC_modulei_68 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\SFP_GEN[13].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[13].ngFEC_modulei_69 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\SFP_GEN[14].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[14].ngFEC_modulei_70 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\SFP_GEN[15].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[15].ngFEC_modulei_71 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[16].ngFEC_modulei_72 /\SFP_GEN[16].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[16].ngFEC_modulei_72 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\SFP_GEN[17].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[17].ngFEC_modulei_73 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\SFP_GEN[18].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[18].ngFEC_modulei_74 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\SFP_GEN[19].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[19].ngFEC_modulei_75 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\SFP_GEN[20].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[20].ngFEC_modulei_76 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\SFP_GEN[21].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[21].ngFEC_modulei_77 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\SFP_GEN[22].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[22].ngFEC_modulei_78 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\SFP_GEN[23].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[23].ngFEC_modulei_79 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[24].ngFEC_modulei_80 /\SFP_GEN[24].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[24].ngFEC_modulei_80 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\SFP_GEN[25].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[25].ngFEC_modulei_81 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\SFP_GEN[26].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[26].ngFEC_modulei_82 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[27].ngFEC_modulei_83 /\SFP_GEN[27].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[27].ngFEC_modulei_83 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[28].ngFEC_modulei_84 /\SFP_GEN[28].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[28].ngFEC_modulei_84 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\SFP_GEN[29].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[29].ngFEC_modulei_85 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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%s
*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\SFP_GEN[30].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[30].ngFEC_modulei_86 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\SFP_GEN[31].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[31].ngFEC_modulei_87 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\SFP_GEN[32].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[32].ngFEC_modulei_88 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\SFP_GEN[33].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[33].ngFEC_modulei_89 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\SFP_GEN[34].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[34].ngFEC_modulei_90 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[35].ngFEC_modulei_91 /\SFP_GEN[35].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[35].ngFEC_modulei_91 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\SFP_GEN[36].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[36].ngFEC_modulei_92 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\SFP_GEN[37].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[37].ngFEC_modulei_93 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\SFP_GEN[38].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[38].ngFEC_modulei_94 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[39].ngFEC_modulei_95 /\SFP_GEN[39].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[39].ngFEC_modulei_95 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\SFP_GEN[40].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[40].ngFEC_modulei_96 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\SFP_GEN[41].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[41].ngFEC_modulei_97 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\SFP_GEN[42].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[42].ngFEC_modulei_98 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst   | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[43].ngFEC_modulei_99 /\SFP_GEN[43].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[43].ngFEC_modulei_99 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|LocalJTAGBridge_inst                                                                                      | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\SFP_GEN[44].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[44].ngFEC_modulei_100 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
 
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%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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%s
*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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¼
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\SFP_GEN[45].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[45].ngFEC_modulei_101 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[46].ngFEC_modulei_102 /\SFP_GEN[46].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[46].ngFEC_modulei_102 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[0].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[0].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[1].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[1].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[2].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[2].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[3].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[3].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[4].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[4].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[5].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[5].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[6].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[6].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[7].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[7].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[8].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[8].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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*synth2£
Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[9].RAM /BRAM_l/xpm_memory_base_inst  | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[9].RAM /BRAM_h/xpm_memory_base_inst                           | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[10].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[10].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[11].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[11].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[12].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[12].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\SFP_GEN[47].ngFEC_module/bram_array[13].RAM /BRAM_l/xpm_memory_base_inst | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\SFP_GEN[47].ngFEC_modulei_103 /\bram_array[13].RAM /BRAM_h/xpm_memory_base_inst                          | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[0].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[0].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[1].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[1].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[2].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[2].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[3].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[3].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[4].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[4].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[5].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
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Ž|\I2C_array[5].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
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%s
*synth2£
Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[6].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\I2C_array[6].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[7].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\I2C_array[7].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_I2C_ifi_104/\i_I2C_if/I2C_array[8].RAM /BRAM_l/xpm_memory_base_inst                                     | gen_wr_b.gen_word_narrow.mem_reg     | 2 K x 32(NO_CHANGE)    | W | R | 2 K x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 2      | 1,1             | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\I2C_array[8].RAM /BRAM_h/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W |   | 512 x 32(NO_CHANGE)    |   | R | Port A and B     | 1      | 0      |                 | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|xpm_memory_base:                                                                                          | gen_wr_b.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W | R | 512 x 32(NO_CHANGE)    | W | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|stat_regs_inst/i_ram_rate/xpm_memory_base_inst                                                            | gen_wr_a.gen_word_narrow.mem_reg     | 512 x 32(NO_CHANGE)    | W | R | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\ipb/udp_if                                                                                               | internal_ram/ram_reg                 | 4 K x 8(READ_FIRST)    | W |   | 4 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_1/\ipb/udp_if /ipbus_rx_ram                                                                             | ram1_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_1/\ipb/udp_if /ipbus_rx_ram                                                                             | ram2_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_1/\ipb/udp_if /ipbus_rx_ram                                                                             | ram3_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_1/\ipb/udp_if /ipbus_rx_ram                                                                             | ram4_reg                             | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 2               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|i_1/\ipb/udp_if /ipbus_tx_ram                                                                             | ram_reg                              | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 7      | 4,2,1,1         | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[47].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[45].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[40].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[5].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[9].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[41].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[7].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[33].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[38].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[37].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[27].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[23].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[17].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[10].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[34].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[31].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[0].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[26].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[6].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[29].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[4].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[1].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[32].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[36].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[11].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[8].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[20].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[18].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[39].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[21].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[3].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[24].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[22].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[12].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
 
¼
%s
*synth2£
Ž|\SFP_GEN[2].ngCCM_gbt /LocalJTAGBridge_inst                                                               | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[44].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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¼
%s
*synth2£
Ž|\SFP_GEN[46].ngCCM_gbt /LocalJTAGBridge_inst                                                              | JTAGMaster_inst/JTAG_BRAM/memory_reg | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 1               | 
2default:defaulth p
x
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*synth2£
Ž+----------------------------------------------------------------------------------------------------------+--------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+

2default:defaulth p
x
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¾
%s
*synth2¥
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
E
%s
*synth2-
Start Technology Mapping
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[6].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[0].ngFEC_modulei_56/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[0].ngFEC_modulei_56/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[10].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
“
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2
kSFP_GEN[0].ngFEC_modulei_56/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
“
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2
kSFP_GEN[0].ngFEC_modulei_56/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
“
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2
kSFP_GEN[0].ngFEC_modulei_56/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
›
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2†
rSFP_GEN[0].ngFEC_modulei_56/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
“
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2
kSFP_GEN[0].ngFEC_modulei_56/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_02default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
š
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2…
qSFP_GEN[1].ngFEC_modulei_57/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_12default:default2
Block2default:defaultZ8-7052h px 
’
ÔThe timing for the instance %s (implemented as a %s RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
4799*oasys2~
jSFP_GEN[1].ngFEC_modulei_57/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg2default:default2
Block2default:defaultZ8-7052h px 
Ý
Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-70522default:default2
1002default:defaultZ17-14h px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
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%s*synth2‘
}Finished Technology Mapping : Time (s): cpu = 00:31:34 ; elapsed = 00:31:30 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
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%s
*synth2'
Start IO Insertion
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
Q
%s
*synth29
%Start Flattening Before IO Insertion
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
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T
%s
*synth2<
(Finished Flattening Before IO Insertion
2default:defaulth p
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
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H
%s
*synth20
Start Final Netlist Cleanup
2default:defaulth p
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
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K
%s
*synth23
Finished Final Netlist Cleanup
2default:defaulth p
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
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ˆ
'tying undriven pin %s:%s to constant 0
3295*oasys2£
Žg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_meta_inferred2default:default2
in02default:defaultZ8-3295h px 
…
'tying undriven pin %s:%s to constant 0
3295*oasys2 
‹g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r_inferred2default:default2
in02default:defaultZ8-3295h px 
†
'tying undriven pin %s:%s to constant 0
3295*oasys2¡
Œg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/strobe_toggle_txusr_r2_inferred2default:default2
in02default:defaultZ8-3295h px 
„
'tying undriven pin %s:%s to constant 0
3295*oasys2Ÿ
Šg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_meta_inferred2default:default2
in02default:defaultZ8-3295h px 

'tying undriven pin %s:%s to constant 0
3295*oasys2œ
‡g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/done_toggle_sys_r_inferred2default:default2
in02default:defaultZ8-3295h px 
‚
'tying undriven pin %s:%s to constant 0
3295*oasys2
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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'tying undriven pin %s:%s to constant 0
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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in02default:defaultZ8-3295h px 
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ú|ngFEC_top   | stat_regs_inst/clk_phase_reg[6]                                                                                                             | 3      | 1     | NO           | NO                 | YES               | 1      | 0       | 
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ú|ngFEC_top   | stat_regs_inst/clk_phase_reg[3]                                                                                                             | 4      | 1     | NO           | NO                 | YES               | 1      | 0       | 
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ú|ngFEC_top   | fabric_clk_div2_q_reg[3]                                                                                                                    | 4      | 1     | NO           | NO                 | YES               | 1      | 0       | 
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ú|ngFEC_top   | ipb/udp_if/IPADDR/IP_addr_rx_block.pkt_mask_reg[41]                                                                                         | 22     | 1     | YES          | NO                 | YES               | 0      | 1       | 
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ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[27]                                                                                         | 6      | 2     | YES          | NO                 | YES               | 2      | 0       | 
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ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[17]                                                                                         | 4      | 2     | YES          | NO                 | YES               | 2      | 0       | 
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*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ping.pkt_mask_reg[35]                                                                                           | 23     | 1     | YES          | NO                 | YES               | 0      | 1       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37]                                                                                      | 23     | 1     | YES          | NO                 | YES               | 0      | 1       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44]                                                                                     | 37     | 1     | YES          | NO                 | YES               | 0      | 2       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_mask_reg[41]                                                                                            | 12     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]                                                                                           | 12     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[15]                                                                                           | 10     | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44]                                                                                      | 31     | 1     | YES          | NO                 | YES               | 0      | 1       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[11]                                                                                      | 10     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_mask_reg[11]                                                                                            | 6      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/IPADDR/IP_addr_rx_block.pkt_mask_reg[19]                                                                                         | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[295]                                                                                       | 5      | 7     | YES          | NO                 | YES               | 7      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[246]                                                                                       | 13     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[243]                                                                                       | 4      | 6     | YES          | NO                 | YES               | 6      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[241]                                                                                       | 6      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[239]                                                                                       | 14     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[229]                                                                                       | 9      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[228]                                                                                       | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/data_block.data_buffer_reg[118]                                                                                       | 7      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/rarp_data_reg[7]                                                                                                      | 6      | 5     | YES          | NO                 | YES               | 5      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/rarp_data_reg[4]                                                                                                      | 7      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/rarp_data_reg[3]                                                                                                      | 11     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/RARP_block/rarp_data_reg[1]                                                                                                      | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_mask_reg[29]                                                                                            | 10     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[127]                                                                                        | 5      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[79]                                                                                         | 6      | 4     | YES          | NO                 | YES               | 4      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[111]                                                                                           | 10     | 4     | YES          | NO                 | YES               | 4      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[90]                                                                                            | 4      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[72]                                                                                            | 5      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[126]                                                                                          | 13     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[123]                                                                                          | 4      | 2     | YES          | NO                 | YES               | 2      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[121]                                                                                          | 6      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[119]                                                                                          | 14     | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[109]                                                                                          | 9      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[108]                                                                                          | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[88]                                                                                           | 7      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú|ngFEC_top   | ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[83]                                                                                           | 5      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulth p
x
 
¨
%s
*synth2
ú+------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+

2default:defaulth p
x
 
¾
%s
*synth2¥
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
K
%s
*synth23
Start Writing Synthesis Report
2default:defaulth p
x
 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
A
%s
*synth2)

Report BlackBoxes: 
2default:defaulth p
x
 
X
%s
*synth2@
,+------+-----------------------+----------+
2default:defaulth p
x
 
X
%s
*synth2@
,|      |BlackBox name          |Instances |
2default:defaulth p
x
 
X
%s
*synth2@
,+------+-----------------------+----------+
2default:defaulth p
x
 
X
%s
*synth2@
,|1     |gig_ethernet_pcs_pma_0 |         1|
2default:defaulth p
x
 
X
%s
*synth2@
,|2     |mgt_ip                 |        48|
2default:defaulth p
x
 
X
%s
*synth2@
,|3     |ttc_mgt                |         1|
2default:defaulth p
x
 
X
%s
*synth2@
,+------+-----------------------+----------+
2default:defaulth p
x
 
A
%s*synth2)

Report Cell Usage: 
2default:defaulth px 
Z
%s*synth2B
.+------+----------------------------+-------+
2default:defaulth px 
Z
%s*synth2B
.|      |Cell                        |Count  |
2default:defaulth px 
Z
%s*synth2B
.+------+----------------------------+-------+
2default:defaulth px 
Z
%s*synth2B
.|1     |gig_ethernet_pcs_pma_0_bbox |      1|
2default:defaulth px 
Z
%s*synth2B
.|2     |mgt_ip_bbox                 |      1|
2default:defaulth px 
Z
%s*synth2B
.|3     |mgt_ip_bbox_2_              |     47|
2default:defaulth px 
Z
%s*synth2B
.|50    |ttc_mgt_bbox                |      1|
2default:defaulth px 
Z
%s*synth2B
.|51    |BUFG                        |      8|
2default:defaulth px 
Z
%s*synth2B
.|52    |BUFGCE_DIV                  |      1|
2default:defaulth px 
Z
%s*synth2B
.|53    |BUFG_GT                     |      3|
2default:defaulth px 
Z
%s*synth2B
.|54    |CARRY8                      |   8602|
2default:defaulth px 
Z
%s*synth2B
.|55    |DSP_ALU                     |   1003|
2default:defaulth px 
Z
%s*synth2B
.|60    |DSP_A_B_DATA                |   1003|
2default:defaulth px 
Z
%s*synth2B
.|62    |DSP_C_DATA                  |   1003|
2default:defaulth px 
Z
%s*synth2B
.|64    |DSP_MULTIPLIER              |   1003|
2default:defaulth px 
Z
%s*synth2B
.|66    |DSP_M_DATA                  |   1003|
2default:defaulth px 
Z
%s*synth2B
.|68    |DSP_OUTPUT                  |   1003|
2default:defaulth px 
Z
%s*synth2B
.|71    |DSP_PREADD                  |   1003|
2default:defaulth px 
Z
%s*synth2B
.|72    |DSP_PREADD_DATA             |   1003|
2default:defaulth px 
Z
%s*synth2B
.|76    |IBUFDS_GTE3                 |      6|
2default:defaulth px 
Z
%s*synth2B
.|77    |LUT1                        |  29020|
2default:defaulth px 
Z
%s*synth2B
.|78    |LUT2                        |  58134|
2default:defaulth px 
Z
%s*synth2B
.|79    |LUT3                        | 111694|
2default:defaulth px 
Z
%s*synth2B
.|80    |LUT4                        | 104041|
2default:defaulth px 
Z
%s*synth2B
.|81    |LUT5                        |  92248|
2default:defaulth px 
Z
%s*synth2B
.|82    |LUT6                        | 149400|
2default:defaulth px 
Z
%s*synth2B
.|83    |MMCME3_ADV                  |      1|
2default:defaulth px 
Z
%s*synth2B
.|84    |MMCME3_BASE                 |      1|
2default:defaulth px 
Z
%s*synth2B
.|85    |MUXF7                       |   1063|
2default:defaulth px 
Z
%s*synth2B
.|86    |MUXF8                       |      3|
2default:defaulth px 
Z
%s*synth2B
.|87    |RAMB18E2                    |    682|
2default:defaulth px 
Z
%s*synth2B
.|89    |RAMB36E2                    |   1428|
2default:defaulth px 
Z
%s*synth2B
.|100   |SRL16E                      |    125|
2default:defaulth px 
Z
%s*synth2B
.|102   |SRLC32E                     |      6|
2default:defaulth px 
Z
%s*synth2B
.|103   |FDCE                        | 188851|
2default:defaulth px 
Z
%s*synth2B
.|104   |FDPE                        |  17656|
2default:defaulth px 
Z
%s*synth2B
.|105   |FDRE                        | 167146|
2default:defaulth px 
Z
%s*synth2B
.|106   |FDSE                        |   4953|
2default:defaulth px 
Z
%s*synth2B
.|107   |IBUF                        |     17|
2default:defaulth px 
Z
%s*synth2B
.|108   |IOBUF                       |     18|
2default:defaulth px 
Z
%s*synth2B
.|109   |OBUF                        |     10|
2default:defaulth px 
Z
%s*synth2B
.|110   |OBUFDS_GTE3                 |      1|
2default:defaulth px 
Z
%s*synth2B
.+------+----------------------------+-------+
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
±
%s*synth2˜
ƒFinished Writing Synthesis Report : Time (s): cpu = 00:56:03 ; elapsed = 00:56:31 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth px 
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulth p
x
 
t
%s
*synth2\
HSynthesis finished with 0 errors, 0 critical warnings and 818 warnings.
2default:defaulth p
x
 
¬
%s
*synth2“
Synthesis Optimization Runtime : Time (s): cpu = 00:47:32 ; elapsed = 00:49:29 . Memory (MB): peak = 8035.457 ; gain = 807.938
2default:defaulth p
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 
¯
%s
*synth2–
Synthesis Optimization Complete : Time (s): cpu = 00:56:03 ; elapsed = 00:56:33 . Memory (MB): peak = 8035.457 ; gain = 6826.992
2default:defaulth p
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 
B
 Translating synthesized netlist
350*projectZ1-571h px 

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:282default:default2
00:00:282default:default2
8035.4572default:default2
0.0002default:defaultZ17-268h px 
i
-Analyzing %s Unisim elements for replacement
17*netlist2
107162default:defaultZ29-17h px 
k
2Unisim Transformation completed in %s CPU seconds
28*netlist2
202default:defaultZ29-28h px 
K
)Preparing netlist for logic optimization
349*projectZ1-570h px 
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138h px 
Ž
'Inserted BUFG_GT_SYNC %s for BUFG_GT %s303*opt2 
BUFG_GT_SYNC2default:default2$
i_refclk125_bufg2default:defaultZ31-441h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:012default:default2 
00:00:00.4252default:default2
8884.7152default:default2
0.0002default:defaultZ17-268h px 
Å
!Unisim Transformation Summary:
%s111*project2ÿ
ê  A total of 1047 instances were transformed.
  BUFG => BUFGCE: 8 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances
  IBUF => IBUF (IBUFCTRL, INBUF): 17 instances
  IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances
  MMCME3_BASE => MMCME3_ADV: 1 instance 
2default:defaultZ1-111h px 
U
Releasing license: %s
83*common2
	Synthesis2default:defaultZ17-83h px 
Ê
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
16012default:default2
6052default:default2
02default:default2
02default:defaultZ4-41h px 
^
%s completed successfully
29*	vivadotcl2 
synth_design2default:defaultZ4-42h px 
‡
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
synth_design: 2default:default2
01:02:222default:default2
01:02:462default:default2
8884.7152default:default2
7856.4732default:defaultZ17-268h px 
Æ
 The %s '%s' has been generated.
621*common2

checkpoint2default:default2a
MD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/synth_1/ngFEC_top.dcp2default:defaultZ17-1381h px 
ˆ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2&
write_checkpoint: 2default:default2
00:03:182default:default2
00:02:322default:default2
8884.7152default:default2
0.0002default:defaultZ17-268h px 
˜
%s4*runtcl2|
hExecuting : report_utilization -file ngFEC_top_utilization_synth.rpt -pb ngFEC_top_utilization_synth.pb
2default:defaulth px 
Š
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2(
report_utilization: 2default:default2
00:00:062default:default2
00:00:062default:default2
8884.7152default:default2
0.0002default:defaultZ17-268h px 
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Exiting %s at %s...
206*common2
Vivado2default:default2,
Fri Mar 12 22:34:24 20212default:defaultZ17-206h px 


End Record