*** Running vivado with args -log ngFEC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ngFEC_top.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ngFEC_top.tcl -notrace Command: link_design -top ngFEC_top -part xcku115-flva2104-1-c Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xcku115-flva2104-1-c INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0.dcp' for cell 'eth/phy' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/mgt_ip.dcp' for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/ttc_mgt.dcp' for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt' Netlist sorting complete. Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 3310.004 ; gain = 152.453 INFO: [Netlist 29-17] Analyzing 10904 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 16 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/mgt_ip/synth/mgt_ip.xdc] for cell 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/synth/ttc_mgt.xdc] for cell 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/ip_0/synth/gig_ethernet_pcs_pma_0_gt.xdc] for cell 'eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/ip_0/synth/gig_ethernet_pcs_pma_0_gt.xdc] for cell 'eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_board.xdc] for cell 'eth/phy/U0' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_board.xdc] for cell 'eth/phy/U0' Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0_clocks.xdc] for cell 'eth/phy/U0' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0_clocks.xdc] for cell 'eth/phy/U0' Parsing XDC File [D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc:129] WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks [D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc:129] INFO: [Timing 38-2] Deriving generated clocks [D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc:129] get_clocks: Time (s): cpu = 00:02:58 ; elapsed = 00:01:42 . Memory (MB): peak = 6297.328 ; gain = 1847.742 Finished Parsing XDC File [D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc] Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0.xdc] for cell 'eth/phy/U0' Finished Parsing XDC File [d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0.xdc] for cell 'eth/phy/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-441] Inserted BUFG_GT_SYNC i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC for BUFG_GT i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst INFO: [Opt 31-441] Inserted BUFG_GT_SYNC i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 for BUFG_GT i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst INFO: [Project 1-1687] 8 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.415 . Memory (MB): peak = 6305.668 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1038 instances were transformed. DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 1003 instances IBUF => IBUF (IBUFCTRL, INBUF): 17 instances IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 18 instances 16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:07:52 ; elapsed = 00:06:28 . Memory (MB): peak = 6305.668 ; gain = 5277.969 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 6305.668 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Ending Cache Timing Information Task | Checksum: 1203813b9 Time (s): cpu = 00:02:43 ; elapsed = 00:01:32 . Memory (MB): peak = 6305.668 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 2153 inverter(s) to 17402 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 251c4a4c5 Time (s): cpu = 00:01:25 ; elapsed = 00:01:04 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-389] Phase Retarget created 637 cells and removed 3130 cells INFO: [Opt 31-1021] In phase Retarget, 770 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 29b57cb64 Time (s): cpu = 00:01:32 ; elapsed = 00:01:11 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-389] Phase Constant propagation created 17 cells and removed 186 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1be47df63 Time (s): cpu = 00:02:01 ; elapsed = 00:01:41 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 652 cells INFO: [Opt 31-1021] In phase Sweep, 4082 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: ipb_rst_BUFG_inst, Net: ipb_rst Phase 4 BUFG optimization | Checksum: 287b45196 Time (s): cpu = 00:02:37 ; elapsed = 00:02:16 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-662] Phase BUFG optimization created 2 cells of which 1 are BUFGs and removed 0 cells. INFO: [Opt 31-1021] In phase BUFG optimization, 6 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 287b45196 Time (s): cpu = 00:02:39 ; elapsed = 00:02:18 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 2950b4a3a Time (s): cpu = 00:02:44 ; elapsed = 00:02:23 . Memory (MB): peak = 6452.953 ; gain = 147.285 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 637 | 3130 | 770 | | Constant propagation | 17 | 186 | 0 | | Sweep | 0 | 652 | 4082 | | BUFG optimization | 2 | 0 | 6 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6452.953 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 1c2bfa8a7 Time (s): cpu = 00:03:19 ; elapsed = 00:02:55 . Memory (MB): peak = 6452.953 ; gain = 147.285 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [Pwropt 34-175] Flop ipb/trans/sm/addr_reg[11]/_DFFRS is having more than maxLoadSize fanouts. Skipped from ODC paradigm. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2110 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [Pwropt 34-201] Structural ODC has moved 56 WE to EN ports Number of BRAM Ports augmented: 9 newly gated: 740 Total Ports: 4220 Ending PowerOpt Patch Enables Task | Checksum: 19bf1e094 Time (s): cpu = 00:03:19 ; elapsed = 00:02:02 . Memory (MB): peak = 13824.258 ; gain = 0.000 Ending Power Optimization Task | Checksum: 19bf1e094 Time (s): cpu = 00:19:54 ; elapsed = 00:09:18 . Memory (MB): peak = 13824.258 ; gain = 7371.305 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Ending Logic Optimization Task | Checksum: 12d2c38ac Time (s): cpu = 00:04:20 ; elapsed = 00:02:43 . Memory (MB): peak = 13824.258 ; gain = 0.000 Ending Final Cleanup Task | Checksum: 12d2c38ac Time (s): cpu = 00:04:28 ; elapsed = 00:02:51 . Memory (MB): peak = 13824.258 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.422 . Memory (MB): peak = 13824.258 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: 12d2c38ac Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.422 . Memory (MB): peak = 13824.258 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 47 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:30:43 ; elapsed = 00:16:52 . Memory (MB): peak = 13824.258 ; gain = 7518.590 INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.321 . Memory (MB): peak = 13824.258 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:06:49 ; elapsed = 00:03:52 . Memory (MB): peak = 13824.258 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx Command: report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:04:50 ; elapsed = 00:02:34 . Memory (MB): peak = 13824.258 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.440 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12083804d Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.728 . Memory (MB): peak = 13824.258 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.421 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15206d954 Time (s): cpu = 00:02:03 ; elapsed = 00:01:31 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d25aec82 Time (s): cpu = 00:09:50 ; elapsed = 00:06:45 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d25aec82 Time (s): cpu = 00:09:53 ; elapsed = 00:06:48 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 1d25aec82 Time (s): cpu = 00:09:59 ; elapsed = 00:06:55 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2415a42a4 Time (s): cpu = 00:12:39 ; elapsed = 00:08:39 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 202454c00 Time (s): cpu = 00:14:08 ; elapsed = 00:09:34 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 2.3 Global Placement Core SLR(matching) [0-1] 14 30 15 69 473 1440 903 124 55 20 24 13 Total: 3180 SLR(matching) [0-1] 17 15 20 116 899 965 838 223 3 28 37 19 Total: 3180 SLR(matching) [0-1] 20 16 19 34 910 1058 949 92 13 29 27 13 Total: 3180 SLR(matching) [0-1] 11 13 22 18 815 1195 968 63 14 22 26 13 Total: 3180 SLR(matching) [0-1] 18 14 15 16 753 1271 981 30 15 22 33 12 Total: 3180 SLR(matching) [0-1] 14 12 12 23 704 1313 993 31 17 21 22 18 Total: 3180 SLR(matching) [0-1] 14 11 11 20 687 1323 1007 28 20 21 18 20 Total: 3180 SLR(matching) [0-1] 13 11 12 20 656 1352 1011 26 20 21 18 20 Total: 3180 SLR(matching) [0-1] 13 12 11 19 577 1401 1042 26 20 21 18 20 Total: 3180 SLR(matching) [0-1] 13 12 11 19 546 1417 1057 26 20 21 18 20 Total: 3180 SLR(matching) [0-1] 12 12 13 20 511 1440 1066 29 16 26 12 23 Total: 3180 SLR(matching) [0-1] 16 13 10 15 524 1418 1080 23 24 23 17 17 Total: 3180 SLR(matching) [0-1] 15 16 17 19 582 1324 1100 27 15 27 29 9 Total: 3180 SLR(matching) [0-1] 18 12 11 21 813 1086 1100 40 19 24 17 19 Total: 3180 SLR(matching) [0-1] 19 17 14 27 912 963 981 166 15 23 22 21 Total: 3180 SLR(matching) [0-1] 17 21 26 214 767 899 847 292 24 26 24 23 Total: 3180 SLR(matching) [0-1] 27 17 168 159 698 855 786 353 35 10 35 37 Total: 3180 SLR(matching) [0-1] 25 26 73 151 653 813 794 389 75 113 36 32 Total: 3180 SLR(matching) [0-1] 42 52 97 160 576 764 704 528 120 62 18 57 Total: 3180 SLR(matching) [0-1] 48 72 102 164 492 771 655 565 168 59 34 50 Total: 3180 SLR(matching) [0-1] 46 71 111 163 404 811 568 679 166 68 34 59 Total: 3180 SLR(matching) [0-1] 50 77 118 160 326 806 621 635 205 70 46 66 Total: 3180 SLR(matching) [0-1] 48 85 115 156 326 793 662 609 187 83 50 66 Total: 3180 SLR(matching) [0-1] 49 80 110 160 347 798 655 578 203 76 61 63 Total: 3180 SLR(matching) [0-1] 51 85 97 175 404 736 668 593 184 70 52 65 Total: 3180 SLR(matching) [0-1] 56 82 105 173 398 717 687 591 180 73 53 65 Total: 3180 SLR(matching) [0-1] 58 81 112 154 403 723 696 566 194 75 54 64 Total: 3180 SLR(matching) [0-1] 59 81 110 165 398 726 689 570 197 84 33 68 Total: 3180 SLR(matching) [0-1] 72 71 117 166 407 716 676 561 192 78 60 64 Total: 3180 SLR(matching) [0-1] 75 74 104 161 419 711 704 557 185 80 42 68 Total: 3180 SLR(matching) [0-1] 78 72 93 177 425 702 680 575 192 72 50 64 Total: 3180 SLR(matching) [0-1] 79 70 99 171 439 680 689 576 187 82 37 71 Total: 3180 SLR(matching) [0-1] 77 73 97 187 424 686 680 574 185 80 54 63 Total: 3180 SLR(matching) [0-1] 78 72 101 179 435 679 679 569 190 82 46 70 Total: 3180 SLR(matching) [0-1] 81 72 98 183 417 703 666 582 189 74 49 66 Total: 3180 SLR(matching) [0-1] 83 65 105 183 498 592 711 553 199 76 50 65 Total: 3180 SLR(matching) [0-1] 80 67 103 177 504 575 721 560 195 82 51 65 Total: 3180 SLR(matching) [0-1] 77 75 107 178 499 592 705 559 208 76 32 72 Total: 3180 SLR(matching) [0-1] 78 71 99 185 508 649 658 547 201 83 31 70 Total: 3180 SLR(matching) [0-1] 83 63 102 192 508 649 646 554 191 80 48 64 Total: 3180 SLR(matching) [0-1] 88 62 100 195 513 633 649 557 193 78 48 64 Total: 3180 SLR(matching) [0-1] 91 57 112 184 521 614 659 554 192 86 47 63 Total: 3180 SLR(matching) [0-1] 90 60 108 181 510 626 665 552 193 86 45 64 Total: 3180 SLR(matching) [0-1] 92 60 111 176 520 610 686 539 194 92 29 71 Total: 3180 Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 2 LUTNM shape to break, 14339 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 2, two critical 0, total 2, new lutff created 1 INFO: [Physopt 32-775] End 1 Pass. Optimized 6506 nets or cells. Created 2 new cells, deleted 6504 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 6 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net TX_CLKEN. Replicated 62 times. INFO: [Physopt 32-81] Processed net ipb/trans/sm/addr_reg[17]_0[12]. Replicated 8 times. INFO: [Physopt 32-81] Processed net ipb/trans/sm/addr_reg[17]_0[13]. Replicated 14 times. INFO: [Physopt 32-81] Processed net ipb/trans/sm/ipb_mosi[0][ipb_addr][18]. Replicated 12 times. INFO: [Physopt 32-81] Processed net ipb/trans/sm/ipb_mosi[0][ipb_addr][19]. Replicated 12 times. INFO: [Physopt 32-81] Processed net ipb/trans/sm/ipb_mosi[0][ipb_addr][26]. Replicated 12 times. INFO: [Physopt 32-232] Optimized 6 nets. Created 120 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 6 nets or cells. Created 120 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 13824.258 ; gain = 0.000 INFO: [Physopt 32-76] Pass 1. Identified 4 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net g_clock_rate_din[14].i_rate_ngccm_status0/E[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net g_clock_rate_din[15].i_rate_ngccm_status0/E[0]. Replicated 7 times. INFO: [Physopt 32-81] Processed net g_clock_rate_din[10].i_rate_ngccm_status0/E[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net stat_regs_inst/wea. Replicated 9 times. INFO: [Physopt 32-232] Optimized 4 nets. Created 30 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 30 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 13824.258 ; gain = 0.000 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.416 . Memory (MB): peak = 13824.258 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 2 | 6504 | 6506 | 0 | 1 | 00:00:27 | | Very High Fanout | 120 | 0 | 6 | 0 | 1 | 00:00:33 | | Fanout | 30 | 0 | 4 | 0 | 1 | 00:00:02 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 152 | 6504 | 6516 | 0 | 9 | 00:01:06 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 180d110ed Time (s): cpu = 00:45:06 ; elapsed = 00:32:11 . Memory (MB): peak = 13824.258 ; gain = 0.000 SLR(matching) [0-1] 105 86 118 253 530 629 663 504 156 71 32 72 Total: 3219 Phase 2.3 Global Placement Core | Checksum: 1d0b6f043 Time (s): cpu = 00:46:24 ; elapsed = 00:33:12 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 2 Global Placement | Checksum: 1d0b6f043 Time (s): cpu = 00:46:26 ; elapsed = 00:33:14 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 12c01f1a5 Time (s): cpu = 00:49:36 ; elapsed = 00:35:32 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs SLR(matching) [0-1] 128 102 103 264 494 634 660 505 148 72 40 69 Total: 3219 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: fa0332fe Time (s): cpu = 00:54:03 ; elapsed = 00:39:01 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.3 Small Shape DP Phase 3.3.1 Small Shape Clustering SLR(matching) [0-1] 118 52 110 316 628 690 743 582 226 141 48 70 Total: 3724 Phase 3.3.1 Small Shape Clustering | Checksum: 165b955cc Time (s): cpu = 01:05:25 ; elapsed = 00:47:59 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.3.2 DP Optimization SLR(matching) [0-1] 117 53 105 326 619 675 756 580 226 148 49 70 Total: 3724 SLR(matching) [0-1] 117 52 105 325 621 673 757 579 228 148 49 70 Total: 3724 SLR(matching) [0-1] 82 41 132 234 623 692 760 627 275 136 61 61 Total: 3724 SLR(matching) [0-1] 85 45 132 254 610 689 740 638 272 141 51 67 Total: 3724 SLR(matching) [0-1] 79 48 142 237 620 673 753 638 272 144 52 66 Total: 3724 SLR(matching) [0-1] 79 51 141 234 617 669 767 630 278 143 50 65 Total: 3724 SLR(matching) [0-1] 85 58 133 240 621 664 771 622 262 156 45 67 Total: 3724 SLR(matching) [0-1] 81 63 142 225 618 666 769 625 276 144 50 65 Total: 3724 SLR(matching) [0-1] 81 63 141 228 616 664 772 626 274 144 50 65 Total: 3724 SLR(matching) [0-1] 90 55 134 237 621 662 775 622 264 146 52 66 Total: 3724 SLR(matching) [0-1] 85 52 130 241 628 663 769 622 270 148 50 66 Total: 3724 SLR(matching) [0-1] 89 57 133 236 621 665 777 614 266 150 50 66 Total: 3724 SLR(matching) [0-1] 89 60 136 231 626 662 786 604 260 151 55 64 Total: 3724 SLR(matching) [0-1] 93 55 131 238 615 674 772 617 262 146 55 66 Total: 3724 SLR(matching) [0-1] 87 56 136 240 623 659 775 617 268 147 50 66 Total: 3724 SLR(matching) [0-1] 86 62 139 235 608 669 774 617 276 141 52 65 Total: 3724 SLR(matching) [0-1] 90 56 130 239 623 679 766 614 263 142 58 64 Total: 3724 SLR(matching) [0-1] 84 54 138 254 628 656 758 622 274 141 51 64 Total: 3724 SLR(matching) [0-1] 85 59 142 243 609 675 761 621 272 139 53 65 Total: 3724 SLR(matching) [0-1] 92 53 127 251 617 674 762 621 266 142 54 65 Total: 3724 SLR(matching) [0-1] 89 53 134 253 615 672 759 623 262 148 50 66 Total: 3724 SLR(matching) [0-1] 86 59 142 246 610 673 764 620 264 140 53 67 Total: 3724 SLR(matching) [0-1] 92 53 127 255 617 673 760 619 262 146 53 67 Total: 3724 SLR(matching) [0-1] 89 55 137 260 619 663 752 618 271 141 53 66 Total: 3724 SLR(matching) [0-1] 89 54 131 252 625 668 756 630 258 148 46 67 Total: 3724 SLR(matching) [0-1] 89 60 147 239 607 676 758 627 268 135 52 66 Total: 3724 SLR(matching) [0-1] 86 57 139 251 620 671 751 628 259 141 53 68 Total: 3724 SLR(matching) [0-1] 87 58 135 253 617 685 743 621 267 140 49 69 Total: 3724 SLR(matching) [0-1] 87 55 147 237 614 683 751 628 268 135 52 67 Total: 3724 SLR(matching) [0-1] 90 56 136 242 623 690 753 611 262 140 54 67 Total: 3724 SLR(matching) [0-1] 95 53 132 246 618 683 750 624 258 149 49 67 Total: 3724 SLR(matching) [0-1] 96 51 136 250 621 684 746 626 263 134 50 67 Total: 3724 SLR(matching) [0-1] 87 54 152 245 597 689 748 627 270 135 54 66 Total: 3724 SLR(matching) [0-1] 90 59 152 238 604 686 750 623 271 135 50 66 Total: 3724 Phase 3.3.2 DP Optimization | Checksum: 176a854a6 Time (s): cpu = 01:50:05 ; elapsed = 01:22:39 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.3.3 Flow Legalize Slice Clusters Phase 3.3.3 Flow Legalize Slice Clusters | Checksum: 1ce246704 Time (s): cpu = 01:50:14 ; elapsed = 01:22:44 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.3.4 Slice Area Swap SLR(matching) [0-1] 118 64 118 329 594 686 739 584 221 149 52 70 Total: 3724 SLR(matching) [0-1] 118 61 124 343 592 709 723 571 221 150 44 68 Total: 3724 Phase 3.3.4 Slice Area Swap | Checksum: 1c9181ea0 Time (s): cpu = 01:54:11 ; elapsed = 01:25:15 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.3 Small Shape DP | Checksum: 1782acbd2 Time (s): cpu = 01:58:14 ; elapsed = 01:27:25 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.4 Re-assign LUT pins Phase 3.4 Re-assign LUT pins | Checksum: 1defb65f4 Time (s): cpu = 01:59:15 ; elapsed = 01:28:42 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.5 Pipeline Register Optimization Phase 3.5 Pipeline Register Optimization | Checksum: 18109ff40 Time (s): cpu = 01:59:30 ; elapsed = 01:28:57 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3.6 Fast Optimization Phase 3.6 Fast Optimization | Checksum: 233f8210c Time (s): cpu = 02:41:57 ; elapsed = 02:04:52 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 233f8210c Time (s): cpu = 02:42:02 ; elapsed = 02:04:57 . Memory (MB): peak = 13824.258 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 27b15345c Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.151 | TNS=-0.183 | Phase 1 Physical Synthesis Initialization | Checksum: 1d230a7f8 Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 14023.328 ; gain = 0.000 INFO: [Place 46-35] Processed net SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0], inserted BUFG to drive 8853 loads. INFO: [Place 46-35] Processed net fabric_clk_div2, inserted BUFG to drive 5252 loads. INFO: [Place 46-45] Replicated bufg driver fabric_clk_div2_reg_replica INFO: [Place 46-35] Processed net SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0], inserted BUFG to drive 1392 loads. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 3, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 195c65012 Time (s): cpu = 00:01:27 ; elapsed = 00:00:55 . Memory (MB): peak = 14023.328 ; gain = 0.000 Phase 4.1.1.1 BUFG Insertion | Checksum: 1becc7975 Time (s): cpu = 03:15:04 ; elapsed = 02:32:04 . Memory (MB): peak = 14023.328 ; gain = 199.070 Phase 4.1.1.2 BUFG Replication INFO: [Place 46-68] Processed net fabric_clk_div2, BUFG replication was skipped in SLR 0 as timing constraints are met. INFO: [Place 46-68] Processed net ipb_rst_BUFG, BUFG replication was skipped in SLR 1 as timing constraints are met. INFO: [Place 46-63] BUFG replication identified 2 candidate nets: Replicated nets: 0, Replicated BUFGs: 0, Replicated BUFG Driver: 0, Skipped due to Placement / Routing Conflict: 0, Skipped due to Timing: 2, Skipped due to constraints: 0 Phase 4.1.1.2 BUFG Replication | Checksum: 1becc7975 Time (s): cpu = 03:15:19 ; elapsed = 02:32:18 . Memory (MB): peak = 14088.500 ; gain = 264.242 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.108. For the most accurate timing information please run report_timing. Phase 4.1.1.3 Replication INFO: [Place 46-19] Post Replication Timing Summary WNS=0.108. For the most accurate timing information please run report_timing. Phase 4.1.1.3 Replication | Checksum: 1d25a6df6 Time (s): cpu = 03:20:32 ; elapsed = 02:36:31 . Memory (MB): peak = 14088.500 ; gain = 264.242 Time (s): cpu = 03:20:32 ; elapsed = 02:36:31 . Memory (MB): peak = 14088.500 ; gain = 264.242 Phase 4.1 Post Commit Optimization | Checksum: 1d25a6df6 Time (s): cpu = 03:20:38 ; elapsed = 02:36:36 . Memory (MB): peak = 14088.500 ; gain = 264.242 Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 14088.500 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1fc52d420 Time (s): cpu = 03:21:02 ; elapsed = 02:36:59 . Memory (MB): peak = 14088.500 ; gain = 264.242 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 4x4| 8x8| |___________|___________________|___________________| | South| 4x4| 8x8| |___________|___________________|___________________| | East| 2x2| 8x8| |___________|___________________|___________________| | West| 1x1| 8x8| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1fc52d420 Time (s): cpu = 03:21:08 ; elapsed = 02:37:05 . Memory (MB): peak = 14088.500 ; gain = 264.242 Phase 4.3 Placer Reporting | Checksum: 1fc52d420 Time (s): cpu = 03:21:13 ; elapsed = 02:37:11 . Memory (MB): peak = 14088.500 ; gain = 264.242 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.416 . Memory (MB): peak = 14088.500 ; gain = 0.000 Time (s): cpu = 03:21:14 ; elapsed = 02:37:11 . Memory (MB): peak = 14088.500 ; gain = 264.242 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ee2a4cd9 Time (s): cpu = 03:21:19 ; elapsed = 02:37:17 . Memory (MB): peak = 14088.500 ; gain = 264.242 Ending Placer Task | Checksum: 1b305f990 Time (s): cpu = 03:21:19 ; elapsed = 02:37:17 . Memory (MB): peak = 14088.500 ; gain = 264.242 INFO: [Common 17-83] Releasing license: Implementation 109 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 03:22:11 ; elapsed = 02:37:53 . Memory (MB): peak = 14088.500 ; gain = 264.242 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:02:52 ; elapsed = 00:00:55 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:14 ; elapsed = 00:02:31 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file ngFEC_top_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.559 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file ngFEC_top_utilization_placed.rpt -pb ngFEC_top_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [runtcl-4] Executing : report_control_sets -verbose -file ngFEC_top_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 14088.500 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 119 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:27:06 ; elapsed = 00:21:45 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:02:45 ; elapsed = 00:00:54 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:34 ; elapsed = 00:02:50 . Memory (MB): peak = 14088.500 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: d9b85ad3 ConstDB: 0 ShapeSum: af553893 RouteDB: 29f8662a Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 16bb683ce Time (s): cpu = 00:05:06 ; elapsed = 00:04:00 . Memory (MB): peak = 14088.500 ; gain = 0.000 Post Restoration Checksum: NetGraph: cf1c8474 NumContArr: 4dbbd8b2 Constraints: 86afc028 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1a3881d4e Time (s): cpu = 00:05:22 ; elapsed = 00:04:16 . Memory (MB): peak = 14088.500 ; gain = 0.000 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 1a3881d4e Time (s): cpu = 00:05:26 ; elapsed = 00:04:20 . Memory (MB): peak = 14088.500 ; gain = 0.000 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 1a3881d4e Time (s): cpu = 00:05:29 ; elapsed = 00:04:23 . Memory (MB): peak = 14088.500 ; gain = 0.000 Phase 2.4 Global Clock Net Routing Number of Nodes with overlaps = 0 Phase 2.4 Global Clock Net Routing | Checksum: 2307bb653 Time (s): cpu = 00:06:25 ; elapsed = 00:05:07 . Memory (MB): peak = 14088.500 ; gain = 0.000 Phase 2.5 Update Timing Phase 2.5 Update Timing | Checksum: 141e8610b Time (s): cpu = 00:20:19 ; elapsed = 00:14:34 . Memory (MB): peak = 14088.500 ; gain = 0.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.214 | TNS=0.000 | WHS=-0.409 | THS=-2029.336| Phase 2 Router Initialization | Checksum: 1f9739516 Time (s): cpu = 00:27:27 ; elapsed = 00:19:08 . Memory (MB): peak = 15637.211 ; gain = 1548.711 Router Utilization Summary Global Vertical Routing Utilization = 0.000486957 % Global Horizontal Routing Utilization = 1.69515e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 833019 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 670349 Number of Partially Routed Nets = 162670 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1f9739516 Time (s): cpu = 00:28:03 ; elapsed = 00:19:33 . Memory (MB): peak = 15637.211 ; gain = 1548.711 Phase 3 Initial Routing | Checksum: 2b52e3896 Time (s): cpu = 00:35:08 ; elapsed = 00:23:59 . Memory (MB): peak = 15637.211 ; gain = 1548.711 INFO: [Route 35-449] Initial Estimated Congestion ________________________________________________________________________ | | Global Congestion | Long Congestion | Short Congestion | | |___________________|___________________|___________________| | Direction | Size | % Tiles | Size | % Tiles | Size | % Tiles | |___________|________|__________|________|__________|________|__________| | NORTH| 4x4| 0.23| 8x8| 1.12| 4x4| 0.85| |___________|________|__________|________|__________|________|__________| | SOUTH| 4x4| 0.29| 4x4| 0.50| 16x16| 0.94| |___________|________|__________|________|__________|________|__________| | EAST| 4x4| 0.29| 8x8| 0.73| 4x4| 0.76| |___________|________|__________|________|__________|________|__________| | WEST| 2x2| 0.05| 2x2| 0.18| 8x8| 0.74| |___________|________|__________|________|__________|________|__________| Congestion Report SHORT Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): SOUTH INT_X40Y168->INT_X47Y183 (CLE_M_X40Y168->DSP_X47Y180) INT_X40Y168->INT_X47Y175 (CLE_M_X40Y168->DSP_X47Y175) Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 167260 Number of Nodes with overlaps = 12831 Number of Nodes with overlaps = 1716 Number of Nodes with overlaps = 494 Number of Nodes with overlaps = 193 Number of Nodes with overlaps = 92 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y4/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y14/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y15/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y5/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y6/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y7/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y12/NORTHREFCLK0 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y13/NORTHREFCLK0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.087 | TNS=0.000 | WHS=-0.058 | THS=-0.683 | Phase 4.1 Global Iteration 0 | Checksum: 1a67f2e1f Time (s): cpu = 01:55:43 ; elapsed = 01:28:44 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.087 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1b31bbede Time (s): cpu = 01:57:56 ; elapsed = 01:30:21 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 157 Number of Nodes with overlaps = 61 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.150 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 178981328 Time (s): cpu = 02:03:59 ; elapsed = 01:36:10 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 4 Rip-up And Reroute | Checksum: 178981328 Time (s): cpu = 02:04:02 ; elapsed = 01:36:14 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1a0f7541c Time (s): cpu = 02:16:08 ; elapsed = 01:46:15 . Memory (MB): peak = 16610.965 ; gain = 2522.465 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.150 | TNS=0.000 | WHS=0.024 | THS=0.000 | Phase 5.1 Delay CleanUp | Checksum: 1a0f7541c Time (s): cpu = 02:16:13 ; elapsed = 01:46:20 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1a0f7541c Time (s): cpu = 02:16:17 ; elapsed = 01:46:24 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 5 Delay and Skew Optimization | Checksum: 1a0f7541c Time (s): cpu = 02:16:20 ; elapsed = 01:46:27 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1aa92852e Time (s): cpu = 02:27:54 ; elapsed = 01:55:52 . Memory (MB): peak = 16610.965 ; gain = 2522.465 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.150 | TNS=0.000 | WHS=0.024 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1e7dabe52 Time (s): cpu = 02:27:58 ; elapsed = 01:55:56 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 6 Post Hold Fix | Checksum: 1e7dabe52 Time (s): cpu = 02:28:02 ; elapsed = 01:56:00 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 17.169 % Global Horizontal Routing Utilization = 16.7945 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 10b819b64 Time (s): cpu = 02:28:41 ; elapsed = 01:56:31 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10b819b64 Time (s): cpu = 02:28:45 ; elapsed = 01:56:35 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y8/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y18/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y19/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y9/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y10/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y11/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y12/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y13/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y14/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y15/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y16/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y17/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y28/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y38/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y39/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y29/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y30/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y31/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y32/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y33/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y34/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y35/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y36/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X0Y37/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y28/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y38/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y39/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y29/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y30/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y31/SOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y32/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y33/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y34/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y35/MGTREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y36/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0 to physical pin GTHE3_CHANNEL_X1Y37/NORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_tcds2_if/i_mgt_wrapper/i_rxrecclk/I to physical pin GTHE3_COMMON_X1Y0/RXRECCLK3 Phase 9 Depositing Routes | Checksum: 10b819b64 Time (s): cpu = 02:30:13 ; elapsed = 01:58:13 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.150 | TNS=0.000 | WHS=0.024 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 10b819b64 Time (s): cpu = 02:30:24 ; elapsed = 01:58:23 . Memory (MB): peak = 16610.965 ; gain = 2522.465 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 02:30:26 ; elapsed = 01:58:25 . Memory (MB): peak = 16610.965 ; gain = 2522.465 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 183 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 02:40:03 ; elapsed = 02:06:05 . Memory (MB): peak = 16610.965 ; gain = 2522.465 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:04:01 ; elapsed = 00:01:18 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:05:48 ; elapsed = 00:02:42 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx Command: report_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:31:53 ; elapsed = 00:24:54 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx Command: report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:07:12 ; elapsed = 00:04:09 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx Command: report_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Timing 38-277] The instance 'i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST' has QPLL1REFCLKSEL pins that are not constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 195 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:08:39 ; elapsed = 00:04:52 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_route_status -file ngFEC_top_route_status.rpt -pb ngFEC_top_route_status.pb report_route_status: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: C, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs report_timing_summary: Time (s): cpu = 00:00:53 ; elapsed = 00:00:40 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_incremental_reuse -file ngFEC_top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file ngFEC_top_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 16610.965 ; gain = 0.000 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file ngFEC_top_bus_skew_routed.rpt -pb ngFEC_top_bus_skew_routed.pb -rpx ngFEC_top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: C, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs write_mem_info: Time (s): cpu = 00:06:04 ; elapsed = 00:06:05 . Memory (MB): peak = 16610.965 ; gain = 0.000 Command: write_bitstream -force ngFEC_top.bit Attempting to get a license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku115' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-2] Input pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. INFO: [Common 17-14] Message 'DRC DPIP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst output ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst output stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-3] PREG Output pipelining: DSP stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 output stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. INFO: [Common 17-14] Message 'DRC DPOP-3' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 WARNING: [DRC DPREG-7] DSP48E2_PregDynOpmodeZmuxP:: The DSP48E2 cell stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst with the given dynamic OPMODE[8:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0 INFO: [Common 17-14] Message 'DRC DPREG-7' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_refclk1_n spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_refclk1_p spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 3, 1. Bits placed in SLR 0: 2, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_rxn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_rxp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_txn spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. WARNING: [DRC IOBUSSLRC-1] IO Bus SLR Crossings: Bus port GBT_txp spans more than one Super Logic Region (SLR). Bits placed in SLR 1: 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12. Bits placed in SLR 0: 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[4].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[5].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[6].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_i[7].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: ctrl_regs_inst/i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_cntr_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[2].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: stat_regs_inst/g_stat_MUX_j[2].g_stat_MUX_i[3].i_DSP_MUX/DSP48E2_inst: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-156' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1669] enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. INFO: [DRC REQP-1669] enum_AREG_0_connects_CEA1_GND_connects_CEA2_GND: stat_regs_inst/i_DSP_rate: When DSP48E2 attribute AREG is set to 0, the CEA1 and CEA2 pins should be tied to GND to save power. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1671] enum_AREG_1_connects_CEA1_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 AREG attribute is set to 1, the CEA1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [Common 17-14] Message 'DRC REQP-1671' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1673] enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: stat_regs_inst/i_DSP_cntr: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. INFO: [DRC REQP-1673] enum_BREG_0_connects_CEB1_GND_connects_CEB2_GND: stat_regs_inst/i_DSP_rate: When DSP48E2 attribute BREG is set to 0, the CEB1 and CEB2 pins should be tied to GND to save power. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [DRC REQP-1675] enum_BREG_1_connects_CEB1_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 BREG attribute is set to 1, the CEB1 input pin is preferred to be tied to GND to save power when OPMODE0 and OPMODE1 are 1. INFO: [Common 17-14] Message 'DRC REQP-1675' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [DRC REQP-1678] enum_CREG_0_connects_CEC_GND: g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst: When the DSP48E2 CREG attribute is set to 0, the CEC input pin should be tied to GND to save power. INFO: [Common 17-14] Message 'DRC REQP-1678' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [DRC REQP-1680] enum_PREG_0_connects_CEP_GND: stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2: When the DSP48E2 PREG attribute is set to 0, the CEP input pin should be tied to GND to save power. INFO: [Common 17-14] Message 'DRC REQP-1680' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[0].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[10].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[2].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[3].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[4].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[5].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[6].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[7].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[8].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1681] with_OPMODE_USE_MULT_NONE: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[9].DSP48E2_inst: To save power with this DSP48E2 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[0].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[10].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[11].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[12].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[13].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[14].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[6].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[7].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[8].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[15].ngFEC_module/bram_array[9].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (SFP_GEN[16].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Common 17-14] Message 'DRC REQP-1934' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2257 Warnings, 2254 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./ngFEC_top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] 'D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sat Mar 13 05:06:36 2021. For additional details about this file, please refer to the WebTalk help file at D:/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 739 Infos, 307 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:09:41 ; elapsed = 00:06:12 . Memory (MB): peak = 18448.871 ; gain = 1837.906 INFO: [Common 17-206] Exiting Vivado at Sat Mar 13 05:06:36 2021...