
Q
Command: %s
53*	vivadotcl2 
route_design2default:defaultZ4-113h px 
£
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xcku1152default:defaultZ17-347h px 
“
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xcku1152default:defaultZ17-349h px 
Ñ
The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2021.012default:defaultZ17-1540h px 
p
,Running DRC as a precondition to command %s
22*	vivadotcl2 
route_design2default:defaultZ4-22h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
V
DRC finished with %s
79*	vivadotcl2
0 Errors2default:defaultZ4-198h px 
e
BPlease refer to the DRC report (report_drc) for more information.
80*	vivadotclZ4-199h px 
V

Starting %s Task
103*constraints2
Routing2default:defaultZ18-103h px 
}
BMultithreading enabled for route_design using a maximum of %s CPUs17*	routeflow2
22default:defaultZ35-254h px 
p

Phase %s%s
101*constraints2
1 2default:default2#
Build RT Design2default:defaultZ18-101h px 
C
.Phase 1 Build RT Design | Checksum: 16bb683ce
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:05:06 ; elapsed = 00:04:00 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 
v

Phase %s%s
101*constraints2
2 2default:default2)
Router Initialization2default:defaultZ18-101h px 
o

Phase %s%s
101*constraints2
2.1 2default:default2 
Create Timer2default:defaultZ18-101h px 
B
-Phase 2.1 Create Timer | Checksum: 1a3881d4e
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:05:22 ; elapsed = 00:04:16 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 
{

Phase %s%s
101*constraints2
2.2 2default:default2,
Fix Topology Constraints2default:defaultZ18-101h px 
N
9Phase 2.2 Fix Topology Constraints | Checksum: 1a3881d4e
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:05:26 ; elapsed = 00:04:20 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 
t

Phase %s%s
101*constraints2
2.3 2default:default2%
Pre Route Cleanup2default:defaultZ18-101h px 
G
2Phase 2.3 Pre Route Cleanup | Checksum: 1a3881d4e
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:05:29 ; elapsed = 00:04:23 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 
{

Phase %s%s
101*constraints2
2.4 2default:default2,
Global Clock Net Routing2default:defaultZ18-101h px 
N
9Phase 2.4 Global Clock Net Routing | Checksum: 2307bb653
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:06:25 ; elapsed = 00:05:07 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 
p

Phase %s%s
101*constraints2
2.5 2default:default2!
Update Timing2default:defaultZ18-101h px 
C
.Phase 2.5 Update Timing | Checksum: 141e8610b
*commonh px 


%s
*constraints2p
\Time (s): cpu = 00:20:19 ; elapsed = 00:14:34 . Memory (MB): peak = 14088.500 ; gain = 0.0002default:defaulth px 

Intermediate Timing Summary %s164*route2L
8| WNS=0.214  | TNS=0.000  | WHS=-0.409 | THS=-2029.336|
2default:defaultZ35-416h px 
I
4Phase 2 Router Initialization | Checksum: 1f9739516
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 00:27:27 ; elapsed = 00:19:08 . Memory (MB): peak = 15637.211 ; gain = 1548.7112default:defaulth px 
p

Phase %s%s
101*constraints2
3 2default:default2#
Initial Routing2default:defaultZ18-101h px 
q

Phase %s%s
101*constraints2
3.1 2default:default2"
Global Routing2default:defaultZ18-101h px 
D
/Phase 3.1 Global Routing | Checksum: 1f9739516
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 00:28:03 ; elapsed = 00:19:33 . Memory (MB): peak = 15637.211 ; gain = 1548.7112default:defaulth px 
C
.Phase 3 Initial Routing | Checksum: 2b52e3896
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 00:35:08 ; elapsed = 00:23:59 . Memory (MB): peak = 15637.211 ; gain = 1548.7112default:defaulth px 
=
Initial Estimated Congestion179*routeZ35-449h px 
s

Phase %s%s
101*constraints2
4 2default:default2&
Rip-up And Reroute2default:defaultZ18-101h px 
u

Phase %s%s
101*constraints2
4.1 2default:default2&
Global Iteration 02default:defaultZ18-101h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X1Y4/SOUTHREFCLK1GTHE3_CHANNEL_X1Y4/SOUTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y14/NORTHREFCLK0 GTHE3_CHANNEL_X1Y14/NORTHREFCLK02default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y15/NORTHREFCLK0 GTHE3_CHANNEL_X1Y15/NORTHREFCLK02default:default8Z35-467h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X1Y5/SOUTHREFCLK1GTHE3_CHANNEL_X1Y5/SOUTHREFCLK12default:default8Z35-467h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X1Y6/SOUTHREFCLK1GTHE3_CHANNEL_X1Y6/SOUTHREFCLK12default:default8Z35-467h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X1Y7/SOUTHREFCLK1GTHE3_CHANNEL_X1Y7/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y12/NORTHREFCLK0 GTHE3_CHANNEL_X1Y12/NORTHREFCLK02default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y13/NORTHREFCLK0 GTHE3_CHANNEL_X1Y13/NORTHREFCLK02default:default8Z35-467h px 
‹
Intermediate Timing Summary %s164*route2J
6| WNS=0.087  | TNS=0.000  | WHS=-0.058 | THS=-0.683 |
2default:defaultZ35-416h px 
H
3Phase 4.1 Global Iteration 0 | Checksum: 1a67f2e1f
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 01:55:43 ; elapsed = 01:28:44 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
u

Phase %s%s
101*constraints2
4.2 2default:default2&
Global Iteration 12default:defaultZ18-101h px 
‹
Intermediate Timing Summary %s164*route2J
6| WNS=0.087  | TNS=0.000  | WHS=N/A    | THS=N/A    |
2default:defaultZ35-416h px 
H
3Phase 4.2 Global Iteration 1 | Checksum: 1b31bbede
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 01:57:56 ; elapsed = 01:30:21 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
u

Phase %s%s
101*constraints2
4.3 2default:default2&
Global Iteration 22default:defaultZ18-101h px 
‹
Intermediate Timing Summary %s164*route2J
6| WNS=0.150  | TNS=0.000  | WHS=N/A    | THS=N/A    |
2default:defaultZ35-416h px 
H
3Phase 4.3 Global Iteration 2 | Checksum: 178981328
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:03:59 ; elapsed = 01:36:10 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
F
1Phase 4 Rip-up And Reroute | Checksum: 178981328
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:04:02 ; elapsed = 01:36:14 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
|

Phase %s%s
101*constraints2
5 2default:default2/
Delay and Skew Optimization2default:defaultZ18-101h px 
p

Phase %s%s
101*constraints2
5.1 2default:default2!
Delay CleanUp2default:defaultZ18-101h px 
r

Phase %s%s
101*constraints2
5.1.1 2default:default2!
Update Timing2default:defaultZ18-101h px 
E
0Phase 5.1.1 Update Timing | Checksum: 1a0f7541c
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:16:08 ; elapsed = 01:46:15 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
‹
Intermediate Timing Summary %s164*route2J
6| WNS=0.150  | TNS=0.000  | WHS=0.024  | THS=0.000  |
2default:defaultZ35-416h px 
C
.Phase 5.1 Delay CleanUp | Checksum: 1a0f7541c
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:16:13 ; elapsed = 01:46:20 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
z

Phase %s%s
101*constraints2
5.2 2default:default2+
Clock Skew Optimization2default:defaultZ18-101h px 
M
8Phase 5.2 Clock Skew Optimization | Checksum: 1a0f7541c
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:16:17 ; elapsed = 01:46:24 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
O
:Phase 5 Delay and Skew Optimization | Checksum: 1a0f7541c
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:16:20 ; elapsed = 01:46:27 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
n

Phase %s%s
101*constraints2
6 2default:default2!
Post Hold Fix2default:defaultZ18-101h px 
p

Phase %s%s
101*constraints2
6.1 2default:default2!
Hold Fix Iter2default:defaultZ18-101h px 
r

Phase %s%s
101*constraints2
6.1.1 2default:default2!
Update Timing2default:defaultZ18-101h px 
E
0Phase 6.1.1 Update Timing | Checksum: 1aa92852e
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:27:54 ; elapsed = 01:55:52 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
‹
Intermediate Timing Summary %s164*route2J
6| WNS=0.150  | TNS=0.000  | WHS=0.024  | THS=0.000  |
2default:defaultZ35-416h px 
C
.Phase 6.1 Hold Fix Iter | Checksum: 1e7dabe52
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:27:58 ; elapsed = 01:55:56 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
A
,Phase 6 Post Hold Fix | Checksum: 1e7dabe52
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:28:02 ; elapsed = 01:56:00 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
o

Phase %s%s
101*constraints2
7 2default:default2"
Route finalize2default:defaultZ18-101h px 
B
-Phase 7 Route finalize | Checksum: 10b819b64
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:28:41 ; elapsed = 01:56:31 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
v

Phase %s%s
101*constraints2
8 2default:default2)
Verifying routed nets2default:defaultZ18-101h px 
I
4Phase 8 Verifying routed nets | Checksum: 10b819b64
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:28:45 ; elapsed = 01:56:35 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
r

Phase %s%s
101*constraints2
9 2default:default2%
Depositing Routes2default:defaultZ18-101h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X0Y8/SOUTHREFCLK1GTHE3_CHANNEL_X0Y8/SOUTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y18/NORTHREFCLK1 GTHE3_CHANNEL_X0Y18/NORTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y19/NORTHREFCLK1 GTHE3_CHANNEL_X0Y19/NORTHREFCLK12default:default8Z35-467h px 
Ä
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2V
GTHE3_CHANNEL_X0Y9/SOUTHREFCLK1GTHE3_CHANNEL_X0Y9/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y10/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y10/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y11/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y11/SOUTHREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y12/MGTREFCLK1GTHE3_CHANNEL_X0Y12/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y13/MGTREFCLK1GTHE3_CHANNEL_X0Y13/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y14/MGTREFCLK1GTHE3_CHANNEL_X0Y14/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y15/MGTREFCLK1GTHE3_CHANNEL_X0Y15/MGTREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y16/NORTHREFCLK1 GTHE3_CHANNEL_X0Y16/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y17/NORTHREFCLK1 GTHE3_CHANNEL_X0Y17/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y28/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y28/SOUTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y38/NORTHREFCLK1 GTHE3_CHANNEL_X0Y38/NORTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y39/NORTHREFCLK1 GTHE3_CHANNEL_X0Y39/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y29/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y29/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y30/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y30/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y31/SOUTHREFCLK1 GTHE3_CHANNEL_X0Y31/SOUTHREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y32/MGTREFCLK1GTHE3_CHANNEL_X0Y32/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y33/MGTREFCLK1GTHE3_CHANNEL_X0Y33/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y34/MGTREFCLK1GTHE3_CHANNEL_X0Y34/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X0Y35/MGTREFCLK1GTHE3_CHANNEL_X0Y35/MGTREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y36/NORTHREFCLK1 GTHE3_CHANNEL_X0Y36/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X0Y37/NORTHREFCLK1 GTHE3_CHANNEL_X0Y37/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y28/SOUTHREFCLK1 GTHE3_CHANNEL_X1Y28/SOUTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y38/NORTHREFCLK1 GTHE3_CHANNEL_X1Y38/NORTHREFCLK12default:default8Z35-467h px 
È
,Router swapped GT pin %s to physical pin %s
200*route2œ
Ág_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Ág_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y39/NORTHREFCLK1 GTHE3_CHANNEL_X1Y39/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y29/SOUTHREFCLK1 GTHE3_CHANNEL_X1Y29/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y30/SOUTHREFCLK1 GTHE3_CHANNEL_X1Y30/SOUTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y31/SOUTHREFCLK1 GTHE3_CHANNEL_X1Y31/SOUTHREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X1Y32/MGTREFCLK1GTHE3_CHANNEL_X1Y32/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X1Y33/MGTREFCLK1GTHE3_CHANNEL_X1Y33/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X1Y34/MGTREFCLK1GTHE3_CHANNEL_X1Y34/MGTREFCLK12default:default8Z35-467h px 
Â
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2T
GTHE3_CHANNEL_X1Y35/MGTREFCLK1GTHE3_CHANNEL_X1Y35/MGTREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y36/NORTHREFCLK1 GTHE3_CHANNEL_X1Y36/NORTHREFCLK12default:default8Z35-467h px 
Æ
,Router swapped GT pin %s to physical pin %s
200*route2š
Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK0Àg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/GTREFCLK02default:default2X
 GTHE3_CHANNEL_X1Y37/NORTHREFCLK1 GTHE3_CHANNEL_X1Y37/NORTHREFCLK12default:default8Z35-467h px 
ƒ
,Router swapped GT pin %s to physical pin %s
200*route2b
%i_tcds2_if/i_mgt_wrapper/i_rxrecclk/I%i_tcds2_if/i_mgt_wrapper/i_rxrecclk/I2default:default2N
GTHE3_COMMON_X1Y0/RXRECCLK3GTHE3_COMMON_X1Y0/RXRECCLK32default:default8Z35-467h px 
E
0Phase 9 Depositing Routes | Checksum: 10b819b64
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:30:13 ; elapsed = 01:58:13 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
t

Phase %s%s
101*constraints2
10 2default:default2&
Post Router Timing2default:defaultZ18-101h px 
‡
Estimated Timing Summary %s
57*route2J
6| WNS=0.150  | TNS=0.000  | WHS=0.024  | THS=0.000  |
2default:defaultZ35-57h px 
¼
šThe final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
127*routeZ35-327h px 
G
2Phase 10 Post Router Timing | Checksum: 10b819b64
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 02:30:24 ; elapsed = 01:58:23 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
@
Router Completed Successfully
2*	routeflowZ35-16h px 
“

%s
*constraints2s
_Time (s): cpu = 02:30:26 ; elapsed = 01:58:25 . Memory (MB): peak = 16610.965 ; gain = 2522.4652default:defaulth px 
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px 
Ç
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
1832default:default2
72default:default2
02default:default2
02default:defaultZ4-41h px 
^
%s completed successfully
29*	vivadotcl2 
route_design2default:defaultZ4-42h px 
ˆ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
route_design: 2default:default2
02:40:032default:default2
02:06:052default:default2
	16610.9652default:default2
2522.4652default:defaultZ17-268h px 
H
&Writing timing data to binary archive.266*timingZ38-480h px 
D
Writing placer database...
1603*designutilsZ20-1893h px 
=
Writing XDEF routing.
211*designutilsZ20-211h px 
J
#Writing XDEF routing logical nets.
209*designutilsZ20-209h px 
J
#Writing XDEF routing special nets.
210*designutilsZ20-210h px 
Œ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:04:012default:default2
00:01:182default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
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 The %s '%s' has been generated.
621*common2

checkpoint2default:default2g
SD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_routed.dcp2default:defaultZ17-1381h px 
‰
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2&
write_checkpoint: 2default:default2
00:05:482default:default2
00:02:422default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
¡
%s4*runtcl2„
pExecuting : report_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx
2default:defaulth px 
¨
Command: %s
53*	vivadotcl2w
creport_drc -file ngFEC_top_drc_routed.rpt -pb ngFEC_top_drc_routed.pb -rpx ngFEC_top_drc_routed.rpx2default:defaultZ4-113h px 
>
IP Catalog is up to date.1232*coregenZ19-1839h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 

#The results of DRC are in file %s.
168*coretcl2Æ
WD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_routed.rptWD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_routed.rpt2default:default8Z2-168h px 
\
%s completed successfully
29*	vivadotcl2

report_drc2default:defaultZ4-42h px 
ƒ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2 
report_drc: 2default:default2
00:31:532default:default2
00:24:542default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
Î
%s4*runtcl2±
œExecuting : report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx
2default:defaulth px 
Ö
Command: %s
53*	vivadotcl2¤
report_methodology -file ngFEC_top_methodology_drc_routed.rpt -pb ngFEC_top_methodology_drc_routed.pb -rpx ngFEC_top_methodology_drc_routed.rpx2default:defaultZ4-113h px 
E
%Done setting XDC timing constraints.
35*timingZ38-35h px 

ËThe instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2ö
îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST	îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2"
QPLL1REFCLKSEL2default:default8Z38-277h px 
Y
$Running Methodology with %s threads
74*drc2
22default:defaultZ23-133h px 
¸
2The results of Report Methodology are in file %s.
450*coretcl2Þ
cD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_methodology_drc_routed.rptcD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_methodology_drc_routed.rpt2default:default8Z2-1520h px 
d
%s completed successfully
29*	vivadotcl2&
report_methodology2default:defaultZ4-42h px 
‹
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2(
report_methodology: 2default:default2
00:07:122default:default2
00:04:092default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
²
%s4*runtcl2•
€Executing : report_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx
2default:defaulth px 
¹
Command: %s
53*	vivadotcl2‡
sreport_power -file ngFEC_top_power_routed.rpt -pb ngFEC_top_power_summary_routed.pb -rpx ngFEC_top_power_routed.rpx2default:defaultZ4-113h px 
E
%Done setting XDC timing constraints.
35*timingZ38-35h px 

ËThe instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2ö
îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST	îi_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2"
QPLL1REFCLKSEL2default:default8Z38-277h px 
K
,Running Vector-less Activity Propagation...
51*powerZ33-51h px 
P
3
Finished Running Vector-less Activity Propagation
1*powerZ33-1h px 
ô
ÒDetected over-assertion of set/reset/preset/clear net with high fanouts, power estimation might not be accurate. Please run Tool - Power Constraint Wizard to set proper switching activities for control signals.282*powerZ33-332h px 
È
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
1952default:default2
102default:default2
02default:default2
02default:defaultZ4-41h px 
^
%s completed successfully
29*	vivadotcl2 
report_power2default:defaultZ4-42h px 
…
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
report_power: 2default:default2
00:08:392default:default2
00:04:522default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
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%s4*runtcl2s
_Executing : report_route_status -file ngFEC_top_route_status.rpt -pb ngFEC_top_route_status.pb
2default:defaulth px 
Œ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
report_route_status: 2default:default2
00:00:092default:default2
00:00:092default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
ð
%s4*runtcl2Ó
¾Executing : report_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation 
2default:defaulth px 
ˆ
UpdateTimingParams:%s.
91*timing2O
; Speed grade: -1, Temperature grade: C, Delay Type: min_max2default:defaultZ38-91h px 
|
CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2
22default:defaultZ38-191h px 
Ž
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2+
report_timing_summary: 2default:default2
00:00:532default:default2
00:00:402default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
‚
%s4*runtcl2f
RExecuting : report_incremental_reuse -file ngFEC_top_incremental_reuse_routed.rpt
2default:defaulth px 
g
BIncremental flow is disabled. No incremental reuse Info to report.423*	vivadotclZ4-1062h px 
‚
%s4*runtcl2f
RExecuting : report_clock_utilization -file ngFEC_top_clock_utilization_routed.rpt
2default:defaulth px 
‘
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
report_clock_utilization: 2default:default2
00:00:492default:default2
00:00:492default:default2
	16610.9652default:default2
0.0002default:defaultZ17-268h px 
É
%s4*runtcl2¬
—Executing : report_bus_skew -warn_on_violation -file ngFEC_top_bus_skew_routed.rpt -pb ngFEC_top_bus_skew_routed.pb -rpx ngFEC_top_bus_skew_routed.rpx
2default:defaulth px 
ˆ
UpdateTimingParams:%s.
91*timing2O
; Speed grade: -1, Temperature grade: C, Delay Type: min_max2default:defaultZ38-91h px 
|
CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2
22default:defaultZ38-191h px 


End Record