O Command: %s 53* vivadotcl2 opt_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xcku1152default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xcku1152default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2021.012default:defaultZ17-1540hpx n ,Running DRC as a precondition to command %s 22* vivadotcl2 opt_design2default:defaultZ4-22hpx R  Starting %s Task 103* constraints2 DRC2default:defaultZ18-103hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx U DRC finished with %s 272*project2 0 Errors2default:defaultZ1-461hpx d BPlease refer to the DRC report (report_drc) for more information. 274*projectZ1-462hpx   %s * constraints2o [Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 6305.668 ; gain = 0.0002default:defaulthpx g  Starting %s Task 103* constraints2, Cache Timing Information2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx  The instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2" QPLL1REFCLKSEL2default:default8Z38-277hpx P ;Ending Cache Timing Information Task | Checksum: 1203813b9 *commonhpx   %s * constraints2o [Time (s): cpu = 00:02:43 ; elapsed = 00:01:32 . Memory (MB): peak = 6305.668 ; gain = 0.0002default:defaulthpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx i Phase %s%s 101* constraints2 1 2default:default2 Retarget2default:defaultZ18-101hpx | )Pushed %s inverter(s) to %s load pin(s). 98*opt2 21532default:default2 174022default:defaultZ31-138hpx K Retargeted %s cell(s). 49*opt2 02default:defaultZ31-49hpx < 'Phase 1 Retarget | Checksum: 251c4a4c5 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:01:25 ; elapsed = 00:01:04 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Retarget2default:default2 6372default:default2 31302default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2 Retarget2default:default2 7702default:defaultZ31-1021hpx u Phase %s%s 101* constraints2 2 2default:default2( Constant propagation2default:defaultZ18-101hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx H 3Phase 2 Constant propagation | Checksum: 29b57cb64 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:01:32 ; elapsed = 00:01:11 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2( Constant propagation2default:default2 172default:default2 1862default:defaultZ31-389hpx f Phase %s%s 101* constraints2 3 2default:default2 Sweep2default:defaultZ18-101hpx 9 $Phase 3 Sweep | Checksum: 1be47df63 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:01 ; elapsed = 00:01:41 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Sweep2default:default2 02default:default2 6522default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2 Sweep2default:default2 40822default:defaultZ31-1021hpx r Phase %s%s 101* constraints2 4 2default:default2% BUFG optimization2default:defaultZ18-101hpx  PPhase BUFG optimization inserted %s global clock buffer(s) for CLOCK_LOW_FANOUT.553*opt2 02default:defaultZ31-1077hpx  OInserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: %s, Net: %s93*opt2: ipb_rst_BUFG_inst ipb_rst_BUFG_inst2default:default2& ipb_rstipb_rst2default:default8Z31-129hpx E 0Phase 4 BUFG optimization | Checksum: 287b45196 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:37 ; elapsed = 00:02:16 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  EPhase %s created %s cells of which %s are BUFGs and removed %s cells.395*opt2% BUFG optimization2default:default2 22default:default2 12default:default2 02default:defaultZ31-662hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2% BUFG optimization2default:default2 62default:defaultZ31-1021hpx | Phase %s%s 101* constraints2 5 2default:default2/ Shift Register Optimization2default:defaultZ18-101hpx  dSRL Remap converted %s SRLs to %s registers and converted %s registers of register chains to %s SRLs546*opt2 02default:default2 02default:default2 02default:default2 02default:defaultZ31-1064hpx O :Phase 5 Shift Register Optimization | Checksum: 287b45196 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:39 ; elapsed = 00:02:18 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2/ Shift Register Optimization2default:default2 02default:default2 02default:defaultZ31-389hpx x Phase %s%s 101* constraints2 6 2default:default2+ Post Processing Netlist2default:defaultZ18-101hpx K 6Phase 6 Post Processing Netlist | Checksum: 2950b4a3a *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:44 ; elapsed = 00:02:23 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2+ Post Processing Netlist2default:default2 02default:default2 02default:defaultZ31-389hpx / Opt_design Change Summary *commonhpx / ========================= *commonhpx   *commonhpx   *commonhpx  z------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Retarget | 637 | 3130 | 770 | | Constant propagation | 17 | 186 | 0 | | Sweep | 0 | 652 | 4082 | | BUFG optimization | 2 | 0 | 6 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- *commonhpx   *commonhpx   *commonhpx a  Starting %s Task 103* constraints2& Connectivity Check2default:defaultZ18-103hpx   %s * constraints2o [Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6452.953 ; gain = 0.0002default:defaulthpx J 5Ending Logic Optimization Task | Checksum: 1c2bfa8a7 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:03:19 ; elapsed = 00:02:55 . Memory (MB): peak = 6452.953 ; gain = 147.2852default:defaulthpx a  Starting %s Task 103* constraints2& Power Optimization2default:defaultZ18-103hpx s 7Will skip clock gating for clocks with period < %s ns. 114*pwropt2 2.002default:defaultZ34-132hpx = Applying IDT optimizations ... 9*pwroptZ34-9hpx ? Applying ODC optimizations ... 10*pwroptZ34-10hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx  The instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2" QPLL1REFCLKSEL2default:default8Z38-277hpx  MFlop %s is having more than maxLoadSize fanouts. Skipped from ODC paradigm. 139*pwropt2X ipb/trans/sm/addr_reg[11]/_DFFRS  ipb/trans/sm/addr_reg[11]/_DFFRS2default:default8Z34-175hpx K ,Running Vector-less Activity Propagation... 51*powerZ33-51hpx P 3 Finished Running Vector-less Activity Propagation 1*powerZ33-1hpx   *pwropthpx e  Starting %s Task 103* constraints2* PowerOpt Patch Enables2default:defaultZ18-103hpx  WRITE_MODE attribute of %s BRAM(s) out of a total of %s has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. 129*pwropt2 02default:default2 21102default:defaultZ34-162hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx  The instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2" QPLL1REFCLKSEL2default:default8Z38-277hpx e +Structural ODC has moved %s WE to EN ports 155*pwropt2 562default:defaultZ34-201hpx  CNumber of BRAM Ports augmented: %s newly gated: %s Total Ports: %s 65*pwropt2 92default:default2 7402default:default2 42202default:defaultZ34-65hpx N 9Ending PowerOpt Patch Enables Task | Checksum: 19bf1e094 *commonhpx   %s * constraints2p \Time (s): cpu = 00:03:19 ; elapsed = 00:02:02 . Memory (MB): peak = 13824.258 ; gain = 0.0002default:defaulthpx J 5Ending Power Optimization Task | Checksum: 19bf1e094 *commonhpx   %s * constraints2s _Time (s): cpu = 00:19:54 ; elapsed = 00:09:18 . Memory (MB): peak = 13824.258 ; gain = 7371.3052default:defaulthpx \  Starting %s Task 103* constraints2! Final Cleanup2default:defaultZ18-103hpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx  The instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2" QPLL1REFCLKSEL2default:default8Z38-277hpx J 5Ending Logic Optimization Task | Checksum: 12d2c38ac *commonhpx   %s * constraints2p \Time (s): cpu = 00:04:20 ; elapsed = 00:02:43 . Memory (MB): peak = 13824.258 ; gain = 0.0002default:defaulthpx E 0Ending Final Cleanup Task | Checksum: 12d2c38ac *commonhpx   %s * constraints2p \Time (s): cpu = 00:04:28 ; elapsed = 00:02:51 . Memory (MB): peak = 13824.258 ; gain = 0.0002default:defaulthpx b  Starting %s Task 103* constraints2' Netlist Obfuscation2default:defaultZ18-103hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.4222default:default2 13824.2582default:default2 0.0002default:defaultZ17-268hp x  K 6Ending Netlist Obfuscation Task | Checksum: 12d2c38ac *commonhpx   %s * constraints2t `Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.422 . Memory (MB): peak = 13824.258 ; gain = 0.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 472default:default2 52default:default2 02default:default2 02default:defaultZ4-41hpx \ %s completed successfully 29* vivadotcl2 opt_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 opt_design: 2default:default2 00:30:432default:default2 00:16:522default:default2 13824.2582default:default2 7518.5902default:defaultZ17-268hp x  E %Done setting XDC timing constraints. 35*timingZ38-35hpx  The instance '%s' has %s pins that are not tied constant, so the corresponding mux will select the input(s) having the worst case (highest frequency) clock(s) for automatic derivation of generated clocks184*timing2 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST2default:default2" QPLL1REFCLKSEL2default:default8Z38-277hpx H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:00:022default:default2 00:00:00.3212default:default2 13824.2582default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2d PD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_opt.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:06:492default:default2 00:03:522default:default2 13824.2582default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2 mExecuting : report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2t `report_drc -file ngFEC_top_drc_opted.rpt -pb ngFEC_top_drc_opted.pb -rpx ngFEC_top_drc_opted.rpx2default:defaultZ4-113hpx > IP Catalog is up to date.1232*coregenZ19-1839hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  #The results of DRC are in file %s. 168*coretcl2 VD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_opted.rptVD:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.runs/impl_1/ngFEC_top_drc_opted.rpt2default:default8Z2-168hpx \ %s completed successfully 29* vivadotcl2 report_drc2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 report_drc: 2default:default2 00:04:502default:default2 00:02:342default:default2 13824.2582default:default2 0.0002default:defaultZ17-268hp x   End Record